4269-90 - Peregrine Semiconductor Corp.

Page 1 of 12

The PE4269 SP6T RF UltraCMOS™ Switch addresses the

specific design needs of the Quad-Band GSM Handset

Antenna Switch Module Market. On-chip CMOS decode logic

facilitat es thr ee-pin low voltage CMOS control. High ESD

tolerance of 1500 V at all ports, no blocking capacitor

requirements and on- chip SAW filter over-voltage protection

devices make this the ultimate in integration and ruggedness.

The PE4269 UltraCMOS™ RF Switch is manufactured in

Peregrine ’s patented Ultra Thin Silicon (UTSi®) CMOS

process, offering the performance of GaAs with the economy

and integration of conventional CMOS.

Product Specification

SP6T UltraCMOS™ 2.6 V Switch

100 – 3000 MHz

Product Description

Figure 1. Functional Diagram Figure 2. Die Top View

PE4269 DIE

Features

• Three pin CMOS logic control with

integral decoder/driver

• Low TX insertion loss: 0.55 dB at 900

MHz, 0.65 dB at 1900 MHz

• TX – RX Isolation of 48 dB at 900 MHz,

40 dB at 1900 MHz

• Low harmonics: 2fo = -85 dBc and

3fo = -72 dBc

• 1500 V HBM ESD tolerance all ports

• 41 dBm P1dB

• No blocking capacitors required

RX1

RX2

RX3

RX4

TX1

TX2

CMOS

Control/Driver

and ESD

V1

V2V3

ANT TX1

TX2

GND

RX1

GND

RX2

GND

RX3

GND

RX4

GND

GND VDD V3 GND V2 V1 GND

GND

Product Specific ation

PE4269

Page 2 of 12

Table 1. Electrical Specifications @ +25 °C, VDD = 2. 6 V (ZS = ZL = 50 )

Parameter Conditions Minimum Typical Maximum Units

Operational Frequency 100 3000 MHz

Insertion Loss

ANT - TX - 850 / 900 MHz

ANT - TX - 1800 / 1900 MHz

ANT - RX - 850 / 900 MHz

ANT - RX - 1800 / 1900 MHz

0.55

0.65

0.90

1.00

0.65

0.75

1.00

1.10

dB

Isolation

TX - RX - 850 / 900 MHz

TX - RX - 1800 / 1900 MHz

TX1 - TX2 - 850 / 900 MHz

TX1 - TX2 - 1800 / 1900 MHz

45

37

26

23

48

40

29

25

dB

Return Loss 850 / 900 MHz

1800 / 1900 MHz 19

15.5 22

23 dB

2nd Harmonic 35 dBm TX Input - 850 / 900 MHz

33 dBm TX Input - 1800 / 1900 MHz

-85

-81 -80

-79 dBc

3rd Harmonic 35 dBm TX Input - 850 / 900 MHz

33 dBm TX Input - 1800 / 1900 MHz -72

-66 -70

-64 dBc

Switching Time (10-90%) (90-10%) RF 2 3 µs

Product Specific ation

PE4269

Page 3 of 12

TX1

PE4269

Die

ANT

TX2

RX1

RX2

VDD

V3

V2

V1

GND

RX3

GND

RX4 GND

12

3

4

5

6

7

8910

11

12

13

14

15

16

17

18

19

20

TX1

PE4269

Die

ANT

TX2

RX1

RX2

VDD

V3

V2

V1

GND

RX3

GND

RX4 GND

12

3

4

5

6

7

8910

11

12

13

14

15

16

17

18

19

20

Table 2. Pin Descriptions

Table 3. Absolute Maximum Ratings

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS™ device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating.

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMO S™

devices are immune to latch-up.

Table 4. DC Electrical Specifications

Table 5. Truth Table

Notes: 1. Bond wires should be physical ly s hort and connected to

ground plane for best perf ormanc e.

2. .Blocking capacitors needed only when non-zero DC

voltage present.

Figure 3. Pin Configuration (Top View)

Pin No. Pin Name Description

12 ANT RF Common – Antenna

22 TX1 RF I/O - TX1

31 GND Ground (Requires two bond wi res)

42 TX2 RF I/O – TX2

51 GND Ground

61 GND Ground

7 VDD Supply

8 V3 Switch control input, CMOS logic level

91 GND Ground

10 V2 Switch control input , CMOS l ogic level

11 V1 Switch control input , CMOS l ogic level

121 GND Ground

131 GND Ground

142 RX4 RF I/O – RX4

151 GND Ground

162 RX3 RF I/O – RX3

171 GND Ground

182 RX2 RF I/O – RX2

191 GND Ground

202 RX1 RF I/O – RX1

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 4.0 V

VI Voltage on any input -0.3 VDD+

0.3 V

TST Storage temperature range -65 +150 °C

TOP Operating temperature range -40 +85 °C

PIN TX input power (50)1 +38 dBm

RX input power (50)1 +23

VESD

ESD Voltage (HBM, MIL_STD

883 Method 3015.7) 1500 V

ESD Voltage (MM, JEDEC,

JESD22-A114-B) 100 V

ESD Voltage (CDM, JEDEC,

JESD22-C101-A) 2000 V

ESD Voltage at ANT Port

(IEC 6100-4-2) 1700 V

Parameter Min Typ Max Units

VDD Supply Voltage 2.4 2.6 2.8 V

IDD Power Supply Current

(VDD = 2.6V) 13 20 µA

Control Voltage Hi gh 0.7 x VDD V

Control Voltage Low 0.3 x VDD V

Path V3 V2 V1

ANT – RX1 0 0 0

ANT – RX2 0 0 1

ANT – RX3 0 1 0

ANT – RX4 0 1 1

ANT - TX1 1 0 x

ANT - TX2 1 1 x

Notes: 1. Max RF specified with VDD applied.

Product Specific ation

PE4269

Page 4 of 12

Evaluation Kit

The SP6T Evaluation Kit board was designed to ease

customer evaluation of the PE4269 RF switch.

The PE4269 has two high power TX ports and four

high isolation RX ports. The ports are designed to work

with the 850, 900, 1800 or 1900 MHz bands. Each

path can be assigned to any of the frequency bands, as

determined by the customer application.

The ANT port connects through a 50  transmission

line to the top SMA connector, J1. The RX and TX

ports connect throu gh 50  transmis s i on lin es to SMA

connectors J2 – J7. A through 50  trans m iss ion li ne

between SMA connectors J9 and J10 allows estimation

of the PCB losses over environmental conditions. An

open transmission line connected to J11 is also

provided.

J8 supplies DC power to the pin marked VDD and the

bottom row of pins, which is GND. 1 M pull-up

resistors are connected from VDD to each of the three

control logic inputs: V1, V2, and V3. These pull-up

resistors are provided for ease of evaluation on this

board and are not required for the PE4269 to operate.

Adding a jumper between a control pin and the

adjacent GND pin on the bottom row of J8 will set a

logic-0 on that control pin. Removing the jumper will

set a logic-1. To evaluate the PE4269, add or remove

jumpers according to the truth table in Table 5.

Figure 4. Evaluation Board Layout

Figure 5. Evaluation Board Schematic

RX1 ANT

RX2

RX3

RX4

TX1

TX2

Open Line

Through-Line

Product Specific ation

PE4269

Page 5 of 12

Typical Performance Data @ VDD = 2.6 V, 25 °C (Unless otherwise noted)

Figure 7. TX Insertion Loss

Figure 9. Isolation Figure 8. TX Insertion Loss

Figure 6. Insertion Loss

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

0 500 1000 1500 2000 2500 3000

RX1 IL

TX2 IL

TX1 IL

RX4 IL

RX3 IL

RX2 IL

Insertion Loss

Frequency (MHz)

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0 500 1000 1500 2000 2500 3000

-40 C

25 C

85 C

Insertion Loss

Frequency (MHz)

Product Specific ation

PE4269

Page 6 of 12

Typical Performance Data @ VDD = 2.6 V, 25 °C (Unless otherwise noted)

Figure 11. TX Harmonics 915MHz

Figure 13. TX Harmonics 1900MHz Figure 12. TX Harmonics 915MHz

Figure 10. Return Loss

Product Specific ation

PE4269

Page 7 of 12

Typical Performance Data @ VDD = 2.6 V, 25 °C (Unless otherwise noted)

Figure 14. TX Harmonics 1900MHz

Product Specific ation

PE4269

Page 8 of 12

Electrical Test and Performance Specifications

PE4269 dice are 100% electrically tested for the

parameters listed below from Table 1 and Table 4. All

other parameters are guaranteed through design and

characterization.

Wafer and Die Packaging

Peregrine Semiconductor has two methods for shipping

dice to our customers. The shipping option used is

based on the customer’s requirements and the number

of dice.

Peregrine offers product dice in two packaging options:

Standard Die Carrier Packages (waffle pack) and dice

on Film Frames.

Wafer Mount/Dicing

In preparation for dicing, wafers are thinned and

polished and 100% electrically probed prior to

mounting on film frame tape and rings. Figure 15

shows a wafer mounted on film frame using PVC

backed mounting tape. In preparation for shipment,

wafers are visually inspected after singulation and

shipped with an el ec tronic map file providing goo d dic e

locations.

• Insertion Loss (all ports)

• TX1 & TX2 Harmonics

• TX – RX Isolation

• IDD supply current

• Control pin leakages

Storage and Preservation

Proper storage conditions are necessary to prevent

product contamination and/or degradation after

shipment.

Product should be stored in the original unopened

packaging or, once opened, in a nitrogen purged

cabinet at room temperature (45% + 15% relative

humidity controlled environment).

Singulated wafers mounted on film frames are intended

for immediate use and have a limited shelf life. This is

primarily due to the nature of the adhesive tape used

for mounting the product. This product can be stored

up to 30 days. This applies whether or not the material

has remained in its original sealed container. To reduce

the risk of contamination or degradation, it is

recommended that product not being used in the

assembly process be returned to their original

containers and resealed with a vacuum seal process.

Figure 15. Wafer on Film Frame

Figure 17. Waffle Pack

Figure 16. Dice and Wafer Processing Flow

Standard Die Carrier Package/Waffle Pack

Waffle packs are available to customers during product

development and prototyping phase only. Orders will

move to film frames at production launch or for large

quantity requirements.

Dice have been 100% electrically probed, singulated,

visually inspected and are packaged in a 2”x2” waffle

pack (400 dice per waffle pack).

Wafer

Processing

Visual

Inspection

Process Control

Monitor (PCM)

Wafer Level

Reliability

(WLR)

Backgrind

and Polish

Dice Picking

100%

Electrical Test

Ink Reject Die or

Electronic

Wafer Map

Outgoing QA

Inspection

Wafer

Singulation

100% Visual

Inspection

Pack and Ship

Wafers

Carrier Loading

Pack and Ship

Dice

Product Specific ation

PE4269

Page 9 of 12

Die Handling

All die products must be handled only at ESD safe

workstations using standard ESD precautions. It is

recommended that the be handled only in a class

10,000 or better designated clean room environment.

Singulated dice are not to be handled with tweezers. A

vacuum wand wit h a non-m etal lic ES D prot ec ted tip

must be used.

Recommended Dice Assembly Procedure

Cleaning

Dice do not require cleaning prior to assembly.

Die Attach

The PE4269 die substrate is sapphire – the

recommended die attach operation for sapphire is

epoxy die attach adhesive. An eutectic die attach

method does not work with sapphire substrates.

Bonding

Thermo compression gold ball o r aluminum ultrasonic

bonding may be used. The ball should cover the

bonding pad, but not excessively, or it may short out the

surroundi ng met al liz at io n. Aluminum or gold 0.8-m il

wire is recommended. Note the bonding pad material is

aluminum.

Shipping Method

Standard die carrier packages and wafer film frames

are placed in a wafer container and then vacuum-

sealed inside an ESD shielded bag. Sealed pr oduct is

then placed inside a corrugated cardboard box

surrounded by bubble wrap or foam for maximum

protection during shipment.

Product Specific ation

PE4269

Page 10 of 12

TX1

PE4269

Die

ANT

TX2

RX1

RX2

VDD

V3

V2

V1

GND

RX3

GND

RX4 GND

12

3

4

5

6

7

8910

11

12

13

14

15

16

17

18

19

20

1.136mm

1.096mm

Table 6. Mechanical Specifications

Parameter Minimum Typical Maximum Units Test Conditions

Die Size (x,y) 1.136 x 1.096 mm As drawn

Die Size (x,y) 1.24 x 1.20 mm Including excess sapphire, max. tolerance = +0.1mm in

either dimension

Wafer Thickness 180 200 220 µm

Wafer Size 150 mm

Table 7. Pad Coordinates

All pad locations ori gi nat e from the die center and refer to the

center of the pad.

All pad openings are 60 x 60 µm except for Pad #3 which is 140 x 60 µm.

Minimum pad pitch is 80 µm.

Note 1. - Double pad, requires two bond wires.

Figure 18. Pad Numbering

Pad # Pad Name Pad Center (µm)

X Y

1 ANT -1.9 488.1

2 TX1

511.3 491.3

3 GND1 511.3 168.9

4 TX2

511.3 -153.5

5 GND

511.3 -233.5

6 GND

511.3 -491.3

7 VDD

337.7 -491.3

8 V3

-25.7 -491.3

9 GND

-160.9 -491.3

10 V2

-296.1 -491.3

11 V1

-376.1 -491.3

12 GND

-511.3 -491.3

13 GND

-511.3 -223.7

14 RX4

-511.3 -105.1

15 GND

-511.3 -25.1

16 RX3

-511.3 93.5

17 GND

-511.3 173.5

18 RX2

-511.3 292.1

19 GND

-511.3 372.1

20 RX1

-511.3 490.7

Product Specific ation

PE4269

Page 11 of 12

PE4269

ESD Protection

Table 9. Ordering Information

ESD Protection Circuit

Handset products must tolerate large ESD surges

at the antenna interface without damage. The IEC

1000-4-2 standard specifies both 8 kV contact and

16 kV air discharges that typical handsets must

survive. By itself, the PE4269 offers protection to

1.5 kV but with the addition of two inexpensive

passive components, the switch can meet the

levels as specified in the IEC spec. Figure 19 is

the suggested solution for compliance with the

IEC standards.

Figure 19. ESD Protection Circuit

Table 8. PE4269 Antenna Application Test Results

(C=150 pF, R=330 Ω, I EC 6100- 4- 2 Stand ard )

L = 27 nH (muRata: LQG1127NJ00),

C = 33 pF (muRata: GRM33C0G330J50)

Test Condition Results

+8 kV contact discharge, 10 times with 1s interv als Pass

-8 kV contact discharge, 10 times with 1s intervals Pass

+16 kV air discharge, 10 times with 1s interv als Pass

-16 kV air discharge, 10 times with 1s intervals Pass

Order Code Die ID Description Package Shipping Method

4269-90 C9798_1 PE4269-DIE-D Film Frame Wafer (Gross Die / Wafer Quantity)

4269-99 C9798_1 PE4269-DIE -400G Waffle Pack 400 Di ce / Waffle Pack

4269-00 C9798_1 PE4269-DIE -1H Evaluation Kit 1/ box

Product Specific ation

PE4269

Page 12 of 12

Sales Offices

United States

Peregrine Semiconductor Corp.

9450 Carroll Park Drive

San Diego, CA 92121

Tel 1-858-731-9400

Fax 1-858-731-9499

Japan

Peregrine Semiconductor K.K.

5A-5, 5F Imperial Tower

1-1-1 Uchisaiwaicho, Chiyoda-ku

Tokyo 100-0011 Japan

Tel: 011-81-3-3502-5211

Fax: 011-81-3-3502-5213

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vents

F- 92380 Garches, France

Tel: 011- 33-1-47-41-91-73

Fax : 011-33-1-47-41-91-73

For a list of representatives in your area, please refer to our Web site at: http://www.psemi.com

Data Sheet Identification

Advance Information

The product is in a formative or design stage. The data

sheet contai ns design target specifications for product

development. Specifications and features may change in

any manner without notice.

Preliminary Specification

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserv es the right

to change specifications at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data. In the event Peregrine

decides to change the specifications, Peregrine will notify

customers of the intended changes by issuing a DCN

(Document Change Notice).

The information in this data sheet is believed to be reliable.

However, Peregrine assumes no liability for the use of this

information. Use shall be entirely at the user’s own risk.

No patent rights or licenses to any circuits described in this

data sheet are implied or granted to any third party.

Peregrine’s products are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to support or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregrine assumes no liability for damages, including

consequential or incidental damages, arising out of the use of

its products in such applications .

Peregrine, t he Peregrine l ogoty pe, P eregri ne S emiconductor Corp., and

UTSi are registered trademarks of Peregrine Semiconductor Corporat i on.

China

Peregrine Semiconductor

28G, Times Square,

No. 500 Zhangyang Road,

Shanghai, 200122, P.R. China

Tel: 011-86-21-5836-8276

Fax: 011-86-21-5836-7652