Product Specification PE4269 DIE SP6T UltraCMOSTM 2.6 V Switch Product Description 100 - 3000 MHz The PE4269 SP6T RF UltraCMOSTM Switch addresses the specific design needs of the Quad-Band GSM Handset Antenna Switch Module Market. On-chip CMOS decode logic facilitates three-pin low voltage CMOS control. High ESD tolerance of 1500 V at all ports, no blocking capacitor requirements and on- chip SAW filter over-voltage protection devices make this the ultimate in integration and ruggedness. Features * Three pin CMOS logic control with integral decoder/driver * Low TX insertion loss: 0.55 dB at 900 MHz, 0.65 dB at 1900 MHz * TX - RX Isolation of 48 dB at 900 MHz, 40 dB at 1900 MHz * Low harmonics: 2fo = -85 dBc and 3fo = -72 dBc * 1500 V HBM ESD tolerance all ports * 41 dBm P1dB * No blocking capacitors required The PE4269 UltraCMOSTM RF Switch is manufactured in Peregrine's patented Ultra Thin Silicon (UTSi(R)) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram Figure 2. Die Top View RX1 ANT TX1 GND RX1 RX2 TX1 GND GND GND RX3 TX2 RX2 GND RX4 RX3 RX4 TX2 GND CMOS Control/Driver and ESD V3 V2 GND V1 GND V2 GND V3 VDD GND V1 Peregrine Semiconductor Corp. (R) http://www.psemi.com Copyright (c) Peregrine Semiconductor Corp. 2005 Page 1 of 12 PE4269 Product Specification Table 1. Electrical Specifications @ +25 C, VDD = 2.6 V (ZS = ZL = 50 ) Parameter Conditions Operational Frequency Insertion Loss Isolation Return Loss 2nd Harmonic 3rd Harmonic Switching Time Typical 100 Maximum Units 3000 MHz ANT - TX - 850 / 900 MHz 0.55 0.65 dB ANT - TX - 1800 / 1900 MHz 0.65 0.75 dB ANT - RX - 850 / 900 MHz 0.90 1.00 dB ANT - RX - 1800 / 1900 MHz 1.00 1.10 dB TX - RX - 850 / 900 MHz 45 48 dB TX - RX - 1800 / 1900 MHz 37 40 dB TX1 - TX2 - 850 / 900 MHz 26 29 dB TX1 - TX2 - 1800 / 1900 MHz 23 25 dB 19 22 15.5 23 850 / 900 MHz 1800 / 1900 MHz dB 35 dBm TX Input - 850 / 900 MHz -85 -80 33 dBm TX Input - 1800 / 1900 MHz -81 -79 35 dBm TX Input - 850 / 900 MHz -72 -70 33 dBm TX Input - 1800 / 1900 MHz -66 -64 2 3 (10-90%) (90-10%) RF Copyright (c) Peregrine Semiconductor Corp. 2005 Page 2 of 12 Minimum dBc dBc s File No. 70/0169-01A UltraCMOSTM RFIC Solutions PE4269 Product Specification Table 3. Absolute Maximum Ratings ANT Figure 3. Pin Configuration (Top View) RX1 20 GND 19 RX2 18 GND 17 RX3 16 GND 14 GND 13 2 1 3 PE4269 Die 15 RX4 Symbol 4 5 TX1 GND GND TX2 GND Min Max Units VDD Power supply voltage -0.3 4.0 V VI Voltage on any input -0.3 VDD+ 0.3 V TST Storage temperature range -65 +150 C TOP Operating temperature range -40 +85 C 6 GND 7 VDD 8 V3 9 GND 10 V2 V1 GND 11 Pin No. Pin Name 12 ANT RF Common - Antenna 22 TX1 RF I/O - TX1 3 42 GND +38 RX input power (50)1 +23 ESD Voltage (HBM, MIL_STD 883 Method 3015.7) 1500 V ESD Voltage (MM, JEDEC, JESD22-A114-B) 100 V ESD Voltage (CDM, JEDEC, JESD22-C101-A) 2000 V 1700 V dBm ESD Voltage at ANT Port (IEC 6100-4-2) Notes: 1. Max RF specified with VDD applied. Table 2. Pin Descriptions 1 TX input power (50)1 PIN VESD 12 Parameter/Conditions Description Ground (Requires two bond wires) Table 4. DC Electrical Specifications Parameter VDD Supply Voltage TX2 RF I/O - TX2 GND Ground Control Voltage High 1 6 GND Ground Control Voltage Low 7 VDD Supply 8 V3 91 GND 10 V2 Switch control input, CMOS logic level Ground Switch control input, CMOS logic level 11 V1 121 GND Ground 131 GND Ground 142 RX4 RF I/O - RX4 151 GND Ground 162 RX3 RF I/O - RX3 171 GND Ground 2 RX2 RF I/O - RX2 1 GND Ground 2 RX1 RF I/O - RX1 18 19 20 Switch control input, CMOS logic level Notes: 1. Bond wires should be physically short and connected to ground plane for best performance. 2. .Blocking capacitors needed only when non-zero DC voltage present. Peregrine Semiconductor Corp. (R) http://www.psemi.com Typ Max Units 2.4 2.6 2.8 V 13 20 A 0.3 x VDD V IDD Power Supply Current 1 5 Min (VDD = 2.6V) 0.7 x VDD V Table 5. Truth Table Path V3 V2 V1 ANT - RX1 0 0 0 ANT - RX2 0 0 1 ANT - RX3 0 1 0 ANT - RX4 0 1 1 ANT - TX1 1 0 x ANT - TX2 1 1 x Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Copyright (c) Peregrine Semiconductor Corp. 2005 Page 3 of 12 PE4269 Product Specification Evaluation Kit Figure 4. Evaluation Board Layout RX1 The SP6T Evaluation Kit board was designed to ease customer evaluation of the PE4269 RF switch. The PE4269 has two high power TX ports and four high isolation RX ports. The ports are designed to work with the 850, 900, 1800 or 1900 MHz bands. Each path can be assigned to any of the frequency bands, as determined by the customer application. RX2 TX1 RX3 TX2 The ANT port connects through a 50 transmission line to the top SMA connector, J1. The RX and TX ports connect through 50 transmission lines to SMA connectors J2 - J7. A through 50 transmission line between SMA connectors J9 and J10 allows estimation of the PCB losses over environmental conditions. An open transmission line connected to J11 is also provided. RX4 J8 supplies DC power to the pin marked VDD and the bottom row of pins, which is GND. 1 M pull-up resistors are connected from VDD to each of the three control logic inputs: V1, V2, and V3. These pull-up resistors are provided for ease of evaluation on this board and are not required for the PE4269 to operate. Adding a jumper between a control pin and the adjacent GND pin on the bottom row of J8 will set a logic-0 on that control pin. Removing the jumper will set a logic-1. To evaluate the PE4269, add or remove jumpers according to the truth table in Table 5. ANT Through-Line Open Line Figure 5. Evaluation Board Schematic Copyright (c) Peregrine Semiconductor Corp. 2005 Page 4 of 12 File No. 70/0169-01A UltraCMOSTM RFIC Solutions PE4269 Product Specification Typical Performance Data @ VDD = 2.6 V, 25 C (Unless otherwise noted) Figure 6. Insertion Loss RX1 IL TX2 IL TX1 IL RX4 IL RX3 IL RX2 IL Figure 7. TX Insertion Loss 0 -0.2 Insertion Loss -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 0 500 1000 1500 2000 2500 3000 Frequency (MHz) Figure 8. TX Insertion Loss Figure 9. Isolation -40 C 25 C 85 C -0.2 Insertion Loss -0.4 -0.6 -0.8 -1 -1.2 0 500 1000 1500 2000 2500 3000 Frequency (MHz) Peregrine Semiconductor Corp. (R) http://www.psemi.com Copyright (c) Peregrine Semiconductor Corp. 2005 Page 5 of 12 PE4269 Product Specification Typical Performance Data @ VDD = 2.6 V, 25 C (Unless otherwise noted) Figure 10. Return Loss Figure 11. TX Harmonics 915MHz Figure 12. TX Harmonics 915MHz Figure 13. TX Harmonics 1900MHz Copyright (c) Peregrine Semiconductor Corp. 2005 Page 6 of 12 File No. 70/0169-01A UltraCMOSTM RFIC Solutions PE4269 Product Specification Typical Performance Data @ VDD = 2.6 V, 25 C (Unless otherwise noted) Figure 14. TX Harmonics 1900MHz Peregrine Semiconductor Corp. (R) http://www.psemi.com Copyright (c) Peregrine Semiconductor Corp. 2005 Page 7 of 12 PE4269 Product Specification Electrical Test and Performance Specifications Figure 15. Wafer on Film Frame PE4269 dice are 100% electrically tested for the parameters listed below from Table 1 and Table 4. All other parameters are guaranteed through design and characterization. * * * * * Insertion Loss (all ports) TX1 & TX2 Harmonics TX - RX Isolation IDD supply current Control pin leakages Wafer and Die Packaging Peregrine Semiconductor has two methods for shipping dice to our customers. The shipping option used is based on the customer's requirements and the number of dice. Peregrine offers product dice in two packaging options: Standard Die Carrier Packages (waffle pack) and dice on Film Frames. Figure 16. Dice and Wafer Processing Flow Wafer Processing 100% Electrical Test Wafer Singulation Dice Picking Process Control Monitor (PCM) Wafer Level Reliability (WLR) Ink Reject Die or Electronic Wafer Map 100% Visual Inspection Carrier Loading Backgrind and Polish Outgoing QA Inspection Visual Inspection Wafer Mount/Dicing In preparation for dicing, wafers are thinned and polished and 100% electrically probed prior to mounting on film frame tape and rings. Figure 15 shows a wafer mounted on film frame using PVC backed mounting tape. In preparation for shipment, wafers are visually inspected after singulation and shipped with an electronic map file providing good dice locations. Pack and Ship Wafers Pack and Ship Dice Figure 17. Waffle Pack Storage and Preservation Proper storage conditions are necessary to prevent product contamination and/or degradation after shipment. Product should be stored in the original unopened packaging or, once opened, in a nitrogen purged cabinet at room temperature (45% + 15% relative humidity controlled environment). Singulated wafers mounted on film frames are intended for immediate use and have a limited shelf life. This is primarily due to the nature of the adhesive tape used for mounting the product. This product can be stored up to 30 days. This applies whether or not the material has remained in its original sealed container. To reduce the risk of contamination or degradation, it is recommended that product not being used in the assembly process be returned to their original containers and resealed with a vacuum seal process. Copyright (c) Peregrine Semiconductor Corp. 2005 Page 8 of 12 Standard Die Carrier Package/Waffle Pack Waffle packs are available to customers during product development and prototyping phase only. Orders will move to film frames at production launch or for large quantity requirements. Dice have been 100% electrically probed, singulated, visually inspected and are packaged in a 2"x2" waffle pack (400 dice per waffle pack). File No. 70/0169-01A UltraCMOSTM RFIC Solutions PE4269 Product Specification Die Handling All die products must be handled only at ESD safe workstations using standard ESD precautions. It is recommended that the be handled only in a class 10,000 or better designated clean room environment. Singulated dice are not to be handled with tweezers. A vacuum wand with a non-metallic ESD protected tip must be used. Bonding Thermo compression gold ball or aluminum ultrasonic bonding may be used. The ball should cover the bonding pad, but not excessively, or it may short out the surrounding metallization. Aluminum or gold 0.8-mil wire is recommended. Note the bonding pad material is aluminum. Shipping Method Recommended Dice Assembly Procedure Cleaning Dice do not require cleaning prior to assembly. Die Attach Standard die carrier packages and wafer film frames are placed in a wafer container and then vacuumsealed inside an ESD shielded bag. Sealed product is then placed inside a corrugated cardboard box surrounded by bubble wrap or foam for maximum protection during shipment. The PE4269 die substrate is sapphire - the recommended die attach operation for sapphire is epoxy die attach adhesive. An eutectic die attach method does not work with sapphire substrates. Peregrine Semiconductor Corp. (R) http://www.psemi.com Copyright (c) Peregrine Semiconductor Corp. 2005 Page 9 of 12 PE4269 Product Specification Table 6. Mechanical Specifications Parameter Typical Minimum Maximum Units Test Conditions Die Size (x,y) 1.136 x 1.096 mm As drawn Die Size (x,y) 1.24 x 1.20 mm Including excess sapphire, max. tolerance = +0.1mm in either dimension Wafer Thickness 180 200 Wafer Size 220 150 m mm Table 7. Pad Coordinates All pad locations originate from the die center and refer to the center of the pad. All pad openings are 60 x 60 m except for Pad #3 which is 140 x 60 m. Minimum pad pitch is 80 m. Note 1. - Double pad, requires two bond wires. Pad # Pad Name 1 Pad Center (m) Figure 18. Pad Numbering X Y ANT -1.9 488.1 2 TX1 511.3 491.3 3 GND1 511.3 168.9 RX1 20 4 TX2 511.3 -153.5 GND 19 RX2 18 GND 17 RX3 16 GND 15 7 VDD 337.7 -491.3 ANT PE4269 Die 4 5 8 V3 -25.7 -491.3 RX4 14 9 GND -160.9 -491.3 GND 13 10 V2 -296.1 -491.3 11 V1 -376.1 -491.3 12 11 10 9 8 7 6 12 GND -511.3 -491.3 GND -491.3 VDD 511.3 V3 GND GND GND GND 6 3 V2 -233.5 TX1 V1 511.3 2 GND GND 1 13 GND -511.3 -223.7 14 RX4 -511.3 -105.1 15 GND -511.3 -25.1 16 RX3 -511.3 93.5 17 GND -511.3 173.5 18 RX2 -511.3 292.1 19 GND -511.3 372.1 20 RX1 -511.3 490.7 Copyright (c) Peregrine Semiconductor Corp. 2005 Page 10 of 12 TX2 GND 1.096mm 5 1.136mm File No. 70/0169-01A UltraCMOSTM RFIC Solutions PE4269 Product Specification ESD Protection Circuit Figure 19. ESD Protection Circuit Handset products must tolerate large ESD surges at the antenna interface without damage. The IEC 1000-4-2 standard specifies both 8 kV contact and 16 kV air discharges that typical handsets must survive. By itself, the PE4269 offers protection to 1.5 kV but with the addition of two inexpensive passive components, the switch can meet the levels as specified in the IEC spec. Figure 19 is the suggested solution for compliance with the IEC standards. PE4269 ESD Protection L = 27 nH (muRata: LQG1127NJ00), C = 33 pF (muRata: GRM33C0G330J50) Table 8. PE4269 Antenna Application Test Results (C=150 pF, R=330 , IEC 6100-4-2 Standard) Test Condition Results +8 kV contact discharge, 10 times with 1s intervals Pass -8 kV contact discharge, 10 times with 1s intervals Pass +16 kV air discharge, 10 times with 1s intervals Pass -16 kV air discharge, 10 times with 1s intervals Pass Table 9. Ordering Information Order Code Die ID Description Package Shipping Method 4269-90 C9798_1 PE4269-DIE-D Film Frame Wafer (Gross Die / Wafer Quantity) 4269-99 C9798_1 PE4269-DIE-400G Waffle Pack 400 Dice / Waffle Pack 4269-00 C9798_1 PE4269-DIE-1H Evaluation Kit 1/ box Peregrine Semiconductor Corp. (R) http://www.psemi.com Copyright (c) Peregrine Semiconductor Corp. 2005 Page 11 of 12 PE4269 Product Specification Sales Offices United States Japan Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 1-858-731-9400 Fax 1-858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 011-81-3-3502-5211 Fax: 011-81-3-3502-5213 Europe China Peregrine Semiconductor Europe Peregrine Semiconductor Batiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: 011- 33-1-47-41-91-73 Fax : 011-33-1-47-41-91-73 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: 011-86-21-5836-8276 Fax: 011-86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: http://www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright (c) 2005 Peregrine Semiconductor Corp. All rights reserved. Copyright (c) Peregrine Semiconductor Corp. 2005 Page 12 of 12 File No. 70/0169-01A UltraCMOSTM RFIC Solutions