2007 Microchip Technology Inc. Preliminary DS22040A-page 1
25AA010A/25LC010A 25AA320A/25LC320A
25AA020A/25LC020A 25AA640A/25LC640A
25AA040A/25LC040A 25AA128/25LC128
25AA080A/25LC080A 25AA256/25LC256
25AA080B/25LC080B 25AA512/25LC512
25AA160A/25LC160A 25AA1024/25LC1024
25AA160B/25LC160B
Features:
• Max Clock Speed
- 10 MHz (1K-256K)
- 20 MHz (512K-1M)
• Byte and Page-level Write Operations
• Low-power CMOS Technology
- Typical Write current: 5 mA
- Typical Read current: 5 mA @ 10 MHz
7 mA @ 20 MHz
- Typical Standby current: 1 A
• Write Cycle Time: 5 ms max.
6 ms max. (25XX1024)
• Self-timed Erase and Write Cycles
• Erase Functions (512K-1M)
- Page Erase: 6 ms max.
- Sector Erase: 15 ms max.
- Chip Erase: 15 ms max.
• Built-in Write Protection
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Block/Sector Write Protection
- Protect none, 1/4, 1/2 or all of array
• Sequential Read
• High Reliability
- Data retention: > 200 years
- ESD protection: > 4000V
- Endurance > 1M Erase/Write Cycles
• Available in Standard 8-pin and 6-pin Packages
• Temperature Ranges Supported:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Pin Function Table
Description:
Microchip Technology Inc. supports the Serial Periph-
eral Interface (SPI) compatible serial bus architecture
with low-voltage serial Electrically Erasable PROMs
(EEPROM) that range in density from 1 Kbits up to 1
Mbits. Byte-level and page-level functions are sup-
ported, but the higher density 512 Kbit and 1 Mbit
devices also feature Sector and Chip erase functions
typically associated with Flash-based products.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The entire series of SPI compatible devices are avail-
able in the standard 8-lead PDIP and SOIC pack-
ages, as well as the more advanced packages such
as the 8-lead TSSOP, MSOP, 2x3 DFN, 5x6 DFN and
6-lead SOT-23. All packages are RoHS compliant
with a Pb-free (Matte Tin) finish.
Pin Diagrams (not to scale)
Name Function
CS Chip Select
SO Serial Data Output
WP Write-Protect
VSS Ground
SI Serial Data Input
SCK Serial Clock Input
HOLD Hold Input
VCC Supply Voltage
DFN
CS
SO
WP
VSS
HOLD
SCK
SI
5
6
7
8
4
3
2
1VCC
(MF)
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
(P, SN, SM)
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
PDIP/SOIC
V
SS
1
2
34
6
5
V
DD
CS
SO
(OT)
SOT-23
SCK
SI
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
(MC)
DFN
TSSOP/MSOP
(ST, MS)
SPI Serial EEPROM Family Data Sheet
25AAXXXX/25LCXXXX
DS22040A-page 2 Preliminary 2007 Microchip Technology Inc.
DEVICE SELECTION TABLE
Part
Number
Density
(bits) Organization VCC
Range
Max Speed
(MHz)
Page Size
(Bytes)
Temp.
Range Packages
25LC010A 1K 128 x 8 2.5-5.5V 10 16 I, E P, MS, SN, ST, MC, OT
25AA010A 1K 128 x 8 1.8-5.5V 10 16 I P, MS, SN, ST, MC, OT
25LC020A 2K 256 x 8 2.5-5.5V 10 16 I, E P, MS, SN, ST, MC, OT
25AA020A 2K 256 x 8 1.8-5.5V 10 16 I P, MS, SN, ST, MC, OT
25LC040A 4K 512 x 8 2.5-5.5V 10 16 I, E P, MS, SN, ST, MC, OT
25AA040A 4K 512 x 8 1.8-5.5V 10 16 I P, MS, SN, ST, MC, OT
25LC080A 8K 1024 x 8 2.5-5.5V 10 16 I, E P, MS, SN, ST
25AA080A 8K 1024 x 8 1.8-5.5V 10 16 I P, MS, SN, ST
25LC080B 8K 1024 x 8 2.5-5.5V 10 32 I, E P, MS, SN, ST
25AA080B 8K 1024 x 8 1.8-5.5V 10 32 I P, MS, SN, ST
25LC160A 16K 2048 x 8 2.5-5.5V 10 16 I, E P, MS, SN, ST
25AA160A 16K 2048 x 8 1.8-5.5V 10 16 I P, MS, SN, ST
25LC160B 16K 2048 x 8 2.5-5.5V 10 32 I, E P, MS, SN, ST
25AA160B 16K 2048 x 8 1.8-5.5V 10 32 I P, MS, SN, ST
25LC320A 32K 4096 x 8 2.5-5.5V 10 32 I, E P, MS, SN, ST
25AA320A 32K 4096 x 8 1.8-5.5V 10 32 I P, MS, SN, ST
25LC640A 64K 8192 x 8 2.5-5.5V 10 32 I, E P, MS, SN, ST
25AA640A 64K 8192 x 8 1.8-5.5V 10 32 I P, MS, SN, ST
25LC128 128K 16,384 x 8 2.5-5.5V 10 64 I, E P, SN, SM, ST, MF
25AA128 128K 16,384 x 8 1.8-5.5V 10 64 I P, SN, SM, ST, MF
25LC256 256K 32,768 x 8 2.5-5.5V 10 64 I, E P, SN, SM, ST, MF
25AA256 256K 32,768 x 8 1.8-5.5V 10 64 I P, SN, SM, ST, MF
25LC512 512K 65,536 x 8 2.5-5.5V 20 128 I, E P, SM, MF
25AA512 512K 65,536 x 8 1.8-5.5V 20 128 I P, SM, MF
25LC1024 1024K 131,072 x 8 2.5-5.5V 20 256 I, E P, SM, MF
25AA1024 1024K 131,072 x 8 1.8-5.5V 20 256 I P, SM, MF
2007 Microchip Technology Inc. Preliminary DS22040A-page 3
25AAXXXX/25LCXXXX
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias.............................................................................................................-40°C to +125°C
ESD protection on all pins.......................................................................................................................................... 4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Note: This is an overview of AC and DC Characteristics. Please refer to the device data sheet for production
specs.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to
+85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to
125°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions Densities
D001 VIH High-level input voltage .7 VCC VCC + 1 V All
D002 VIL Low-level input voltage -0.3 0.3 VCC VVCC 2.7V (Note 1) All
D003 VIL -0.3 0.2 VCC VVCC 2.7V (Note 1) All
D004 VOL Low-level output voltage — 0.4 V IOL = 2.1 mA, VCC = 4.5V All
D005 VOL —0.2VIOL = 1.0 mA, VCC = 2.5V All
D006 VOH High-level output voltage VCC -0.5 — V IOH = -400 AAll
D007 ILI Input leakage current — ±1 ACS = VCC, VIN = VSS or VCC All
D008 ILO Output leakage current — ±1 ACS = VCC, VOUT = VSS or VCC All
D009 CINT Internal capacitance (all
inputs and outputs)
—7pFTA = 25°C, CLK = 1.0 MHZ,
VCC = 5.0V (NOTE 1)
All
D010 ICC
Read
Operating current
—10
5
mA VCC = 5.5V; FCLK = 20.0 MHz;
Vcc = 2.5V; FCLK = 10.0 MHz
512K and 1M
2.5
0.5
6
2.5
mA VCC = 5.5V; FCLK = 10.0 MHz;
Vcc = 2.5V; FCLK = 5.0 MHz
1K-256K
D011 ICC
WRITE
—7
5
mA VCC = 5.5V
Vcc = 2.5V
512K and 1M
0.16
0.15
5
3
mA VCC = 5.5V
VCC = 2.5V
1K-256K
D012 ICCS Standby current — 20
12
ACS = VCC = 5.5V, 125°C
CS = VCC = 5.5V, 85°C
(Inputs tied to VCC or VSS)
512K and 1M
—5
1
ACS
= VCC = 5.5V, 125°C
CS = VCC = 5.5V, 85°C
(Inputs tied to VCC or VSS)
1K-256K
D13 ICCSPD Deep power-down current — 1 ACS = VCC = 5.5V
(Inputs tied to VCC or VSS)
512K and 1M
Note 1: This parameter is periodically sampled and not 100% tested.
25AAXXXX/25LCXXXX
DS22040A-page 4 Preliminary 2007 Microchip Technology Inc.
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions Densities
1F
CLK Clock frequency —
—
—
20
10
2
MHz 4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
—
—
—
10
5
3
MHz 4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
2T
CSS CS setup time 25
50
250
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
50
100
150
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
3T
CSH CS hold time
(Note 3)
50
100
150
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
100
200
250
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
4T
CSD CS disable time 50 — ns 1K-256K
5TSU Data setup time 5
10
50
—ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
10
20
30
—ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
6THD Data hold time 10
20
100
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
20
40
50
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
7TRCLK rise time
(Note 1)
— 20 ns 512K and 1M
— 100 ns 128K and 256K
— 500 ns 8K and 16K
— 2000 ns 1K-4K, 32K-64K
8T
FCLK fall time
(Note 1)
— 20 ns 512K and 1M
— 100 ns 128K and 256K
— 500 ns 8K and 16K
— 2000 ns 1K-4K, 32K-64K
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but established by characterization and qualification. For
endurance estimates in a specific application, please consult the Total Endurance™
Model, which can be obtained from Microchip’s web site: www.microchip.com.
3: Includes THI time.
2007 Microchip Technology Inc. Preliminary DS22040A-page 5
25AAXXXX/25LCXXXX
9THI Clock high time 25
50
250
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
50
100
150
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
10 TLO Clock low time 25
50
250
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
50
100
150
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
11 TCLD Clock delay time 50 — ns All
12 TCLE Clock enable time 50 — ns All
13 TVOutput valid from
clock low
—25
50
250
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
—50
100
160
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
14 THO Output hold time
(Note 1)
0—ns
15 TDIS Output disable
time (Note 1)
—25
50
250
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
—40
80
160
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
16 THS HOLD setup time 10
20
100
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
20
40
80
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
17 THH HOLD Hold time 10
20
100
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
20
40
80
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions Densities
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but established by characterization and qualification. For
endurance estimates in a specific application, please consult the Total Endurance™
Model, which can be obtained from Microchip’s web site: www.microchip.com.
3: Includes THI time.
25AAXXXX/25LCXXXX
DS22040A-page 6 Preliminary 2007 Microchip Technology Inc.
18 THZ HOLD low to
output High-Z
(Note 1)
15
30
150
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
30
60
160
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
19 THV HOLD high to
output valid
15
30
150
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
512K and 1M
30
60
160
—
ns
ns
ns
4.5 VCC 5.5
2.5 VCC 4.5
1.8 VCC 2.5
1K-256K
20 TREL CS high to
Standby mode
—100s1.8V VCC 5.5V 512K and 1M
21 TPD CS high to Deep
power-down
—100s1.8V VCC 5.5V 512K and 1M
22 TCE Chip erase cycle
time
—15ms1.8V VCC 5.5V 512K and 1M
23 TSE Sector erase
cycle time
—15ms1.8V VCC 5.5V 512K and 1M
24 TWC Internal write
cycle time
— 6 ms Byte or Page mode and
Page Erase 512K and 1M
— 5 ms Byte or Page mode 1K-256K
25 — Endurance
(Note 2)
> 1M — E/W
Cycles
Per Pabe 512K and 1M
Per Byte 1K-256K
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions Densities
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but established by characterization and qualification. For
endurance estimates in a specific application, please consult the Total Endurance™
Model, which can be obtained from Microchip’s web site: www.microchip.com.
3: Includes THI time.
TABLE 1-3: AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V —
VHI = VCC - 0.2V (Note 1)
VHI = 4.0V (Note 2)
CL = 30 pF —
Timing Measurement Reference Level
Input
Output
0.5 VCC
0.5 VCC
Note 1: For VCC 4.0V.
2: For VCC > 4.0V.
2007 Microchip Technology Inc. Preliminary DS22040A-page 7
25AAXXXX/25LCXXXX
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
HOLD
17
16 16 17
19
18
Don’t Care 5
High-Impedance
n + 2 n + 1 n n - 1
n
n + 2 n + 1 n nn - 1
CS
SCK
SI
SO
65
8
711
3
LSB in
MSB in
High-Impedance
12
Mode 1,1
Mode 0,0
2
4
CS
SCK
SO
10
9
13
MSB out LSB out
3
15
Don’t Care
SI
Mode 1,1
Mode 0,0
14
25AAXXXX/25LCXXXX
DS22040A-page 8 Preliminary 2007 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 25-Series of Serial EEPROMs is designed to inter-
face directly with the Serial Peripheral Interface (SPI)
port of many of today's popular microcontroller families,
including Microchip's PIC® microcontrollers. It may
also interface with microcontrollers that do not have a
built-in SPI port by using discrete I/O lines programmed
properly in firmware to match the SPI protocol.
This family of EEPROMs contains an 8-bit instruction
register. The device is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The
CS pin must be low and the HOLD pin must be high for
the entire operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the EEPROM in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
Block Diagram
TABLE 2-1: INSTRUCTION SET
2.2 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the EEPROM
followed by the address. After the correct READ instruc-
tion and address are sent, the data stored in the mem-
ory at the selected address is shifted out on the SO pin.
The data stored in the memory at the next address can
be read sequentially by continuing to provide clock
pulses.
The internal Address Pointer is automatically incre-
mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached, the address counter rolls over to address
00000h, allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by raising the
CS pin. See Figure 2-1A/B/C for byte read.
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
Instruction Name Instruction Format Description
Instructions for all devices.
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WREN 0000 0110 Set the write enable latch (enable write operations)
WRDI 0000 0100 Reset the write enable latch (disable write operations)
RDSR 0000 0101 Read STATUS register
WRSR 0000 0001 Write STATUS register
Additional Instructions for 25XX512 and 25XX1024
PE 0100 0010 Page Erase – erase one page in memory array
SE 1101 1000 Sector Erase – erase one sector in memory array
CE 1100 0111 Chip Erase – erase all sectors in memory array
RDID 1010 1011 Release from Deep power-down and read electronic signature
DPD 1011 1001 Deep Power-Down mode
2007 Microchip Technology Inc. Preliminary DS22040A-page 9
25AAXXXX/25LCXXXX
TABLE 2-2: READ/WRITE SEQUENCE
ADDRESSING
FIGURE 2-1A: READ SEQUENCE WITH EITHER 8-BIT OR 9-BIT ADDRESSING
FIGURE 2-1B: READ SEQUENCE WITH 16-BIT ADDRESSING
Density Address
Bits
Highest
Address Page Size
1K 7 007F 16 Bytes
2K 8 00FF 16 Bytes
4K 9 01FF 16 Bytes
8K 10 03FF 16 or 32
Bytes*
16K 11 07FF 16 or 32
Bytes*
32K 12 0FFF 32 Bytes
64K 12 1FFF 32 Bytes
128K 14 3FFF 64 Bytes
256K 15 7FFF 64 Bytes
512K 16 FFFF 256 Bytes
1024K 17 1FFFF 256 Bytes
Note: Version A – 16 Bytes
Version B – 32 Bytes
SO
SI
SCK
CS
0 2345678910111
01A8*
00001A7A6A5A4A1A0
76543210
Data Out
High-Impedance
A3A2
Lower Address Byte
12 13 14 15 16 17 18 19 20 21 22 23
Instruction+Address MSb
* A8 is a don’t care for 1K and 2K upper address bit.
SO
SI
SCK
CS
0 234567891011 21222324252627282930311
01000001A15 A14 A13 A12 A2A1A0
76543210
Instruction 16-bit Address
Data Out
High-Impedance
25AAXXXX/25LCXXXX
DS22040A-page 10 Preliminary 2007 Microchip Technology Inc.
FIGURE 2-1C: READ SEQUENCE WITH 24-BIT ADDRESSING
2.3 Write Sequence
Prior to any attempt to write data to the EEPROM, the
write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
EEPROM. After all eight bits of the instruction are
transmitted, CS must be brought high to set the write
enable latch. If the write operation is initiated immedi-
ately after the WREN instruction without CS being
brought high, the data will not be written to the array
because the write enable latch will not have been
properly set.
A write sequence includes an automatic, self timed
erase cycle. It is not required to erase any portion of the
memory prior to issuing a Write command.
Once the Write Enable Latch is set, the user may pro-
ceed by setting CS low, issuing a WRITE instruction,
followed by the address and then the data to be written.
Depending upon the density, a page of data that ranges
from 16 bytes to 256 bytes can be sent to the device
before a write cycle is necessary. The only restriction is
that all of the bytes must reside in the same page. See
Table 2-2 for information on page sizes.
In the 24XX512 and 24XX1024 devices, the entire
page is always refreshed regardless of whether the
entire page is written. For this reason, endurance for
these devices is specified per page.
SO
SI
SCK
CS
0 234567891011 29303132333435363738391
01000001A23 A22 A21 A20 A2A1A0
76543210
Instruction 24-bit Address
Data Out
High-Impedance
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multi-
ples of the page buffer size (or ‘page
size’), and end at addresses that are inte-
ger multiples of page size – 1. If a Page
Write command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data previ-
ously stored there), instead of being writ-
ten to the next page as might be expected.
It is therefore necessary for the application
software to prevent page write operations
that would attempt to cross a page
boundary.
2007 Microchip Technology Inc. Preliminary DS22040A-page 11
25AAXXXX/25LCXXXX
For the data to be actually written to the array, CS must
be brought high after the Least Significant bit (D0) of
the nth data byte has been clocked in. If CS is brought
high at any other time, the write operation will not be
completed. Refer to Figure 2-2A/B/C and Figure 2-3A/
B/C/D for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register
may be read to check the status of the WIP and WEL
bits (Figure 2-6). A read attempt of a memory array
location will not be possible during a write cycle. When
the write cycle is completed, the write enable latch is
reset.
FIGURE 2-2A: BYTE WRITE SEQUENCE WITH EITHER 8-BIT OR 9-BIT ADDRESSING
FIGURE 2-2B: BYTE WRITE SEQUENCE WITH 16-BIT ADDRESSING
FIGURE 2-2C: BYTE WRITE SEQUENCE WITH 24-BIT ADDRESSING
SI
CS
91011
00A8*
00001 76543210
Data Byte
SCK
0 23456718
Instruction+Address MSb Lower Address Byte
A7A6A5A4A3A1A0
A2
12 13 14 15 16 17 18 19 20 21 22 23
Twc
SO High-Impedance
* Upper address bit A8 is a don’t care for 1K and 2K.
SO
SI
CS
9 1011 2122232425262728293031
00000001A15 A14 A13 A12 A2A1A076543210
Instruction 16-bit Address Data Byte
High-Impedance
SCK
0 23456718
Twc
SO
SI
CS
9 1011 2930313233343536373839
00000001A23 A22 A21 A20 A2A1A076543210
Instruction 24-bit Address Data Byte
High-Impedance
SCK
0 23456718
Twc
25AAXXXX/25LCXXXX
DS22040A-page 12 Preliminary 2007 Microchip Technology Inc.
FIGURE 2-3A: PAGE WRITE SEQUENCE WITH EITHER 8-BIT OR 9-BIT ADDRESSING
FIGURE 2-3B: PAGE WRITE SEQUENCE WITH 16-BIT ADDRESSING
SI
CS
91011
00
A8*
00001 76543210
Data Byte 1
SCK
0 23456718
SI
CS
33 34 35 38 39
76543210
Data Byte n (16 max)
SCK
24 26 27 28 29 30 3125 32
76543210
Data Byte 3
76543210
Data Byte 2
36 37
Instruction Address Byte
A7A6A5A4A3A1A0
A2
12 13 14 15 16 17 18 19 20 21 22 23
* Upper address bit A8 is a don’t care for 1K and 2K.
SI
CS
9 1011 2122232425262728293031
00000001A15 A14 A13 A12 A2A1A076543210
Instruction 16-bit Address Data Byte 1
SCK
0 23456718
SI
CS
41 42 43 46 47
76543210
Data Byte n (16/32 max)
SCK
32 34 35 36 37 38 3933 40
76543210
Data Byte 3
76543210
Data Byte 2
44 45
2007 Microchip Technology Inc. Preliminary DS22040A-page 13
25AAXXXX/25LCXXXX
FIGURE 2-3C: PAGE WRITE SEQUENCE WITH 24-BIT ADDRESSING
2.4 Write Enable (WREN) and Write
Disable (WRDI)
The EEPROM contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
•WRDI instruction successfully executed
•WRSR instruction successfully executed
•WRITE instruction successfully executed
•WP
pin is brought low (1K, 2K, 4K only)
Additional instructions available on 25XX512 and
25XX1024:
•PE instruction successfully executed
•SE instruction successfully executed
•CE instruction successfully executed
FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)
SI
CS
9 1011 2930313233343536373839
00000001A23 A22 A21 A20 A2A1A076543210
Instruction 24-bit Address Data Byte 1
SCK
0 23456718
SI
CS
49 50 51 54 55
76543210
Data Byte n (256 max)
SCK
40 42 43 44 45 46 4741 48
76543210
Data Byte 3
76543210
Data Byte 2
52 53
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 01
25AAXXXX/25LCXXXX
DS22040A-page 14 Preliminary 2007 Microchip Technology Inc.
FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)
2.5 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-3: STATUS REGISTER
The Write-In-Process (WIP) bit indicates whether the
EEPROM is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate which
blocks are currently write-protected. These bits are set
by the user issuing the WRSR instruction. These bits are
nonvolatile and are shown in Table 2-4. See Figure 2-6
for the RDSR timing sequence.
FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 01
0
76543210
W/R — — — W/R W/R R R
WPEN X X X BP1 BP0 WEL WIP
W/R = writable/readable. R = read-only.
Note: WPEN bit not available in 24XX010A,
24XX020A and 24XX040A devices.
SO
SI
CS
91011 12131415
11000000
7654 2 10
Instruction
Data from STATUS register
High-Impedance
SCK
0 23456718
3
2007 Microchip Technology Inc. Preliminary DS22040A-page 15
25AAXXXX/25LCXXXX
2.6 Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS reg-
ister as shown in Table 2-3. The user is able to select
one of four levels of protection for the array by writing
to the appropriate bits in the STATUS register. The
array is divided up into four segments. The user has the
ability to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
is shown in Table 2-4.
In EEPROM densities starting at 8 Kbits and higher, the
Write-Protect Enable (WPEN) bit is a nonvolatile bit
that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the pro-
grammable hardware write-protect feature. Hardware
write protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes
to nonvolatile bits in the STATUS register are disabled.
See Table 2-6 for a matrix of functionality on the WPEN
bit. See Figure 2-7 for the WRSR timing sequence.
TABLE 2-4: ARRAY PROTECTION
TABLE 2-5: ARRAY PROTECTED ADDRESS LOCATIONS
FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
BP1 BP0 Array Addresses Write-Protected Array Addresses Unprotected
00 none All (Sectors 0, 1, 2 and 3)
01 Upper 1/4 (Sector 3) Lower 3/4 (Sectors 0, 1 and 2)
10Upper 1/2 (Sectors 2 and 3) Lower 1/2 (Sectors 0 and 1)
11All (Sectors 0, 1, 2 and 3) none
Density Upper 1/4
(Sector 3)
Upper 1/2
(Sectors 2 and 3) All Sectors
1K 60h-7Fh 40h-7Fh 00h-7Fh
2K C0h-FFh 80h-FFh 00h-FFh
4K 180h-1FFh 100h-1FFh 000h-1FFh
8K 300h-3FFh 200h-3FFh 000h-3FFh
16K 600h-7FFh 400h-7FFh 000h-7FFh
32K C00h-FFFh 800h-FFFh 000h-FFFh
64K 1800h-1FFFh 1000h-1FFFh 0000h-1FFFh
128K 3000h-3FFFh 2000h-3FFFh 0000h-3FFFh
256K 6000h-7FFFh 4000h-7FFFh 0000h-7FFFh
512K C000h-FFFFh 8000h-FFFFh 0000h-FFFFh
1024K 18000h-1FFFFh 10000h-1FFFFh 00000h-1FFFFh
SO
SI
CS
91011 12131415
01000000
7654 210
Instruction Data to STATUS register
High-Impedance
SCK
0 23456718
3
25AAXXXX/25LCXXXX
DS22040A-page 16 Preliminary 2007 Microchip Technology Inc.
2.7 Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
•CS
must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
2.8 Power-On State
The Serial EEPROM powers on in the following state:
• The device is in low-power Standby mode (CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active State
TABLE 2-6: WRITE-PROTECT FUNCTIONALITY MATRIX
2.9 Page Erase
The Page Erase is a typical Flash function that has
been implemented only on the 512 Kbit and 1024 Kbit
Serial EEPROMs. This function is used to erase all bits
(FFh) inside a given page. A Write Enable (WREN)
instruction must be given prior to attempting a Page
Erase. This is done by setting CS low and then clocking
out the proper instruction into the EEPROM. After all
eight bits of the instruction are transmitted, the CS must
be brought high to set the write enable latch.
The Page Erase function is entered by driving CS low,
followed by the instruction code (Figure 2-8A/B) and
two or three address bytes. Any address inside the
page to be erased is a valid address.
CS must then be driven high after the last bit if the
address or the Page Erase will not execute. Once the
CS is driven high, the self-timed Page Erase cycle is
started. The WIP bit in the STATUS register can be
read to determine when the Page Erase cycle is
complete.
If a Page Erase function is given to an address that has
been protected by the Block Protect bits (BP0, BP1)
then the sequence will be aborted and no erase will
occur.
FIGURE 2-8A: PAGE ERASE SEQUENCE WITH 24-BIT ADDRESSING
WEL (SR bit 1) WPEN (SR bit 7) * WP (pin 3) Protected
Blocks
Unprotected
Blocks STATUS Register
0XXProtected Protected Protected
10XProtected Writable Writable
110 (low) Protected Writable Protected
111 (high) Protected Writable Writable
X = Don’t Care
* = WPEN bit is not available on 24XX010A/020A/040A.
SO
SI
SCK
CS
0 234567891011 2930311
00000101A23 A22 A21 A20 A2A1A0
Instruction 24-bit Address
High-Impedance
2007 Microchip Technology Inc. Preliminary DS22040A-page 17
25AAXXXX/25LCXXXX
FIGURE 2-8B: PAGE ERASE SEQUENCE WITH 16-BIT ADDRESSING
2.10 Sector Erase
The Sector Erase is a typical Flash function that has
been implemented only on the 512 Kbit and 1024 Kbit
Serial EEPROMs. This function is used to erase all bits
(FFh) inside a given sector. A Write Enable (WREN)
instruction must be given prior to attempting a Sector
Erase. This is done by setting CS low and then clocking
out the proper instruction into the EEPROM. After all
eight bits of the instruction are transmitted, the CS must
be brought high to set the write enable latch.
The Sector Erase function is entered by driving CS low,
followed by the instruction code (Figure 2-9A/B), and
two or three address bytes. Any address inside the
sector to be erased is a valid address.
CS must then be driven high after the last bit if the
address or the Sector Erase will not execute. Once the
CS is driven high, the self-timed Sector Erase cycle is
started. The WIP bit in the STATUS register can be
read to determine when the Sector Erase cycle is
complete.
If a SECTOR ERASE instruction is given to an address
that has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
See Table 2-2 and Table 2-3 for Sector Addressing.
FIGURE 2-9A: SECTOR ERASE SEQUENCE WITH 24-BIT ADDRESSING
SO
SI
SCK
CS
0 234567891011 2122231
00000101A15 A14 A13 A12 A2A1A0
Instruction 16-bit Address
High-Impedance
SO
SI
SCK
CS
0 234567891011 2930311
00110110A23 A22 A21 A20 A2A1A0
Instruction 24-bit Address
High-Impedance
25AAXXXX/25LCXXXX
DS22040A-page 18 Preliminary 2007 Microchip Technology Inc.
FIGURE 2-9B: SECTOR ERASE SEQUENCE WITH 16-BIT ADDRESSING
2.11 Chip Erase
The Chip Erase function will erase all bits (FFh) in the
array. A Write Enable (WREN) instruction must be given
prior to executing a Chip Erase. This is done by setting
CS low and then clocking out the proper instruction into
the EEPROM. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. The Chip Erase function is entered
by driving the CS low, followed by the instruction code
(Figure 2-10) onto the SI line.
The CS pin must be driven high after the eighth bit of
the instruction code has been given or the Chip Erase
function will not be executed. Once the CS pin is driven
high, the self-timed Chip Erase function begins. While
the device is executing the Chip Erase function the WIP
bit in the STATUS register can be read to determine
when the Chip Erase function is complete. The Chip
Erase function is ignored if either of the Block Protect
bits (BP0, BP1) are not ‘0’, meaning ¼, ½, or all of the
array is protected.
FIGURE 2-10: CHIP ERASE SEQUENCE
2.12 Deep Power-Down Mode
Deep Power-Down mode is available on the high-density
25XX512 and 25XX1024 Serial EEPROMs and is the
lowest power consumption state for these devices. While
in the Deep Power-Down mode, these devices will not
respond to any of the Read or Write commands, and
therefore it can be used as an additional software write
protection feature.
The Deep Power-Down mode is entered by driving CS
low, followed by the instruction code (Figure 2-11) onto
the SI line, followed by driving CS high.
If the CS pin is not driven high after the eighth bit of the
instruction code has been given, the device will not
execute Deep power-down. Once the CS line is driven
high, there is a delay (TDP) before the current settles to
its lowest consumption.
All instructions given during Deep Power-Down mode
are ignored except the Read Electronic Signature
Command (RDID). The RDID command will release
the device from Deep power-down and outputs the
electronic signature on the SO pin, and then returns the
device to Standby mode after delay (TREL).
SO
SI
SCK
CS
0 234567891011 2122231
00110110A15 A14 A13 A12 A2A1A0
Instruction 16-bit Address
High-Impedance
SCK
0 2345671
SI
High-Impedance
SO
CS
111000 11
2007 Microchip Technology Inc. Preliminary DS22040A-page 19
25AAXXXX/25LCXXXX
Deep Power-Down mode automatically releases at
device power-down. Once power is restored to the
device, it will power-up in the Standby mode.
FIGURE 2-11: DEEP POWER-DOWN SEQUENCE
SCK
0 2345671
SI
High-Impedance
SO
CS
100111 10
25AAXXXX/25LCXXXX
DS22040A-page 20 Preliminary 2007 Microchip Technology Inc.
2.13 Release from Deep Power-Down
and Read Electronic Signature
Once a device has entered Deep Power-Down mode
all instructions are ignored except the Release from
Deep Power-down and Read Electronic Signature
command. This command can also be used when the
device is not in Deep Power-down, to read the
electronic signature out on the SO pin unless another
command is being executed such as Erase, Program
or Write STATUS register.
Release from Deep Power-Down mode and Read
Electronic Signature is entered by driving CS low,
followed by the RDID instruction code (Figure 2-12A/
B).Then a dummy address of 24 bits (A23-A0) for the
25XX1024 and 16 bits (A15-A0) for the 25XX512 can
be sent. After the last bit of the dummy address is
clocked in, the 8-bit Electronic signature is clocked out
on the SO pin. After the signature has been read out at
least once, the sequence can be terminated by driving
CS high. The device will then return to Standby mode
and will wait to be selected so it can be given new
instructions. If additional clock cycles are sent after the
electronic signature has been read once, it will continue
to output the signature on the SO line until the
sequence is terminated.
FIGURE 2-12A: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE
(24-BITS)
FIGURE 2-12B: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE
(16-BITS)
Driving CS high after the 8-bit RDID command, but
before the Electronic Signature has been transmitted,
will still ensure the device will be taken out of Deep
Power-Down mode. However, there is a delay TREL
that occurs before the device returns to Standby mode
(ICCS), as shown in Figure 2-13.
SO
SI
SCK
CS
0 234567891011 29303132333435363738391
01101011A23 A22 A21 A20 A2A1A0
76543210
Instruction 24-bit Address
Electronic Signature Out
High-Impedance
0 1010010
Manufacturers ID 0x29
TREL
SO
SI
SCK
CS
0 234567891011 21222324252627282830311
01101011A15 A14 A13 A12 A2A1A0
76543210
Instruction 16-bit Address
Electronic Signature Out
High-Impedance
0 1010010
Manufacturers ID 0x29
TREL
2007 Microchip Technology Inc. Preliminary DS22040A-page 21
25AAXXXX/25LCXXXX
FIGURE 2-13: RELEASE FROM DEEP POWER-DOWN
SO
SI
SCK
CS
0 2345671
01101011
Instruction
High-Impedance
TREL
25AAXXXX/25LCXXXX
DS22040A-page 22 Preliminary 2007 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already initi-
ated or in progress will be completed, regardless of the
CS input signal. If CS is brought high during a program
cycle, the device will go into Standby mode as soon as
the programming cycle is complete. When the device is
deselected, SO goes to the high-impedance state,
allowing multiple parts to share the same SPI bus. A
low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
3.2 Serial Output (SO)
The SO pin is used to transfer data out of the
EEPROM. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
3.3 Write-Protect (WP)
The WP pin is a hardware write-protect input pin. In the
lower densities of 4 Kbits and below, a logic low on this
pin will reset the write enable latch and programming
will be inhibited. However, if a write cycle is already in
progress, WP going low will not change or disable the
write cycle. See Table 2-4 for the Write-Protect
Functionality Matrix.
In densities of 8 Kbits and higher the WP pin is used in
conjunction with the WPEN bit in the STATUS register
to prohibit writes to the nonvolatile bits in the STATUS
register. When WP is low and WPEN is high, writing to
the nonvolatile bits in the STATUS register are dis-
abled. All other operations will function normally. When
WP is set to a logic high, all functions, including writes
to the nonvolatile bits in the STATUS register will oper-
ate normally. If the WPEN bit is set, a logic low on the
WP pin during a STATUS register write sequence will
disable writing to the STATUS register. If an internal
write cycle has already begun, WP going low will have
no effect on the write in progress.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the EEPROM in a system with WP pin grounded
and still be able to write to the STATUS register. The
WP pin functions will be enabled when the WPEN bit is
set to a logic high.
3.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock
3.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the EEPROM. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
EEPROM while in the middle of a serial sequence with-
out having to retransmit the entire sequence again. It
must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The EEPROM must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial commu-
nication will not resume. Pulling the HOLD line low at
any time will tri-state the SO line.
Name Pin Number Function
CS 1 Chip Select Input
SO 2 Serial Data Output
WP 3 Write-Protect Pin
VSS 4 Ground
SI 5 Serial Data Input
SCK 6 Serial Clock Input
HOLD 7 Hold Input
VCC 8 Supply voltage
2007 Microchip Technology Inc. Preliminary DS22040A-page 23
25AAXXXX/25LCXXXX
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
XXXXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
I/P 1L7
25LC080A
0628
Example: Pb-Free
3
e
8-Lead PDIP Package Marking (Pb-Free)
Device Line 1 Marking Device Line 1 Marking
25AA010A 25AA010A 25LC010A 25LC010A
25AA020A 25AA020A 25LC020A 25LC020A
25AA040A 25AA040A 25LC040A 25LC040A
25AA080A 25AA080A 25LC080A 25LC080A
25AA080B 25AA080B 25LC080B 25LC080B
25AA160A 25AA160A 25LC160A 25LC160A
25AA160B 25AA160B 25LC160B 25LC160B
25AA320A 25AA320A 25LC320A 25LC320A
25AA640A 25AA640A 25LC640A 25LC640A
25AA128 25AA128 25LC128 25LC128
25AA256 25AA256 25LC256 25LC256
25AA512 25AA512 25LC512 25LC512
25AA1024 25AA1024 25LC1024 25LC1024
Note: T = Temperature Grade (I, E).
Legend: XX...X Part number or part number code
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
25AAXXXX/25LCXXXX
DS22040A-page 24 Preliminary 2007 Microchip Technology Inc.
XXXXYYWW
XXXXXXXT
NNN
8-Lead SOIC
SN 0628
25L080AI
1L7
Example: Pb-Free
3
e
8-Lead SOIC Package Marking (Pb-Free)
Device Line 1 Marking Device Line 1 Marking
25AA010A 25AA01AT 25LC010A 25LC01AT
25AA020A 25AA02AT 25LC020A 25LC02AT
25AA040A 25AA04AT 25LC040A 25LC04AT
25AA080A 25A080AT 25LC080A 25L080AT
25AA080B 25A080BT 25LC080B 25L080BT
25AA160A 25A160AT 25LC160A 25L160AT
25AA160B 25A160BT 25LC160B 25L160BT
25AA320A 25AA32AT 25LC320A 25LC32AT
25AA640A 25AA64AT 25LC640A 25LC64AT
25AA128
(also available in SM)
25AA128T 25LC128 25LC128T
25AA256
(also available in SM)
25AA256T 25LC256 25LC256T
25AA512
(also available in SM)
25AA512T 25LC512 25LC512T
25AA1024
(available only in SM - not
available in SN)
25AA1024 25LC1024 25LC1024
Note: T = Temperature Grade (I, E).
Legend: XX...X Part number or part number code
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
2007 Microchip Technology Inc. Preliminary DS22040A-page 25
25AAXXXX/25LCXXXX
8-Lead TSSOP Package Marking (Pb-Free)
Device Line 1 Marking Device Line 1 Marking
25AA010A 5A1A 25LC010A 5L1A
25AA020A 5A2A 25LC020A 5L2A
25AA040A 5A4A 25LC040A 5L4A
25AA080A 5A8A 25LC080A 5L8A
25AA080B 5A8B 25LC080B 5L8B
25AA160A 5AAA 25LC160A 5LAA
25AA160B 5AAB 25LC160B 5LAB
25AA320A 5ABA 25LC320A 5LBA
25AA640A 5ACA 25LC640A 5LCA
25AA128 5AD 25LC128 5LD
25AA256 5AE 25LC256 5LE
Note: T = Temperature Grade (I, E).
NNN
XXXX
TYWW
8-Lead TSSOP
1L7
5L8A
I628
Example: Pb-Free
Legend: XX...X Part number or part number code
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
25AAXXXX/25LCXXXX
DS22040A-page 26 Preliminary 2007 Microchip Technology Inc.
8-Lead MSOP Package Marking (Pb-Free)
Device Line 1 Marking Device Line 1 Marking
25AA010A 5A1AT 25LC010A 5L1AT
25AA020A 5A2AT 25LC020A 5L2AT
25AA040A 5A4AT 25LC040A 5L4AT
25AA080A 5A8AT 25LC080A 5L8AT
25AA080B 5A8BT 25LC080B 5L8BT
25AA160A 5AAAT 25LC160A 5LAAT
25AA160B 5AABT 25LC160B 5LABT
25AA320A 5ABAT 25LC320A 5LBAT
25AA640A 5ACAT 25LC640A 5LCAT
Note: T = Temperature Grade (I, E).
8-Lead MSOP Example: Pb-Free
XXXXXXT
YWWNNN
5L8AI
6281L7
Legend: XX...X Part number or part number code
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
2007 Microchip Technology Inc. Preliminary DS22040A-page 27
25AAXXXX/25LCXXXX
8-Lead SOT-23 Package Marking (Pb-Free)
Device I-Temp Marking Device I-Temp Marking E-Temp Marking
25AA010A 12NN 25LC010A 15NN 16NN
25AA020A 22NN 25LC020A 25NN 26NN
25AA040A 32NN 25LC040A 35NN 36NN
Example: Pb-Free
6-Lead SOT-23
XXNN 32L7
Legend: XX...X Part number or part number code
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
25AAXXXX/25LCXXXX
DS22040A-page 28 Preliminary 2007 Microchip Technology Inc.
8-Lead 2x3 DFN Package Marking (Pb-Free)
Device I-Temp Marking Device I-Temp Marking E-Temp Marking
25AA010A 401 25LC010A 404 405
25AA020A 411 25LC020A 414 415
25AA040A 421 25LC040A 424 425
Note: NN = Alphanumeric Traceability Code.
8-Lead 2x3 DFN Example: Pb-Free
421
627
L7
XXX
YWW
NN
Legend: XX...X Part number or part number code
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
2007 Microchip Technology Inc. Preliminary DS22040A-page 29
25AAXXXX/25LCXXXX
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A 1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 . 365 .400
Ti p to Seating Plane L . 115 .130 . 150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
N
E1
NOTE 1
D
12
3
A
A1
A2
L
b1
b
e
E
eB
c
Microchip Technology Drawing C04-018
B
25AAXXXX/25LCXXXX
DS22040A-page 30 Preliminary 2007 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN ) – Narrow, 3.90 mm Body [SOIC]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff
§
A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E 1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ0° – 8°
Lead Thickness c 0.17 – 0.25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α5° – 15°
Mold Draft Angle Bottom β5° – 15°
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
Microchip Technology Drawing C04-057
B
2007 Microchip Technology Inc. Preliminary DS22040A-page 31
25AAXXXX/25LCXXXX
8-Lead Plastic Small Outline (SM) – Medium, 5.28 mm Body [SOIJ]
Notes:
1. SOIJ, JEITA/EIAJ Standard, formerly called SOIC.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 1.77 – 2.03
Molded Package Thickness A2 1.75 – 1.98
Standoff § A1 0.05 – 0.25
Overall Width E 7.62 – 8.26
Molded Package Width E1 5.11 – 5.38
Overall Length D 5.13 – 5.33
Foot Length L 0.51 – 0.76
Foot Angle φ0° – 8°
Lead Thickness c 0.15 – 0.25
Lead Width b 0.36 – 0.51
Mold Draft Angle Top α– – 15°
Mold Draft Angle Bottom β– – 15°
φ
β
α
L
c
A2
A1
A
b
12
e
E
E1
N
D
Microchip Technology Drawing C04-056B
25AAXXXX/25LCXXXX
DS22040A-page 32 Preliminary 2007 Microchip Technology Inc.
8-Lead Plastic Thin Shri nk Small Outline (ST) – 4.4 mm Body [TSSOP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.65 BS C
Overall Height A – – 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 – 0.15
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 2.90 3.00 3.10
Foot Length L 0.45 0.60 0. 75
Footprint L1 1.00 REF
Foot Angle φ0° – 8°
Lead Thickness c 0.09 – 0.20
Lead Width b 0.19 – 0.30
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
Microchip Technology Drawing C04-086
B
2007 Microchip Technology Inc. Preliminary DS22040A-page 33
25AAXXXX/25LCXXXX
8-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.65 BS C
Overall Height A – – 1.10
Molded Package Thickness A2 0.75 0.85 0.95
Standoff A1 0.00 – 0.15
Overall Width E 4.90 BSC
Molded Package Width E1 3.00 BSC
Overall Length D 3.00 BSC
Foot Length L 0.40 0.60 0. 80
Footprint L1 0.95 REF
Foot Angle φ0° – 8°
Lead Thickness c 0.08 – 0.23
Lead Width b 0.22 – 0.40
D
N
E
E1
NOTE 1
12
e
b
A
A1
A2
c
L1 L
φ
Microchip Technology Drawing C04-111
B
25AAXXXX/25LCXXXX
DS22040A-page 34 Preliminary 2007 Microchip Technology Inc.
6-Lead Plastic Small Outline Transistor (OT) [SOT-23]
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM M AX
Number of Pins N 6
Pitch e 0.95 BSC
Outside Lead Pitch e1 1.90 BSC
Overall Height A 0.90 – 1.45
Molded Package Thickness A2 0. 89 – 1 .30
Standoff A1 0.00 – 0.15
Overall Width E 2.20 – 3.20
Molded Package Width E1 1.30 – 1.80
Overall Length D 2.70 – 3.10
Foot Length L 0.10 – 0.60
Footprint L1 0.35 – 0.80
Foot Angle φ0° – 30°
Lead Thickness c 0.08 – 0.26
Lead Width b 0.20 – 0.51
b
E
4
N
E1
PIN 1 ID BY
LASER MARK
D
123
e
e1
A
A1
A2 c
L
L1
φ
Microchip Technology Drawing C04-028
B
2007 Microchip Technology Inc. Preliminary DS22040A-page 35
25AAXXXX/25LCXXXX
8-Lead Plastic Dual Fla t, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for in form ation purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.50 BSC
Overall Height A 0.80 0 .90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Length D 2.00 BSC
Overall Width E 3.00 BSC
Exposed Pad Length D2 1.30 – 1.75
Exposed Pad Width E 2 1.50 – 1. 90
Contact Width b 0.18 0.25 0.30
Contact Length L 0.30 0.40 0.50
Contact-to-Exposed Pad K 0.20 – –
D
N
E
NOTE 1
12
EXPOSED PAD
NOTE 1
21
D2
K
L
E2
N
e
b
A3A1
A
NOTE 2
BOTTOM VIEW
TOP VIEW
Microchip Technology Drawing C04-123
B
25AAXXXX/25LCXXXX
DS22040A-page 36 Preliminary 2007 Microchip Technology Inc.
8-Lead Plastic Dual Fla t, No Lead Package (MF) – 6x5 mm Body [DFN-S]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for in form ation purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 0.80 0 .85 1.00
Standoff A1 0.00 0.01 0.05
Contact Thickness A3 0.20 REF
Overall Length D 5.00 BSC
Overall Width E 6.00 BSC
Exposed Pad Length D2 3.90 4.00 4.10
Exposed Pad Width E 2 2.20 2.30 2.40
Contact Width b 0.35 0.40 0.48
Contact Length L 0.50 0.60 0.75
Contact-to-Exposed Pad K 0.20 – –
NOTE 2
A1
A
A3
NOTE 1 12
E
N
D
EXPOSED PAD
NOTE 1
21
E2
L
N
e
b
K
BOTTOM VIEW
TOP VIEW
D2
Microchip Technology Drawing C04-122
B
2007 Microchip Technology Inc. Preliminary DS22040A-page 37
25AAXXXX/25LCXXXX
APPENDIX A: REVISION HISTORY
Revision A (05/2007)
Original release of document.
(Package Drawings Rev. AP)
25AAXXXX/25LCXXXX
DS22040A-page 38 Preliminary 2007 Microchip Technology Inc.
NOTES:
2007 Microchip Technology Inc. Preliminary DS22040A-page 39
25AAXXXX/25LCXXXX
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
25AAXXXX/25LCXXXX
DS22040A-page 40 Preliminary 2007 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS22040A25AAXXXX/25LCXXXX
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2007 Microchip Technology Inc. Preliminary DS22040A-page 41
25AAXXXX/25LCXXXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X/XX
PackageTemperature
Range
Device Part
Examples:
a) 25AA010A-I/SN: 1K
b) 25AA040A-I/MS: 4K
c) 25LC040AT-I/OT: 4K
d) 25LC1024-I/SM: 1M
Device: EEPROM Series – 25
Voltage – AA = 1.8V-5.5V
LC = 2.5V-5.5V
Density: 010A = 1 Kbit
020A = 2 Kbit
040A = 4 Kbit
080A = 8 Kbit
080B = 8 Kbit
160A = 16 Kbit
160B = 16 Kbit
320A = 32 Kbit
640A = 64 Kbit
128 = 128 Kbit
256 = 256 Kbit
512 = 512 Kbit
1024 = 1024 Kbit (1Mbit)
Temperature
Range:
I = -40°C to +85°C
E = -40°C to +125°C
Packaging
Medium:
T = Tape and Reel
Blank = Std. Pkg.
Package: P = 8-lead Plastic DIP (300 mil body)
SN = 8-lead Plastic SOIC (3.90 mm body)
SM = 8-lead Plastic SOIC (5.28 mm body)
ST = 8-lead Plastic TSSOP (4.4 mm)
MS = 8-lead Plastic Micro Small Outline (MSOP)
MC = 8-lead 2x3 mm DFN
MF = 8-lead 6x5 mm DFN
OT = 6-lead SOT-23
Number
X
Packaging
Medium
25AAXXXX/25LCXXXX
DS22040A-page 42 Preliminary 2007 Microchip Technology Inc.
NOTES:
2007 Microchip Technology Inc. Preliminary DS22040A-page 43
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS22040A-page 44 Preliminary 2007 Microchip Technology Inc.
AMERICAS
Corporate Office
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Fax: 480-792-7277
Technical Support:
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Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
12/08/06
