TC74LCX16374AFT
2007-10-19
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74LCX16374AFT
Low-Voltage 16-Bit D-Type Flip-Flop with 5-V Tolerant Inputs and Outputs
The TC74LCX16374AFT is a high-performance CMOS 16-bit
D-type flip-flop. Designed for use in 3.3-V systems, it achieves
high-speed operation while maintaining the CMOS low power
dissipation.
The device is designed for low-voltage (3.3 V) VCC applications,
but it could be used to interface to 5-V supply environment for
both inputs and outputs.
This 16-bit D-type flip-flop is controlled by a clock input (CK)
and an output enable input ( OE ) which are common to each byte.
It can be used as two 8-bit flip-flops or one 16-bit flip-flop. When
the OE input is high, the outputs are in a high-impedance state.
All inputs are equipped with protection circuits against static
discharge.
Features
• Low-voltage operation: VCC = 2.0 to 3.6 V
• High-speed operation: tpd = 7.0 ns (max) (VCC = 3.0 to 3.6 V)
• Ouput current: |IOH|/IOL = 24 mA (min) (VCC = 3.0 V)
• Latch-up performance: −500 mA
• Package: TSSOP
• Power-down protection provided on all inputs and outputs
Weight: 0.25 g (typ.)
TC74LCX16374AFT
2007-10-19
2
Pin Assignment (top view) IEC Logic Symbol
1CK 48
1D1
1D2
GND
47
46
45
44
43
42
OE1 1
2
3
4
5
6
7
GND
1Q3
1Q4
VCC
1Q5
1Q6
1D3
8
9
10
1D5
1D6
GND
41
40
39
1D4
VCC
GND
1Q1
1Q2
1D7
38
1D8
2D1
2D2
37
36
35
34
33
32
1Q7 11
12
13
14
15
16
17
2Q2
GND
2Q3
2Q4
VCC
2Q5
GND
18
19
20
VCC
2D5
2Q6
31
30
29
2D3
2D4
2D6
1Q8
2Q1
28 21
GND
2Q7
2Q8
22
23
24
2D7
2D8
OE2
27
26
25
GND
2CK
48
1
25
24
47
44
46
OE1
1D1 1D 1
1D3
1D2
41
43
38
40
36
37
33
35
1D5
1D4
1D7
1D6
2D1
1D8
2D3
2D2
30
32
27
29
26
2D5
2D4
2D7
2D6
2D8
2
5
8
11
1Q1
1Q3
1Q5
1Q7
3
6
9
1Q2
1Q4
1Q6
14
17
20
23
2Q2
2Q4
2Q6
2Q8
13
16
19
22
2Q1
2Q3
2Q5
2Q7
C1
1EN
2EN
C2
2D 2
12 1Q8
1CK
2CK
OE2
TC74LCX16374AFT
2007-10-19
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Truth Table
Inputs Outputs
OE1 1CK 1D1-1D8 1Q1-1Q8
H X X Z
L X Qn
L L L
L H H
Inputs Outputs
OE2 2CK 2D1-2D8 2Q1-2Q8
H X X Z
L X Qn
L L L
L H H
X: Don’t care
Z: High impedance
Qn: No change
System Diagram
1CK
OE1
1
48
47
2
CK Q
D
1Q1
1D1
3
Q
D
1Q2
1D2
5
Q
D
1Q3
1D3
6
Q
D
1Q4
1D4
8
Q
D
1Q5
1D5
9
Q
D
1Q6
1D6
11
Q
D
1Q7
1D7
12
Q
D
1Q8
1D8
46 44 43 41 40 38 37
2CK
OE2
25
36
13
Q
D
2Q1
2D1
14
Q
D
2Q2
2D2
16
Q
D
2Q3
2D3
17
Q
D
2Q4
2D4
19
Q
D
2Q5
2D5
20
Q
D
2Q6
2D6
22
Q
D
2Q7
2D7
23
Q
D
2Q8
2D8
35 33 32 30 29 27 26
24
CK CK CK CK CK CK CK
CK CK CK CK CK CK CK CK
TC74LCX16374AFT
2007-10-19
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Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Power supply voltage VCC −0.5 to 7.0 V
Input voltage VIN −0.5 to 7.0 V
−0.5 to 7.0 (Note 2)
Output voltage VOUT −0.5 to VCC + 0.5
(Note 3)
V
Input diode current IIK −50 mA
Output diode current IOK ±50 (Note 4) mA
DC output current IOUT ±50 mA
Power dissipation PD 400 mW
DC VCC/ground current per supply pin ICC/IGND ±100 mA
Storage temperature Tstg −65 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: Output in OFF state
Note 3: High or low state. IOUT absolute maximum rating must be observed.
Note 4: VOUT < GND, VOUT > VCC
Operating Ranges (Note 1)
Characteristics Symbol Rating Unit
2.0 to 3.6
Power supply voltage VCC 1.5 to 3.6 (Note 2)
V
Input voltage VIN 0 to 5.5 V
0 to 5.5 (Note 3)
Output voltage VOUT 0 to VCC (Note 4)
V
±24 (Note 5)
Output current IOH/IOL
±12 (Note 6)
mA
Operating temperature Topr −40 to 85 °C
Input rise and fall time dt/dv 0 to 10 (Note 7) ns/V
Note 1: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Note 2: Data retention only
Note 3: Output in OFF state
Note 4: High or low state
Note 5: VCC = 3.0 to 3.6 V
Note 6: VCC = 2.7 to 3.0 V
Note 7: VIN = 0.8 to 2.0 V, VCC = 3.0 V
TC74LCX16374AFT
2007-10-19
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Electrical Characteristics
DC Characteristics (Ta = −40 to 85°C)
Characteristics Symbol Test Condition
VCC (V)
Min Max Unit
H-level VIH ⎯ 2.7 to 3.6 2.0 ⎯
Input voltage
L-level VIL ⎯ 2.7 to 3.6 ⎯ 0.8
V
IOH = −100 μA 2.7 to 3.6 VCC
− 0.2 ⎯
IOH = −12 mA 2.7 2.2 ⎯
IOH = −18 mA 3.0 2.4 ⎯
H-level VOH VIN = VIH or VIL
IOH = −24 mA 3.0 2.2 ⎯
IOL = 100 μA 2.7 to 3.6 ⎯ 0.2
IOL = 12 mA 2.7 ⎯ 0.4
IOL = 16 mA 3.0 ⎯ 0.4
Output voltage
L-level VOL V
IN = VIH or VIL
IOL = 24 mA 3.0 ⎯ 0.55
V
Input leakage current IIN VIN = 0 to 5.5 V 2.7 to 3.6 ⎯ ±5.0 μA
3-state output OFF state current IOZ VIN = VIH or VIL
VOUT = 0 to 5.5 V 2.7 to 3.6 ⎯ ±5.0 μA
Power-off leakage current IOFF V
IN/VOUT = 5.5 V 0 ⎯ 10.0 μA
VIN = VCC or GND 2.7 to 3.6 ⎯ 20.0
Quiescent supply current ICC
VIN/VOUT = 3.6 to 5.5 V 2.7 to 3.6 ⎯ ±20.0
Increase in Icc per input ΔICC V
IH = VCC − 0.6 V 2.7 to 3.6 ⎯ 500
μA
TC74LCX16374AFT
2007-10-19
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AC Characteristics (Ta = −40 to 85°C)
Characteristics Symbol Test Condition
VCC (V)
Min Max Unit
2.7 ⎯ ⎯
Maximum clock frequency fmax Figure 1, Figure 2
3.3 ± 0.3 170 ⎯
MHz
2.7 ⎯ 8.0 Propagation delay time
(CK-Q)
tpLH
tpHL Figure 1, Figure 2
3.3 ± 0.3 1.5 7.0
ns
2.7 ⎯ 8.2
3-state output enable time tpZL
tpZH Figure 1, Figure 3
3.3 ± 0.3 1.5 7.2
ns
2.7 ⎯ 8.2
3-state output disable time tpLZ
tpHZ Figure 1, Figure 3
3.3 ± 0.3 1.5 7.2
ns
2.7 4.0 ⎯ Minimum pulse width
(CK)
tw (H)
tw (L) Figure 1, Figure 2
3.3 ± 0.3 3.0 ⎯
ns
2.7 2.5 ⎯
Minimum setup time ts Figure 1, Figure 2
3.3 ± 0.3 2.5 ⎯
ns
2.7 1.5 ⎯
Minimum hold time th Figure 1, Figure 2
3.3 ± 0.3 1.5 ⎯
ns
2.7 ⎯ ⎯
Output to output skew tosLH
tosHL (Note)
3.3 ± 0.3 ⎯ 1.0
ns
Note: Parameter guaranteed by design.
(tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|)
Dynamic Switching Characteristics
(Ta = 25°C, input: tr = tf = 2.5 ns, CL = 50 pF, RL = 500 Ω)
Characteristics Symbol Test Condition
VCC (V)
Typ. Unit
Quiet output maximum
dynamic VOL VOLP V
IH = 3.3 V, VIL = 0 V 3.3 0.8 V
Quiet output minimum
dynamic VOL |VOLV| VIH = 3.3 V, VIL = 0 V 3.3 0.8 V
Capacitive Characteristics (Ta = 25°C)
Characteristics Symbol Test Condition
VCC (V)
Typ. Unit
Input capacitance CIN ⎯ 3.3 7 pF
Output capacitance COUT ⎯ 3.3 8 pF
Power dissipation capacitance CPD f
IN = 10 MHz (Note) 3.3 25 pF
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr) = CPD･VCC･fIN + ICC/16 (per bit)
TC74LCX16374AFT
2007-10-19
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AC Test Circuit
AC Waveform
Open
6.0 V
GND
Switch
Output Measure
RL = 500 Ω
CL = 50 pF
Parameter Switch
tpLH, tpHL Open
tpLZ, tpZL 6.0 V
tpHZ, tpZH GND
tw, ts, th, fmax Open
RL RL
CL
Figure 1
Figure 2 tpLH, tpHL, tw, ts, th
90%
1.5 V
10%
tr 2.5 ns
1.5 V
tf 2.5 ns
2.7 V
GND
90%
1.5 V
10%
ts (H) th (H) th (L)ts (L)
tw (H) tw (L)
Input
(CK)
2.7 V
GND
Input
(D)
tf 2.5 nstr 2.5 ns
Output
(Q)
VOH
VOL
tpLH tpHL
Figure 3 tpLZ, tpHZ, tpZL, tpZH
90%
10%
VOL
3.0 V
GND
2.7 V
1.5 V
tpHZ tpZH
tr 2.5 ns tf 2.5 ns
1.5 V
GND
VOH
Outputs
enabled
1.5 V
tpLZ tpZL
VOL
+ 0.3 V
VOH − 0.3 V
Outputs
disabled
Outputs
enabled
Output Enable
(OE )
Output (Q)
Low to Off to Low
Output (Q)
High to Off to High
TC74LCX16374AFT
2007-10-19
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Package Dimensions
Weight: 0.25 g (typ.)
TC74LCX16374AFT
2007-10-19
9
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