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FEATURES

Access time :55ns

Low powe r consumption:

Operating current:10 mA (TYP.)

Standby current: 1 µA (TYP.)

Fully Compatible with all Competitors 3.3V product

Fully static operation

Tri-state output

Data retention voltage : 1.5V (MIN.)

All products are ROHS Compliant

Package : 32-pin 450 mil SOP

32-pin 600 mil P-DIP

32-pin 8mm x 20mm TSOP-I

32-pin 8mm x 13.4mm sTSOP

36-ball 6mm x 8mm TFBGA

GENERA L DESCRIPTION

The AS6C1008 is a 1,048,57 6-bit low powe r

CMOS static random access memory organized as

131,072 words by 8 bits. Itis fabricated using very

high performance, high reliability

CMO S technolo gy. Its

standby current is stable within the ra nge of

operating temperature.

The AS6C1008 is well designed for very low power

system applications, a nd particularly well suited for

battery

back-up non-volatile memory a pplication.

The AS6C1008 operates from a single power supply

of 2.7V ~ 5.5V.

FUNCTIONAL BLOCK DIAGRAM

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

128Kx8

MEMORY ARRAY

COLUMN I/O

A0-A16

Vcc

Vss

DQ0-DQ7

CE#

WE#

OE#

CE2

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A16 Address Inputs

DQ0 – DQ7 Data Inputs/Outputs

CE#, CE2 Chip Enable Inputs

WE# Write Enable Input

OE# Output Enable Input

VCC Power Supply

VSS Ground

NC No Connection

Single 2.7V ~ 5.5V power supply

Fully Compatible with all Competitors 5V product

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 1 of 14

PIN CONFIGURATION

A12

DQ0

DQ1

DQ2

Vss

A14

Vcc

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

AS6C1008

SOP/P-DIP

1716

A13

CE#

OE#

WE#

A16

CE2

A15

TS OP -I/sTSOP

DQ3

A11

A13

DQ2

A10

A14

A12

Vc c

DQ7

DQ6

DQ5

DQ4

Vss

DQ1

DQ0

A4 A3

AS6C1008

1716

OE #

WE #

CE #

CE 2

A15

A16

TFBGA

OE#

WE#

31A11A 21A

CE2

A10 A14

A15

DQ5

DQ6

DQ7

Vss

A16

DQ4

Vcc

DQ3

Vss

DQ2

DQ1

DQ0

A6A1 A3

CN 5A

A4A2

1 2 3 4 5 6

CE#

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 2 of 14

ABSOLUTE MAXIMUM RATINGS*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS VTERM -0.5 to 7.0 V

0 to 70(C grade)

T erutarepmeT gnitarepO A

-40 to 85(I grade)

ºC

T erutarepmeT egarotS STG -65 to 150 ºC

P noitapissiD rewoP D 1 W

I tnerruC tuptuO CD OUT 50 mA

Soldering Temperature (under 10 sec) TSOLDER 260 ºC

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE CE# CE2 OE# WE# I/O OPERATION SUPPLY CURRENT

H X X X High-Z ISB1

Standby X L X X High-Z ISB1

Output Disable L H H H High-Z ICC,ICC1

Read L H L H DOUT ICC,ICC1

Write L H X L DIN ICC,ICC1

Note: H = VIH, L = VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION MIN. TYP. *4 MAX. UNIT

Supply Voltage VCC V 5.5 0.3 7.2

Input High Voltage VIH*1 V -ccV*7.0 CC+0.3 V

Input Low Voltage VIL*2 V 6.0 - 2.0 -

Input Leakage Current ILI VCC ≧ VIN ≧ VSS - 1 - 1 µA

Output Leakage

Current ILO VCC ≧ VOUT ≧ VSS,

Output Disabled - 1 - 1 µA

Output High Voltage VOH IOH V - 7.2 2.2 Am1- =

Output Low Voltage VOL IOL = 2mA - - 0.4 V

- 55 - 10 60 mA

ICC

Cycle time = Min.

CE# = VIL and CE2 = VIH,

II/O = 0mA

Average Operating

Power supply Current

ICC1

Cycle time = 1µs

CE#≦0.2V and CE2≧VCC-0.2V,

II/O = 0mA

other pins at 0.2V or VCC-0.2V

- 1 10 mA

C* - 1 20 µA

Standby Power

Supply Current ISB1 CE# V≧CC-0.2V

or CE2≦0.2V I* - 1 50 µA

*C=Commercial temperature/I= Industrial temperature

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 3 of 14

Notes:

1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.

2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.

3. Over/Undershoot specifications are characterized, not 100% tested.

4. Typical values are included for reference only and are not guaranteed or tested.

Typical valued are measured at VCC = VCC(TYP.) and TA= 25ºC

CAPACITANCE (TA= 25 , f℃= 1.0MHz)

PARAMETER SYMBOL MIN. MAX UNIT

CecnaticapaCtupnI IN -6 pF

Input/Output Capacitance CI/O -8 pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

VotV2.0sleveLesluPtupnI CC - 0.2V

sn3semiTllaFdnaesiRtupnI

Input and Output Timing Reference Levels 1.5V

CdaoLtuptuO L=30pF + 1TTL, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE AS6C1008-55

PARAMETER SYM. MIN. MAX. UNIT

Read Cycle Time tRC 55 - ns

Address Access Time tAA - 55 ns

Chip Enable Access Time tACE - 55 ns

Output Enable Access Time tOE - 30 ns

Chip Enable to Output in Low-Z tCLZ* 10 - ns

Output Enable to Output in Low-Z tOLZ* 5 - ns

Chip Disable to Output in High-Z tCHZ* - 20 ns

Output Disable to Output in High-Z tOHZ* - 20 ns

Output Hold from Address Change tOH 10 - ns

(2) WRITE CYCLE

PARAMETER SYM. MIN. MAX. UNIT

Write Cycle Time tWC 55 - ns

Address Valid to End of Write tAW 50 - ns

Chip Enable to End of Write tCW 50 - ns

Address Set-up Time tAS 0 - ns

Write Pulse Width tWP 45 - ns

Write Recovery Time tWR 0 - ns

Data to Write Time Overlap tDW 25 - ns

Data Hold from End of Write Time tDH 0 - ns

Output Active from End of Write tOW* 5 - ns

Write to Output in High-Z tWHZ* - 20 ns

*These parameters are guaranteed by device characterization, but not production tested.

AS6C1008-55

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 4 of 14

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

Dout Data Valid

tOHtAA

Address

tRC

Previous Data Valid

READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)

Dout Data Valid

tOH

OE#

High-ZHigh-Z

tCLZ

tOLZ

tOE

tCHZ

tOHZ

CE2

tACE

CE#

tAA

Address

tRC

Notes :

1.WE# is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low., CE2 = high.

3.Address must be valid prior to or coincident with CE# = low,CE2 = high; otherwise tAA is the limiting parameter.

4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL= 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 5 of 14

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

Dout

Din Data Valid

tDW tDH

(4) High-Z

tWHZ

WE#

tWP

tCW

tWRtAS

(4)

TOW

CE#

tAW

Address

tWC

CE2

WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)

Dout

Din Data Valid

tDW tDH

(4) High-Z

tWHZ

WE#

tWP

tCW

CE# tWRtAS

tAW

Address

tWC

CE2

Notes :

1.WE#, CE# must be high or CE2 must be low during all address transitions.

2.A write occurs during the overlap of a low CE#, high CE2, low WE#.

3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high

impedance state.

6.tOW and tWHZ are specified with CL= 5pF. Transition is measured ±500mV from steady state.

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 6 of 14

®®

DATA RETENTION CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

VCC for Data Retention VDR CE# V≧CC - 0.2V

or CE2 ≦0.2V 1.5 - 5.5 V

C** - 0.5 12 µA

Data Retention Current IDR

VCC = 1.5V

CE# V≧CC - 0.2V

or CE2 ≦0.2V I** 0 30 µA

Chip Disable to Data

Retention Time tCDR See Data Retention

Waveforms (below) 0 - - ns

Recovery Time tRtRC*- - ns

tRC*= Read Cycle Time C=Commercial temp/I = Industrial temp**

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (CE# controlled)

Vcc

CE#

VDR ≧1.5V

CE# V≧cc-0.2V

Vcc(min.)

VIH

tRtCDR

VIH

Vcc(min.)

Low Vcc Data Retention Waveform (2) (CE2 controlled)

Vcc

CE2

VDR ≧1.5V

CE2 ≦0.2V

Vcc(min.)

VIL

tRtCDR

VIL

Vcc(min.)

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 7 of 14

PACKAGE OUTLINE DIMENSION

32 pin 450 mil SOP Package Outline Dimension

UNIT

SYM. INCH.(BASE) MM(REF)

A0.118 (MAX) 2.997 (MAX)

A1 0.004(MIN) 0.102(MIN)

A2 0.111(MAX) 2.82(MAX)

b0.016(TYP) 0.406(TYP)

c0.008(TYP) 0.203(TYP)

D0.817(MAX) 20.75(MAX)

E0.445 ±0.005 11.303 ±0.127

E1 0.555 ±0.012 14.097 ±0.305

e0.050(TYP) 1.270(TYP)

L0.0347 ±0.008 0.881 ±0.203

L1 0.055 ±0.008 1.397 ±0.203

S0.026(MAX) 0.660 (MAX)

y0.004(MAX) 0.101(MAX)

Θ0o -10o 0o -10o

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 8 of 14

®®

32 pin 600 mil P-DIP Package Outline Dimension

Note : D/E1/S dimension do not include mold flash.

UNIT

SYM. INCH(BASE) MM(REF)

A1 0.001 (MIN) 0.254 (MIN)

A2 0.150 ± 0.005 3.810 ± 0.127

B 0.018 ± 0.005 0.457 ± 0.127

D 1.650 ± 0.005 41.910 ± 0.127

E 0.600 ± 0.010 15.240 ± 0.254

E1 0.544 ± 0.004 13.818 ± 0.102

e 0.100 (TYP) 2.540 (TYP)

eB 0.640 ± 0.020 16.256 ± 0.508.

L 0.130 ± 0.010 3.302 ± 0.254

S 0.075 ± 0.010 1.905 ± 0.254

Q1 0.070 ± 0.005 1.778 ± 0.127

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 9 of 14

32 pin 8mm x 20mm TSOP-I Package Outline Dimension

UNIT

SYM. INCH(BASE) MM(REF)

A0.047 (MAX) 1.20 (MAX)

A1 0.004 ±0.002 0.10 ±0.05

A2 0.039 ±0.002 1.00 ±0.05

b0.008 + 0.002

- 0.001

0.20 + 0.05

-0.03

c0.005 (TYP) 0.127 (TYP)

D0.724 ±0.004 18.40 ±0.10

E0.315 ±0.004 8.00 ±0.10

e0.020 (TYP) 0.50 (TYP)

HD 0.787 ±0.008 20.00 ±0.20

L0.0197 ±0.004 0.50 ±0.10

L1 0.0315 ±0.004 0.08 ±0.10

y0.003 (MAX) 0.076 (MAX)

Θ0o～5o0o～5o

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 10 of 14

®®

32 pin 8mm x 13.4mm sTSOP Package Outline Dimension

16 17

"A"

12° (2x)12° (2x)

Seating Plane y

A2A1

0.254

GAUGE PLANE

12° (2X)

SEATING PLANE

"A" DETAIL VIEW L1

UNIT

SYM. INCH(BASE) MM(REF)

A0.049 (MAX) 1.25 (MAX)

A1 0.005 ±0.002 0.130 ±0.05

A2 0.039 ±0.002 1.00 ±0.05

b0.008 ±0.01 0.20±0.025

c0.005 (TYP) 0.127 (TYP)

D0.465 ±0.004 11.80 ±0.10

E0.315 ±0.004 8.00 ±0.10

e0.020 (TYP) 0.50 (TYP)

HD 0.528±0.008 13.40 ±0.20.

L0.0197 ±0.004 0.50 ±0.10

L1 0.0315 ±0.004 0.8 ±0.10

y0.003 (MAX) 0.076 (MAX)

Θ0o～5o0o～5o

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 11 of 14

36 ball 6mm × 8mm TFBGA Package Outline Dimension

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 12 of 14

Alliance Memory, Inc.

1116 South Amphlett, #2,

San Mateo, CA 94402

Tel: 650-525-3737

Fax: 650-525-0449

www.alliancememory.com

Part Number: AS6C1008

Document Version: v. 1.0

Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this

document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data

contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any

time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in

this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,

any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any

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warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in

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Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,

trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in

life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of

Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all

claims arising from such use.

February 2007

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

02/February/07, v 1.0

Alliance Memory Inc.

Page 14 of 14