1
¬
FN6708.0
ISL62870
PWM DC/DC Voltage Regulator Controller
The ISL62870 IC is a Single-Phase Synchronous-Buck
PWM voltage regulator featuring Intersil’s Robust Ripple
Regulator (R3) Technology™. The ISL62870 provides a low
cost solution for compact high performance applications.The
wide 3.3V to 25V input voltage range is ideal for systems
that run on battery or AC adapter power sources. Resistor
programmed output voltage setpoint and capacitor
programmed soft-start delay allow for fast and easy
implementation. Robust integrated MOSFET drivers and
Schottky bootstrap diode reduce the im pl eme nt a tio n are a an d
lower component cost.
Intersil’s R3 Technology™ combines the best features of
both fixed-frequency and hysteretic PWM control. The PWM
frequency is 300kHz during static operation, becoming
variable during changes in load, setpoint voltage, and input
voltage when changing between battery and AC adapter
power. The modulators ability to change the PWM switching
frequency during these events in conjunction with external
loop compensation produces superior transient response.
For maximum efficiency, the converter automatically enters
diode-emulation mode (DEM) during ligh t-lo ad conditions
such as system standby.
Pinout ISL62870
(16 LD 2.6X1.8 µTQFN)
TOP VIEW
Features
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 3.3V
• Output Load to 30A
• Simple Resistor Programming for Output Voltage
• ±0.75% System Accuracy: -10°C to +100°C
• Capacitor Programming for Soft-Start Delay
• Fixed 300kHz PWM Frequency in Continuous Conduction
• External Compensation Af fords Optimum Con trol Loop
Tuning
• Automatic Diode Emulation Mode for Highest Efficiency
• Integrated High-Current MOSFET Drivers and Schottky
Boot-Strap Diode for Optimal Efficiency
• Choice of Overcurrent Detection Schemes
- Lossless Inductor DC R Curr en t Sen s i n g
- Precision Resistive Current Sensing
• Power-Good Monitor for Soft-Start and Fault Detection
• Fault Protection
- Undervoltage
- Overvoltage
- Overcurrent (DCR-Sense or Resistive-Sense Capability)
- Over-Temperature Protection
- Fault Identification by PGOOD Pull-Down Resistance
• Pb-Free (RoHS Compliant)
Applications
• Mobile PC Graphical Processing Unit VCC Rail
• Mobile PC I/O Controller Hub (ICH) VCC Rail
• Mobile PC Memory Controller Hub (GMCH) VCC Rail
12
11
10
9
16
15
14
13
5
6
7
8
1
2
3
4
GND
EN
NC
SREF
BOOT
UGATE
PHASE
OCSET
PGND
LGATE
PVCC
VCC
NC
PGOOD
FB
VO
Ordering Information
PART NUMBER
(Note) PART
MARKING TEMP RANGE
(°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISL62870HRUZ GAL -10 to +100 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A
ISL62870HRUZ-T* GAL -10 to +100 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Data Sheet August 14, 2008
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN6708.0
August 14, 2008
Block Diagram
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL62870
PGND
PVCC
OVP
+
−
UVP
+
−
POR
SREF
BOOT
LGATE
DRIVER UGATE
DRIVER
PHASE
VO
OCSET
+
−
OCP
VSET
FB
PGOOD
100pF
VREF
100kΩ
VCC
GND
IOCSET
10µF
+
−
+
−
+
−
Cr
H
L
IN
VCC
PWM
VW
EN
PWM
RUN
RUN
RUN
FAULT
500mV
gmVO
gmVIN
VR
VCOMP
+
−
EA
FB
PROTECTION
SHOOT-THROUGH
OTP
FAULT
ISL62870
3FN6708.0
August 14, 2008
Application Schematics
FIGURE 2. ISL62870 APPLICATION SCHEMATIC WITH DCR CURRENT SENSE
FIGURE 3. ISL62870 APPLICATION SCHEMATIC WITH RESISTOR CURRENT SENSE
EN
GND
SREF
NC
CBOOT
LO
COC
COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25V
0.5V TO 3.3V
RO
COB
CINCCINB
VIN
VOUT
CSOFT
CVCC
CPVCC
GPIO
GPIO
8
7
6
5
13
14
15
16
VO
FB
PGOOD
NC
VCC
PVCC
LGATE
PGND
11 UGATE
BOOT
2
112
9OCSET
PHASE
4
310
+5V
RVCC
RPGOOD
VCC
ROFS
EN
GND
SREF
NC
CBOOT
LO
COC
COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25V
0.5V TO 3.3V
RO
COB
CINCCINB
VIN
VOUT
CSOFT
CVCC
CPVCC
GPIO
8
7
6
5
13
14
15
16
VO
FB
PGOOD
NC
VCC
PVCC
LGATE
PGND
11 UGATE
BOOT
2
112
9OCSET
PHASE
4
310
+5V
RVCC
GPIO
RPGOOD
VCC
ROFS
RSNS
ISL62870
4FN6708.0
August 14, 2008
Absolute Maximum Ratings
VCC, PVCC, PGOOD to GND. . . . . . . . . . . . . . . . . . -0.3V to +7.0V
VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, VO, FB, OCSET, SREF. . . . . . . . . . . -0.3V to GND, VCC +0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . .-0.3V to 33V
BOOT To PHASE Voltage (VBOOT-PHASE). . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 28V
GND -8V (<20ns Pulse Width, 10µJ)
UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) θJA (°C/W)
16 Ld µTQFN Package . . . . . . . . . . . . . . . . . . . . . . 84
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperat ure Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +100°C
Converter Input Voltage to GND . . . . . . . . . . . . . . . . . . 3.3V to 25V
VCC, PVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise stated. All typical specifications
TA= +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VCC and PVCC
VCC Input Bias Current IVCC EN = 5V, VCC = 5V, FB = 0.55V, SREF<FB - 1.1 1.5 mA
VCC Shutdown Current IVCCoff EN = GND, VCC = 5V - 0.1 1.0 µA
PVCC Shutdown Current IPVCCoff EN = GND, PVCC = 5V - 0.1 1.0 µA
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage VVCC_THR 4.40 4.49 4.60 V
Falling VCC POR Threshold Voltage VVCC_THF 4.10 4.22 4.35 V
REGULATION
Reference Voltage VREF(int) -0.50- V
System Accuracy PWM Mode = CCM -0.75 - +0.75 %
PWM
Switching Frequency FSW PWM Mode = CCM 270 300 330 kHz
VO
VO Input Voltage Range VVO 0-3.6V
VO Input Impedance RVO EN = 5V - 600 - kΩ
VO Reference Offset Current IVOSS VENTHR < EN, SREF = Soft-Start Mode - 10 - µA
VO Input Leakage Current IVOoff EN = GND, VO = 3.6V - .1 - µA
ERROR AMPLIFIER
FB Input Bias Current IFB EN = 5V, FB = 0.50V -20 - +50 nA
SREF
SREF Voltage VSREF -0.5- V
Soft-Start Current ISS 10 20 30 µA
ISL62870
5FN6708.0
August 14, 2008
POWER GOOD
PGOOD Pull-down Impedance RPG_SS PGOOD = 5mA Sink 75 95 150 Ω
RPG_UV PGOOD = 5mA Sink 75 95 150 Ω
RPG_OV PGOOD = 5mA Sink 50 65 90 Ω
RPG_OC PGOOD = 5mA Sink 25 35 50 Ω
PGOOD Leakage Current IPG PGOOD = 5V - 0.1 1.0 μA
PGOOD Maximum Sink Current (Note 2) IPG_max -5.0-mA
GATE DRIVER
UGATE Pull-Up Resistance (Note 2) RUGPU 200mA Source Current - 1.0 1.5 Ω
UGATE Source Current (Note 2) IUGSRC UGATE - PHASE = 2.5V - 2.0 - A
UGATE Sink Resistance (Note 2) RUGPD 250mA Sink Current - 1.0 1.5 Ω
UGATE Sink Current (Note 2) IUGSNK UGAT E - PHASE = 2.5V - 2.0 - A
LGATE Pull-Up Resistance (Note 2) RLGPU 250mA Source Current - 1.0 1.5 Ω
LGATE Source Current (Note 2) ILGSRC LGATE - GND = 2.5V - 2.0 - A
LGATE Sink Resistance (Note 2) RLGPD 250mA Sink Current - 0.5 0.9 Ω
LGATE Sink Current (Note 2) ILGSNK LGATE - PGND = 2.5V - 4.0 - A
UGATE to LGATE Deadtime tUGFLGR UGATE falling to LGATE rising, no load - 21 - ns
LGATE to UGATE Deadtime tLGFUGR LGATE falling to UGATE rising, no load - 21 - ns
PHASE
PHASE Input Impedance RPHASE -33-kΩ
BOOTSTRAP DIODE
Forward Voltage VFPVCC = 5V, IF = 2mA - 0.58 - V
Reverse Leakage IRVR = 25V - 0.2 - µA
CONTROL INPUTS
EN High Threshold Voltage VENTHR 2.0 - - V
EN Low Threshold Voltage VENTHF --1.0V
EN Input Bias Current IEN EN = 5V 1.5 2.0 2.5 µA
EN Leakage Current IENoff EN = GND - 0.1 1.0 µA
PROTECTION
OCP Threshold Voltage VOCPTH VOCSET - VO-1.75 - 1.75 mV
OCP Reference Current IOCP EN = 5.0V 9.0 10 11 µA
OCSET Input Resistance ROCSET EN = 5.0V - 600 - kΩ
OCSET Leakage Current IOCSET EN = GND - 0 - µA
UVP Threshold Voltage VUVTH VFB = %VSREF 81 84 87 %
OVP Rising Threshold Voltage VOVRTH VFB = %VSREF 113 116 120 %
OVP Falling Threshold Voltage VOVFTH VFB = %VSREF 100 102 106 %
OTP Rising Threshold T emperature (Note 2) TOTRTH -150- °C
OTP Hysteresis (Note 2) TOTHYS -25-°C
NOTE:
2. Limits established by characterization and are not production tested.
Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise stated. All typical specifications
TA= +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
ISL62870
6FN6708.0
August 14, 2008
Functional Pin Descriptions
GND (Pin 1)
IC ground for bias supply and signal reference.
EN (Pin 2)
Enable input for the IC. Pulling EN above the VENTHR rising
threshold voltage initializes the soft-start sequence.
NC (Pins 3, 5)
No internal connection. Pins 3 and 5 should be connected to
the GND pin.
SREF (Pin 4)
Soft-start programming capacitor input. Connects internally
to the invertin g in pu t of the VSET voltage setpoint amplifier.
PGOOD (Pin 6)
Power-good open-drain indicator output. This pin changes to
high impedance when the converter is able to supply
regulated voltage. The pull-down resistance between the
PGOOD pin and the GND pin identifies which protective fault
has shut down the regulator. See Table 1 on page 10.
FB (Pin 7)
Voltage feedback sense input. Connects internally to the
inverting input of the control-loop error amplifier. The
converter is in regulation when the voltage at the FB pin
equals the voltage on the SREF pin. The control loop
compensation network connects between the FB pin and the
converter output. See Figure 8 on page 10.
VO (Pin 8)
Output voltage sense input for the R3 modulator. The VO pin
also serves as the reference input for the overcurrent
detection circuit. See Figure 5 on page 7.
OCSET (Pin 9)
Input for the overcurrent dete ction circuit. The overcurrent
setpoint programming resistor ROCSET connects from this
pin to the sense node. See “OVERCURRENT
PROGRAMMING CIRCUIT” on page 7.
PHASE (Pin 10)
Return current path for the UGATE high-side MOSF ET
driver . VIN sense input for the R3 modulator . Inductor current
polarity detector input. Connect to junction of output inductor ,
high-side MOSFET, and low-side MOSFET. See “Application
Schematics” on page 3 (Figures 2 and 3).
UGATE (Pin 11)
High-side MOSFET gate driver output. Con nect to the gate
terminal of the high-side MOSFET of the converter.
BOOT (Pin 12)
Positive input supply for the UGA TE high-side MOSFET gate
driver. The BOOT pin is internally connected to the cathode
of the Schottky boot-strap diode. Connect an MLCC
between the BOOT pin and the PHASE pin.
VCC (Pin 13)
Input for the IC bias voltage. Connect +5V to the VCC pin
and decouple with at least a 1µF MLCC to the GND pin. See
“Application Schematics” on page 3 (Figures 2 and 3).
PVCC (Pin 14)
Input for the LGATE and UGATE MOSFET driver circuits.
The PVCC pin is internally connected to the anode of the
Schottky boot-strap diode. Connect +5V to the PVCC pin
and decouple with a 10µF MLCC to the PGND pin. See
“Application Schematics” on page 3 (Figures 2 and 3).
LGATE (Pin 15)
Low-side MOSFET gate driver output. Connect to the gate
terminal of the low-side MOSFET of the converter.
PGND (Pin 16)
Return current path for the LGATE MOSFET driver . Connect
to the source of the low-side MOSFET.
Setpoint Reference Voltage
The 500mV output of the setpoint reference voltage (VSREF)
appears at the SREF pin. This signal is the output of the
current limited voltage follower that buffers an internal
500mV voltage reference (VREF.) The converter is in
regulation when the voltage at the FB pin (VFB) equals the
VSREF voltage at the SREF pin. Both of these pins are
measured relative to the GND pin, not the PGND pin.
The feedback voltage-divider network consisting of offset
resistor (ROFS) and loop-compensation resistor (RFB) scale
down the converter output voltage (VOUT) such that the
voltage VFB equals VSREF when VOUT equals the desired
output voltage of the converter. The voltage-divider relation
is given in Equation 1:
Where:
-V
FB = VSREF
-R
FB is the loop-compensation feedback resistor that
connects from the FB pin to the converter output
-R
OFS is the voltage-scaling programming resistor that
connects from the FB pin to the GND pin
The value of offset resistor ROFS must be recalculated
whenever the value of loop-compensation resistor RFB has
been changed. Calculation of ROFS is written as shown in
Equation 2:
VFB VOUT ROFS
RFB ROFS
+
----------------------------------
⋅=(EQ. 1)
ROFS VSREF R⋅FB
VOUT VSREF
–
-----------------------------------------
=(EQ. 2)
ISL62870
7FN6708.0
August 14, 2008
Soft-Start Delay
Circuit Description
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage VVCC_THR, and the voltage on
the EN pin has increased above the rising enable threshold
voltage VENTHR, the SREF pin releases its discharge clamp,
and enables the reference amplifier VSET. The soft-start
current ISS is limited to 20µA and is sourced out of the SREF
pin and charges capacitor CSOFT until VSREF equals VREF.
The regulator controls the PWM such that the voltage on the
FB pin tracks the rising voltage on the SREF pin. The
elapsed time from when the EN pin is asserted to when
VSREF has charged CSOFT to VREF is called the soft-start
delay tSS which is given by Equation 3:
Where:
-I
SS is the soft-start current source at the 20µA limit
-V
SREF is the buffered VREF reference voltage
The end of soft-start is detected by ISS tapering off when
capacitor CSOFT charges to VREF. The internal SSOK flag is
set, the PGOOD pin goes high, and diode emulation mode
(DEM) is enabled.
Component Selection For CSOFT Capacitor
Choosing the CSOFT capacitor to meet the requirements of a
particular soft-st a rt delay tSS is calculated using Equation 4,
which is written as follows:
Where:
-t
SS is the soft-start delay
-I
SS is the 20µA soft-start current source at the 20µA
limit
-V
SREF is the buffered VREF reference voltage
Fault Protection
Overcurrent
The overcurrent protection (OCP) setpoint is programmed
with resistor ROCSET, which is connected across the
OCSET and PHASE pins. Resistor RO is connected
between the VO pin and the actual output voltage of the
converter. During normal operation, the VO pin is a high
impedance path, therefore there is no voltage drop across
RO. The value of resistor RO should always match the value
of resistor ROCSET.
Figure 5 shows the overcurrent set circuit. The inductor
consists of inductance L and the DC resistance DCR. The
inductor DC current IL creates a voltage drop across DCR,
which is given by Equation 5:
The IOCSET current source sinks 10µA into the OCSET pin,
creating a DC voltage drop across the resistor ROCSET,
which is given by Equation 6:
The DC voltage difference between the OCSET pin and the
VO pin, which is given by Equation 7:
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than th e
voltage of the VO pin for more than 10µs, an OCP fault
latches the converter off.
Component Selection For ROCSET and CSEN
The value of ROCSET is calculated with Equation 8 which is
written as follows:
Where:
-R
OCSET (Ω) is the resistor used to program the
overcurrent setpoint
-I
OC is the output DC load current that will activate the
OCP fault detection circuit
- DCR is the inducto r DC resistance
FIGURE 4. ISL62870 VOLTAGE PROGRAMMING CIRCUIT
SREF
VSET
+
−
VREF
CSOFT
EA
+
−
FB
ROFS
RFB
VOUT
VCOMP
tSS VSREF CSOFT
⋅
ISS
-------------------------------------------
=(EQ. 3)
CSOFT tSS ISS
⋅
VSREF
-----------------------
=(EQ. 4)
FIGURE 5. OVERCURRENT PROGRAMMING CIRCUIT
PHASE
CO
L
VO
ROCSET CSEN
OCSET
VO
RO
DCR IL
10µ
+_
VDCR
+_
VROCSET
VDCR ILDCR⋅=(EQ. 5)
VROCSET 10μAR
OCSET
⋅=(EQ. 6)
VOCSET V–VO VDCR V–ROCSET ILDCR⋅IOCSET ROCSET
⋅–==
(EQ. 7)
(EQ. 8)
ROCSET IOC DCR⋅
IOCSET
----------------------------
=
ISL62870
8FN6708.0
August 14, 2008
For example, if IOC is 20A and DCR is 4.5mΩ, the choice of
ROCSET is = 20Ax4.5mΩ/10µA = 9kΩ.
Resistor ROCSET and capacitor CSEN form an R-C network
to sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant ROCSET CSEN
needs to match the inductor time constant L/DCR. The value
of CSEN is then written as fo llows:
For example, if L is 1.5µH, DCR is 4.5mΩ, and ROCSET is
9kΩ, the choice of CSEN = 1.5µH/(9kΩx4.5mΩ) = 0.037µF.
When an OCP fault is declared, the PGOOD pin will
pull-down to 35Ω and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage VENTHF or if VCC has decayed
below the falling POR threshold voltage VVCC_THF
Overvoltage
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold VOVRTH for
more than 2µs. For example, i f the convert er is programme d
to regulate 1.0V at the FB pin, that voltage would have to
rise above the typical VOVRTH threshold of 116% for more
than 2µs in order to trip the OVP fault latch. In numerical terms,
that woul d be 116% x 1.0V = 1.16V. When an OVP fault is
declared, the PGOOD pin will pull-down to 65Ω and latch-off
the converter. The OVP fault will remain latched until VCC
has decayed below the falling POR threshold voltage
VVCC_THF. An OVP fault cannot be reset by pul ling the EN
pin below the falling EN threshold voltage VENTHF.
Although the converter has latched-of f in response to a n OVP
fault, the LGATE gate-driver output will ret a in the ability to
toggle the low-side MOSFET on and off, in response to the
output volt age transversing the V OVRTH and VOVFTH
thresholds. The LGATE gate-driver will turn-on the low -side
MOSFET to discharge the output voltag e, protecting the load.
The LGATE gate-driver will turn-off the low-side MOSFET
once the FB pin volta ge is lower than the fa lling ove rvolt age
threshold VOVRTH for more than 2µs. The falling overvolt age
threshold VOVFTH is typically 102%. That means if the FB pin
voltage falls below 102% x 1.0V = 1.02V, for more than 2µs,
the LGATE gate-driver will turn off the low-side MOSFET. If
the output voltage rises again, the L GATE driver will again
turn on the low-side MOSFET when the FB pin volt age is
above the rising overvoltage thre shold VOVRTH for more than
2µs. By doing so, the IC protects the load when there is a
consistent overvoltage co ndition.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold VUVTH for more
than 2µs. For example, if the converter is programmed to
regulate 1.0V at the FB pin, that voltage would have to fall
below the typical VUVTH threshold of 84% for more than 2µs
in order to trip the UVP fault latch. In numerical terms, that
would be 84% x 1.0V = 0.84V. When a UVP fault is declared,
the PGOOD pin will pull-down to 95 Ω and latch-off the
converter. The fault will remain latched until the EN pin has
been pulled below the falling EN threshold voltage VENTHF
or if VCC has decayed below the falling POR threshold
voltage VVCC_THF.
Over-Temperature
When the temperature of the IC increases above the rising
threshold temperature TOTRTH, it will enter the OTP state
that suspends the PWM, forcing the LGATE and UGATE
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch -off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature TOTHYS, at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage VENTHF or if
VCC has decayed below the falling POR threshold vo ltage
VVCC_THF. All other protection circu i ts remain functional
while the IC is in the OTP state. It is likely that the IC will
detect an UVP fault because in the absence of PWM, the
output voltage decays below the undervoltage threshold
VUVTH.
Theory of Operation
The modulator features Intersil’s R3 Robust-Ripple
Regulator technology, a hybrid of fixed frequency PWM
control and variable frequency hysteretic control. The PWM
frequency is maintained at 300kHz under static continuous
conduction mode operation within the entire specified
envelope of input voltage, output voltage, and output load. If
the application should experience a rising load transient
and/or a falling line transient such that the output voltage
starts to fall, the modulator will extend the on-time and/or
reduce the off-time of the PWM pulse in progress.
Conversely, if the application should experience a falling
load transient and/or a rising line transient such that the
output voltage starts to rise, the modulator will truncate the
on-time and/or extend the off-time of the PWM pulse in
progress. The period and duty cycle of the ensuing PWM
pulses are optimized by the R3 modulator for the remainder
of the transient and work in concert with the error amplifier
VERR to maintain output voltage regulation. Once the
transient has dissipated and the control loop has recovered,
the PWM frequency returns to the nominal static 300kHz.
Modulator
The R3 modulator synthesizes an AC signal VR, which is an
analog representation of the output inductor ripple current.
The duty-cycle of VR is the result of charge and discharge
current through a ripple capacitor CR. The current through
CR is provided by a transconductance amplifier gm that
measures the input voltage (VIN) at the PHASE pi n and
(EQ. 9)
CSEN L
ROCSET DCR⋅
------------------------------------------
=
ISL62870
9FN6708.0
August 14, 2008
output voltage (VOUT) at the VO pin. The positive slope of
VR can be written as Equation 10:
The negative slope of VR can be written as Equation 11:
Where gm is the gain of the transconductance amplifier.
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ri pp l e voltage VR is compared. The amplitude of
VW is controlled internally by the IC. The VR, VCOMP, and
VW signals feed into a window comparator in which VCOMP
is the lower threshold voltage and VW is the higher threshold
voltage. Figure 6 shows PWM pulses being generated as VR
traverses the V W and VCOMP thresholds. The PWM
switching frequency is proportional to the slew rates of the
positive and negative slopes of VR; it is inversely
proportional to the voltage between VW and VCOMP.
Synchronous Rectification
A standard DC/DC buck regulator uses a free-wheeling
diode to maintain uninterrupted current conduction through
the output inductor when the high-side MOSFET switches off
for the balance of the PWM switching cycle. Low conversion
efficiency as a result of the conduction loss of the diode
makes this an unattractive option for all but the lowest
current applications. Efficiency is dramatically improved
when the free-wheeling diode is replaced with a MOSFET
that is turned on whenever the high-side MOSF ET is turned
off. This modification to the standard DC/DC buck regulator
is referred to as synchronous rectification, th e topology
implemented by the ISL62870 controller.
Diode Emulation
The polarity of the output inductor current is defined as positive
when conducting away from the phase node, and defined as
negative when conducting towards the phase node. The DC
component of the inductor current is positive, but the AC
component known as the ripple current, can be either positive
or negative. Should the sum of the AC and DC components of
the inductor current remain positive for the entire switching
period, the converter is in continuous-conduction-mode (CCM.)
However, if the inductor current becomes negative or zero, the
converter is in discontinuous-conduction-mode (DCM.)
Unlike the standard DC/DC buck regulator, the synchronous
rectifier can sink current from the output filter inductor during
DCM, reducing the light-load efficiency with unnecessary
conduction loss as the low-side MOSFET sinks the inductor
current. The ISL62870 controller avoids the DCM conduction
loss by making the low-side MOSFET emulate the current
blocking behavior of a diode. This smart-diode operation
called diode-emulation-mode (DEM) is tri ggered when the
negative inductor current produces a positive voltage drop
across the rDS(ON) of the low-side MOSFET for eight
consecutive PWM cycles while the LGATE pin is high. The
converter will exit DEM on the next PWM pulse after
detecting a negative voltage across the rDS(ON) of the low-
side MOSFET.
It is characteristic of the R3 architecture for the PWM
switching frequency to decrease while in DCM, increasing
efficiency by reducing unnecessary gate-driver switching
losses. The extent of the frequency reduction is proportional
to the reduction of load current. Upon entering DEM, the
PWM frequency is forced to fall approximately 30% by
forcing a similar increase of the window voltage VW. This
measure is taken to prevent oscillating between modes at
the boundary between CCM and DCM. The 30% increase of
VW is removed upon exit of DEM, forcing the PWM switching
frequency to jump back to the nominal CCM value.
Power-On Reset
The IC is disabled until the voltage at the VCC pin ha s
increased above the rising power-on reset (POR) threshold
voltage VVCC_THR. The controller will become disabled
when the voltage at the VCC pin decreases below the falling
POR threshold voltage VVCC_THF. The POR detector has a
noise filter of approximately 1µs.
VIN and PVCC Voltage Sequence
Prior to pulling EN above the VENTHR rising threshold
voltage, the following criteria must be met:
1. VPVCC is at least equivalent to the VCC rising power-on
reset voltage VVCC_THR
2. VVIN must be 3.3V or the minimum required by the
application.
Start-Up Timing
Once VCC has ramped above VVCC_THR, the controller can
be enabled by pulling the EN pin voltage above the input high
threshold VENTHR. Approximately 20µs later , the voltage at the
SREF pin begins slewing to the designated VID set-point. The
VRPOS gm
()VIN VOUT
–()CR
⁄⋅=(EQ. 10)
VRNEG gmVOUT CR
⁄⋅=(EQ. 11)
FIGURE 6. MODULA T OR W A VEFORMS DURING LOAD
TRANSIENT
PWM
RIPPLE CAPACITOR VOLTAGE CRWINDOW VOLTAGE V
W
ERROR AMPLIFIER VOLTAGE VCOMP
ISL62870
10 FN6708.0
August 14, 2008
converter output voltage at the FB feedback pin follows the
voltage at the SREF pin. During soft-st art, the regulator always
operates in CCM until the soft-start sequence is complete.
PGOOD Monitor
The PGOOD pin indicates when the converter is capable of
supplying regulated volt age. The PGOOD pin is an undefined
impedance if the VCC pin has not reached the rising POR
threshold VVCC_THR, or if the VCC pin is below the fall ing
POR threshold VVCC_THF. The PGOOD pull-down resist ance
corresponds to a specific prot ecti ve fault, thereb y reducing
troubleshooting time and effort. Table 1 maps the pull-down
resistance of the PGOOD pin to the corresponding fault status
of the controller.
LGATE and UGATE MOSFET Gate-Drivers
The LGATE pin and UGATE pins are MOSFET driver
outputs. The LGATE pin drives the low-side MOSFET of the
converter while the UGAT E pin drives the high-side
MOSFET of the converter.
The LGATE driver is optimized for low duty-cycle
applications where the low-side MOSFET experiences long
conduction times. In this environment, the low-side
MOSFETs require exceptionally low rDS(ON) and tend to
have large parasitic charges that conduct transient currents
within the devices in response to high dv/dt switching
present at the phase node. The drain-gate charge in
particular can conduct sufficient current through the driver
pull-down resistance that the VGS(th) of the device can be
exceeded and turned on. For this reason, the LGATE driver
has been designed with low pull-down resistance and high
sink current capability to ensure clamping the MOSFETs
gate voltage below VGS(th).
Adaptive Shoot-Through Protection
Adaptive shoot-through protection prevents a gate-driver
output from turning on until the opposite gate-driver output
has fallen below approximately 1V. The dead-time shown in
Figure 7 is extended by the additional period that the falling
gate voltage remains above the 1V threshold. The high-side
gate-driver output voltage is me asured across the UGATE
and PHASE pins while the low-side gate-driver output
voltage is measured across the LGA TE and PGND pins. The
power for the LGATE gate-driver is sourced directly from the
PVCC pin. The power for the UGATE gate-driver is supplied
by a boot-strap capacitor connected across the BOOT and
PHASE pins. The capacitor is charged each time the phase
node voltage falls a diode drop below PVCC, such as when
the low-side MOSFET is turned on.
Compensation Design
Figure 8 shows the recommended T ype-II compensation
circuit. The FB pin is the inverting input of the error amplifier .
The COMP signal, the output of the error amplifier , is inside the
chip and unavailable to users. CINT is a 100pF capacitor
integrated inside the IC, connecting across the FB pin and the
COMP signal. RFB, RCOMP, CCOMP and CINT form the T ype-II
compensator. The frequency domain transfer function is given
by Equation 12:
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R3 modulator used in the
IC makes the LC output filter resemble a first order system in
which the closed loop stability can be achieved with the
recommended T ype-II compensation network. Intersil provides
a PC-based tool that can be used to calculate compensation
network component value s and help simulate the loop
frequency response.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to desi gn a single-p hase
power converter. It is assumed that the reader is familiar with
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION PGOOD RESISTANCE
VCC Below POR Undefined
Soft-Start or Undervoltage 95Ω
Overvoltage 65Ω
Overcurrent 35Ω
FIGURE 7. GATE DRIVER ADAPTIVE SHOOT-THROUGH
1V
1V
UGATE
LGATE
1V
1V
(EQ. 12)
GCOMP s() 1sR
FB RCOMP
+()C⋅COMP
⋅+
sR
FB CINT 1sR
COMP C⋅COMP
⋅+()⋅⋅ ⋅
---------------------------------------------------------------------------------------------------------------
=
ROFS
EA
+
FB
CINT = 100pF
-
SREF
VOUT
FIGURE 8. COMPENSATION REFERENCE CIRCUIT
RFB
RCOMP CCOMP
COMP
ISL62870
11 FN6708.0
August 14, 2008
many of the basic skills and techniques refere nced in the
following. In addition to this guide , Intersil provides comp lete
reference designs that include schematics, bills of mate ri als,
and example board l ayouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
shown in Equation 13:
The output inductor peak-to-peak ripp le current is written as
shown in Equation 14:
A typical step-down DC/DC converter will have an IP-P of
20% to 40% of the maximum DC output load current. The
value of IP-P is selected based upon several criteria, such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be es t im ated using Equation 15:
Where ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be given
to the DCR selection. Another factor to consider when choosing
the inductor is its saturation characteristics at elevated
temperature. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capa cit ance CO
into which ripple current IP-P can flow . Current I P-P develops a
corresponding ripple voltage VP-P across CO, which is the
sum of the voltage drop across the capacitor ESR and of the
voltage change stemmi ng fro m charge moved in and out of
the capacitor. These two voltages are written as Eq uations 16
and 17:
and:
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required VP-P is achieved. The
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
capacitors should be considered. A capacitor dissipates heat as
a function of RMS current and frequency. Be sure that IP-P is
shared by a sufficient quantity of paralleled cap acitors so that
they operate below the maximum rated RMS current at FSW.
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 9 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as
expressed in Equation 18:
Where:
-I
MAX is the maximum continuous ILOAD of the converter
- x is a multiplie r (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter
Duty cycle is written as expressed in Equation 19:
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
Selecting The Bootstrap Capacitor
Adding an external cap acitor across the BOOT and PHASE
pins completes the bootstrap circuit. W e selected the
bootstrap cap acitor breakdown volt age to be at lea st 10V.
Although the theoretical maximum voltage of the cap acitor is
PVCC - VDIODE (voltage drop across the boot diode), large
excursions below ground by the PHASE node re quires that
DVO
VIN
---------
=(EQ. 13)
(EQ. 14)
IPP–VO1D–()⋅
FSW L⋅
-------------------------------
=
(EQ. 15)
PCOPPER ILOAD2DCR⋅=
ΔVESR IPP–E⋅SR=(EQ. 16)
ΔVC
I
PP–
8C
OF⋅SW
⋅
---------------------------------
=(EQ. 17)
(EQ. 18)
IIN_RMS
IMAX2DD
2
–()⋅()xI
MAX2D
12
------
⋅⋅
⎝⎠
⎛⎞
+
IMAX
-----------------------------------------------------------------------------------------------------
=
(EQ. 19)
DVO
VIN EFF⋅
--------------------------
=
FIGURE 9. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
NORMALIZED INPUT RMS RIPPLE CURRENT
DUTY CYCLE
x = 0.75
x = 0.50
x = 0.25
x = 0
x = 1
ISL62870
12 FN6708.0
August 14, 2008
we select a capa cito r with at least a breakd own rating o f 10V.
The bootstrap capacitor can be chosen from Equation 20:
Where:
-Q
GATE is the amoun t of gate charge required to fully
charge the gate of the upper MOSFET
-ΔVBOOT is the maximum decay across the BOOT
capacitor
As an example, suppose an upper MOSFET has a gate
charge, QGATE, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125µF is required.
The next larger standard value capacitance is 0.15µF. A
good quality ceramic capacitor such as X7R or X5R is
recommended.
Driver Power Dissipation
Switching power dissipation in the driver is mainly a function
of the switching frequency and total gate charge of the
selected MOSFETs. Calculating the power dissipation in the
driver for a desired application is critical to ensuring safe
operation. Exceeding the maximum allowable power
dissipation level will push the IC beyond the maximum
recommended operating junction temperature of +125°C.
When designing the application, it is recommended that the
following calculation be performed to ensure safe operati on
at the desired frequency for the selected MOSFETs. The
power dissipated by the drivers is approximated using
Equation 21:
Where:
-F
sw is the switching frequency of the PWM signal
-V
U is the upper gate driver bias supply voltage
-V
L is the lower gate driver bias supply voltage
-Q
U is the charge to be delivered by the upper driver into
the gate of the MOSFET and discrete capacitors
-Q
L is the charge to be delivered by the lower driver into
the gate of the MOSFET and discrete capacitors
-P
L is the quiescent power consumption of the lower driver
-P
U is the quiescent power consumption of the upper driver
MOSFET Selection and Considera tions
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum VDS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET,
which has the drain-source voltage clamped by its body
diode during turn-off, the high-side MOSFET turns off with
VIN-VOUT, plus the spike, across it. Th e preferred low-side
MOSFET emphasizes low rDS(ON) when fully saturated to
minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as Eq uation 22:
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 23:
For the high-side MOSFET, its switching loss is written as
Equation 24:
CBOOT QGATE
ΔVBOOT
------------------------
≥(EQ. 20)
FIGURE 10. BOOTSTRAP CAP ACIT ANCE vs BOOT RIPPLE
VOLTAGE
20nC
ΔVBOOT_CAP (V)
CBOOT_CAP (µF
2.0
1.6
1.4
1.0
0.8
0.6
0.4
0.2
0.0 0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
QGATE = 100nC
1.2
1.8
50nC
PF
sw 1.5VUQUVLQL
+()PLPU
++=(EQ. 21)
FIGURE 11. POWER DISSIPATION vs FREQUENCY
FREQUENCY (kHz)
0
100
200
300
400
500
600
700
800
900
1000
0 200 400 600 800 1000 1200 1400 1600 1800 2000
POWER (mW)
QU=50nC
QL=50nC
QU=50nC
QL=100nC
QU=100nC
QL=200nC
QU=20nC
QL=50nC
(EQ. 22)
PCON_LS ILOAD2r⋅DS ON()_LS 1D–()⋅≈
(EQ. 23)
PCON_HS ILOAD2r⋅DS ON()_HS D⋅=
(EQ. 24
)
PSW_HS VIN IVALLEY tON F⋅SW
⋅⋅
2
----------------------------------------------------------------------VIN IPEAK tOFF F⋅SW
⋅⋅
2
------------------------------------------------------------------
+=
ISL62870
13 FN6708.0
August 14, 2008
Where:
-I
VALLEY is the difference of the DC component of th e
inductor current minus 1/2 of the inductor ripple current
-I
PEAK is the sum of the DC component of th e inductor
current plus 1/2 of the inductor ripple current
-t
ON is the time required to drive the device into
saturation
-t
OFF is the time required to drive the device into cut-off
Layout Considerations
The IC, analog signals, and logic signals should all be on the
same side of the PCB, located away from powerful emission
sources. The power conversion components should be
arranged in a manner similar to the example in Figure 12
where the area enclosed by the current circulating through
the input capacitors, high-side MOSFETs, and low-side
MOSFETs is as small as possible and al l located on the
same side of the PCB. The power components can be
located on either side of the PCB relative to the IC.
Signal Ground
The GND pin is the signal-common also known as analog
ground of the IC. When laying out the PCB, it is very
important that the connection of the GND pin to the bottom
feedback voltage-divider resistor and the CSOFT capacitor
be made as close as possible to the GND pin on a conductor
not shared by any other components.
In addition to the critical single point connection discussed in
the previous paragraph, the ground plane layer of the PCB
should have a single-point-connected island located under
the area encompassing the IC, feedback voltage divider,
compensation components, CSOFT capacitor, and the
interconnecting traces among the components and the IC.
The island should be connected using several filled vias to
the rest of the ground plane layer at one point that is not in
the path of either large static curre nts or high di/dt currents.
The single connection poin t should also be where the VCC
decoupling capacitor and the GND pin of the IC are
connected.
Power Ground
Anywhere not within the analog-ground island is Power
Ground.
VCC AND PVCC PINS
Place the decoupling capacitors as close as practical to the
IC. In particular , the PVCC decoupling capacitor should have
a very short and wide connection to the PGND pin. The VCC
decoupling capacitor should not share any vias with the
PVCC decoupling capacitor.
EN AND PGOOD PINS
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET AND VO PINS
The current-sensing network consisting of ROCSET, RO, and
CSEN needs to be connected to the inductor pads for
accurate measurement of the DCR voltage drop. These
components however, should be located physically close to
the OCSET and VO pins with traces leading back to the
inductor. It is critical that the traces are shielded by the
ground plane layer all th e way to the inductor pads. The
procedure is the same for resistive current sense.
FB AND SREF PINS
The input impedance of these pins is high, making it critical
to place the loop compensation components, feedback
voltage divider resistors, and CSOFT capacitor close to the
IC, keeping the length of the traces short.
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are high dv/dt and
high di/dt, with high peak charging and discharging curre nt.
The PGND pin can only flow current from the gate-source
charge of the low-side MOSFETs when LGATE goes low.
Ideally, route the tra ce from the LGATE pin in parallel with
the trace from the PGND pin; route the trace from the
UGATE pin in parallel with the trace from the PHASE pin,
and route the trace from the BOOT pin in parallel with the
trace from the PHASE pin. These pairs of traces should be
short, wide, and away from other traces with high input
impedance; weak signal traces should not be in proximity
with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
VIN
VOUT
PHASE
NODE
GND OUTPUT
CAPACITORS
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
++
HIGH-SIDE
MOSFETS
FIGURE 12. TYPICAL POWER COMPONENT PLACEMENT
OUTPUT
CAPACITORS
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
HIGH-SIDE
MOSFETS
PHASE
NODE
VOUT
VIN
GND
ISL62870
14 FN6708.0
August 14, 2008
Typical Performance
FIGURE 13. EFFICIENCY AT VOUT = 1.1V FIGURE 14. LOAD REGULATION AT VOUT =1.1V
FIGURE 15. SWITCHING FREQUENCY AT VOUT = 1.1V FIGURE 16. START-UP, VIN =12.6V, V
OUT = 1.05V, LOAD = 10A
FIGURE 17. START-UP INTO 750mV PRE-BIASED OUTPUT,
VIN =12.6V, V
OUT = 1.05V, LOAD = 10A FIGURE 18. SHUT -DOWN, VIN = 12.6V , VOUT = 1.05V,
LOAD = 50mΩ
IOUT (A)
EFFICIENCY (%)
0 2 10 12 14 16
60
65
70
75
80
85
90
95
100 VIN = 8V
18 20
50
55
468
VIN = 19V
VIN = 12.6V
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-1.0
-0.8
0 2 10 12 14 16 18 20468
REGULATION (%)
IOUT (A)
VIN = 19V
VIN = 12.6V VIN = 8V
0 2 10 12 14 16 18 20486
VIN = 8V
VIN = 19V
VIN = 12.6V
IOUT (A)
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-1.0
-0.8
REGULATION (%)
EN
SREF
PGOOD
VOUT
EN
SREF
PGOOD
VOUT
EN
SREF
PGOOD VOUT
20us
ISL62870
15 FN6708.0
August 14, 2008
FIGURE 19. SHUT-DOWN, VIN =12.6V, V
OUT = 1.05V,
LOAD = OPEN-CIRCUIT FIGURE 20. CCM STEADY-STATE OPERATION,
VIN = 12.6V, VOUT = 1.0V, IOUT = 10A
FIGURE 21. DCM STEADY-STATE OPERATION,
VIN = 12.6V, VOUT = 1.0V, IOUT =3A FIGURE 22. CCM LOAD TRANSIENT RESPONSE
VIN = 12.6V, VOUT =1.0V
FIGURE 23. DCM LOAD TRANSIENT RESPONSE VIN = 12.6V, VOUT =1.0V
Typical Performance (Continued)
EN
SREF
PGOOD VOUT
10s
PHASE
UGATE
LGATE
VOUT
PHASE
UGATE
LGATE
VOUT
PHASE
IOUT
VOUT
5ADC
+10A/µ
5ADC
15ADC
-10A/¬
PHASE
IOUT
VOUT
1ADC
+10A/µ
1ADC
11ADC
-10A/µ
ISL62870
16
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of I nter sil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6708.0
August 14, 2008
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
6
B
E
A
D
0.10 C
2X
C
0.05 CA
0.10 C
A1
SEATING PLANE
INDEX AREA
21
N
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NX (b)
SECTION "C-C" e
CC
5
C
L
TERMINAL TIP
(A1)
L
0.10 C
2X
e
L1
NX L
21
0.10 M CAB
0.05 M C
5
NX b
(DATUM B)
(DATUM A)
PIN #1 ID
16X
3.00
1.40
2.20
0.40
0.50
0.20
0.40
0.20
0.90
1.40
1.80
LAND PATTERN
10
L16.2.6x1.8A
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.45 0.50 0.55 -
A1 - - 0.05 -
A3 0.127 REF -
b 0.15 0.20 0.25 5
D 2.55 2.60 2.65 -
E 1.75 1.80 1.85 -
e 0.40 BSC -
L 0.35 0.40 0.45 -
L1 0.45 0.50 0.55 -
N162
Nd 4 3
Ne 4 3
θ0-124
Rev. 4 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
ISL62870
