CQFP to FBGA Adapter Sockets
16
CQFP to FBGA Adapter Pin Mapping List
The CQFP to FBGA adapter is routed from the FBGA package to match the existing die pad available for
the CQFP device being prototyped. Table 2 includes information on where to download the pin mapping
lists.
Prototyped Product, Adapter, and PCB Design Matrix
Designing the PCB for a specific product requires an understanding of which adapter socket will work.
Each adapter socket is routed differently. The design is based on the Axcelerator device or its
RadTolerant equivalent derivative being prototyped and the commercial Axcelerator FG package used
for prototyping. Table 3 shows the combinations that will work.
Table 2 • CQFP to FBGA Adapter Pin Mapping List
Adapter Socket Ordering Part Number
Prototyped and
Prototype Device
Adapter Pin Mapping
List Document #
CQ352 to FG484
23x23
SK-AX250-CQ352RTFG484S For prototyping RTAX250S/L-CQ352 or
AX250-CQ352 using the AX250-FG484
package
Refer to the Prototyping
Solutions section of the
Microsemi SoC Products
Group website:
www.microsemi.com/soc/
techdocs/package/default
.aspx.
CQ352 to FG896 SK-AX1-AX2-KITTOP and
SK-AX1-CQ352-KITBTM
For prototyping RTAX1000S/L-CQ352
or AX1000-CQ352 using the
AX1000-FG896 package
CQ352 to FG896 SK-AX1-AX2-KITTOP and
SK-AX2-CQ352-KITBTM
For prototyping RTAX2000S/L-CQ352
or AX2000-CQ352 using the
AX2000-FG896 package
Table 3 • Prototyping Design Matrix
Prototyped Product Adapter Part Number Prototype Vehicle PCB Design
AX250-CQ352 SK-AX250-CQ352RTFG484S AX250-FG484 23x23 AX250-CQ352
AX1000-CQ352 SK-AX1-AX2-KITTOP and
SK-AX1-CQ352-KITBTM
AX1000-FG896 AX1000-CQ352
AX2000-CQ352 SK-AX1-AX2-KITTOP and
SK-AX2-CQ352-KITBTM
AX2000-FG896 AX2000-CQ352
RTAX250S-CQ352,
RTAX250SL-CQ352
SK-AX250-CQ352RTFG484S AX250-FG484 23x23 AX250-CQ352 1
Notes:
1. The PCB designer should consider the eight pin pairs of the phase-locked loop (PLL) analog power supply
(VCCPLA/VCOMPLA, VCCPLB/VCOMPLB, VCCPLC/VCOMPLC, VCCPLD/VCOMPLD, VCCPLE/VCOMPLE,
VCCPLF/VCOMPLF, VCCPLG/VCOMPLG, and VCCPLH/VCOMPLH). They should be treated as follows:
• VCCPLA/B/C/D/E/F/G/H —There are eight in each device. VCCPLA supports the PLL associated with global
resource HCLKA, and VCCPLB supports the PLL associated with global resource HCLKB. These PLL analog power
supply pins should be connected to 1.5 V whether or not the PLL is used. Refer to the Axcelerator Family FPGAs
and RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs datasheets for pin assignment information.
• VCOMPLA/B/C/D/E/F/G/H —These are compensation reference signals for the internal PLL. There are eight in
each device. VCOMPLA supports the PLL associated with global resource HCLKA, and VCOMPLE supports the
PLL associated with global resource HCLKE. The VCOMPLX pins should be left floating if the PLL is not being used.
Refer to the Axcelerator Family FPGAs and RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs datasheets for
pin assignment information.
2. Since the Axcelerator and RTAX-S/L devices are exactly pin-compatible except for the PLL, which RTAX-S/L does not
have, designing the PCB with VCCPL(X) pins connected to 1.5 V will not affect the function of the RTAX-S/L devices.
Pins for VCOMPL(X) can be designed with land patterns only. These 16 PLL pins are not connected internally inside the
RTAX-S packages.