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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DLPC3433

DLPC3438

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

DLPC3433 and DLPC3438 Display Controller

1 Features

1• Display Controller for DLP3010 (.3 720p) TRP

DMD

– Supports Input Image Sizes up to 720p

– Low-Power DMD Interface With Interface

Training

• 24-Bit, Input Pixel Interface Support:

– Parallel or BT656, Interface Protocols

– Pixel Clock up to 150 MHz

– Multiple Input Pixel Data Format Options

• MIPI DSI Interface Type 3 (Only Supported With

DLPC3433)

– 1-4 Lanes, up to 470 Mbps Lane Speed

• Pixel Data Processing:

– IntelliBright™ Suite of Image Processing

Algorithms

– Content Adaptive Illumination Control

– Local Area Brightness Boost

– Image Resizing (Scaling)

– 1D Keystone Correction

– Color Coordinate Adjustment

– Programmable Degamma

– Active Power Management Processing

– Color Space Conversion

– 4:2:2 to 4:4:4 Chroma Interpolation

– Field Scaled De-interlacing

• Two Package Options:

– 176-Pin, 7- × 7-mm, 0.4-mm Pitch, NFBGA

– 201-Pin, 13- × 13-mm, 0.8-mm Pitch, NFBGA

• External Flash Support

• Auto DMD Parking at Power Down

• Embedded Frame Memory (eDRAM)

• System Features:

– I2C Control of Device Configuration

– Programmable Splash Screens

– Programmable LED Current Control

– Display Image Rotation

– One Frame Latency

– Compatible With DLPA2000, DLPA2005, and

DLPA3000 PMIC's

2 Applications

• Battery Powered Mobile Accessory HD Projector

• Battery Powered Smart HD Accessory

• Embedded Projection (Notebooks, Laptops,

Tablets, Hot Spots, and So Forth)

• Digital Signage

• Wearable Display (Near Eye or Head Mounted)

• Interactive Display

• Low-Latency Gaming Display

3 Description

The DLPC343x digital controller, part of the DLP3010

(.3 720p) chipset, supports reliable operation of the

DLP3010 digital micromirror device (DMD). The

DLPC343x controller provides a convenient, multi-

functional interface between system electronics and

the DMD, enabling small form factor, low power, and

high resolution HD displays.

Device Information (1)(2)

PART NUMBER PACKAGE BODY SIZE (NOM)

DLPC3433 NFBGA (176) 7.00 × 7.00 mm2

DLPC3438 NFBGA (201) 13.00 × 13.00 mm2

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(2) DSI is available for the DLPC3433 only. DSI is not available

for the DLPC3438.

Typical Standalone System

DLPC3433

DLPC3438

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

www.ti.com

Product Folder Links: DLPC3433 DLPC3438

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 4

6 Specifications....................................................... 14

6.1 Absolute Maximum Ratings .................................... 14

6.2 ESD Ratings............................................................ 14

6.3 Recommended Operating Conditions..................... 15

6.4 Thermal Information................................................ 15

6.5 Electrical Characteristics over Recommended

Operating Conditions .............................................. 16

6.6 Electrical Characteristics......................................... 17

6.7 High-Speed Sub-LVDS Electrical Characteristics... 20

6.8 Low-Speed SDR Electrical Characteristics............. 21

6.9 System Oscillators Timing Requirements............... 22

6.10 Power-Up and Reset Timing Requirements ......... 22

6.11 Parallel Interface Frame Timing Requirements .... 23

6.12 Parallel Interface General Timing Requirements.. 24

6.13 BT656 Interface General Timing Requirements ... 25

6.14 DSI Host Timing Requirements .......................... 25

6.15 Flash Interface Timing Requirements................... 26

7 Parameter Measurement Information ................ 27

7.1 HOST_IRQ Usage Model ....................................... 27

7.2 Input Source............................................................ 28

8 Detailed Description............................................ 31

8.1 Overview................................................................. 31

8.2 Functional Block Diagram....................................... 31

8.3 Feature Description................................................. 31

8.4 Device Functional Modes........................................ 42

9 Application and Implementation ........................ 43

9.1 Application Information............................................ 43

9.2 Typical Application ................................................. 43

10 Power Supply Recommendations ..................... 46

10.1 System Power-Up and Power-Down Sequence... 46

10.2 DLPC343x Power-Up Initialization Sequence....... 48

10.3 DMD Fast PARK Control (PARKZ)....................... 49

10.4 Hot Plug Usage..................................................... 49

10.5 Maximum Signal Transition Time.......................... 49

11 Layout................................................................... 50

11.1 Layout Guidelines ................................................. 50

11.2 Layout Example .................................................... 55

11.3 Thermal Considerations........................................ 55

12 Device and Documentation Support................. 56

12.1 Device Support .................................................... 56

12.2 Related Links ........................................................ 58

12.3 Community Resources.......................................... 58

12.4 Trademarks........................................................... 58

12.5 Electrostatic Discharge Caution............................ 58

12.6 Glossary................................................................ 58

13 Mechanical, Packaging, and Orderable

Information........................................................... 58

13.1 Package Option Addendum.................................. 59

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (January 2016) to Revision C Page

• Added DSI pin functions in Pin Functions - DSI Input Data and Clock.................................................................................. 8

• Added DSI Host Timing Requirements ............................................................................................................................... 25

• Updated Input Source........................................................................................................................................................... 28

• Added DSI Interface - Supported Data Transfer Formats.................................................................................................... 30

• Added Display Serial Interface DSI ..................................................................................................................................... 32

• Added 3-D Glasses Operation.............................................................................................................................................. 39

• Added PCB Layout Guidelines for DSI Interface.................................................................................................................. 52

• Added MSL Peak Temp to Packaging Information ............................................................................................................. 59

Changes from Revision A (September 2014) to Revision B Page

• Moved the storage temperature to the Absolute Maximum Ratings table ........................................................................... 14

• Updated the Handling Ratings table to an ESD Ratings table ............................................................................................ 14

• Updated the device markings .............................................................................................................................................. 56

• Added Community Resources ............................................................................................................................................. 58

DLPC3433

DLPC3438

www.ti.com

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

Product Folder Links: DLPC3433 DLPC3438

Changes from Original (February 2014) to Revision A Page

• Changed device status from Product Preview to Production Data and released full version of the document..................... 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DMD_LS_C

DMD_LS_W

DATA

DMD_HS_W

DATAH_P

DMD_HS_W

DATAG_P

DMD_HS_W

DATAF_P

DMD_HS_W

DATAE_P

DMD_HS_CLK_

DMD_HS_W

DATAD_P

DMD_HS_W

DATAC_P

DMD_HS_W

DATAB_P

DMD_HS_W

DATAA_P CMP_OUT SPI0_CLK SPI0_CSZ0 CMP_PW M

DMD_DEN_

ARSTZ

DMD_LS_R

DATA

DMD_HS_W

DATAH_N

DMD_HS_W

DATAG_N

DMD_HS_W

DATAF_N

DMD_HS_W

DATAE_N

DMD_HS_CLK_

DMD_HS_W

DATAD_N

DMD_HS_W

DATAC_N

DMD_HS_W

DATAB_N

DMD_HS_W

DATAA_N SPI0_DIN SPI0_DOUT LED_SEL_1 LED_SEL_0

DD3P DD3N VDDLP12 VSS VDD VSS VCC VSS VCC HWTEST_E

NRESETZ SPI0_CSZ1 PARKZ GPIO_00 GPIO_01

DD2P DD2N VDD VCC VDD VSS VDD VSS VDD VSS VCC_FLSH VDD VDD GPIO_02 GPIO_03

DCLKP DCLKN VDD VSS VCC VSS GPIO_04 GPIO_05

DD1P DD1N RREF VSS V SS VSS VSS VSS V SS VCC VDD GPIO_06 GP IO_07

DD0P DD0N VS S_PLLM VSS VSS VSS VSS VSS VSS VSS VSS GPIO_08 GPIO_09

PLL_REFCL

K_I VDD_PLLM VSS_PLLD VSS VS S VSS VSS VSS VS S VSS VDD GPIO_10 GPIO_11

PLL_REFCL

K_O VDD_PLLD VSS VDD VSS VSS VSS VSS VSS VDD VSS GPIO_12 GPIO_13

PDATA_1 PDATA_0 VDD VSS VSS VSS VSS VSS VSS VSS VCC GPIO_14 GPIO_15

PDATA_3 PDATA_2 VSS VDD VDD VDD GPIO_16 GPIO_17

PDATA_5 PDATA_4 VCC_INTF VSS VSS VDD VCC_INTF VSS VDD VDD VCC VSS JTAGTMS1 GPIO_18 GPIO_19

PDATA_7 PDATA_6 VCC_INTF PDM_CVS_

TE HSYNC_CS 3DR V CC_INTF HOST_IRQ IIC0_SDA IIC0_SCL JTAGTMS2 JTAGTDO2 JTAGTDO1 TSTPT_6 TSTPT_7

VSYNC_WE DATEN_CM

DPCLK PDATA_11 PDATA_13 PDATA_15 PDATA_17 PDATA_19 PDATA_21 PDATA_23 JTAGTRSTZ JTAGTCK JTAGTDI TSTPT_4 TSTPT_5

PDATA_8 PDATA_9 PDATA_10 PDATA_12 PDATA_14 PDATA_16 PDATA_18 PDATA_20 PDATA_22 IIC1_SDA IIC1_SCL TSTPT_0 TSTPT_1 TSTPT_2 TSTPT_3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DMD_LS_C

DMD_LS_W

DATA

DMD_HS_W

DATAH_P

DMD_HS_W

DATAG_P

DMD_HS_W

DATAF_P

DMD_HS_W

DATAE_P

DMD_HS_CLK_

DMD_HS_W

DATAD_P

DMD_HS_W

DATAC_P

DMD_HS_W

DATAB_P

DMD_HS_W

DATAA_P CMP_OUT SPI0_CLK SPI0_CSZ0 CMP_PW M

DMD_DEN_

ARSTZ

DMD_LS_R

DATA

DMD_HS_W

DATAH_N

DMD_HS_W

DATAG_N

DMD_HS_W

DATAF_N

DMD_HS_W

DATAE_N

DMD_HS_CLK_

DMD_HS_W

DATAD_N

DMD_HS_W

DATAC_N

DMD_HS_W

DATAB_N

DMD_HS_W

DATAA_N SPI0_DIN SPI0_DOUT LED_SEL_1 LED_SEL_0

DD3P DD3N VDDLP12 VSS VDD VSS VCC VSS VCC HWTEST_E

NRESETZ SPI0_CSZ1 PARKZ GPIO_00 GPIO_01

DD2P DD2N VDD VCC VDD VSS V DD VSS VDD VSS VCC_FLSH VDD VDD GPIO_02 GPIO_03

DCLKP DCLKN VDD VSS VCC VSS GPIO_04 GPIO_05

DD1P DD1N RREF VSS VCC VDD GPIO_06 GPIO_07

DD0P DD0N VS S_PLLM VSS VSS VSS GPIO_08 GPIO_09

PLL_REFCL

K_I VDD_PLLM VSS_PLLD VSS VSS VDD GPIO_10 GP IO_11

PLL_REFCL

K_O VDD_PLLD VSS VDD VDD VSS GPIO_12 GPIO_13

PDATA_1 PDATA_0 VDD V SS VSS VCC GPIO_14 GPIO_15

PDATA_3 PDATA_2 VSS VDD V DD VDD GPIO_16 GPIO_17

PDATA_5 PDATA_4 VCC_INTF VSS VSS VDD VCC_INTF VSS VDD VDD VCC VSS JTAGTMS1 GPIO_18 GPIO_19

PDATA_7 PDATA_6 VCC_INTF PDM_CVS_

TE HSYNC_CS 3DR VCC_INTF HOST_IRQ IIC0_SDA IIC0_SCL JTAGTMS2 JTAGTDO2 JTAGTDO1 TSTPT_6 TSTPT_7

VSYNC_WE DATEN_CM

DPCLK PDATA_11 PDATA_13 PDATA_15 PDATA_17 PDATA_19 PDATA_21 PDATA_23 JTAGTRSTZ JTAGTCK JTAGTDI TSTPT_4 TSTPT_5

PDATA_8 PDATA_9 PDATA_10 PDATA_12 PDATA_14 PDATA_16 PDATA_18 PDATA_20 PDATA_22 IIC1_SDA IIC1_SCL TSTPT_0 TSTPT_1 TSTPT_2 TSTPT_3

DLPC3433

DLPC3438

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

www.ti.com

Product Folder Links: DLPC3433 DLPC3438

5 Pin Configuration and Functions

ZVB Package

176-Pin NFBGA

Bottom View

ZEZ Package

201-Pin NFBGA

Bottom View

Figure 1. DLPC3433 7- × 7-mm Package – VF Ball

Grid Array

Figure 2. DLPC3438 7- × 7-mm Package – VF Ball

Grid Array

Pin Functions – Board Level Test, Debug, and Initialization

PIN I/O DESCRIPTION

NAME NUMBER

HWTEST_EN C10 I6Manufacturing test enable signal. This signal should be connected directly to ground on the

PCB for normal operation.

DLPC3433

DLPC3438

www.ti.com

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

Product Folder Links: DLPC3433 DLPC3438

Pin Functions – Board Level Test, Debug, and Initialization (continued)

PIN I/O DESCRIPTION

NAME NUMBER

(1) If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor,

then this I/O can be left open or unconnected for normal operation. If operation does not call for an external pullup, but there is external

logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.

(2) External pullup resistor must be 8 kΩ, or less, for pins with internal pullup or down resistors.

(3) If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor,

then the TSTPT I/O can be left open/ unconnected for normal operation. If operation does not call for an external pullup, but there is

external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a

logic low.

PARKZ C13 I6

DMD fast PARK control (active low Input) (hysteresis buffer). PARKZ must be set high to

enable normal operation. PARKZ should be set high prior to releasing RESETZ (that is, prior to

the low-to-high transition on the RESETZ input). PARKZ should be set low for a minimum of 32

µs before any power is removed from the DLPC343x such that the fast DMD PARK operation

can be completed. Note for PARKZ, fast PARK control should only be used when loss of power

is eminent and beyond the control of the host processor (for example, when the external power

source has been disconnected or the battery has dropped below a minimum level). The longest

lifetime of the DMD may not be achieved with the fast PARK operation. The longest lifetime is

achieved with a normal PARK operation. Because of this, PARKZ is typically used in

conjunction with a normal PARK request control input through GPIO_08. The difference being

that when the host sets PROJ_ON low, which connects to both GPIO_08 and the DLPA200x or

DLPA3000 PMIC chip, the DLPC343x takes much longer than 32 µs to park the mirrors. The

DLPA200x or DLPA3000 holds on all power supplies, and keep RESETZ high, until the longer

mirror parking has completed. This longer mirror parking time, of up to 500 µs, ensures the

longest DMD lifetime and reliability.

The DLPA200x or DLPA3000 monitors power to the DLPC343x and detects an eminent power

loss condition and drives the PARKZ signal accordingly.

Reserved P12 I6TI internal use. Should be left unconnected.

Reserved P13 I6TI internal use. Should be left unconnected.

Reserved N13(1) O1TI internal use. Should be left unconnected.

Reserved N12(1) O1TI internal use. Should be left unconnected.

Reserved M13 I6TI internal use. Should be left unconnected.

Reserved N11 I6TI internal use. Should be left unconnected.

Reserved P11 I6TI internal use

This pin must be tied to ground, through an external 8-kΩ, or less, resistor for normal operation.

Failure to tie this pin low during normal operation will cause startup and initialization problems.

RESETZ C11 I6

DLPC343x power-on reset (active low input) (hysteresis buffer). Self-configuration starts when a

low-to-high transition is detected on RESETZ. All ASIC power and clocks must be stable before

this reset is de-asserted. Note that the following signals will be tri-stated while RESETZ is

asserted:

SPI0_CLK, SPI0_DOUT, SPI0_CSZ0,

SPI0_CSZ1, and GPIO(19:00)

External pullups or downs (as appropriate) should be added to all tri-stated output signals listed

(including bidirectional signals to be configured as outputs) to avoid floating ASIC outputs

during reset if connected to devices on the PCB that can malfunction. For SPI, at a minimum,

any chip selects connected to the devices should have a pullup.

Unused bidirectional signals can be functionally configured as outputs to avoid floating ASIC

inputs after RESETZ is set high.

The following signals are forced to a logic low state while RESETZ is asserted and

corresponding I/O power is applied:

LED_SEL_0, LED_SEL_1 and DMD_DEN_ARSTZ

No signals will be in their active state while RESETZ is asserted.

Note that no I2C activity is permitted for a minimum of 500 ms after RESETZ (and PARKZ) are

set high.

TSTPT_0 R12 B1

Test pin 0 (includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ, and then driven as an output.

Normal use: reserved for test output. Should be left open for normal use.

Note: An external pullup should not be applied to this pin to avoid putting the DLPC343x in a

test mode.

Without external pullup (2)

Feeds TMSEL(0) With external pullup(3)

Feeds TMSEL(0)

DLPC3433

DLPC3438

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

www.ti.com

Product Folder Links: DLPC3433 DLPC3438

Pin Functions – Board Level Test, Debug, and Initialization (continued)

PIN I/O DESCRIPTION

NAME NUMBER

TSTPT_1 R13 B1

Test pin 1 (includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Normal use: reserved for test output. Should be left open for normal use.

Note: An external pullup should not be applied to this pin to avoid putting the DLPC343x in a

test mode.

Without external pullup(2)

Feeds TMSEL(1) With external pullup(3)

Feeds TMSEL(1)

TSTPT_2 R14 B1

Test pin 2 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Normal use: reserved for test output. Should be left open for normal use.

Note: An external pullup should not be applied to this pin to avoid putting the DLPC343x in a

test mode.

Without external pullup(2)

Feeds TMSEL(2) With external pullup(3)

Feeds TMSEL(2)

TSTPT_3 R15 B1

Test pin 3 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Normal use: reserved for for test output. Should be left open for normal use.

TSTPT_4 P14 B1

Test pin 4 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Normal use: reserved for test output. Should be left open for normal use.

TSTPT_5 P15 B1

Test pin 5 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Normal use: reserved for test output. Should be left open or unconnected for normal use.

TSTPT_6 N14 B1

Test pin 6 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Normal use: reserved for test output. should be left open for normal use.

Alternative use: none. External logic shall not unintentionally pull this pin high to avoid putting

the DLPC343x in a test mode.

TSTPT_7 N15 B1

Test pin 7 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.

Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of

RESETZ and then driven as an output.

Normal use: reserved for test output. should be left open for normal use.

DLPC3433

DLPC3438

www.ti.com

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

Product Folder Links: DLPC3433 DLPC3438

(1) PDATA(23:0) bus mapping is pixel format and source mode dependent. See later sections for details.

(2) PDM_CVS_TE is optional for parallel interface operation. If unused, inputs should be grounded or pulled down to ground through an

external resistor (8 kΩor less).

(3) Pixel clock capture edge is software programmable.

(4) The parallel data mask signal input is optional for parallel interface operations. If unused, inputs should be grounded or pulled down to

ground through an external resistor (8 kΩor less).

(5) Unused inputs should be grounded or pulled down to ground through an external resistor (8 kΩor less).

(6) VSYNC, HSYNC, and DATAEN polarity is software programmable.

Pin Functions – Parallel Port Input Data and Control(1)(2)

PIN I/O DESCRIPTION

NAME NUMBER PARALLEL RGB MODE BT656 INTERFACE MODE

PCLK P3 I11 Pixel clock(3) Pixel clock(3)

PDM_CVS_TE N4 B5Parallel data mask(4) Unused(5)

VSYNC_WE P1 I11 Vsync(6) Unused(5)

HSYNC_CS N5 I11 Hsync(6) Unused(5)

DATAEN_CMD P2 I11 Data Valid(6) Unused(5)

(TYPICAL RGB 888)

PDATA_0

PDATA_1

PDATA_2

PDATA_3

PDATA_4

PDATA_5

PDATA_6

PDATA_7

I11

Blue (bit weight 1)

Blue (bit weight 2)

Blue (bit weight 4)

Blue (bit weight 8)

Blue (bit weight 16)

Blue (bit weight 32)

Blue (bit weight 64)

Blue (bit weight 128)

BT656_Data (0)

BT656_Data (1)

BT656_Data (2)

BT656_Data (3)

BT656_Data (4)

BT656_Data (5)

BT656_Data (6)

BT656_Data (7)

(TYPICAL RGB 888)

PDATA_8

PDATA_9

PDATA_10

PDATA_11

PDATA_12

PDATA_13

PDATA_14

PDATA_15

I11

Green (bit weight 1)

Green (bit weight 2)

Green (bit weight 4)

Green (bit weight 8)

Green (bit weight 16)

Green (bit weight 32)

Green (bit weight 64)

Green (bit weight 128)

Unused

(TYPICAL RGB 888)

PDATA_16

PDATA_17

PDATA_18

PDATA_19

PDATA_20

PDATA_21

PDATA_22

PDATA_23

P10

I11

Red (bit weight 1)

Red (bit weight 2)

Red (bit weight 4)

Red (bit weight 8)

Red (bit weight 16)

Red (bit weight 32)

Red (bit weight 64)

Red (bit weight 128)

Unused

3DR N6

3D reference

• For 3D applications: left or right 3D reference (left = 1, right = 0). To be provided by the

host when a 3D command is not provided. Must transition in the middle of each frame

(no closer than 1 ms to the active edge of VSYNC)

• If a 3D application is not used, then this input should be pulled low through an external

resistor.

DLPC3433

DLPC3438

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

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Product Folder Links: DLPC3433 DLPC3438

(1) For DSI, Differential Data Bus(0) is required for DSI operation with the remaining 3 data lanes being optional/ implementation specific as

needed. Any unused DSI LVDS pairs should be unconnected and left floating.

(2) RREF is an analog signal that requires a fixed precision resistor connected to this pin when DSI is utilized. If DSI is NOT utilized then

this signal should be unconnected and left floating on the board design.

Pin Functions - DSI Input Data and Clock

Added PIN I/O DESCRIPTION

NAME NUMBER MIPI DSI MODE

DCLKN

DCLKP E2

E1 B10 DSI Interface; DSI - LVDS Differential Clock

DD0N

DD0P

DD1N

DD1P

DD2N

DD2P

DD3N

DD3P

B10 DSI Interface, DSI Data Lane LVDS Differential Pair inputs 0-> 3

(Support a maximum of 4 input DSI Lanes)(1)

RREF F3 DSI Reference Resistor A 30k Ohm +/- 1% external trim resistor

should be connected from this pin to ground(2)

Pin Functions – DMD Reset and Bias Control

PIN I/O DESCRIPTION

NAME NUMBER

DMD_DEN_ARSTZ B1 O2

DMD driver enable (active high)/ DMD reset (active low). Assuming the

corresponding I/O power is supplied, this signal will be driven low after the DMD is

parked and before power is removed from the DMD. If the 1.8-V power to the

DLPC343x is independent of the 1.8-V power to the DMD, then TI recommends a

weak, external pulldown resistor to hold the signal low in the event DLPC343x

power is inactive while DMD power is applied.

DMD_LS_CLK A1 O3DMD, low speed interface clock

DMD_LS_WDATA A2 O3DMD, low speed serial write data

DMD_LS_RDATA B2 I6DMD, low speed serial read data

Pin Functions – DMD Sub-LVDS Interface

PIN I/O DESCRIPTION

NAME NUMBER

DMD_HS_CLK_P

DMD_HS_CLK_N A7

B7 O4DMD high speed interface

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

A10

B10

A11

B11

O4DMD high speed interface lanes, write data bits: (The true numbering and

application of the DMD_HS_DATA pins are software configuration dependent)

DLPC3433

DLPC3438

www.ti.com

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

Product Folder Links: DLPC3433 DLPC3438

(1) External pullup resistor must be 8 kΩor less.

(2) For more information about usage, see HOST_IRQ Usage Model.

Pin Functions – Peripheral Interface(1)

PIN I/O DESCRIPTION

NAME NUMBER

CMP_OUT A12 I6

Successive approximation ADC comparator output (DLPC343x Input). Assumes a successive

approximation ADC is implemented with a WPC light sensor and/or a thermistor feeding one input of

an external comparator and the other side of the comparator is driven from the ASIC’s CMP_PWM pin.

Should be pulled-down to ground if this function is not used. (hysteresis buffer)

CMP_PWM A15 O1Successive approximation comparator pulse-duration modulation (output). Supplies a PWM signal to

drive the successive approximation ADC comparator used in WPC light-to-voltage sensor applications.

Should be left unconnected if this function is not used.

HOST_IRQ(2) N8 O9

Host interrupt (output)

HOST_IRQ indicates when the DLPC343x auto-initialization is in progress and most importantly when

it completes.

The DLPC343x tri-states this output during reset and assumes that an external pullup is in place to

drive this signal to its inactive state.

IIC0_SCL N10 B7

I2C slave (port 0) SCL (bidirectional, open-drain signal with input hysteresis): An external pullup is

required. The slave I2C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by VCC_INTF

(which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to an equal or higher supply

voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH

specification of the slave I2C input buffers).

Reserved R11 B8TI internal use. TI recommends an external pullup resistor.

IIC0_SDA N9 B7

I2C slave (port 0) SDA. (bidirectional, open-drain signal with input hysteresis): An external pullup is

required. The slave I2C port is the control port of ASIC. The slave I2C I/Os are 3.6-V tolerant (high-volt-

input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups

must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup

supply voltage would not likely satisfy the VIH specification of the slave I2C input buffers).

Reserved R10 B8TI internal use. TI recommends an external pullup resistor.

LED_SEL_0 B15 O1

LED enable select. Controlled by programmable DMD sequence

Timing

LED_SEL(1:0)

Enabled LED

DLPA200x / DLPA3000 application

None

Red

Green

Blue

LED_SEL_1 B14 O1

These signals will be driven low when RESETZ is asserted and the corresponding I/O power is

supplied. They will continue to be driven low throughout the auto-initialization process. A weak,

external pulldown resistor is still recommended to ensure that the LEDs are disabled when I/O power is

not applied.

SPI0_CLK A13 O13 Synchronous serial port 0, clock

SPI0_CSZ0 A14 O13 SPI port 1, chip select 0 (active low output)

TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during

ASIC reset assertion.

SPI0_CSZ1 C12 O13 SPI port 1, chip select 1 (active low output)

TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during

ASIC reset assertion.

SPI0_DIN B12 I12 Synchronous serial port 0, receive data in

SPI0_DOUT B13 O13 Synchronous serial port 0, transmit data out

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(1) GPIO signals must be configured through software for input, output, bidirectional, or open-drain. Some GPIO have one or more

alternative use modes, which are also software configurable. The reset default for all GPIO is as an input signal. An external pullup is

required for each signal configured as open-drain.

(2) DLPC343x general purpose I/O. These GPIO are software configurable.

Pin Functions – GPIO Peripheral Interface(1)

PIN I/O DESCRIPTION(2)

NAME NUMBER

GPIO_19 M15 B1

General purpose I/O 19 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

2. MTR_SENSE, Motor Sense (Input): For Focus Motor control applications, this GPIO must be

configured as an input to the DLPC343x fed from the focus motor position sensor.

3. KEYPAD_4 (input): keypad applications

GPIO_18 M14 B1

General purpose I/O 18 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

2. KEYPAD_3 (input): keypad applications

GPIO_17 L15 B1

General purpose I/O 17 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

2. KEYPAD_2 (input): keypad applications

GPIO_16 L14 B1

General purpose I/O 16 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

2. KEYPAD_1 (input): keypad applications

GPIO_15 K15 B1

General purpose I/O 15 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

2. KEYPAD_0 (input): keypad applications

GPIO_14 K14 B1

General purpose I/O 14 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_13 J15 B1

General purpose I/O 13 (hysteresis buffer). Options:

1. CAL_PWR (output): Intended to feed the calibration control of the successive approximation ADC

light sensor.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_12 J14 B1

General purpose I/O 12 (hysteresis buffer). Options:

1. (Output) power enable control for LABB light sensor.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_11 H15 B1

General purpose I/O 11 (hysteresis buffer). Options:

1. (Output): thermistor power enable.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_10 H14 B1

General Purpose I/O 10 (hysteresis buffer). Options:

1. RC_CHARGE (output): Intended to feed the RC charge circuit of the successive approximation ADC

used to control the light sensor comparator.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_09 G15 B1

General purpose I/O 09 (hysteresis buffer). Options:

1. LS_PWR (active high output): Intended to feed the power control signal of the successive

approximation ADC light sensor.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

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Pin Functions – GPIO Peripheral Interface(1) (continued)

PIN I/O DESCRIPTION(2)

NAME NUMBER

GPIO_08 G14 B1

General purpose I/O 08 (hysteresis buffer). Options:

1. (All) Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A

logic low on this signal will cause the DLPC343x to PARK the DMD, but it will not power down the

DMD (the DLPA200x does that instead). The minimum high time is 200 ms. The minimum low time is

also 200 ms.

GPIO_07 F15 B1

General purpose I/O 07 (hysteresis buffer). Options:

1. (Output): LABB output sample and hold sensor control signal.

2. (All) GPIO (bidirectional): Optional GPIO. Should be configured as a logic zero GPIO output and left

unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating

GPIO input).

GPIO_06 F14 B1

General purpose I/O 06 (hysteresis buffer). Option:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used.

An external pulldown resistor is required to deactivate this signal during reset and auto-initialization

processes.

GPIO_05 E15 B1

General purpose I/O 05 (hysteresis buffer). Options:

1. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_04 E14 B1

General purpose I/O 04 (hysteresis buffer). Options:

1. 3D glasses control (output): intended to be used to control the shutters on 3D glasses (Left = 1, Right

= 0).

2. SPI1_CSZ1 (active-low output): optional SPI1 chip select 1 signal. An external pullup resistor is

required to deactivate this signal during reset and auto-initialization processes.

3. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_03 D15 B1

General purpose I/O 03 (hysteresis buffer). Options:

1. SPI1_CSZ0 (active low output): Optional SPI1 chip select 0 signal. An external pullup resistor is

required to deactivate this signal during reset and auto-initialization processes.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

GPIO_02 D14 B1

General purpose I/O 02 (hysteresis buffer). Options:

1. SPI1_DOUT (output): Optional SPI1 data output signal.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

3. DSI Bus Width Config 1 (input): This GPIO is sampled during boot and is used to define the number

of lanes to be used for DSI operation. An external pull-up or pull-down must be used to select the

desired configuration as defined in Table 1. After Boot, this GPIO can be used for other operation as

long as the external pull-up/down doesn't interfere.

GPIO_01 C15 B1

General purpose I/O 01 (hysteresis buffer). Options:

1. SPI1_CLK (output): Optional SPI1 clock signal.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

3. DSI Bus Width Config 1 (input): This GPIO is sampled during boot and is used to define the number

of lanes to be used for DSI operation. An external pull-up or pull-down must be used to select the

desired configuration as defined in Table 1. After Boot, this GPIO can be used for other operation as

long as the external pull-up/down doesn't interfere.

GPIO_00 C14 B1

General purpose I/O 00 (hysteresis buffer). Options:

1. SPI1_DIN (input): Optional SPI1 data input signal.

2. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used

(otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).

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Table 1. GPIO_01 and GPIO_02

GPIO_02 GPIO_01 Number of DSI Data

Lanes

DSI-Lane-Config_1 DSI-Lane-Config_0

001

012

103

114

Pin Functions – Clock and PLL Support

PIN I/O DESCRIPTION

NAME NUMBER

PLL_REFCLK_I H1 I11 Reference clock crystal input. If an external oscillator is used in place of a crystal, then this pin

should be used as the oscillator input.

PLL_REFCLK_O J1 O5Reference clock crystal return. If an external oscillator is used in place of a crystal, then this pin

should be left unconnected (that is floating with no added capacitive load).

(1) The only power sequencing restrictions are:

(a) The DSI-PHY LP supply must sequence ON after the 1.1V core supply and must sequence OFF before the 1.1V core supply when

fed from a separate (from VDD) supply

(b) The VDD supply should ramp up with a 1-ms minimum rise time.

(2) It is recommended that VDDLP12 rail is tied to the VDD rail. The DSI LP supply (VDDLP12) is only used for read responses from the

ASIC which are not supported. As such, there is no need to provide a separate 1.2V rail. If a separate 1.2V supply is already being used

to power this rail, a voltage tolerance of ±6.67% is allowed on this separate 1.2V supply.

Pin Functions – Power and Ground(1)

PIN I/O DESCRIPTION

NAME NUMBER

VDD C5, D5, D7, D12, J4, J12, K3, L4, L12, M6,

M9, D9, D13, F13, H13, L13, M10, D3, E3 PWR Core power 1.1 V (main 1.1 V)

VDDLP12 C3 PWR DSI PHY Low Power mode driver supply (2)

VSS

Common to all package types

C4, D6, D8, D10, E4, E13, F4, G4, G12, H4,

H12, J3, J13, K4, K12, L3, M4, M5, M8, M12,

G13, C6, C8

Only available on DLPC343x

F6, F7, F8, F9, F10, G6, G7, G8, G9, G10,

H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6,

K7, K8, K9, K10

GND Core ground (eDRAM, I/O ground, thermal ground)

VCC18 C7, C9, D4, E12, F12, K13, M11 PWR All 1.8-V I/O power:

(1.8-V power supply for all I/O other than the host or parallel

interface and the SPI flash interface. This includes RESETZ,

PARKZ LED_SEL, CMP, GPIO, IIC1, TSTPT, and JTAG pins)

VCC_INTF M3, M7, N3, N7 PWR Host or parallel interface I/O power: 1.8 to 3.3 V (Includes IIC0,

PDATA, video syncs, and HOST_IRQ pins)

VCC_FLSH D11 PWR Flash interface I/O power:1.8 to 3.3 V

(Dedicated SPI0 power pin)

VDD_PLLM H2 PWR MCG PLL 1.1-V power

VSS_PLLM G3 RTN MCG PLL return

VDD_PLLD J2 PWR DCG PLL 1.1-V power

VSS_PLLD H3 RTN DCG PLL return

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Table 2. I/O Type Subscript Definition

I/O SUPPLY REFERENCE ESD STRUCTURE

SUBSCRIPT DESCRIPTION

1 1.8 LVCMOS I/O buffer with 8-mA drive Vcc18 ESD diode to GND and supply rail

2 1.8 LVCMOS I/O buffer with 4-mA drive Vcc18 ESD diode to GND and supply rail

3 1.8 LVCMOS I/O buffer with 24-mA drive Vcc18 ESD diode to GND and supply rail

4 1.8 sub-LVDS output with 4-mA drive Vcc18 ESD diode to GND and supply rail

5 1.8, 2.5, 3.3 LVCMOS with 4-mA drive Vcc_INTF ESD diode to GND and supply rail

6 1.8 LVCMOS input Vcc18 ESD diode to GND and supply rail

7 1.8-, 2.5-, 3.3-V I2C with 3-mA drive Vcc_INTF ESD diode to GND and supply rail

8 1.8-V I2C with 3-mA drive Vcc18 ESD diode to GND and supply rail

9 1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive Vcc_INTF ESD diode to GND and supply rail

10 DSI LVDS DPHY I/O VDD / VDDLP12 ESD diode to GND and supply rail

11 1.8, 2.5, 3.3 LVCMOS input Vcc_INTF ESD diode to GND and supply rail

12 1.8-, 2.5-, 3.3-V LVCMOS input Vcc_FLSH ESD diode to GND and supply rail

13 1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive Vcc_FLSH ESD diode to GND and supply rail

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(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended

operating conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) Overlap currents, if allowed to continue flowing unchecked, not only increase total power dissipation in a circuit, but degrade the circuit

reliability, thus shortening its usual operating life.

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature (unless otherwise noted) MIN MAX UNIT

SUPPLY VOLTAGE(2)(3)

V(VDD) (core) –0.3 1.21 V

V(VDDLP12) (core) –0.3 1.32 V

Power + sub-LVDS –0.3 1.96 V

V(VCC_INTF)

Host I/O power –0.3 3.60

If 1.8-V power used –0.3 1.99

If 2.5-V power used –0.3 2.75

If 3.3-V power used –0.3 3.60

V(VCC_FLSH)

Flash I/O power –0.3 3.60

If 1.8-V power used –0.3 1.96

If 2.5-V power used –0.3 2.72

If 3.3-V power used –0.3 3.58

V(VDD_PLLM) (MCG PLL) –0.3 1.21 V

V(VDD_PLLD) (1DCG PLL) –0.3 1.21 V

GENERAL

TJOperating junction temperature –30 125 °C

Tstg Storage temperature –40 125 °C

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD)(1) Electrostatic

discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) ±2000 V

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3) ±500

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(1) It is recommended that VDDLP12 rail is tied to the VDD rail. The DSI LP supply (VDDLP12) is only used for read responses from the

ASIC which are not supported. As such, there is no need to provide a separate 1.2V rail. If a separate 1.2V supply is already being used

to power this rail, a voltage tolerance of ±6.67% is allowed on this separate 1.2V supply.

(2) When the DSI-PHY LP supply (VDDLP12) is fed from a separate (from VDD) supply, the VDDLP12 power must sequence ON after the

1.1V core supply and must sequence OFF before the 1.1V core supply.

(3) These supplies have multiple valid ranges.

(4) These I/O supply ranges are wider to facilitate additional filtering.

(5) The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value at

0 forced air flow (RθJA at 0 m/s), a JEDEC JESD51 standard test card and environment, along with min and max estimated power

dissipation across process, voltage, and temperature. Thermal conditions vary by application, which will impact RθJA. Thus, maximum

operating ambient temperature varies by application.

(a) Ta_min = Tj_min – (Pd_min × RθJA) = –30°C – (0.0W × 30.3°C/W) = –30°C

(b) Ta_max = Tj_max – (Pd_max × RθJA) = +105°C – (0.348W × 30.3°C/W) = +94.4°C

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

V(VDD) Core power 1.1 V (main 1.1 V) ±5% tolerance 1.045 1.1 1.155 V

V(VDDLP12) DSI PHY Low Power mode driver supply ±5% tolerance

See (1)(2) 1.045 1.10 1.155 V

V(VCC18)

All 1.8-V I/O power:

(1.8-V power supply for all I/O other than the host or

parallel interface and the SPI flash interface. This

includes RESETZ, PARKZ LED_SEL, CMP, GPIO,

IIC1, TSTPT, and JTAG pins.)

±8.5% tolerance 1.64 1.8 1.96 V

V(VCC_INTF) Host or parallel interface I/O power: 1.8 to 3.3 V

(includes IIC0, PDATA, video syncs, and HOST_IRQ

pins) ±8.5% tolerance

See (3)

1.64 1.8 1.96 V2.28 2.5 2.72

3.02 3.3 3.58

V(VCC_FLSH) Flash interface I/O power:1.8 to 3.3 V ±8.5% tolerance

See (3)

1.64 1.8 1.96 V2.28 2.5 2.72

3.02 3.3 3.58

V(VDD_PLLM) MCG PLL 1.1-V power ±9.1% tolerance

See (4) 1.025 1.1 1.155 V

V(VDD_PLLD) DCG PLL 1.1-V power ±9.1% tolerance

See (4) 1.025 1.1 1.155 V

TAOperating ambient temperature range(5) –30 85 °C

TJOperating junction temperature –30 105 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Thermal coefficients abide by JEDEC Standard 51. RθJA is the thermal resistance of the package as measured using a JEDEC defined

standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC343x PCB and thus the reported thermal

resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different , it is the best

information available during the design phase to estimate thermal performance.

(3) Example: (0.5 W) × (0.2 C/W) ≈1.00°C temperature rise.

6.4 Thermal Information

THERMAL METRIC(1) DLPC343x

UNITZEZ (NFBGA) ZVB (NFBGA)

201 PINS 176 PINS

RθJC Junction-to-case thermal resistance 10.1 11.2 °C/W

RθJA Junction-to-air thermal resistance at 0 m/s of forced airflow(2) 28.8 30.3 °C/W

at 1 m/s of forced airflow(2) 25.3 27.4 °C/W

at 2 m/s of forced airflow(2) 24.4 26.6 °C/W

ψJT(3) Temperature variance from junction to package top center temperature, per

unit power dissipation .23 .27 °C/W

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(1) Assumes 12.5% activity factor, 30% clock gating on appropriate domains, and mixed SVT or HVT cells

(2) Programmable host and flash I/O are at minimum voltage (that is 1.8 V) for this typical scenario.

(3) Max currents column use typical motion video as the input. The typical currents column uses SMPTE color bars as the input.

(4) Some applications (that is, high-resolution 3D) may be forced to use 1-oz copper to manage ASIC package heat.

(5) Input image is 1280 × 720 (720p) 24-bits on the parallel interface at the frame rate shown with a 0.3-inch 720p DMD.

(6) In normal operation while displaying an image with CAIC enabled.

(7) Assumes typical case power PVT condition = nominal process, typical voltage, typical temperature (55°C junction). 720p resolution.

(8) Assumes worse case power PVT condition = corner process, high voltage, high temperature (105°C junction), 720p resolution.

6.5 Electrical Characteristics over Recommended Operating Conditions (1)(2)(3)(4)

PARAMETER TEST CONDITIONS(5)(6) MIN TYP(7) MAX(8) UNIT

V(VDD) +

V(VDDLP12) Core current 1.1 V (main 1.1 V) IDLE disabled, 720p, 60 Hz 161 334 mA

IDLE disabled, 720p, 120 Hz 185 368

V(VDD_PLLM) MCG PLL 1.1 V current IDLE disabled, 720p, 60 Hz 4 7 mA

IDLE disabled, 720p, 120 Hz 4 7

V(VDD_PLLD) DCG PLL 1.1 V current IDLE disabled, 720p, 60 Hz 4 7 mA

IDLE disabled, 720p, 120 Hz 4 7

V(VDD) +

V(VDD_PLLM)

+ V(VDD_PLLD) Core Current 1.1 V + MCG PLL 1.1 V

current + DCG PLL 1.1 V current IDLE disabled, 720p, 60 Hz 169 348 mA

IDLE disabled, 720p, 120 Hz 193 382

V(VCC18)

Main 1.8 V I/O current: 1.8 V power

supply for all I/O other than the host or

parallel interface and the SPI flash

interface. IDLE disabled, 720p, 60 Hz 13 18

This includes sub-LVDS DMD I/O ,

RESETZ, PARKZ, LED_SEL, CMP,

GPIO, IIC1, TSTPT and JTAG pins

SPACE

IDLE disabled, 720p, 120 Hz

SPACE 13 18

V(VCC_INTF) Host or parallel interface I/O current:

1.8 to 3.3 V ( includes IIC0, PDATA,

video syncs, and HOST_IRQ pins)

IDLE disabled, 720p, 60 Hz 2 3 mA

IDLE disabled, 720p, 120 Hz 4 6

V(VCC_FLSH) Flash interface I/O current: 1.8 to 3.3 V IDLE disabled, 720p, 60 Hz 1 1.5 mA

IDLE disabled, 720p, 120 Hz 1 1.5

V(VCC18) +

V(VCC_INTF) +

V(VCC_FLSH)

Main 1.8 V I/O current + VCC_INTF

current + VCC_FLSH current IDLE disabled, 720p, 60 Hz 16 22.5 mA

IDLE disabled, 720p, 120 Hz 18 25.5

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(1) I/O is high voltage tolerant; that is, if VCC = 1.8 V, the input is 3.3-V tolerant, and if VCC = 3.3 V, the input is 5-V tolerant.

(2) ASIC pins: CMP_OUT; PARKZ; RESETZ; GPIO_00 through GPIO_19 have slightly varied VIH and VIL range from other 1.8-V I/O.

(3) The number inside each parenthesis for the I/O refers to the type defined in Table 2.

6.6 Electrical Characteristics(1)(2)

over operating free-air temperature range (unless otherwise noted)

PARAMETER(3) TEST CONDITIONS MIN TYP MAX UNIT

VIH

High-level

input

threshold

voltage

I2C buffer (I/O type 7) 0.7 × VCC_INTF (1)

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 1.17 3.6

1.8-V LVTTL (I/O type 1, 6)

identified below: (2)

CMP_OUT; PARKZ; RESETZ;

GPIO 0 →19 1.3 3.6

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13) 1.7 3.6

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13) 2 3.6

VIL

Low-level

input

threshold

voltage

I2C buffer (I/O type 7) –0.5 0.3 × VCC_INTF

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) –0.3 0.63

1.8-V LVTTL (I/O type 1, 6)

identified below: (2)

CMP_OUT; PARKZ; RESETZ;

GPIO_00 through GPIO_19 –0.3 0.5

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13) –0.3 0.7

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13) –0.3 0.8

VCM Steady-state

common

mode voltage 1.8 sub-LVDS (DMD high speed)

(I/O type 4) 0.8 0.9 1 mV

ǀVODǀDifferential

output

magnitude 1.8 sub-LVDS (DMD high speed)

(I/O type 4) 200 mV

VOH High-level

output

voltage

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 1.35

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13) 1.7

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13) 2.4

1.8 sub-LVDS – DMD high

speed (I/O type 4) 1

VOL Low-level

output

voltage

I2C buffer (I/O type 7) VCC_INTF > 2 V 0.4

I2C buffer (I/O type 7) VCC_INTF < 2 V 0.2 × VCC_INTF

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 0.45

2.5 V LVTTL (I/O type 5, 9, 11,

12, 13) 0.7

3.3 V LVTTL (I/O type 5, 9, 11,

12, 13) 0.4

1.8 sub-LVDS – DMD high

speed (I/O type 4) 0.8

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Electrical Characteristics(1)(2) (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER(3) TEST CONDITIONS MIN TYP MAX UNIT

IOH High-level

output

current

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 4 mA 2

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 8 mA 3.5

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 24 mA 10.6

2.5-V LVTTL (I/O type 5) 4 mA 5.4

2.5-V LVTTL (I/O type 9, 13) 8 mA 10.8

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13) 24 mA 28.7

3.3-V LVTTL (I/O type 5 ) 4 mA 7.8

3.3-V LVTTL (I/O type 9, 13) 8 mA 15

IOL Low-level

output

current

I2C buffer (I/O type 7) 3

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 4 mA 2.3

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 8 mA 4.6

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 24 mA 13.9

2.5-V LVTTL (I/O type 5) 4 mA 5.2

2.5-V LVTTL (I/O type 9, 13) 8 mA 10.4

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13) 24 mA 31.1

3.3-V LVTTL (I/O type 5 ) 4 mA 4.4

3.3-V LVTTL (I/O type 9, 13) 8 mA 8.9

IOZ

High-

impedance

leakage

current

I2C buffer (I/O type 7) 0.1 × VCC_INTF < VI

< 0.9 × VCC_INTF –10 10

µA

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) –10 10

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13) –10 10

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13) –10 10

Input

capacitance

(including

package)

I2C buffer (I/O type 7) 5

1.8-V LVTTL (I/O type 1, 2, 3, 5,

6, 8, 9, 11, 12, 13) 2.6 3.5

2.5-V LVTTL (I/O type 5, 9, 11,

12, 13) 2.6 3.5

3.3-V LVTTL (I/O type 5, 9, 11,

12, 13) 2.6 3.5

1.8 sub-LVDS – DMD high

speed (I/O type 4) 3

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(1) The resistance is dependent on the supply voltage level applied to the I/O.

(2) An external 8-kΩpullup or pulldown (if needed) would work for any voltage condition to correctly pull enough to override any associated

internal pullups or pulldowns.

Table 3. Internal Pullup and Pulldown Characteristics(1)(2)

INTERNAL PULLUP AND PULLDOWN RESISTOR

CHARACTERISTICS VCCIO MIN MAX UNIT

Weak pullup resistance 3.3 V 29 63 kΩ

2.5 V 38 90 kΩ

1.8 V 56 148 kΩ

Weak pulldown resistance 3.3 V 30 72 kΩ

2.5 V 36 101 kΩ

1.8 V 52 167 kΩ

20%

80% tFtR

+ Vod

- Vod

Vod

Differential Output Signal

(Note Vcm is removed when the signals are viewed differentially)

|Vod|

Vcm

Vcm(ûpp) Vcm(ûss)

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(1) Definition of VCM changes: \

(2) Note that VOD is the differential voltage swing measured across a 100-Ωtermination resistance connected directly between the

transmitter differential pins. |VOD| is the magnitude of this voltage swing relative to 0. Rise and fall times are defined for the differential

VOD signal as follows:

6.7 High-Speed Sub-LVDS Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN NOM MAX UNIT

VCM Steady-state common mode voltage 0.8 0.9 1.0 V

VCM (Δpp)(1) VCM change peak-to-peak (during switching) 75 mV

VCM (Δss)(1) VCM change steady state –10 10 mV

|VOD|(2) Differential output voltage magnitude 200 mV

VOD (Δ) VOD change (between logic states) –10 10 mV

VOH Single-ended output voltage high 1.00 V

VOL Single-ended output voltage low 0.80 V

tR(2) Differential output rise time 250 ps

tF(2) Differential output fall time 250 ps

tMAX Max switching rate 1200 Mbps

DCout Output duty cycle 45% 50% 55%

Txterm(1) Internal differential termination 80 100 120 Ω

Txload 100-Ωdifferential PCB trace

(50-Ωtransmission lines) 0.5 6 inches

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(1) VILD(AC) min applies to undershoot.

(2) VIHD(AC) max applies to overshoot.

(3) Signal group 1 output slew rate for rising edge is measured between VILD(DC) to VIHD(AC).

(4) Signal group 1 output slew rate for falling edge is measured between VIHD(DC) to VILD(AC).

(5) Signal group 1: See Figure 3.

(6) Signal groups 2 and 3 output slew rate for rising edge is measured between VILD(AC) to VIHD(AC).

6.8 Low-Speed SDR Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER ID TEST CONDITIONS MIN MAX UNIT

Operating voltage VCC18 (all signal groups) 1.64 1.96 V

DC input high voltage VIHD(DC)

Signal group 1 All 0.7 × VCC18 VCC18 + 0.5 V

DC input low voltage(1) VILD(DC)

Signal group 1 All –0.50 0.3 × VCC18 V

AC input high voltage(2) VIHD(AC)

Signal group 1 All 0.8 × VCC18 VCC18 + 0.5 V

AC input low voltage VILD(AC)

Signal group 1 All –0.5 0.2 × VCC18 V

Slew rate (3)(4)(5)(6) Signal group 1 1 3.0 V/nsSignal group 2 0.25

Signal group 3 0.5

Figure 3. Low Speed (LS) I/O Input Thresholds

tw(L)

RESETZ 80%

50%

20%

DC Power

Supplies

80%

50%

20%

80%

50%

20%

80%

50%

20%

tw(L) tw(L)

tttt

MOSC 50%

80%

20%

50% 50%

tw(H) tw(L)

80%

20%

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(1) The I/O pin TSTPT_6 must be left open for 24 MHz timing to work properly inside the DLPC343x.

(2) The frequency accuracy for MOSC is ±200 PPM. (This includes impact to accuracy due to aging, temperature, and trim sensitivity.) The

MOSC input cannot support spread spectrum clock spreading.

(3) Applies only when driven through an external digital oscillator.

6.9 System Oscillators Timing Requirements(1)

MIN MAX UNIT

ƒclock Clock frequency, MOSC(2) 24-MHz oscillator 23.998 24.002 MHz

tcCycle time, MOSC(2) 24-MHz oscillator 41.670 41.663 ns

tw(H) Pulse duration(3), MOSC, high 50% to 50% reference points (signal) 40 tc%

tw(L) Pulse duration(3), MOSC, low 50% to 50% reference points (signal) 40 tc%

ttTransition time(3), MOSC, tt= tƒ/ tr20% to 80% reference points (signal) 10 ns

tjp Long-term, peak-to-peak, period jitter(3), MOSC

(that is the deviation in period from ideal period due solely to high frequency jitter) 2%

(1) For more information on RESETZ, see Pin Configuration and Functions.

Figure 4. System Oscillators

6.10 Power-Up and Reset Timing Requirements

NUMBER MIN MAX UNIT

1 tw(L) Pulse duration, inactive low, RESETZ 50% to 50% reference points (signal) 1.25 µs

2 ttTransition time, RESETZ(1), tt= tƒ/ tr20% to 80% reference points (signal) 0.5 µs

Figure 5. Power-Up and Power-Down RESETZ Timing

VSYNC_WE

HSYNC_CS

DATAEN_CMD

tp_vsw

1 Frame

tp_vbp tp_vfp

HSYNC_CS

DATAEN_CMD

tp_hsw

1 Line

tp_hfp

tp_hbp

PDATA(23/15:0) P0

PCLK

P1 P2 P3 P

n-2 P

n-1 Pn

(This diagram assumes the VSYNC

active edge is the rising edge)

(This diagram assumes the HSYNC

active edge is the rising edge)

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(1) The minimum total vertical blanking is defined by the following equation: tp_tvb(min) = 6 + [8 × Max(1, Source_ALPF/ DMD_ALPF)] lines

where:

(a) SOURCE_ALPF = Input source active lines per frame

(b) DMD_ALPF = Actual DMD used lines per frame supported

(2) Total horizontal blanking is driven by the max line rate for a given source which will be a function of resolution and orientation. The

following equation can be applied for this: tp_thb = Roundup[(1000 × ƒclock)/ LR] – APPL

where:

(a) ƒclock = Pixel clock rate in MHz

(b) LR = Line rate in kHz

(d) If tp_thb is calculated to be less than tp_hbp + tp_hfp then the pixel clock rate is too low or the line rate is too high, and one or both

must be adjusted.

6.11 Parallel Interface Frame Timing Requirements MIN MAX UNIT

tp_vsw Pulse duration – VSYNC_WE high 50% reference points 1 lines

tp_vbp Vertical back porch (VBP) – time from the leading edge of

VSYNC_WE to the leading edge HSYNC_CS for the first active

line (see (1))

50% reference points 2 lines

tp_vƒp Vertical front porch (VFP) – time from the leading edge of the

HSYNC_CS following the last active line in a frame to the

leading edge of VSYNC_WE (see (1))

50% reference points 1 lines

tp_tvb Total vertical blanking – time from the leading edge of

HSYNC_CS following the last active line of one frame to the

leading edge of HSYNC_CS for the first active line in the next

frame. (This is equal to the sum of VBP (tp_vbp) + VFP (tp_vfp).)

50% reference points See (1) lines

tp_hsw Pulse duration – HSYNC_CS high 50% reference points 4 128 PCLKs

tp_hbp Horizontal back porch – time from rising edge of HSYNC_CS

to rising edge of DATAEN_CMD 50% reference points 4 PCLKs

tp_hfp Horizontal front porch – time from falling edge of

DATAEN_CMD to rising edge of HSYNC_CS 50% reference points 8 PCLKs

tp_thb Total horizontal blanking – sum of horizontal front and back

porches 50% reference points See (2) PCLKs

Figure 6. Parallel Interface Frame Timing

PCLK

tp_su tp_h

tp_wh tp_wl

tp_clkper

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(1) The active (capture) edge of PCLK for HSYNC_CS, DATEN_CMD and PDATA(23:0) is software programmable, but defaults to the

rising edge.

(2) Clock jitter (in ns) should be calculated using this formula: Jitter = [1 / ƒclock – 5.76 ns]. Setup and hold times must be met during clock

jitter.

6.12 Parallel Interface General Timing Requirements(1)

MIN MAX UNIT

ƒclock Clock frequency, PCLK 1.0 150.0 MHz

tp_clkper Clock period, PCLK 50% reference points 6.66 1000 ns

tp_clkjit Clock jitter, PCLK Max ƒclock see (2) see (2)

tp_wh Pulse duration low, PCLK 50% reference points 2.43 ns

tp_wl Pulse duration high, PCLK 50% reference points 2.43 ns

tp_su Setup time – HSYNC_CS, DATEN_CMD,

PDATA(23:0) valid before the active edge of PCLK 50% reference points 0.9 ns

tp_h Hold time – HSYNC_CS, DATEN_CMD,

PDATA(23:0) valid after the active edge of PCLK 50% reference points 0.9 ns

ttTransition time – all signals 20% to 80% reference

points 0.2 2.0 ns

Figure 7. Parallel Interface General Timing

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bus Assignment Mapping

PDATA(7:0) of the Input Pixel data bus

Data bit mapping on the pins of the ASIC

23 22 21 20 19 18 17 16

PDATA(23:0) t BT.656 Mapping

n/a n/a n/a n/a n/a n/a n/a n/an/a n/a n/a n/a n/a n/a n/a n/a

BT.656 Bus Mode t YCrCb 4:2:2 Source

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(1) The BT.656 interface accepts 8-bits per color, 4:2:2 YCb/Cr data encoded per the industry standard through PDATA(7:0) on the active

edge of PCLK (that is programmable). See Figure 8.

(2) Clock jitter should be calculated using this formula: Jitter = [1 / ƒclock – 5.76 ns]. Setup and hold times must be met during clock jitter.

6.13 BT656 Interface General Timing Requirements(1)

The DLPC343x ASIC input interface supports the industry standard BT.656 parallel video interface. See the appropriate ITU-

R BT.656 specification for detailed interface timing requirements. MIN MAX UNIT

ƒclock Clock frequency, PCLK 1.0 33.5 MHz

tp_clkper Clock period, PCLK 50% reference points 29.85 1,000 ns

tp_clkjit Clock jitter, PCLK Max ƒclock See (2) See (2)

tp_wh Pulse duration low, PCLK 50% reference points 10.0 ns

tp_wl Pulse duration high, PCLK 50% reference points 10.0 ns

tp_su Setup time – PDATA(7:0) before the active edge of

PCLK 50% reference points 3.0 ns

tp_h Hold time – PDATA(7:0) after the active edge of

PCLK 50% reference points 0.9 ns

ttTransition time – all signals 20% to 80% reference points 0.2 3.0 ns

(1) Example: At 172 MHz and THS-PREPARE = 51.46ns -> 51.46ns + THS-ZERO >= 465ns. Therefore THS-ZERO >= 413.54ns.

(2) Minimum values are higher than those required by the MIPI standard. THS-PREPARE must be within the MIPI specified range.

(3) Maximum values are higher than those required by the MIPI standard.

A. BT.656 data bits should be mapped to the DLPC343x PDATA bus as shown.

Figure 8. DLPC343x PDATA Bus – BT.656 Interface Mode Bit Mapping

6.14 DSI Host Timing Requirements

This section describes timing requirements for specific host minimum values that are higher than those specified in the MIPI

standards. It is critical for proper operation that the host meet these minimum timing requirements for specified MIPI

parameters. MIN MAX UNIT

Supported Frequency

Lane Clock Lane 80 235 MHz

Data Lane effective data rate 160 470 Mbps

Number of Data Lanes selectable 1 4 Lanes

THS-PREPARE+ THS-

ZERO

During a LP to HS transition, the time that

the transmitter drives the HS-0 state prior to

transmitting the Sync sequence

80 MHz to 94 MHz HS

Clock 565 ns

95 MHz to 235 MHz HS

Clock(1) 465(2) ns

THS-SETTLE

Time interval during which the HS reciever

shall ignore any data lane HS transitions,

starting from the beginning of THS-PREPARE.

The HS receiver shall ignore any data lane

transitions before the minimum value, and

shall respond to any data lane transitions

after the maximum value

80 MHz to 94 MHz HS

Clock 565(3) ns

95 MHz to 235 MHz HS

Clock 465(3) ns

SPI_CLK

(ASIC Output)

SPI_DIN

(ASIC Inputs)

SPI_DOUT, SPI_CS(1:0)

(ASIC Outputs)

tp_h

tclkper

twh twl tp_su

tp_clqx

tp_clqv

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(1) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC343x does

transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI

devices with long clock-to-Q timing. DLPC343x hold capture timing has been set to facilitate reliable operation with standard external

SPI protocol devices.

(2) With the above output timing, DLPC343x provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the rising

edge of SPI_CLK.

(3) This range includes the 200 ppm of the external oscillator (but no jitter).

6.15 Flash Interface Timing Requirements(1)(2)

The DLPC343x ASIC flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The

DLPC343x can support 1- to 16-Mb flash memories. MIN MAX UNIT

ƒclock Clock frequency, SPI_CLK See (3) 1.42 36.0 MHz

tp_clkper Clock period, SPI_CLK 50% reference points 704 27.7 ns

tp_wh Pulse duration low, SPI_CLK 50% reference points 352 ns

tp_wl Pulse duration high, SPI_CLK 50% reference points 352 ns

ttTransition time – all signals 20% to 80% reference

points 0.2 3.0 ns

tp_su Setup time – SPI_DIN valid before SPI_CLK falling

edge 50% reference points 10.0 ns

tp_h Hold time – SPI_DIN valid after SPI_CLK falling edge 50% reference points 0.0 ns

tp_clqv SPI_CLK clock falling edge to output valid time –

SPI_DOUT and SPI_CSZ 50% reference points 1.0 ns

tp_clqx SPI_CLK clock falling edge output hold time –

SPI_DOUT and SPI_CSZ 50% reference points –3.0 3.0 ns

Figure 9. Flash Interface Timing

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7 Parameter Measurement Information

7.1 HOST_IRQ Usage Model

• While reset is applied HOST_IRQ will reset to tri-state (an external pullup pulls the line high).

• HOST_IRQ will remain tri-state (pulled high externally) until the microprocessor boot completes. While the

signal is pulled high, this indicates that the ASIC is performing boot-up and auto-initialization.

• As soon as possible after boot-up, the microprocessor will drive HOST_IRQ to a logic high state to indicate

that the ASIC is continuing to perform auto-initialization (no real state change occurs on the external signal)

• Upon completion of auto-initialization, software will set HOST_IRQ to a logic low state to indicate the

completion of auto-initialization. (At the falling edge, the system is said to enter the INIT_DONE state.)

• The 500-ms max shown from the rising edge of RESETZ to the falling edge of HOST_IRQ may become

longer than 500 ms if many commands are added to the autoinit batch file in flash which automatically runs at

power up.

Figure 10. Host IRQ Timing

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(1) The user must stay within specifications for all source interface parameters such as max clock rate and max line rate.

(2) The max DMD size for all rows in the table is 1280 × 720.

(3) To achieve the ranges stated, the composer-created firmware used must be defined to support the source parameters used.

(4) These interfaces are supported with the DMD sequencer sync mode command (3Bh) set to auto.

(5) Bits / Pixel does not necessarily equal the number of data pins used on the DLPC343x. Fewer pins are used if multiple clocks are used

per pixel transfer.

(6) By using an I2C command, portrait image inputs can be rotated on the DMD by minus 90 degrees so that the image is displayed in

landscape format.

(7) All parameters in this row follow the BT.656 standard. The image format is always landscape.

(8) BT.656 uses 16-bit 4:2:2 YCr/Cb.

7.2 Input Source

Table 4. Supported Input Source Ranges(1)(2)(3)(4)

INTERFACE BITS / PIXEL

(5) IMAGE TYPE

SOURCE RESOLUTION RANGE(6)

FRAME RATE

RANGE

HORIZONTAL VERTICAL

Landscape Portrait Landscape Portrait

Parallel 24 max 2D only 320 to 1280 200 to 800 200 to 800 320 to 1280 10 to 122 Hz

Parallel 24 max 3D only 320 to 1280 200 to 720 200 to 720 320 to 1280 98 to 102 Hz

118 to 122 Hz

DSI 24 max 2D only 320 to 1280 200 to 800 200 to 800 320 to 1280 10 to 122 Hz

DSI 24 max 3D only 320 to 1280 200 to 720 200 to 720 320 to 1280 98 to 102 Hz

118 to 122 Hz

BT.656-NTSC

(7) See (8) 2D only 720 n/a 240 n/a 60 ±2 Hz

BT.656-PAL (7) See (8) 2D only 720 n/a 288 n/a 50 ±2 Hz

7.2.1 Input Source - Frame Rates and 3-D Display Orientation

For 3D sources on the parallel or MIPI DSI interface, images must be frame sequential (L, R, L, ...) when input to

the DLPC343x. Any processing required to unpack 3D images and to convert them to frame sequential must be

done by external electronics prior to inputting the images to the DLPC343x. Each 3D source frame input must

contain a single eye frame of data separated by a VSYNC where an eye frame contains image data for a single

left or right eye. The signal 3DR input to the DLPC343x tells whether the input frame is for the left eye or right

eye.

Each DMD frame will be displayed at the same rate as the input interface frame rate. Typical timing for a 50-Hz

or 60-Hz 3D HDMI source frame, the input interface of the DLPC343x, and the DMD is shown in Figure 11.

GPIO_04 is optionally sent to a transmitter on the system PCB for wirelessly transmitting a sync signal to 3D

glasses. The glasses are then in phase with the DMD images being displayed. Alternately, 3-D Glasses

Operation shows how DLP Link pulses can be used instead.

Figure 11. DLPC343x L/R Frame and Signal Timing

23 0

765432107654321076543210

Green / YRed / Cr Blue / Cb

Input Input

765432107654321076543210

Input

ASIC Internal Re-

Mapping

ASIC Input

Mapping

23 0

Input Input

765432107654321076543210

Green / YRed / Cr Blue / Cb

765432107654321076543210

Input

ASIC Input

Mapping

ASIC Internal Re-

Mapping

765432107654321076543210

23 0

Green / YRed / Cr Blue / Cb

765432107654321076543210

Green / YRed / Cr Blue / Cb

ASIC Input

Mapping

ASIC Internal Re-

Mapping

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7.2.2 Parallel Interface Supports Six Data Transfer Formats

• 24-bit RGB888 or 24-bit YCrCb888 on a 24 data wire interface

• 18-bit RGB666 or 18-bit YCrCb666 on a 18 data wire interface

• 16-bit RGB565 or 16-bit YCrCb565 on a 16 data wire interface

• 16-bit YCrCb 4:2:2 (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, …)

• 8-bit RGB888 or 8-bit YCrCb888 serial (1 color per clock input; 3 clocks per displayed pixel)

– On an 8 wire interface

• 8-bit YCrCb 4:2:2 serial (1 color per clock input; 2 clocks per displayed pixel)

– On an 8 wire interface

PDATA Bus – Parallel Interface Bit Mapping Modes shows the required PDATA(23:0) bus mapping for these six

data transfer formats.

7.2.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes

Figure 12. RGB-888 / YCrCb-888 I/O Mapping

Figure 13. RGB-666 / YCrCb-666 I/O Mapping

Figure 14. RGB-565 / YCrCb-565 I/O Mapping

23 0

YCr/Cb Blue / Cb

7654321076543210

76543210

YCr/Cb Blue / Cb

Second Input Clock

First Input Clock

[Output 1 full pixel per clock t Non-Contiguous]

[Input 1 single Y/Cr-Cb pixel per clock t Contiguous]

76543210

Input Order must be Cr/Cb ->Y

76543210

7654321

ASIC Input

Mapping

ASIC Internal Re-

Mapping

23 0

Green / YRed / Cr Blue / Cb

7654321076543210

76543210

Green / YRed / Cr Blue / Cb

Third Input Clock

[Output 1 full pixel per clock t Non-Contiguous]

[Input 1 single color pixel per clock t Contiguous]

Input Order must be R->G->B

76543210

ASIC Internal Re-

Mapping

ASIC Input

Mapping

Second Input Clock

First Input Clock

7654321076543210

23 0

YCr / Cb N/A

ASIC Input

Mapping

ASIC Internal Re-

Mapping 765432107654321076543210

YCr/Cb n/a

76543210

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Figure 15. 16-Bit YCrCb-880 I/O Mapping

Figure 16. 8-Bit RGB-888 or YCrCb-888 I/O Mapping

Figure 17. 8-Bit Serial YCrCb-422 I/O Mapping

7.2.3 DSI Interface - Supported Data Transfer Formats

• 24-bit RGB888 - each pixel using 3 bytes (DSI Data Type = 0x3E)

• 18-bit RGB666 - packed (DSI Data Type = 0x1E)

• 18-bit RGB666 - loosely packed into 3 bytes (DSI Data Type = 0x2E)

• 16-bit RGB565 - each pixel using 2 bytes (DSI Data Type = 0x0E)

• 16-bit 4:2:2 YCbCr - packed (DSI Data Type = 0x2C)

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8 Detailed Description

8.1 Overview

The DLPC343x is the display controller for the DLP3010 (.3 720) DMD. DLPC343x is part of the chipset

comprising DLPC343x controller, DLP3010 (.3 720) DMD, and DLPA200x PMIC/LED driver. All three

components of the chipset must be used in conjunction with each other for reliable operation of the DLP3010 (.3

720) DMD. The DLPC343x display controller provides interfaces and data/image processing functions that are

optimized for small form factor and power-constrained display applications. Applications include projection within

cell phones, camera, camcorders and tablets, pico projectors, wearable displays, and digital signage. Standalone

projectors must include a separate front-end chip to interface to the outside world (for example, video decoder,

HDMI receiver, triple ADC, or USB I/F chip).

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Interface Timing Requirements

This section defines the timing requirements for the external interfaces for the DLPC343x ASIC.

8.3.1.1 Parallel Interface

The parallel interface complies with standard graphics interface protocol, which includes a vertical sync signal

(VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit data

bus (PDATA), and a pixel clock (PCLK). The polarity of both syncs and the active edge of the clock are

programmable. Figure 6 shows the relationship of these signals. The data valid signal (DATAEN_CMD) is

optional in that the DLPC343x provides auto-framing parameters that can be programmed to define the data

valid window based on pixel and line counting relative to the horizontal and vertical syncs.

In addition to these standard signals, an optional side-band signal (PDM_CVS_TE) is available, which allows

periodic frame updates to be stopped without losing the displayed image. When PDM_CVS_TE is active, it acts

as a data mask and does not allow the source image to be propagated to the display. A programmable PDM

polarity parameter determines if it is active high or active low. This parameter defaults to make PDM_CVS_TE

active high; if this function is not desired, then it should be tied to a logic low on the PCB. PDM_CVS_TE is

restricted to change only during vertical blanking.

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Feature Description (continued)

NOTE

VSYNC_WE must remain active at all times (in lock-to-VSYNC mode) or the display

sequencer will stop and cause the LEDs to be turned off.

8.3.2 Display Serial Interface DSI

The DPP343x input interface supports the industry standard DSI Type-3 LVDS video interface up to 4-lanes. DSI

is a source synchronous, high speed, low power, low cost physical layer. The DSI-PHY unit is responsible for the

reception of data in High speed (HS) or reception / transmission of data in Low Power (LP) mode for

Unidirectional Data Lanes. Point-to-point lane interconnect can be used for either data or clock signal

transmission. The high speed receiver is a differential line receiver while the low-power receiver is an un-

terminated, single-ended receiver circuit Figure 18 shows a single lane module with PPI Interface.

For a given frame rate, the DSI High-Speed (HS) clock frequency must be fixed. If a different DSI clock rate is

ever needed to support another frame rate, I2C command "Write DSI Parameters (BDh)" must be sent to tell the

DLPC3430 the new DSI clock frequency.

• Compliant with DSI-MIPI specification for Display Serial Interface (V 1.02.00) (except for those items noted in

the DSI Host Timing Requirements ).

• Compliant with D-PHY standard MIPI Specification (V 1.0).

• MIPI DSI Type 3 architecture.

• Supports display resolutions from 320x200 to 1280x800.

• Supports video mode (command mode not supported).

• Commands sent over I2C (MIPI DCS commands sent over DSI not supported).

• Supports multiple packets per transmission.

• Supports trigger messages in the forward direction.

• Data lanes configurable from one to four channels.

• EOT (End of Transfer) command is supported and must be enabled.

• CRC and ECC (Error Correction Code) for header supported. CRC and ECC can be disabled.

• Checksum for long packets with error reporting (but no ECC).

• Supports one virtual channel for video mode.

• Supports Burst Mode.

• Supports Non-Burst w/ Sync Pulses and w/ Sync Event.

• BTA (Bus Turn-Around) mode not supported and must be disabled in the DSI host processor.

• DSI is available for the DLPC3433 only. DSI is not available for the DLPC3438.

• LP (Low Power) mode supported (during V blanking and sync but not between pixel lines).

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Feature Description (continued)

Figure 18. DSI - High Level View

The differential DSI Clock lane (DCLKN:DCLKP) must be in the LP11 (Idle) state upon the de-assertion of

RESETZ (i.e. zero-to-one transition) and must remain in this state for a minimum of 100 µsec thereafter to

ensure proper DSI initialization.

Differential Data lane '0' (DDON:DD0P) is required for DSI operation with the remaining 3 data lanes being

optional / implementation specific as needed.

The state of GPIO (2:1) pins upon the de-assertion of RESETZ (i.e. a zero-to-one transition) will determine the

number of DSI data lanes that will be enabled for both LP and HS bus operation.

8.3.3 Serial Flash Interface

DLPC343x uses an external SPI serial flash memory device for configuration support. The minimum required

size is dependent on the desired minimum number of sequences, CMT tables, and splash options while the

maximum supported is 16 Mb.

For access to flash, the DLPC343x uses a single SPI interface operating at a programmable frequency

complying to industry standard SPI flash protocol. The programmable SPI frequency is defined to be equal to

180 MHz/N, where N is a programmable value between 5 to 127 providing a range from 36.0 to 1.41732 MHz.

Note that this results in a relatively large frequency step size in the upper range (for example, 36 MHz, 30 MHz,

25.7 MHz, 22.5 MHz, and so forth) and thus this must be taken into account when choosing a flash device.

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Feature Description (continued)

The DLPC343x supports two independent SPI chip selects; however, the flash must be connected to SPI chip

select zero (SPI0_CSZ0) because the boot routine is only executed from the device connected to chip select

zero (SPI0_CSZ0). The boot routine uploads program code from flash to program memory, then transfers control

to an auto-initialization routine within program memory. The DLPC343x asserts the HOST_IRQ output signal high

while auto-initialization is in progress, then drives it low to signal its completion to the host processor. Only after

auto-initialization is complete will the DLPC343x be ready to receive commands through I2C.

The DLPC343x should support any flash device that is compatible with the modes of operation, features, and

performance as defined in Table 5 and Table 6.

Table 5. SPI Flash Required Features or Modes of Operation

FEATURE DLPC343x REQUIREMENT

SPI interface width Single

SPI protocol SPI mode 0

Fast READ addressing Auto-incrementing

Programming mode Page mode

Page size 256 B

Sector size 4 KB sector

Block size any

Block protection bits 0 = Disabled

Status register bit(0) Write in progress (WIP) {also called flash busy}

Status register bit(1) Write enable latch (WEN)

Status register bits(6:2) A value of 0 disables programming protection

Status register bit(7) Status register write protect (SRWP)

Status register bits(15:8)

(that is expansion status byte)

The DLPC343x only supports single-byte status register R/W command execution, and thus may not be

compatible with flash devices that contain an expansion status byte. However, as long as expansion status

byte is considered optional in the byte 3 position and any write protection control in this expansion status

byte defaults to unprotected, then the device should be compatible with DLPC343x.

To support flash devices with program protection defaults of either enabled or disabled, the DLPC343x always

assumes the device default is enabled and goes through the process of disabling protection as part of the boot-

up process. This process consists of:

• A write enable (WREN) instruction executed to request write enable, followed by

• A read status register (RDSR) instruction is then executed (repeatedly as needed) to poll the write enable

latch (WEL) bit

• After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction is executed that writes

0 to all 8-bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC343x issues:

• A write enable (WREN) instruction to request write enable, followed by

• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit

• After the write enable latch (WEL) bit is set, the program or erase instruction is executed

• Note the flash automatically clears the write enable status after each program and erase instruction

The specific instruction OpCode and timing compatibility requirements are listed in Table 8 and Table 7. Note

however that DLPC343x does not read the flash’s electronic signature ID and thus cannot automatically adapt

protocol and clock rate based on the ID.

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(1) Only the first data byte is show, data continues

(2) DLPC343x does not support access to a second/ expansion Write Status byte

Table 6. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements

SPI FLASH COMMAND FIRST BYTE

(OPCODE) SECOND

BYTE THIRD BYTE FOURTH BYTE FIFTH BYTE SIXTH BYTE

Fast READ (1 Output) 0x0B ADDRS(0) ADDRS(1) ADDRS(2) dummy DATA(0)(1)

Read status 0x05 n/a n/a STATUS(0)

Write status 0x01 STATUS(0) (2)

Write enable 0x06

Page program 0x02 ADDRS(0) ADDRS(1) ADDRS(2) DATA(0)(1)

Sector erase (4KB) 0x20 ADDRS(0) ADDRS(1) ADDRS(2)

Chip erase 0xC7

(1) The timing values are related to the specification of the flash device itself, not the DLPC343x.

(2) The DLPC343x does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins should be tied to

a logic high on the PCB through an external pullup.

The specific and timing compatibility requirements for a DLPC343x compatible flash are listed in Table 7 and

Table 8.

Table 7. SPI Flash Key Timing Parameter Compatibility Requirements(1)(2)

SPI FLASH TIMING PARAMETER SYMBOL ALTERNATE SYMBOL MIN MAX UNIT

Access frequency (all commands) FR ƒC≤1.42 MHz

Chip select high time (also called chip select deselect

time) tSHSL tCSH ≤200 ns

Output hold time tCLQX tHO ≥0 ns

Clock low to output valid time tCLQV tV≤11 ns

Data in set-up time tDVCH tDSU ≤5 ns

Data in hold time tCHDX tDH ≤5 ns

(1) The flash supply voltage must match VCC_FLSH on the DLPC343x. Special attention needs to be paid when ordering devices to be

sure the desired supply voltage is attained as multiple voltage options are often available under the same base part number.

(2) Beware when considering Numonyx (Micron) serial flash devices as they typically do not have the 4KB sector size needed to be

DLPC343x compatible.

(3) All of these flash devices appear compatible with the DLPC343x, but only those marked with yes in the DVT column have been

validated on the EVM343x reference design. Those marked with no can be used at the ODM’s own risk.

The DLPC343x supports 1.8-, 2.5-, or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied with the

corresponding voltage. Table 8 contains a list of 1.8-, 2.5-, and 3.3-V compatible SPI serial flash devices

supported by DLPC343x.

Table 8. DLPC343x Compatible SPI Flash Device Options(1) (2)

DVT(3) DENSITY (Mb) VENDOR PART NUMBER PACKAGE SIZE

1.8-V COMPATIBLE DEVICES

Yes 4 Mb Winbond W25Q40BWUXIG 2 × 3 mm USON

Yes 4 Mb Macronix MX25U4033EBAI-12G 1.43 × 1.94 mm WLCSP

Yes 8 Mb Macronix MX25U8033EBAI-12G 1.68 × 1.99 mm WLCSP

2.5- OR 3.3-V COMPATIBLE DEVICES

Yes 16 Mb Winbond W25Q16CLZPIG 5 × 6 mm WSON

8.3.4 Serial Flash Programming

Note that the flash can be programmed through the DLPC343x over I2C or by driving the SPI pins of the flash

directly while the DLPC343x I/O are tri-stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by

holding RESETZ in a logic low state while power is applied to the DLPC343x. Note that SPI0_CSZ1 is not tri-

stated by this same action.

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8.3.5 SPI Signal Routing

The DLPC343x is designed to support two SPI slave devices on the SPI0 interface, specifically, a serial flash

and the DLPA200x. This requires routing associated SPI signals to two locations while attempting to operate up

to 36 MHz. Take special care to ensure that reflections do not compromise signal integrity. To this end, the

following recommendations are provided:

• The SPI0_CLK PCB signal trace from the DLPC343x source to each slave device should be split into

separate routes as close to the DLPC343x as possible. In addition, the SPI0_CLK trace length to each device

should be equal in total length.

• The SPI0_DOUT PCB signal trace from the DLPC343x source to each slave device should be split into

separate routes as close to the DLPC343x as possible. In addition, the SPI0_DOUT trace length to each

device should be equal in total length(use the same strategy as SPI0_CLK).

• The SPI0_DIN PCB signal trace from each slave device to the point where they intersect on their way back to

the DLPC343x should be made equal in length and as short as possible. They should then share a common

trace back to the DLPC343x.

• SPI0_CSZ0 and SPI0_CSZ1 need no special treatment because they are dedicated signals which drive only

one device.

8.3.6 I2C Interface Performance

Both DLPC343x I2C interface ports support 100-kHz baud rate. By definition, I2C transactions operate at the

speed of the slowest device on the bus, thus there is no requirement to match the speed grade of all devices in

the system.

8.3.7 Content-Adaptive Illumination Control

Content-adaptive illumination control (CAIC) is an image processing algorithm that takes advantage of the fact

that in common real-world image content most pixels in the images are well below full scale for the for the R, G,

and B digital channels being input to the DLPC343x. As a result of this the average picture level (APL) for the

overall image is also well below full scale, and the system’s dynamic range for the collective set of pixel values is

not fully utilized. CAIC takes advantage of this headroom between the source image APL and the top of the

available dynamic range of the display system.

CAIC evaluates images frame by frame and derives three unique digital gains, one for each of the R, G, and B

color channels. During CAIC image processing, each gain is applied to all pixels in the associated color channel.

CAIC derives each color channel’s gain that is applied to all pixels in that channel so that the pixels as a group

collectively shift upward and as close to full scale as possible. To prevent any image quality degradation, the

gains are set at the point where just a few pixels in each color channel are clipped. Figure 19 and Figure 20

show an example of the application of CAIC for one color channel.

Figure 19. Input Pixels Example

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Figure 20. Displayed Pixels After CAIC Processing

Figure 20 shows the gain that is applied to a color processing channel inside the DLPC343x. CAIC will also

adjust the power for the R, G, and B LED. For each color channel of an individual frame, CAIC will intelligently

determine the optimal combination of digital gain and LED power. The decision regarding how much digital gain

to apply to a color channel and how much to adjust the LED power for that color is heavily influenced by the

software command settings sent to the DLPC343x for configuring CAIC.

As CAIC applies a digital gain to each color channel independently, and adjusts each LED’s power

independently, CAIC also makes sure that the resulting color balance in the final image matches the target color

balance for the projector system. Thus, the effective displayed white point of images is held constant by CAIC

from frame to frame.

Since the R, G, and B channels can be gained up by CAIC inside the DLPC343x, the LED power can be turned

down for any color channel until the brightness of the color on the screen is unchanged. Thus, CAIC can achieve

an overall LED power reduction while maintaining the same overall image brightness as if CAIC was not used.

Figure 21 shows an example of LED power reduction by CAIC for an image where the R and B LEDs can be

turned down in power.

CAIC can alternatively be used to increase the overall brightness of an image while holding the total power for all

LEDs constant. In summary, when CAIC is enabled CAIC can operate in one of two distinct modes:

• Power Reduction Mode – holds overall image brightness constant while reducing LED power

• Enhanced Brightness Mode – holds overall LED power constant while enhancing image brightness

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Figure 21. CAIC Power Reduction Mode (for Constant Brightness)

8.3.8 Local Area Brightness Boost

Local area brightness boost (LABB), is an image processing algorithm that adaptively gains up regions of an

image that are dim relative to the average picture level. Some regions of the image will have significant gain

applied, and some regions will have little or no gain applied. LABB evaluates images frame by frame and derives

the local area gains to be used uniquely for each image. Since many images have a net overall boost in gain

even if some parts of the image get no gain, the overall perceived brightness of the image is boosted.

Figure 22 shows a split screen example of the impact of the LABB algorithm for an image that includes dark

areas.

Figure 22. Boosting Brightness in Local Areas of an Image

LABB works best when the decision about the strength of gains used is determined by ambient light conditions.

For this reason, there is an option to add an ambient light sensor which can be read by the DLPC343x during

each frame. Based on the sensor readings, LABB will apply higher gains for bright rooms to help overcome any

washing out of images. LABB will apply lower gains in dark rooms to prevent over-punching of images.

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8.3.9 3-D Glasses Operation

For supporting 3D glasses, the DLPC343x -based chip set outputs sync information to synchronize the Left

eye/Right eye shuttering in the glasses with the displayed DMD image frames.

Two different types of glasses are often used to achieve synchronization. One relies on an IR transmitter on the

system PCB to send an IR sync signal to an IR receiver in the glasses. In this case DLPC343x output signal

GPIO_04 can be used to cause the IR transmitter to send an IR sync signal to the glasses. The timing for signal

GPIO_04 is shown in Figure 11.

The second type of glasses relies on sync information that is encoded into the light being outputted from the

projection lens. This is referred to as the DLP Link approach for 3D, and many 3D glasses from different

suppliers have been built using this method. This demonstrates that the DLP Link method can work reliable. The

advantage of the DLP Link approach is that it takes advantage of existing projector hardware to transmit the sync

information to the glasses. This can save cost, size and power in the projector.

For generating the DLP Link sync information, one light pulse per DMD frame is outputted from the projection

lens while the glasses have both shutters closed. To achieve this, the DLPC343x will tell the DLPA2000 or

DLPA2005 when to turn on the illumination source (typically LEDs or lasers) so that an encoded light pulse is

output once per DMD frame. Since the shutters in the glasses are both off when the DLP Link pulse is sent, the

projector illumination source will also be off except for the when light is sent to create the DLP Link pulse. The

timing for the light pulses for DLP Link 3D operation is shown in Figure 23 and Figure 24.

Figure 23. DLPC343x L/R Frame and Signal Timing

Video

Video A A

Pulse position changes

on alternate subframes

Both

shutters

off

shutter

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NOTE: The period between DLPLink pulses alternates between the subframe period =D and the subframe period -D,

where D is the delta period.

Figure 24. 3D DLP Link Pulse Timing

8.3.10 DMD (Sub-LVDS) Interface

The DLPC343x ASIC DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum

clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz.

The DLPC343x sub-LVDS interface supports a number of DMD display sizes, and as a function of resolution, not

all output data lanes are needed as DMD display resolutions decrease in size. With internal software selection,

the DLPC343x also supports a limited number of DMD interface swap configurations that can help board layout

by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 9

shows the four options available for the DLP3010 (.3 720p) DMD specifically.

Table 9. DLP3010 (.3720p) DMD – ASIC to 8-Lane DMD Pin Mapping Options

DLPC343x ASIC 8 LANE DMD ROUTING OPTIONS DMD PINS

OPTION 1

Swap Control = x0 OPTION 2

Swap Control = x2

HS_WDATA_D_P

HS_WDATA_D_N HS_WDATA_E_P

HS_WDATA_E_N Input DATA_p_0

Input DATA_n_0

HS_WDATA_C_P

HS_WDATA_C_N HS_WDATA_F_P

HS_WDATA_F_N Input DATA_p_1

Input DATA_n_1

HS_WDATA_B_P

HS_WDATA_B_N HS_WDATA_G_P

HS_WDATA_G_N Input DATA_p_2

Input DATA_n_2

HS_WDATA_A_P

HS_WDATA_A_N HS_WDATA_H_P

HS_WDATA_H_N Input DATA_p_3

Input DATA_n_3

HS_WDATA_H_P

HS_WDATA_H_N HS_WDATA_A_P

HS_WDATA_A_N Input DATA_p_4

Input DATA_n_4

HS_WDATA_G_P

HS_WDATA_G_N HS_WDATA_B_P

HS_WDATA_B_N Input DATA_p_5

Input DATA_n_5

HS_WDATA_F_P

HS_WDATA_F_N HS_WDATA_C_P

HS_WDATA_C_N Input DATA_p_6

Input DATA_n_6

HS_WDATA_E_P

HS_WDATA_E_N HS_WDATA_D_P

HS_WDATA_D_N Input DATA_p_7

Input DATA_n_7

8.3.11 Calibration and Debug Support

The DLPC343x contains a test point output port, TSTPT_(7:0), which provides selected system calibration

support as well as ASIC debug support. These test points are inputs while reset is applied and switch to outputs

when reset is released. The state of these signals is sampled upon the release of system reset and the captured

value configures the test mode until the next time reset is applied. Each test point includes an internal pulldown

resistor, thus external pullups must be used to modify the default test configuration. The default configuration

(x000) corresponds to the TSTPT_(7:0) outputs remaining tri-stated to reduce switching activity during normal

operation. For maximum flexibility, an option to jumper to an external pullup is recommended for TSTPT_(2:0).

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Pullups on TSTPT_(6:3) are used to configure the ASIC for a specific mode or option. TI does not recommend

adding pullups to TSTPT_(7:3) because this has adverse affects for normal operation. This external pullup is only

sampled upon a 0-to-1 transition on the RESETZ input, thus changing their configuration after reset is released

will not have any effect until the next time reset is asserted and released. Table 10 defines the test mode

selection for one programmable scenario defined by TSTPT(2:0).

(1) These are only the default output selections. Software can reprogram the selection at any time.

Table 10. Test Mode Selection Scenario Defined by TSTPT(2:0)(1)

TSTPT(2:0) CAPTURE VALUE NO SWITCHING ACTIVITY CLOCK DEBUG OUTPUT

x000 x010

TSTPT(0) HI-Z 60 MHz

TSTPT(1) HI-Z 30 MHz

TSTPT(2) HI-Z 0.7 to 22.5 MHz

TSTPT(3) HI-Z HIGH

TSTPT(4) HI-Z LOW

TSTPT(5) HI-Z HIGH

TSTPT(6) HI-Z HIGH

TSTPT(7) HI-Z 7.5 MHz

8.3.12 DMD Interface Considerations

The sub-LVDS HS interface waveform quality and timing on the DLPC343x ASIC is dependent on the total length

of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well

matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many

factors.

As an example, DMD interface system timing margin can be calculated as follows:

Setup Margin = (DLPC343x output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation) (1)

Hold-time Margin = (DLPC343x output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)

where PCB SI degradation is signal integrity degradation due to PCB affects which includes such things as

Simultaneously Switching Output (SSO) noise, cross-talk and Inter-symbol Interference (ISI) noise. (2)

DLPC343x I/O timing parameters as well as DMD I/O timing parameters can be found in their corresponding data

sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However,

PCB SI degradation is a more complicated adjustment.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design

guidelines are provided as a reference of an interconnect system that will satisfy both waveform quality and

timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these

recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab

measurements.

DMD_HS Differential Signals DMD_LS Signals

Figure 25. DMD Interface Board Stack-Up Details

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8.4 Device Functional Modes

DLPC343x has two functional modes (ON/OFF) controlled by a single pin PROJ_ON:

• When pin PROJ_ON is set high, the projector automatically powers up and an image is projected from the

DMD.

• When pin PROJ_ON is set low, the projector automatically powers down and only microwatts of power are

consumed.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DLPC343x controller is required to be coupled with DLP3010 DMD to provide a reliable display solution for

various data and video display applications. The DMDs are spatial light modulators which reflect incoming light

from an illumination source to one of two directions, with the primary direction being into a projection or collection

optic. Each application is derived primarily from the optical architecture of the system and the format of the data

coming into the DLPC343x. Applications of interest include accessory projectors, projectors embedded in display

devices like notebooks, laptops, tablets, and hot spots. Other applications include wearable (near-eye or head

mounted) displays, interactive display, low latency gaming display, and digital signage.

9.1.1 DLPC343x System Design Consideration

System power regulation: It is acceptable for VDD_PLLD and VDD_PLLM to be derived from the same regulator

as the core VDD, but to minimize the AC noise component they should be filtered as recommended in the PCB

Layout Guidelines for Internal ASIC PLL Power.

9.2 Typical Application

A common application when using DLPC343x controller with DLP3010 DMD and DLPA200x/DLPA3000

PMIC/LED driver is for creating an accessory Pico projector for a smartphone, tablets, or any other display

source. The DLPC343x in the accessory Pico projector typically receives images from a host processor or a multi

media processor.

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Typical Application (continued)

9.2.1 Design Requirements

A Pico projector is created by using a DLP chipset comprised of DLP3010 ( .3 720p) DMD, DLPC343x controller

and DLPA200x/DLPA3000 PMIC/LED driver. The DLPC343x does the digital image processing, the

DLPA200x/DLPA3000 provides the needed analog functions for the projector, and DMD is the display device for

producing the projected image.

In addition to the three DLP chips in the chipset, other chips may be needed. At a minimum a flash part is

needed to store the software and firmware to control the DLPC343x.

The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often

contained in three separate packages, but sometimes more than one color of LED die may be in the same

package to reduce the overall size of the pico-projector.

For connecting the DLPC343x to the host processing for receiving images, parallel interface is used. I2C should

be connected to the host processor for sending commands to the DLPC343x.

The only power supplies needed external to the projector are the battery (SYSPWR) and a regulated 1.8-V

supply.

The entire pico-projector can be turned on and off by using a single signal called PROJ_ON. When PROJ_ON is

high, the projector turns on and begins displaying images. When PROJ_ON is set low, the projector turns off and

draws just microamps of current on SYSPWR. When PROJ_ON is set low, the 1.8V supply can continue to be

left at 1.8 V and used by other non-projector sections of the product. If PROJ_ON is low, the

DLPA200x/DLPA3000 will not draw current on the 1.8-V supply.

9.2.2 Detailed Design Procedure

For connecting together the DLP3010 (.3 720p) DMD, DLPC343x controller and DLPA200x/DLPA3000

PMIC/LED Driver see the reference design schematic. When a circuit board layout is created from this schematic

a very small circuit board is possible. An example small board layout is included in the reference design data

base. Follow the layout guidelines to achieve a reliable projector.

The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical

OEM who specializes in designing optics for DLP projectors.

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 500 1000 1500 2000 2500 3000

Current mA

Luminance vs. Current

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Typical Application (continued)

9.2.3 Application Curve

As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the

brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white

screen lumens changes with LED currents is shown in Figure 26 when using the DLPA2005. For the LED

currents shown, it is assumed that the same current amplitude is applied to the red, green, and blue LEDs.

SPACE

Figure 26. Luminance vs Current

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10 Power Supply Recommendations

10.1 System Power-Up and Power-Down Sequence

Although the DLPC343x requires an array of power supply voltages, (for example, VDD, VDDLP12,

VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), if VDDLP12 is tied to the 1.1-V VDD supply (which is assumed

to be the typical configuration), then there are no restrictions regarding the relative order of power supply

sequencing to avoid damaging the DLPC343x. (This is true for both power-up and power-down scenarios).

Similarly, there is no minimum time between powering-up or powering-down the different supplies if VDDLP12 is

tied to the 1.1-V VDD supply.

If however VDDLP12 is not tied to the VDD supply, then VDDLP12 must be powered-on after the VDD supply is

powered-on, and powered-off before the VDD supply is powered-off. In addition, if VDDLP12 is not tied to VDD,

then VDDLP12 and VDD supplies should be powered on or powered off within 100 ms of each other.

Although there is no risk of damaging the DLPC343x if the above power sequencing rules are followed, the

following additional power sequencing recommendations must be considered to ensure proper system operation.

• To ensure that DLPC343x output signal states behave as expected, all DLPC343x I/O supplies should remain

applied while VDD core power is applied. If VDD core power is removed while the I/O supply (VCC_INTF) is

applied, then the output signal state associated with the inactive I/O supply will go to a high impedance state.

• Additional power sequencing rules may exist for devices that share the supplies with the DLPC343x, and thus

these devices may force additional system power sequencing requirements.

Note that when VDD core power is applied, but I/O power is not applied, additional leakage current may be

drawn. This added leakage does not affect normal DLPC343x operation or reliability.

Figure 27 and Figure 28 show the DLPC343x power-up and power-down sequence for both the normal PARK

and fast PARK operations of the DLPC343x ASIC.

VDD_PLLM/D (1.1 V)

VDD (1.1 V)

PARKZ

PLL_REFCLK

RESETZ

I2C (activity)

HOST_IRQ

500 ms Min

0 µs Min

0 µs

Max

VCC18 (1.8 V)

VDDLP12 (if not

tied to VDD)

Point at which all supplies reach 95% of

their specified nominal values.

PARKZ must be set high a minimum

of 0 µs before RESETZ is released to

support auto-initialization.

PLL_REFCLK may be active

before power is applied.

HOST_IRQ is driven high when

power and RESETZ are applied to

indicate the DPP343x is not ready for

operation, and then is driven low after

initialization is complete.

PLL_REFCLK must become stable within

5 ms of all power being applied (for

external oscillator application this is

oscillator dependent and for crystal

applications this is crystal and ASIC

oscillator cell dependent).

I2C access can start immediately

after HOST_IRQ goes low (this

should occur within 500 ms from the

release of RESETZ).

PROJ_ON input

(GPIO_8)

0 µs

Min

0 µs

Min

5 ms Min

0 µs Min

HOST_IRQ is pulled high

immediately after RESETZ is

asserted low.

VCC_INTF (1.8 to 3.3 V)

VCC_FLSH (1.8 to 3.3 V)

500 µs

Min

PLL_REFCLK and all ASIC

supplies (except VDDLP12)

must remain active for a

minimum of 500 µs after

PROJ_ON goes low.

VCC18 must remain ON long

enough to satisfy DMD power

sequencing requirements

defined in the DLPA200x

specification.

I2C activity should cease

immediately upon de-

assertion on PROJ_ON.

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System Power-Up and Power-Down Sequence (continued)

Figure 27. DLPC343x Power-Up / PROJ_ON = 0 Initiated Normal PARK and Power-Down

500 ms Min

PLL_REFCLK may be active

before power is applied.

HOST_IRQ is driven high when

power and RESETZ are applied to

indicate the DPP343x is not ready for

operation, and then is driven low after

initialization is complete.

0 µs Min

0 µs

Max

PARKZ must be set low a

minimum of 32 µs before any

power is removed (except

VDDLP12), before PLL_REFCLK

is stopped and before RESETZ is

asserted low to allow time for the

DMD mirrors to be parked.

0 µs Min

5 ms Min

PLL_REFCLK must become stable within

5 ms of all power being applied (for

external oscillator application this is

oscillator dependent and for crystal

applications this is crystal and ASIC

oscillator cell dependent).

I2C access can start immediately

after HOST_IRQ goes low (this

should occur within 500 ms from the

release of RESETZ)

HOST_IRQ is pulled high

immediately after RESETZ is

asserted low.

PARKZ

PLL_REFCLK

RESETZ

I2C (activity)

HOST_IRQ

VDD_PLLM/D (1.1 V)

VDD (1.1 V)

VCC18 (1.8 V)

VDDLP12 (if not tied to VDD)

Point at which all supplies reach 95% of

their specified nominal values.

PARKZ must be set high a minimum

of 0 µs before RESETZ is released to

support auto-initialization.

PROJ_ON input

(GPIO_8)

VCC_INTF (1.8 to 3.3 V)

VCC_FLSH (1.8 to 3.3 V)

I2C activity should cease

immediately upon active low

assertion of PARKZ.

0 µs

Min

VCC18 must remain ON long

enough to satisfy DMD power

sequencing requirements defined

in the DLPA2000 specification.

32 µs Min

0 µs

Min

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System Power-Up and Power-Down Sequence (continued)

Figure 28. DLPC343x Power-Up / PARKZ = 0 Initiated Fast PARK and Power-Down

10.2 DLPC343x Power-Up Initialization Sequence

It is assumed that an external power monitor will hold the DLPC343x in system reset during power-up. It must do

this by driving RESETZ to a logic low state. It should continue to assert system reset until all ASIC voltages have

reached minimum specified voltage levels, PARKZ is asserted high, and input clocks are stable. During this time,

most ASIC outputs will be driven to an inactive state and all bidirectional signals will be configured as inputs to

avoid contention. ASIC outputs that are not driven to an inactive state are tri-stated. These include LED_SEL_0,

LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0 (see RESETZ pin description for full signal descriptions in Pin

Configuration and Functions. After power is stable and the PLL_REFCLK_I clock input to the DLPC343x is

stable, then RESETZ should be deactivated (set to a logic high). The DLPC343x then performs a power-up

initialization routine that first locks its PLL followed by loading self configuration data from the external flash.

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DLPC343x Power-Up Initialization Sequence (continued)

Upon release of RESETZ all DLPC343x I/Os will become active. Immediately following the release of RESETZ,

the HOST_IRQ signal will be driven high to indicate that the auto initialization routine is in progress. However,

since a pullup resistor is connected to signal HOST_IRQ, this signal will have already gone high before the

DLPC343x actively drives it high. Upon completion of the auto-initialization routine, the DLPC343x will drive

HOST_IRQ low to indicate the initialization done state of the DLPC343x has been reached.

Note that the host processor can start sending I2C commands after HOST_IRQ goes low.

10.3 DMD Fast PARK Control (PARKZ)

The PARKZ signal is defined to be an early warning signal that should alert the ASIC 40 µs before DC supply

voltages have dropped below specifications in fast PARK operation. This allows the ASIC time to park the DMD,

ensuring the integrity of future operation. Note that the reference clock should continue to run and RESETZ

should remain deactivated for at least 40 µs after PARKZ has been deactivated (set to a logic low) to allow the

park operation to complete.

10.4 Hot Plug Usage

The DLPC343x provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF). This allows

these inputs to be driven high even when no I/O power is applied. Under this condition, the DLPC343x will not

load the input signal nor draw excessive current that could degrade ASIC reliability. For example, the I2C bus

from the host to other components would not be affected by powering off VCC_INTF to the DLPC343x. TI

recommends weak pullups or pulldowns on signals feeding back to the host to avoid floating inputs.

If the I/O supply (VCC_INTF) is powered off, but the core supply (VDD) is powered on, then the corresponding

input buffer may experience added leakage current, but this does not damage the DLPC343x.

10.5 Maximum Signal Transition Time

Unless otherwise noted, 10 ns is the maximum recommended 20 to 80% rise or fall time to avoid input buffer

oscillation. This applies to all DLPC343x input signals. However, the PARKZ input signal includes an additional

small digital filter that ignores any input buffer transitions caused by a slower rise or fall time for up to 150 ns.

VSS

VDD

VSS_

PLLD

VDD_

PLLD

0.1uF

VSS

VSS_

PLLM

Signal

VSS

VDD

PLL_

REF

CLK_I

Signal

VDD_

PLLM

Signal VSS

VIA to Common Analog

Digital Board Power Plane

VIA to Common Analog

Digital Board Ground Plane

ASIC Pad

PCB Pad

Local

Decoupling

for the PLL

Digital Supply

Signal VIA

Signal

PLL_

REF

CLK_O

0.01uF

Crystal Circuit

1.1 V

PWR

GND

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11 Layout

11.1 Layout Guidelines

11.1.1 PCB Layout Guidelines for Internal ASIC PLL Power

The following guidelines are recommended to achieve desired ASIC performance relative to the internal PLL.

The DLPC343x contains 2 internal PLLs which have dedicated analog supplies (VDD_PLLM , VSS_PLLM,

VDD_PLLD, VSS_PLLD). As a minimum, VDD_PLLx power and VSS_PLLx ground pins should be isolated using

a simple passive filter consisting of two series Ferrites and two shunt capacitors (to widen the spectrum of noise

absorption). It’s recommended that one capacitor be a 0.1uf capacitor and the other be a 0.01uf capacitor. All

four components should be placed as close to the ASIC as possible but it’s especially important to keep the

leads of the high frequency capacitors as short as possible. Note that both capacitors should be connected

across VDD_PLLM and VSS_PLLM / VDD_PLLD and VSS_PLLD respectfully on the ASIC side of the Ferrites.

For the ferrite beads used, their respective characteristics should be as follows:

• DC resistance less than 0.40 Ω

• Impedance at 10 MHz equal to or greater than 180 Ω

• Impedance at 100 MHz equal to or greater than 600 Ω

The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog

signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC343x to both capacitors

and then through the series ferrites to the power source. The power and ground traces should be as short as

possible, parallel to each other, and as close as possible to each other.

Figure 29. PLL Filter Layout

PLL_REFCLK_O

Crystal

RFB

CL1

CL2

PLL_REFCLK_I

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Layout Guidelines (continued)

11.1.2 DLPC343x Reference Clock

The DLPC343x requires an external reference clock to feed its internal PLL. A crystal or oscillator can supply this

reference. For flexibility, the DLPC343x accepts either of two reference clock frequencies (see Table 12), but

both must have a maximum frequency variation of ±200 ppm (including aging, temperature, and trim component

variation). When a crystal is used, several discrete components are also required as shown in Figure 30.

A. CL = Crystal load capacitance (farads)

B. CL1 = 2 × (CL – Cstray_pll_refclk_i)

C. CL2 = 2 × (CL – Cstray_pll_refclk_o)

D. Where: Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the ASIC

pin pll_refclk_i. Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with

the ASIC pin pll_refclk_o.

Figure 30.

11.1.2.1 Recommended Crystal Oscillator Configuration

Table 11. Crystal Port Characteristics

PARAMETER NOM UNIT

PLL_REFCLK_I TO GND capacitance 1.5 pF

PLL_REFCLK_O TO GND capacitance 1.5 pF

(1) Temperature range of –30°C to +85°C

(2) The crystal bias is determined by the ASIC's VCC_INTF voltage rail, which is variable (not the VCC18 rail).

Table 12. Recommended Crystal Configuration(1)(2)

PARAMETER RECOMMENDED UNIT

Crystal circuit configuration Parallel resonant

Crystal type Fundamental (first harmonic)

Crystal nominal frequency 24 or 16 MHz

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200 PPM

Maximum startup time 1.0 ms

Crystal equivalent series resistance (ESR) 120 max Ω

Crystal load 6 pF

RS drive resistor (nominal) 100 Ω

RFB feedback resistor (nominal) 1Meg Ω

CL1 external crystal load capacitor See equation in Figure 30 notes pF

CL2 external crystal load capacitor See equation in Figure 30 notes pF

PCB layout A ground isolation ring around the

crystal is recommended

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(1) These crystal devices appear compatible with the DLPC343x, but only those marked with yes in the DVT column have been validated.

(2) Crystal package sizes: 2.0 × 1.6 mm for both crystals.

(3) Operating temperature range: –30°C to +85°C for all crystals.

If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC343x

ASIC and the PLL_REFCLK_O pins should be left unconnected.

Table 13. DLPC343x Recommended Crystal Parts(1)(2)(3)

PASSED

DVT MANUFACTURER PART NUMBER SPEED TEMPERATURE

AND AGING ESR LOAD

CAPACITANCE

Yes KDS DSX211G-24.000M-8pF-50-50 24 MHz ±50 ppm 120-Ωmax 8 pF

Yes Murata XRCGB24M000F0L11R0 24 MHz ±100 ppm 120-Ωmax 6 pF

Yes NDK NX2016SA 24M

EXS00A-CS05733 24 MHz ±145 ppm 120-Ωmax 6 pF

11.1.2.1.1 PCB Layout Guidelines for DSI Interface

The DSI LVDS interface should follow the following PCB layout guidelines to ensure proper DSI operation

• The differential clock and data lines should be routed to match 50 Ohm single-ended and 100 Ohm

differential impedance.

• The length of dp and dn should be matched, or if that is not possible, dp should be slightly longer than dn

(delta delay not to exceed 8-10ps), especially for the clock-lane. This is to prevent propagation on the clock

lane during HS-> LP transition.

• No thru-hole VIAS permitted on High Speed Traces.

• Route preferably on top or bottom layers

• Must have a ground reference plane.

• Avoid power plane transitions in upper or lower layers.

• Avoid using larger than 0402 SMS resistors if required. If 0402 resistors are used in the traces then the layer

below must have a void.

• No thru-hole SMA connectors.

• Minimize trace length as possible.

• Perform signal integrity simulations to ensure board performance.

11.1.3 General PCB Recommendations

TI recommends 1-oz. copper planes in the PCB design to achieve needed thermal connectivity.

11.1.4 General Handling Guidelines for Unused CMOS-Type Pins

To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends that unused

ASIC input pins be tied through a pullup resistor to its associated power supply or a pulldown to ground. For

ASIC inputs with an internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown

unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be

expected to drive the external line. The DLPC343x implements very few internal resistors and these are noted in

the pin list. When external pullup or pulldown resistors are needed for pins that have built-in weak pullups or

pulldowns, use the value 8 kΩ(max).

Unused output-only pins should never be tied directly to power or ground, but can be left open.

When possible, TI recommends that unused bidirectional I/O pins be configured to their output state such that

the pin can be left open. If this control is not available and the pins may become an input, then they should be

pulled-up (or pulled-down) using an appropriate, dedicated resistor.

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(1) Max signal routing length includes escape routing.

(2) Multi-board DMD routing length is more restricted due to the impact of the connector.

(3) Due to board variations, these are impossible to define. Any board designs should SPICE simulate with the ASIC IBIS models to ensure

single routing lengths do not exceed requirements.

11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths

Table 14. Max Pin-to-Pin PCB Interconnect Recommendations(1)(2)

DMD BUS SIGNAL SIGNAL INTERCONNECT TOPOLOGY UNIT

SINGLE BOARD SIGNAL ROUTING

LENGTH MULTI-BOARD SIGNAL ROUTING

LENGTH

DMD_HS_CLK_P

DMD_HS_CLK_N 6.0

152.4 See (3) inch

(mm)

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

6.0

152.4 See (3) inch

(mm)

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_LS_CLK 6.5

165.1 See (3) inch

(mm)

DMD_LS_WDATA 6.5

165.1 See (3) inch

(mm)

DMD_LS_RDATA 6.5

165.1 See (3) inch

(mm)

DMD_DEN_ARSTZ 7.0

177.8 See (3) inch

(mm)

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(1) These values apply to PCB routing only. They do not include any internal package routing mismatch associated with the DLPC343x, the

DMD.

(2) DMD HS data lines are differential, thus these specifications are pair-to-pair.

(3) Training is applied to DMD HS data lines, so defined matching requirements are slightly relaxed.

(4) DMD LS signals are single ended.

(5) Mismatch variance applies to high-speed data pairs. For all high-speed data pairs, the maximum mismatch between pairs should be 1

mm or less.

Table 15. High Speed PCB Signal Routing Matching Requirements(1)(2)(3)(4)

SIGNAL GROUP LENGTH MATCHING

INTERFACE SIGNAL GROUP REFERENCE SIGNAL MAX MISMATCH(5) UNIT

DMD

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_CLK_P

DMD_HS_CLK_N ±1.0

(±25.4) inch

(mm)

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD DMD_LS_WDATA

DMD_LS_RDATA DMD_LS_CLK ±0.2

(±5.08) inch

(mm)

DMD DMD_DEN_ARSTZ N/A N/A inch

(mm)

11.1.6 Number of Layer Changes

• Single-ended signals: Minimize the number of layer changes.

• Differential signals: Individual differential pairs can be routed on different layers, but the signals of a given pair

should not change layers.

11.1.7 Stubs

• Stubs should be avoided.

11.1.8 Terminations

• No external termination resistors are required on DMD_HS differential signals.

• The DMD_LS_CLK and DMD_LS_WDATA signal paths should include a 43-Ωseries termination resistor

located as close as possible to the corresponding ASIC pins.

• The DMD_LS_RDATA signal path should include a 43-Ωseries termination resistor located as close as

possible to the corresponding DMD pin.

• DMD_DEN_ARSTZ does not require a series resistor.

11.1.9 Routing Vias

• The number of vias on DMD_HS signals should be minimized and should not exceed two.

• Any and all vias on DMD_HS signals should be located as close to the ASIC as possible.

• The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals should be minimized and not

exceed two.

• Any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals should be located as close to the ASIC

as possible.

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11.2 Layout Example

Figure 31. Example Layout

11.3 Thermal Considerations

The underlying thermal limitation for the DLPC343x is that the maximum operating junction temperature (TJ) not

be exceeded (this is defined in the Recommended Operating Conditions). This temperature is dependent on

operating ambient temperature, airflow, PCB design (including the component layout density and the amount of

copper used), power dissipation of the DLPC343x, and power dissipation of surrounding components. The

DLPC343x’s package is designed primarily to extract heat through the power and ground planes of the PCB.

Thus, copper content and airflow over the PCB are important factors.

The recommended maximum operating ambient temperature (TA) is provided primarily as a design target and is

based on maximum DLPC343x power dissipation and RθJA at 0 m/s of forced airflow, where RθJA is the thermal

resistance of the package as measured using a JEDEC standard high-k 2s2p PCB with two, 1-oz. power planes.

This JEDEC test PCB is not necessarily representative of the DLPC343x PCB; the reported thermal resistance

may not be accurate in the actual product application. Although the actual thermal resistance may be different, it

is the best information available during the design phase to estimate thermal performance. However, after the

PCB is designed and the product is built, TI highly recommended that thermal performance be measured and

validated.

To do this, measure the top center case temperature under the worse case product scenario (max power

dissipation, max voltage, max ambient temperature) and validated not to exceed the maximum recommended

case temperature (TC). This specification is based on the measured φJT for the DLPC343x package and provides

a relatively accurate correlation to junction temperature. Take care when measuring this case temperature to

prevent accidental cooling of the package surface. TI recommends a small (approximately 40 gauge)

thermocouple. The bead and thermocouple wire should contact the top of the package and be covered with a

minimal amount of thermally conductive epoxy. The wires should be routed closely along the package and the

board surface to avoid cooling the bead through the wires.

Terminal A1 corner identifier

DLPC343xRXXX

XXXXXXXXXX-TT

LLLLLL.ZZZ

PH YYWW

DLPC343x SC

DLPC3433

DLPC3438

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

www.ti.com

Product Folder Links: DLPC3433 DLPC3438

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 Device Nomenclature

12.1.2.1 Device Markings

Marking Definitions:

Line 1: DLP®Device Name: DLPC343x = xindicates a 3 or 8 device name ID.

SC: Solder ball composition

e1: Indicates lead-free solder balls consisting of SnAgCu

G8: Indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with silver content

less than or equal to 1.5% and that the mold compound meets TI's definition of green.

Line 2: TI Part Number

DLP®Device Name: DLPC343x = xindicates a 3 or 8 device name ID.

Rcorresponds to the TI device revision letter for example A, B or C

XXX corresponds to the device package designator.

Line 3: XXXXXXXXXX-TT Manufacturer part number

Line 4: LLLLLL.ZZZ Foundry lot code for semiconductor wafers and lead-free solder ball marking

LLLLLL: Fab lot number

ZZZ: Lot split number

Vertical Back Porch (VBP)

Vertical Front Porch (VFP)

Horizontal

Back

Porch

(HBP)

Horizontal

Front

Porch

(HFP)

TLPF

TPPL

APPL

ALPF

DLPC3433

DLPC3438

www.ti.com

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

Product Folder Links: DLPC3433 DLPC3438

Device Support (continued)

Line 5: PH YYWW: Package assembly information

PH: Manufacturing site

YYWW: Date code (YY = Year :: WW = Week)

NOTE

1. Engineering prototype samples are marked with an Xsuffix appended to the TI part

number. For example, 2512737-0001X.

2. See Table 4, for DLPC343x resolutions on the DMD supported per part number.

12.1.3 Video Timing Parameter Definitions

Active Lines Per Frame (ALPF) Defines the number of lines in a frame containing displayable data: ALPF is a

subset of the TLPF.

Active Pixels Per Line (APPL) Defines the number of pixel clocks in a line containing displayable data: APPL

is a subset of the TPPL.

Horizontal Back Porch (HBP) Blanking Number of blank pixel clocks after horizontal sync but before the first

active pixel. Note: HBP times are reference to the leading (active) edge of the respective sync

signal.

Horizontal Front Porch (HFP) Blanking Number of blank pixel clocks after the last active pixel but before

Horizontal Sync.

Horizontal Sync (HS) Timing reference point that defines the start of each horizontal interval (line). The

absolute reference point is defined by the active edge of the HS signal. The active edge (either

rising or falling edge as defined by the source) is the reference from which all horizontal blanking

parameters are measured.

Total Lines Per Frame (TLPF)Defines the vertical period (or frame time) in lines: TLPF = Total number of lines

per frame (active and inactive).

Total Pixel Per Line (TPPL) Defines the horizontal line period in pixel clocks: TPPL = Total number of pixel

clocks per line (active and inactive).

Vertical Sync (VS)Timing reference point that defines the start of the vertical interval (frame). The absolute

reference point is defined by the active edge of the VS signal. The active edge (either rising or

falling edge as defined by the source) is the reference from which all vertical blanking parameters

are measured.

Vertical Back Porch (VBP) Blanking Number of blank lines after the leading edge of vertical sync but before

the first active line.

Vertical Front Porch (VFP) Blanking Number of blank lines after the leading edge of the last active line but

before vertical sync.

DLPC3433

DLPC3438

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

www.ti.com

Product Folder Links: DLPC3433 DLPC3438

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 16. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

DLPC3433 Click here Click here Click here Click here Click here

DLPC3438 Click here Click here Click here Click here Click here

DLPA2000 Click here Click here Click here Click here Click here

DLPA2005 Click here Click here Click here Click here Click here

DLPA3000 Click here Click here Click her Click here Click here

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

IntelliBright, E2E are trademarks of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

DLPC3433

DLPC3438

www.ti.com

DLPS035C –FEBRUARY 2014–REVISED DECEMBER 2016

Product Folder Links: DLPC3433 DLPC3438

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by

weight in homogeneous material)

space

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief

on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third

parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for

release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

13.1 Package Option Addendum

13.1.1 Packaging Information

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking(4)(5)

DLPC3433CZVB ACTIVE NFBGA ZVB 176 260 Call TI Call TI Level-3-260C-168 HRS –30 to 85

DLPC3438CZEZ ACTIVE NFBGA ZEZ 201 160 Call TI Call TI Level-3-260C-168 HRS –30 to 85

www.ti.com

PACKAGE OUTLINE

A13.1

12.9 B

13.1

12.9

1 MAX

TYP

0.31

0.21

11.2

TYP

11.2 TYP

0.8 TYP

201X 0.4

0.3

(0.9) TYP

NFBGA - 1 mm max heightZEZ0201A

PLASTIC BALL GRID ARRAY

4221521/A 03/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

BALL A1 CORNER

SEATING PLANE

BALL TYP 0.1 C

0.15 C A B

0.08 C

SYMM

BALL A1 CORNER

12345678910 11

12 13 14 15

SCALE 1.000

www.ti.com

EXAMPLE BOARD LAYOUT

201X ( )0.4

(0.8) TYP

( )

METAL

0.4 0.05 MAX

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

( )

SOLDER MASK

OPENING

0.4

0.05 MIN

NFBGA - 1 mm max heightZEZ0201A

PLASTIC BALL GRID ARRAY

4221521/A 03/2015

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

12345678910 11

12 13 14 15

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(0.8) TYP

(0.8) TYP ( ) TYP0.4

NFBGA - 1 mm max heightZEZ0201A

PLASTIC BALL GRID ARRAY

4221521/A 03/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

12345678910 11

12 13 14 15

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

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