MAX13326GUI/V+T - Maxim Integrated

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

EVALUATION KIT AVAILABLE

19-5136; Rev 5; 4/13

/V denotes an automotive qualified part.

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

Ordering Information

Typical Operating Circuit

General Description

The MAX13325/MAX13326 dual audio line drivers provide

a reliable differential interface between automotive audio

components. The devices feature differential inputs and

outputs, integrated output diagnostics, and are controlled

using an I2C interface or operate in stand-alone mode.

The outputs can deliver up to 4VRMS into 100I loads.

The MAX13325 buffers analog audio signals for trans-

mission over long cable distances with a fixed gain of

12dB, whereas the MAX13326 provides a 0dB fixed

gain. The diagnostics on the outputs report conditions

on a per channel basis, including short to GND, short

to battery, overcurrent, overtemperature, and excessive

offset. The output amplifiers can drive capacitive loads

up to 4nF to ground and 3nF differentially.

The outputs are protected according to IEC 61000-4-2

Q8kV Contact Discharge, and Q15kV Air Gap. The

MAX13325/MAX13326 are specified from -40NC to

+105NC and are available in a 28-pin TSSOP package

with an exposed pad.

Applications

Automotive Radio and Rear Seat Entertainment

Professional Remote Audio Amplifiers

Features

S Comprehensive Programmability and Diagnostics

Using I2C Interface

S Autoretry Function in Stand-Alone Mode

S Drive Capacitive Loads ≤ 3nF Differentially, ≤ 4nF

to Ground

S 112dB Signal-to-Noise Ratio

S Low 0.002% THD at 4VRMS into 2.7kI Loads

S High PSRR (70dB at 1kHz)

S High CMRR (80dB at 1kHz)

S Low Output Noise (3µVRMS), MAX13326

S Excellent Channel-to-Channel Matching

S Load-Dump Transient Protection

S Protected Output Against Various Short-Circuit

Conditions

S ESD Protection for ±8kV Contact Discharge,

±15kV Air Gap

S Long-Distance Drive Capability Typically Up to

15m or Greater

S Noise-Rejecting Differential Inputs and Outputs

S Low-Power Shutdown Mode < 10µA

S Hardware or Software MUTE Function

S 28-Pin TSSOP Package with Exposed Pad

PART PIN-

PACKAGE TEMP RANGE GAIN

(dB)

MAX13325GUI/V+ 28 TSSOP-EP* -40NC to

+105NC12

MAX13326GUI/V+ 28 TSSOP-EP* -40NC to

+105NC0

ADD1

100nF

MICROPROCESSOR

FROM AUDIO

SOURCE

FROM AUDIO

SOURCE

ADD0

SDA

SCL

FLAG

SHDN

MUTE

+12V

+5V R1

* OPTIONAL

D2**

1µF

VDD

VSUP

1kI

PGND

BIAS

CSS

GND

CHARGE

PUMP

I2C INTERFACE

AND

DIGITAL CONTROL

BIAS

CHOLDCMCP

470nF C2

1µF

220nF

10µF

OUTLP

OUTLM

OUTRM

OUTRP

1nF

2.2µF

LEFT

INLP

INLM

2.2µF

C10

2.2µF

RIGHT

INRP

INRM

*OPTIONAL : NEEDED FOR AUTOMOTIVE LOAD DUMP PROTECTION ONLY

**USE D2 WHEN CHARGE PUMP IS OFF AND EXTERNAL SUPPLY IS PROVIDED TO C HOLD

OUTPUT

DIAGNOSTIC

ESD

PROTECTION

MAX13325

MAX13326

1nF

2 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

VDD to PGND ........................................................-0.3V to +28V

CHOLD ................................................................. -0.3V to +28V

VL to GND ...............................................................-0.3V to +6V

GND, PGND ........................................................-0.3V to +0.3V

OUT_ to PGND ........................................................ -0.3V to 28V

IN_, BIAS to AGND ..................................-0.3V to (VDD + 0.3V)

SCL, SDA, ADD0, ADD1, MUTE, SHDN,

FLAG to GND ..........................................................-0.3V to +6V

OUT_ Short Circuit to PGND or VDD ......................... Continuous

Short Circuits Between Any OUT_ ............................Continuous

Continuous Power Dissipation (TA = +70NC) (multilayer board)

28-Pin TSSOP (derate 27mW/NC above +70NC) ..... 2162.2mW

Operating Temperature Range ........................ -40NC to +105NC

Storage Temperature Range ............................ -65NC to +150NC

Junction Temperature .....................................................+150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

ELECTRICAL CHARACTERISTICS

(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC,

unless otherwise noted.) (Note 2)

ABSOLUTE MAXIMUM RATINGS

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Junction-to-Ambient Thermal Resistance (qJA) ..........37°C/W

Junction-to-Case Thermal Resistance (qJC) .................2°C/W

PACKAGE THERMAL CHARACTERISTICS (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AMPLIFIER DC CHARACTERISTICS

Transient Supply Voltage

(Load Dump) VDDMAX Using external nMOS-RTR020N05, 300ms

duration 50 V

Operating Supply Voltage Range VDD 4.5 18 V

VL2.7 5.5

VDD OVLO Threshold VDDOV Rising edge 18.5 19.2 V

VDD UVLO Threshold VDDUV Falling edge 3.3 3.5 V

VL UVLO Threshold VLUV Falling edge 2.2 2.4 V

Supply Current IDD TA = +25NC, no load 39 mA

TA = -40NC to +105NC, no load 50 mA

Logic Supply Current ILVL = 5V 1.7 mA

Shutdown Supply Current ISHDN IDD TA = +25NC 0.5 10 FA

TA = -40NC to +105NC 0.5

IL< 0.1 2 FA

Turn-On Time (from Shutdown) MUTE = VL 220 ms

Turn-On Time (from Mute) SHDN = VL, CCSS = 220nF 6 ms

Differential Input Resistance RINDIF Measure across input 18 24 30 kI

Single-Ended Input Impedance RIN

Each input to ground (MAX13325) 15 20 25 kI

Each input to ground (MAX13326) 12 16 20

Signal-Path Gain (Note 3) AVMAX13325 11.8 12 12.2 dB

MAX13326 -0.2 0 +0.2

3Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC,

unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Channel-to-Channel Gain

Tracking Q0.4 dB

Differential Mode Output Balance

OUT_+ to OUT_- (Note 4) -40 dB

Output Offset Voltage

(OUT_+ to OUT_-) VOOS

MUTE = GND, TA = +25NCQ0.5 Q10 mV

MUTE = VL, TA = +25NCQ0.2 Q3

BIAS Voltage VBIAS Relative to VDD 50 52.5 %

BIAS Impedance ZBIAS IBIAS = Q10FA 69 92 115 kI

Output-Voltage Swing Differential VDD = 14.4V, VIN = Q14.4V, RL = 1kI Q12.5 V

VDD = 5.0V, VIN = Q5V, RL = 1kI Q4.2

Power-Supply Rejection Ratio PSRR

VDD = 4.5V to 18V -80 -96

dBVDD = 14.5V, +500mVP-P ripple at 1kHz -95

VDD = 14.5V, +500mVP-P ripple at 10kHz -80

Common-Mode Rejection Ratio CMRR VIN = 1VRMS, 100Hz to 10kHz -48 -80 dB

AMPLIFIER AC CHARACTERISTICS

Total Harmonic Distortion Plus

Noise (Note 5) THD+N

VOUT = 4VRMS, RL = 2.7kI0.002

VOUT = 4VRMS, RL = 1kI0.004

VOUT = 4VRMS, RL = 100I, VDD = 8V 0.03

VOUT = 7VRMS, RL = 1kI0.2

Total Harmonic Distortion Plus

Noise at VDD = 5V (Note 5) THD+N

VOUT = 1VRMS, RL = 2.7kI0.01

%VOUT = 1VRMS, RL = 1kI0.02

VOUT = 2VRMS, RL = 1kI0.8

Capacitive-Load Stability 3 nF

Capacitive-Load Drive Capability No sustained

oscillation

CLOAD to GND 4 nF

CLOAD differential 3

Signal-to-Noise Ratio (Note 5) SNR

MAX13325, gain = 12dB, VOUT = 4VRMS,

A-weighted 112

MAX13326, gain = 0dB, VOUT = 4VRMS,

A-weighted 122

Unity-Gain Bandwidth 3 MHz

Output Slew Rate 2.5 V/Fs

Output-Voltage Noise A-weighted, MAX13325 10 FV

A-weighted, MAX13326 3

Crosstalk VIN = 1VRMS, 1kHz -110 dB

Mute Time To achieve soft mute, CCSS = 220nF 4 ms

Mute Attenuation VIN = 1VRMS, 1kHz -75 dB

Click-and-Pop Level (Note 6) KCP Into and out of mute -70 dBV

Click-and-Pop Level (Note 6) KCP Into and out of shutdown, 1kI-45 dBV

4 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC,

unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CHARGE PUMP

Charge-Pump Overdrive Voltage,

VCHOLD – VDD (Hard Mode) VCPH VDD = 4.5V, ISOURCE = 6.6mA 3.2 4.0 V

VDD = 18V, ISOURCE = 6.6mA 4.5 5.5

VCHOLD - VDD (Soft Mode) VCPS

VDD unconnected, ISOURCE = 40FA,

VL = 3.3V 2.1 V

VL = 5V 3.9

Charge-Pump Frequency fCP CPOFF = 0

CPF[1:0] = 00 333

kHz

CPF[1:0] = 01 190

CPF[1:0] = 10 426

CPF[1:0] = 11 260

DIAGNOSTICS

Output Current Limit Short to GND or battery 580 mA

Current-Limit Warning Threshold 230 mA

Open-Load Detection 10 kI

Output Offset Detection Valid when muted Q250 mV

Thermal Warning Threshold 135 NC

Thermal Shutdown Threshold 165 NC

Thermal Shutdown Hysteresis 15 NC

ESD PROTECTION

Air Gap IEC 61000-4-2 OUT_ pins Q15 kV

Contact Discharge IEC 61000-4-2 OUT_ pins Q8 kV

HBM All pins Q2 kV

5Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

DIGITAL CHARACTERISTICS

(VDD = 14.4V, VL = 3.3V, TA = TJ = -40NC to +105NC, typical values are TA = +25NC, unless otherwise noted.) (Note 2)

Note 2: All devices are 100% tested at TA = +25NC. Limits over temperature are guaranteed by design.

Note 3: Signal path gain is defined as:

Note 3: Signal Path Gain is defined as

OUT_ OUT_

IN_ IN

(V ) (V )

20 log .

(V ) (V )

−

+−



−



−





Note 4: Measured in differential output mode, differential input voltage 4VP-P (for 0dB gain), 1VP-P (for 12dB gain) 1kHz.

Common-mode output balance is defined as:

Common-Mode Output Balance is defined as

OUT_ OUT_

OUT_ OUT

(|V ) (V )

20 log .

(V ) (V ) 2

−

+−



−



×

+×





Note 5: 22Hz to 22kHz measurement bandwidth.

Note 6: KCP level is calculated as 20log[(peak voltage during mode transition, no input signal)/1VRMS]. Units are expressed in

dBV.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INTERFACE

Input-Voltage High VINH VL = 2.7V to 5.5V 0.75 x VLV

Input-Voltage Low VINL VL = 2.7V to 5.5V 0.25 x VLV

Input-Voltage Hysteresis 50 mV

Input Leakage Current Q100 FA

Output Low Voltage FLAG, SDA, ISINK = 3mA 0.4 V

Output Leakage Current FLAG, SDA = 5.5V 2 FA

Stand-Alone FLAG Pulse Width ADD0, ADD1 = GND 100 ms

Stand-Alone Fault Retry Time ADD0, ADD1 = GND 500 ms

I2C TIMING

Serial-Clock Frequency fSCL 0 400 kHz

Bus Free Time tBUF Between START and STOP conditions 1.3 Fs

Hold Time tHD:STA Repeated START condition 0.6 Fs

SCL Low Time tLOW 1.3 Fs

SCL High Time tHIGH 0.6 Fs

Data Hold Time tHD:DAT 0 900 ns

Data Setup Time tSU:DAT 100 ns

Bus Capacitance CBPer bus line 400 pF

Receiving Rise Time tRSCL, SDA 20 + 0.1CB300 ns

Receiving Fall Time tFSCL, SDA 20 + 0.1CB300 ns

Transmitting Fall Time tFSDA, VL = 3.6V 20 + 0.05CB250 ns

STOP Condition Setup Time tSU:STO 0.6 Fs

Pulse Width of Suppressed Spike tSP 0 50 ns

6 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Typical Operating Characteristics

(VDD = 14.4V, VL = 5V, RL = 1kI, gain = 12dB, TA = +25NC, unless otherwise noted.)

SHUTDOWN CURRENT

vs. TEMPERATURE

MAX13325 toc01

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

9580-25 -10 5 35 5020 65

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

-40

NO LOAD

INPUTS SHORTED

VSHDN = 0V

COMMON-MODE REJECTION RATIO

vs. FREQUENCY

MAX13325 toc02

FREQUENCY (Hz)

CMRR (dB)

10k1k100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

10 100k

1VRMS INPUT

20kHz AES17 FILTER

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

MAX13325 toc03

FREQUENCY (Hz)

THDN (%)

10k1k100

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.010

10 100k

LEFT CHANNEL

1VRMS OUTPUT

RIGHT CHANNEL

TOTAL HARMONIC DISTORTION PLUS

NOISE vs. OUTPUT VOLTAGE

MAX13325 toc04

OUTPUT VOLTAGE (VRMS)

THD+N (%)

986 72 3 4 51

0.002

0.004

0.006

0.008

0.010

0.012

0.014

0.016

0.018

0.020

fIN = 1kHz

POWER-SUPPLY REJECTION RATIO

vs. FREQUENCY

MAX13325 toc05

FREQUENCY (Hz)

PSRR (dB)

10k1k100

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-120

10 100k

500mVP-P RIPPLE

CROSSTALK vs. FREQUENCY

MAX13325 toc06

FREQUENCY (Hz)

CROSSTALK (dB)

10k1k100

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-140

10 100k

1VRMS INPUT

20kHz AES17 FILTER

LEFT TO RIGHT

RIGHT TO LEFT

MUTE ATTENUATION vs. FREQUENCY

MAX13325 toc07

FREQUENCY (Hz)

MUTE ATTENUATION (dB)

10k1k100

-76

-72

-68

-64

-60

-80

10 100k

2VRMS INPUT

A-WEIGHTED

RIGHT CHANNEL

LEFT CHANNEL

OUTPUT-NOISE VOLTAGE vs. FREQUENCY

MAX13325 toc08

FREQUENCY (kHz)

OUTPUT-NOISE VOLTAGE (dBV)

181612 144 6 8 102

-130

-140

-120

-110

-100

-80

-70

-60

-50

-40

-30

-20

-10

-150

FFT vs. FREQUENCY

MAX13325 toc09

FREQUENCY (Hz)

FFT (dBV)

10k1k100

-135

-120

-105

-90

-75

-60

-45

-30

-15

-150

10 100k

VOUT = 1VRMS

1kHz

7Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Typical Operating Characteristics (continued)

(VDD = 14.4V, VL = 5V, RL = 1kI, gain = 12dB, TA = +25NC, unless otherwise noted.)

OUTPUT VOLTAGE vs. CHARGE-PUMP

OVERDRIVE VOLTAGE

MAX13325 toc12

(VCHOLD - VDD) (V)

OUTPUT VOLTAGE (V)

4.0 4.53.52.5 3.00.5 1.0 1.5 2.0

7.5

8.0

8.5

9.0

9.5

10.5

10.0

7.0

0 5.0

THDN = 1%

fIN = 1kHz

VDD = 14.4

RL = 1kI

CPOFF = 1

GAIN vs. TEMPERATURE

MAX13325 toc14

TEMPERATURE (°C)

GAIN (dB)

9580-25 -10 5 35 5020 65

-0.15

-0.10

-0.05

0.05

0.10

0.15

0.20

-0.20

-40

MAX13326 (0dB)

VOUT = 1VRMS

RIGHT CHANNEL

LEFT CHANNEL

GAIN ERROR vs. TEMPERATURE

MAX13325 toc10

TEMPERATURE (°C)

GAIN ERROR (dB)

9580-25 -10 5 35 5020 65

-0.015

-0.010

-0.005

0.005

0.010

0.015

0.020

-0.020

-40

LEFT CHANNEL

RIGHT CHANNEL

OUTPUT-NOISE VOLTAGE vs. FREQUENCY

MAX13325 toc13

FREQUENCY (kHz)

OUTPUT NOISE VOLTAGE (dBV)

181612 144 6 8 102

-130

-140

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-150

MAX13326 (0dB)

GAIN ERROR vs. FREQUENCY

MAX13325 toc12

FREQUENCY (Hz)

GAIN ERROR (dB)

10k1k100

-0.040

-0.035

-0.030

-0.025

-0.020

-0.015

-0.010

-0.005

0.005

0.010

0.015

0.020

0.050

0.045

0.025

0.030

0.035

0.040

-0.050

-0.045

10 100k

1VRMS OUTPUT

GAIN ERROR vs. FREQUENCY

MAX13325 toc15

FREQUENCY (Hz)

GAIN ERROR (dB)

10k1k100

-0.040

-0.030

-0.020

-0.010

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0.045

0.050

-0.050

-0.045

-0.035

-0.025

-0.015

-0.005

0.005

10 100k

MAX13326 (0dB)

1VRMS OUTPUT

8 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Pin Description

Pin Configuration

CSS

I.C.

BIAS

TOP VIEW

MAX13325

MAX13326

OUTLP

OUTLM

PGND

INRM

INLM

7CHOLD

VDD

10 OUTRM

I.C.

9OUTRP

INRP

CONNECT TO PGND.

ADD1

11 GND

I.C.

14 SCL

13 SDA

INLP

TSSOP

SHDN

MUTE

ADD0

FLAG

PIN NAME FUNCTION

1 BIAS Analog Bias Voltage. Bypass BIAS to GND with a 10FF capacitor.

2 VLLogic Supply Voltage. Connect VL to a 2.7V to 5V logic supply. Bypass VL to GND with a 0.1FF

capacitor.

3, 4, 10, 11 I.C. Internally Connected. Leave unconnected.

5 INLP Left Audio Positive Input. Either input of each pair can be used as a single-ended input, with the

complementary input bypassed to GND.

6 INLM Left Audio Negative Input. Either input of each pair can be used as a single-ended input, with the

complementary input bypassed to GND.

7 VDD Power-Supply Input. Connect VDD to the supply voltage. Bypass VDD to GND through a 1FF

capacitor.

8 INRM Right Audio Negative Input. Either input of each pair can be used as a single-ended input, with the

complementary input bypassed to GND.

9 INRP Right Audio Positive Input. Either input of each pair can be used as a single-ended input, with the

complementary input bypassed to GND.

12 SHDN Shutdown Input. Drive SHDN low to power down the device.

13 MUTE Mute Input. Drive MUTE low to mute the outputs. The outputs are low impedance in mute.

9Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Pin Description (continued)

Detailed Description

The MAX13325/MAX13326 audio line drivers are designed

to transmit audio data across noisy environments. The dif-

ferential interface is highly resistant to noise injection from

external sources common to automotive applications.

The MAX13325/MAX13326 operate in stand-alone or

I2C-compatible mode with diagnostic outputs capable

of detecting short to GND or battery, overcurrent, over-

temperature, or excessive offset. A short across another

audio output signal line is also protected.

Table 1. Register Address Map

PIN NAME FUNCTION

14 ADD0 I2C Address Inputs. Connect ADD0 and ADD1 to VL, GND, SCL, or SDA to select 7 I2C addresses.

Connect ADD0 and ADD1 to GND for stand-alone mode.

15 SCL Serial Clock

16 SDA Serial-Data IO

17 ADD1 I2C Address Inputs. Connect ADD0 and ADD1 to VL, GND, SCL, or SDA to select 7 I2C addresses.

Connect ADD0 and ADD1 to GND for stand-alone mode.

18 GND Analog Ground. Ground connection for the input bias and gain circuits.

19 OUTRM Right Audio Negative Output. Each output is current limited.

20 OUTRP Right Audio Positive Output . Each output is current limited.

21 PGND Power Ground. Ground connection for the output stage drivers.

22 CHOLD Charge-Pump Output (When Charge Pump is On; CPOFF = 0). When the charge pump is off,

provide an external supply through a diode to the CHOLD input. Bypass CHOLD with 1µF to PGND.

23 OUTLM Left Audio Negative Output. Each output is current limited.

24 OUTLP Left Audio Positive Outputs. Each output is current limited.

25 CP Charge-Pump Flying Capacitor, Positive Connection

26 CM Charge-Pump Flying Capacitor, Negative Connection

27 FLAG Open-Drain Fault Flag Output. FLAG indicates a fault on any one channel. In stand-alone mode,

FLAG is stretched to a typical pulse width of 100ms.

28 CSS Soft-Start Capacitor Connection. CSS is charged/discharged by < 100FA current to get soft mute/

play transition. Bypass to GND through a 220nF capacitor.

— EP Exposed Pad. Connect to PGND.

ADDRESS REGISTER TYPE NAME READ/WRITE DEFAULT

0x00 Configuration CONFIG Read/Write 0x00

0x01 Command Byte CMD Read/Write 0x00

0x02 General Fault GFAULT Read 0x00

0x03 Left-Channel Fault LFAULT Cleared on Read 0x00

0x04 Right-Channel Fault RFAULT Cleared on Read 0x00

0x05 Flag FLAG Read 0x04 (12dB)

0x05 (0dB)

0x06 General Mask GMASK Read/Write 0x00

0x07 Left-Channel Mask LMASK Read/Write 0x00

0x08 Right-Channel Mask RMASK Read/Write 0x00

10 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Configuration Register

DIAG: Set DIAG to 1 to enable diagnostic mode. Write '0' to disable diagnostic mode.

ENABLE: Set ENABLE bit to 1 to enable the device. Write ‘0’ disables the device. Low on the SHDN pin overrides the

ENABLE bit.

MUTE: Set the MUTE bit to 1 to mute both the output channels. Output is low impedance when in mute. Low on the

MUTE pin input overrides the MUTE bit.

CPOFF: Set the CPOFF bit to 1 to turn off the charge pump. CHOLD pin must be externally supplied (see the VCPH

parameter in the Electrical Characteristics table). Charge pump is enabled when CPOFF = 0.

OLDL: Write 1 to the OLDL bit to initiate the open-load detection for the left channel. To run OLDL again, write ‘0’ and

‘1’ again.

OLDR: Write 1 to the OLDR bit to initiate the open-load detection for the right channel. To run OLDR again, write ‘0’

and ‘1’ again.

CPF[1:0]: Sets the frequency of the charge pump.

Command Byte Register

RETRYR: The right-channel power amplifier switches off after a fault condition. Write ‘1’ to turn it back on after the fault

condition.

RETRYL: The left-channel power amplifier switches off after a fault condition. Write ‘1’ to turn on the left-channel power

amplifier after the fault condition.

Table 2. Configuration Register Format

Table 3. Command Byte Register Format

Table 2a. Charge-Pump Frequency Bits

FUNCTION ADDRESS

CODE (HEX)

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Configuration

FUNCTION ADDRESS

CODE (HEX)

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Command Byte

CPF1 CPF0 FREQUENCY (kHz)

0 0 333

0 1 190

1 0 426

1 1 260

11Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

General Faults

TWARN: The TWARN bit is set to ‘1’ when the temperature warning threshold is reached.

TSHDN: The TSHDN is set to ‘1’ when the temperature shutdown threshold is reached.

DUMP: The DUMP bit is set to ‘1’ when the VDD voltage exceeds the overvoltage threshold.

Set the appropriate mask bit in the GMASK register to detect the general faults. See Table 8.

Left-Channel Faults

SVDDL: The SVDDL bit is set to ‘1’ when a short to VDD is detected on the left channel.

SGNDL: The SGNDL bit is set to ‘1’ when a short to GND is detected on the left channel.

LIMITL: The LIMITL bit is set to ‘1’ when the current-limit threshold is tripped for left output.

OFFSETL: The OFFSETL bit is set to ‘1’ when excessive offset is detected on the left-channel output.

OPENL: The OPENL bit is set to ‘1’ when an open load is detected on the left channel.

Set the appropriate mask bit in the LMASK register to detect the faults on the left channel. See Table 9.

When any bit of the LFAULT register is high, the FLAG output is low.

Right-Channel Faults

SVDDR: The SVDDR bit is set to ‘1’ when a short to VDD is detected on the right channel.

SGNDR: The SGNDR bit is set to ‘1’ when a short to GND is detected on the right channel.

LIMITR: The LIMITR bit is set to ‘1’ when the current-limit threshold is tripped for right output.

OFFSETR: The OFFSETR bit is set to ‘1’ when excessive offset is detected on the right-channel output.

OPENR: The OPENR bit is set to ‘1’ when an open load is detected on the right channel.

Set the appropriate mask bit in the RMASK register to detect the faults on the right channel. See Table 10.

When any bit of the RFAULT register is high, the FLAG output is pulled low.

Table 4. General Fault Register Format

Table 5. Left-Channel Fault Register Format

Table 6. Right-Channel Fault Register Format

FUNCTION ADDRESS

CODE (HEX)

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

General Fault

FUNCTION

ADDRESS

CODE

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Left-Channel

Fault Register 0x03 SVDDL SGNDL LIMITL x OFFSETL OPENL x x 0x00

FUNCTION

ADDRESS

CODE

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Right-Channel

Fault Register 0x04 SVDDR SGNDR LIMITR x OFFSETR OPENR x x 0x00

12 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

FLAG Register

FLAG: FLAG bit is set to ‘1’ when the FLAG output is logic-low. The FLAG bit allows to quickly access the status of the

device without using the FLAG output and without having to read all the fault registers.

LHIGHZ: The LHIGHZ bit is set to ‘1’ when the left-channel output is high impedance; for example due to a short circuit.

RHIGHZ: The RHIGHZ bit is set to ‘1’ when the right-channel output is high impedance; for example due to a short

circuit.

OFFSETL: The OFFSETL bit is set to ‘1’ when excessive offset is detected on the left-channel output.

OFFSETR: The OFFSETR bit is set to ‘1’ when excessive offset is detected on the right-channel output.

ID[2:0]: The ID[2:0] bits indicate the device type (12dB = 100 and 0dB = 101).

General Mask Register

MTWARN: Set MTWARN to ‘1’ to enable the TWARN fault detection. See Table 4.

MTSHDN: Set MTSHDN to ‘1’ to enable the TSHDN fault detection. See Table 4.

MDUMP: Set MDUMP to ‘1’ to enable the DUMP fault detection. See Table 4.

Left-Channel Mask Register

MSVDDL: Set MSVDDL to 1 to enable the short to VDD detection on the left channel.

MSGNDL: Set MSGNDL to 1 to enable the short to GND detection on the left channel.

MLIMITL: Set MLIMITL to 1 to enable overcurrent detection on the left channel.

MOFFSETL: Set MOFFSETL to 1 to enable excessive-offset detection on the left-channel output.

MOPENL: Set MOPENL to 1 to enable open-load detection on the left channel.

Table 8. General Mask Register Format

Table 9. Left-Channel Mask Register

Table 7. Flag Register Format

FUNCTION

ADDRESS

CODE

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

General Mask

FUNCTION

ADDRESS

CODE

(HEX)

STATE

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Left-Channel

Mask Register 0x07 MSVDDL MSGNDL MLIMITL 0 MOFFSETL MOPENL x x 0x00

FUNCTION

ADDRESS

CODE

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

FLAG

13Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Right-Channel Mask Register

MSVDDR: Set MSVDDR to 1 to enable the short to VDD detection on the right channel.

MSGNDR: Set MSGNDR to 1 to enable the short to GND detection on the right channel.

MLIMITR: Set MLIMITR to 1 to enable overcurrent detection on the right channel.

MOFFSETR: Set MOFFSETR to 1 to enable excessive-offset detection on the right channel.

MOPENR: Set MOPENR to 1 to enable open-load detection on the right channel.

Table 10. Right-Channel Mask Register

Table 11. Output Short to VDD

/Battery Diagnostic

I2C and Stand-Alone Diagnostics

When the DIAG bit and the appropriate mask bits are set

to 1, the MAX13325/MAX13326 enter diagnostic mode.

In this mode, the MAX13325/MAX13326 detect short

to GND, short to battery, overcurrent condition, over-

temperature condition, excessive offset, and report the

diagnosis using the I2C serial interface, FLAG bit, and

the FLAG output.

For stand-alone mode, there exists a 500ms stand-alone

fault retry function (for autoretry) until the fault goes

away. The FLAG output is pulsed to indicate a fault.

Output Short to VDD

When in diagnostic mode, the MAX13325/MAX13326

detect if any of the differential outputs is shorted to VDD

or battery. Upon detection of the short to VDD or battery,

the faulted channel is switched off and its output goes

into a high-impedance state. The fault is reported using

the I2C interface and the FLAG output. See Table 11.

FUNCTION

ADDRESS

CODE

(HEX)

STATE

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

Right-Channel

Mask Register 0x08 MSVDDR MSGNDR MLIMITR 0 MOFFSETR MOPENR x x 0x00

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Left-Channel Output

Short to VDD

FLAG is asserted low. In LMASK register, set

MSVDDL bit to 1.

See Table 9.

Cleared on reading the LFAULT

Note: 500ms autoretry in stand-

alone mode.

FLAG bit set. See Table 7.

SVDDL bit is set in the LFAULT

Left channel switches off and output

goes to high-impedance state. Cannot be masked.

Output is enabled by setting the

RETRYL bit to 1 in the Common

Byte register. See Table 3.

Right-Channel

Output Short to VDD

FLAG is asserted low. In RMASK register, set

MSVDDR bit to 1. See

Table 10.

Cleared on reading the RFAULT

Note: 500ms autoretry in stand-

alone mode.

FLAG bit set. See Table 7.

SVDDR bit is set in the RFAULT

Right channel switches off and

output goes to high-impedance

state.

Cannot be masked.

Output is enabled by setting the

RETRYR bit to 1 in the Command

Byte register. See Table 3.

14 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Table 12. Output Short to GND Diagnostic

Table 13. Overtemperature Diagnostic

Output Short to GND

When in diagnostic mode, the MAX13325/MAX13326

detect if any of the differential outputs is shorted to

ground. Upon detection of the short to ground, the

faulted channel is switched off and its output goes into a

high-impedance state. The fault is reported using the I2C

interface and the FLAG output. See Table 12.

Overtemperature

When in diagnostic mode, if the MAX13325/MAX13326

exceed the overtemperature warning or temperature shut-

down thresholds the device reports the condition using

the I2C interface and the FLAG output. See Table 13.

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Left-Channel Output

Short to GND

FLAG is asserted low. In LMASK register, set

MSGNDL bit to 1. See

Table 9.

Cleared on reading the LFAULT

Note: 500ms autoretry in stand-

alone mode.

FLAG bit set. See Table 7.

SGNDL bit is set in the LFAULT

Left channel switches off and output

goes to high-impedance state. Cannot be masked.

Output is enabled by setting the

RETRYL bit to 1 in the Command

Byte register. See Table 3.

Right-Channel Output

Short to GND

FLAG is asserted low. In RMASK register, set

MSGNDR bit to 1. See

Table 10.

Cleared on reading the RFAULT

Note: 500ms autoretry in stand-

alone mode.

FLAG bit set. See Table 7.

SGNDR bit is set in the RFAULT

Right channel switches off and

output goes to high-impedance

state.

Cannot be masked.

Output is enabled by setting the

RETRYR bit to 1 in the Command

Byte register. See Table 3.

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Overtemperature

Warning

FLAG is asserted low. In GMASK register, set

MTWARN bit to 1. See

Table 8.

Die temperature falls below warning

threshold.

Cleared on reading the GFAULT

FLAG bit set. See Table 7.

TWARN bit is set in the GFAULT

Overtemperature

Shutdown

FLAG is asserted low.

In GMASK register, set

MTSHDN bit to 1. See

Table 8.

Die temperature falls below

shutdown threshold.

Cleared on reading the GFAULT

Note: 500ms autoretry in stand-

alone mode.

FLAG bit set. See Table 7.

TSHDN bit is set in the GFAULT

Left and right channels switch

off and output goes to high-

impedance state.

Cannot be masked.

Left channel is enabled by setting

the RETRYL bit to 1 in the Command

Byte register.

Right channel is enabled by

setting the RETRYR bit to 1 in the

Command Byte register.

See Table 3.

15Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Table 15. Overcurrent Diagnostic

Table 16. Open-Load Diagnostic

Table 14. Excessive Offset Diagnostic

Excessive Offset

When in diagnostic mode with mute enabled, if there

is excessive offset on any output, the MAX13325/

MAX13326 reports the condition through the I2C inter-

face and the FLAG output. See Table 14.

Overcurrent

When in diagnostic mode, if any of the output pairs is

excessively loaded, the MAX13325/MAX13326 issue a

warning and report the condition through the I2C inter-

face and the FLAG output. The faulted channel is not

switched off. See Table 15.

Open Load

When in diagnostic mode and the open-load detec-

tion is initiated, the selected channel is switched off for

1ms during which the diagnosis is taking place. Upon

detecting an open load on any channel, the MAX13325/

MAX13326 report the condition using the I2C interface

and the FLAG output. See Table 16.

Overvoltage

When in diagnostic mode, if the MAX13325/MAX13326

exceed the VDD overvoltage threshold (for example

during a load-dump condition), the device reports the

condition using the I2C interface and the FLAG output.

See Table 17.

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Excessive Output

Offset on Left

Channel

FLAG is asserted low. In the LMASK register, set

MOFFSETL bit to 1. See

Table 9.

Cleared on reading the LFAULT

FLAG bit set. See Table 7.

OFFSETL bit is set in the LFAULT

Excessive Output

Offset on Right

Channel

FLAG is asserted low. In the RMASK register, set

MOFFSETR bit to 1. See

Table 10.

Cleared on reading the RFAULT

FLAG bit set.

OFFSETR bit is set in the RFAULT

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Overcurrent on Left

Channel

FLAG is asserted low. In the LMASK register,

set MLIMITL bit to 1. See

Table 9.

Load current falls below the

current-limit threshold.

Cleared on reading the LFAULT

FLAG bit set. See Table 7.

LIMITL bit is set in the LFAULT

Overcurrent on Right

Channel

FLAG is asserted low. In the RMASK register,

set MLIMITR bit to 1. See

Table 10.

Load current falls below the

current-limit threshold.

Cleared on reading the RFAULT

FLAG bit set. See Table 7.

LIMITR bit is set in the RFAULT

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Left-Channel Open

Load

FLAG is asserted low. In the LMASK register,

set MOPENL bit to 1. See

Table 9.

Cleared on reading

the LFAULT register.

FLAG bit set. See Table 7.

OPENL bit is set in the LFAULT

Right-Channel Open

Load

FLAG is asserted low. In the RMASK register,

set MOPENR bit to 1. See

Table 10.

Cleared on reading

the RFAULT register.

FLAG bit set. See Table 7.

OPENR bit is set in the RFAULT

16 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Applications Information

Serial Interface

Writing to the MAX13325/MAX13326 using I2C requires

that first the master sends a START (S) condition fol-

lowed by the device’s I2C address. After the address,

the master sends the register address of the register

that is to be programmed. The master then ends com-

munication by issuing a STOP (P) condition to relinquish

control of the bus, or a Repeated START (Sr) condition to

communicate to another I2C slave (see Figure 1).

Bit Transfer

Each SCL rising edge transfers one data bit. The data

on SDA must remain stable during the high portion of the

SCL clock pulse (see Figure 2). Changes in SDA while

SCL is high are read as control signals (see the START

and STOP Conditions section). When the serial interface

is inactive, SDA and SCL idle high.

Figure 1. I2C Timing

Figure 2. Bit Transfer

Table 17. Overvoltage Diagnostic

tLOW

SDA

SCL

tHD:STA

tSU:STA

tHD:DAT tHIGH

tLOW

tSU:DAT

tFtHD:STA tSP

tSU:STO

SSr

tBUF

SDA

SCL

DATA LINE

STABLE;

DATA VALID

CHANGE OF

DATA ALLOWED

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Overvoltage

Shutdown

FLAG is asserted low.

In GMASK register, set

MDUMP bit to 1.

See Table 8.

VDD voltage falls below overvoltage

threshold. Cleared on reading the

GFAULT register. Note: 500ms

autoretry in stand-alone mode.

FLAG bit set. See Table 7.

DUMP bit is set in the GFAULT

Left and right channels switch

off and output goes to a

high-impedance state.

Cannot be masked.

Left channel is enabled by setting

the RETRYL bit to 1. Right channel

is enabled by setting the RETRYR

bit to 1. See Table 3.

17Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

START and STOP Conditions

A master device initiates communication by issuing

a START condition, which is a high-to-low transition

on SDA with SCL high. A START condition from the

master signals the beginning of a transmission to the

MAX13325/MAX13326. The master terminates transmis-

sion by a STOP condition (see the Acknowledge Bit

section). A STOP condition is a low-to-high transition

on SDA while SCL is high (Figure 3). The STOP condi-

tion frees the bus. If a Repeated START condition is

generated instead of a STOP condition, the bus remains

active. When a STOP condition or incorrect slave ID is

detected, the device internally disconnects SCL from the

serial interface until the next START or Repeated START

condition, minimizing digital noise and feedthrough.

Acknowledge Bit

The acknowledge (ACK) bit is a clocked 9th bit that

the MAX13325/MAX13326 use to handshake receipt of

each byte of data when in write mode. The MAX13325/

MAX13326 pull down SDA during the entire master-

generated 9th clock pulse if the previous byte is suc-

cessfully received (see Figure 4). Monitoring ACK

allows for detection of unsuccessful data transfers. An

unsuccessful data transfer occurs if a receiving device

is busy or if a system fault has occurred. In the event

Figure 3. START/STOP Conditions

Figure 4. Acknowledge and Not-Acknowledge Bits

Table 18. Slave Address

SDA

START

CONDITION

STOP

CONDITION

SCL

SDA

SCL 18

NOT ACKNOWLEDGE

ACKNOWLEDGE

ADD1 ADD0 A6 A5 A4 A3 A2 A1 A0 R/W

SLAVE

ADDRESS

READ

(HEX)

SLAVE

ADDRESS

WRITE

(HEX)

MODE

GND GND — — — — — — — — — — Stand-

alone

VLGND 1 1 0 0 0 0 1 1/0 0xC3 0xC2 I2C

GND VL1 1 0 0 0 1 0 1/0 0xC5 0xC4 I2C

VLVL1 1 0 0 0 1 1 1/0 0xC7 0xC6 I2C

SCL VL1 1 0 0 1 0 0 1/0 0xC9 0xC8 I2C

SDA VL1 1 0 0 1 0 1 1/0 0xCB 0xCA I2C

VLSCL 1 1 0 0 1 1 0 1/0 0xCD 0xCC I2C

VLSDA 1 1 0 0 1 1 1 1/0 0xCF 0xCE I2C

18 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

of an unsuccessful data transfer, the bus master may

retry communication. The master must pull down SDA

during the 9th clock cycle to acknowledge receipt of

data when the MAX13325/MAX13326 are in read mode.

An acknowledge must be sent by the master after each

read byte to allow data transfer to continue. A not-

acknowledge is sent when the master reads the final

byte of data from the MAX13325/MAX13326, followed by

a STOP condition.

Slave Address

The MAX13325/MAX13326 are programmable to one of

seven I2C slave addresses. These slave addresses are

unique device IDs. Connect ADD_ to GND, VL, SCL, or

SDA to set the I2C slave address. The address is defined

as the seven most significant bits (MSBs) followed by

the read/write bit. Set the read/write bit to 1 to configure

the MAX13325/MAX13326 to read mode. Set the read/

write bit to 0 to configure the device to write mode. The

address is the first byte of information sent after the

START condition.

Single-Byte Write Operation

For a single-byte write operation, send the slave address

as the first byte followed by the register address and

then a single data byte (see Figure 5).

Burst Write Operation

For a burst write operation, send the slave address as

the first byte followed by the register address and then

the data bytes (see Figure 6).

Single-Byte Read Operation

For a single-byte read operation, send the slave address

with the read bit set, as the first byte followed by the reg-

ister address. Then send a Repeated START condition

followed by the slave address. After the slave sends the

data byte, send a not-acknowledge followed by a STOP

condition (see Figure 7).

Burst Read Operation

For a burst read operation, send the slave address with

a write as the first byte followed by the register address.

Then send a Repeated START condition followed by the

slave address. The slave sends data bytes until a not-

acknowledge condition is sent (see Figure 8).

Figure 5. A Single-Byte Write Operation

Figure 6. A Burst Write Operation

S S7 S6 S5 S4 S3 S2 S1 ACK

B7 B6 B5 B4 B3 B2 B1 B0 ACK P

C7 C6 C5 C4 C3 C2 C1 C0 ACK

R/W

= 0

SLAVE ADDRESS

DATA 1

S S7 S6 S5 S4 S3 S2 S1 ACK

B7 B6 B5 B4 B3 B2 B1 B0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK

R7 R6 R5 R4 R3 R2 R1 R0 ACK

SLAVE ADDRESS

DATA 1

DATA 2

R/W

= 0

ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK P

DATA N

19Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Figure 7. A Single-Byte Read Operation

Figure 8. A Burst Read Operation

Charge Pump

The MAX13325/MAX13326 charge pump can be dis-

abled depending on application requirements. When

charge pump is enabled [CPOFF = 0], please follow the

charge-pump capacitor selections. When the charge

pump is disabled [CPOFF = 1], the flying capacitor

(C1) is not needed. There are internal diodes between

VDD/OUT_ to CHOLD, so it is important that CHOLD

not be forced below VDD or any of the outputs. A series

diode needs to be placed between the external supply

(VSUP) and CHOLD. See D2 in the Typical Operating

Circuit.

Charge-Pump Capacitor Selection

Use ceramic capacitors with a low ESR for optimum per-

formance. For optimal performance over the extended

temperature range, select capacitors with an X7R

dielectric. Table 19 lists suggested manufacturers.

Flying Capacitor (C1)

The value of the flying capacitor (see the Typical

Operating Circuit) affects the charge pump’s load regu-

lation and output resistance. A C1 value that is too small

degrades the device’s ability to provide sufficient current

drive, which leads to a loss of output voltage. Increasing

the value of C1 improves load regulation and reduces

the charge-pump output resistance. For optimum perfor-

mance, use a 470nF capacitor for C1. When the charge

pump is disabled [CPOFF = 1], the flying capacitor (C1)

is not needed.

Hold Capacitor (C2)

The hold capacitor value (see the Typical Operating

Circuit) and ESR directly affect the ripple at the internal

negative rail. Increasing the value of C2 reduces output

ripple. Likewise, decreasing the ESR of C2 reduces both

ripple and output resistance. Lower capacitance values

can be used in systems with low maximum output power

levels. For optimum performance, use a 1FF capacitor

for C2.

Table 19. Suggested Capacitor Vendors

S S7 S6 S5 S4 S3 S2 S1 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK

SLAVE ADDRESS REGISTER ADDRESS

R/W

= 0

Sr S7 S6 S5 S4 S3 S2 S1 ACK B7 B6 B5 B4 B3 B2 B1 B0 NACK P

SLAVE ADDRESS DATA

R/W

= 1

S S7 S6 S5 S4 S3 S2 S1 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK

SLAVE ADDRESS REGISTER ADDRESS

R/W

= 0

Sr S7 S6 S5 S4 S3 S2 S1 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK

SLAVE ADDRESS DATA 1

R/W

= 1

ACK B7 B6 B5 B4 B3 B2 B1 B0 NACK P

DATA N

SUPPLIER PHONE FAX WEBSITE

Murata Electronics North America, Inc. 770-436-1300 770-436-3030 www.murata-northamerica.com

Taiyo Yuden 800-348-2496 847-925-0899 www.t-yuden.com

TDK Corp. 847-803-6100 847-390-4405 www.component.tdk.com

20 Maxim Integrated

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages.

Note that a “+”, “#”, or “-” in the package code indicates RoHS

status only. Package drawings may show a different suffix

character, but the drawing pertains to the package regardless

of RoHS status.

Chip Information

PROCESS: BCD

Power-Supply Bypass Capacitor (C3)

The power-supply bypass capacitor (see the Typical

Operating Circuit) lowers the output impedance of the

power supply, and reduces the impact of the MAX13325/

MAX13326 charge-pump switching transients. Bypass

VDD with C3, the same value as C2, and place it physi-

cally close to the VDD and PGND pins.

Load-Dump Protection

With minimal external components, the MAX13325/

MAX13326 can be protected against automotive load-

dump conditions. See the Typical Operating Circuit.

nMOSFET (Q1)

Q1 should be selected to withstand the full-voltage expo-

sure (BVDSS > 45V). The gate-source turn-on voltage

should be chosen to be less than VCPS to ensure initial

startup. Using an external nMOS, RTR020N05, 300ms

duration component provides 50V load-dump protection.

Zener Diode (D1)

During short-to-battery condition, OUT_ lifts up CHOLD

using an internal diode. In order not to violate the maxi-

mum gate-source voltage of Q1, a zener diode of appro-

priate clamping voltage should be added between the

gate and source terminals.

Series Resistor (R1)

Normally, a series resistor for current limitation is needed

during short-to-battery condition. R1 should be chosen

according to (18V - VDD(min) - VZENER)/1mA so that no

excessive current is being drawn from CHOLD.

Layout and Grounding

Proper layout and grounding are essential for optimum

performance. Connect the EP and GND together at a

single point on the PCB. Ensure ground return resistance

is minimized for optimum crosstalk performance.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND PATTERN

NO.

28 TSSOP-EP U28E+5 21-0108 90-0147

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent

licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and

max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 21

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

MAX13325/MAX13326

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 1/10 Initial release —

1 3/10 Updated the Typical Operating Circuit 1

2 4/10 Added new register bits to Tables 1, 2, and 7. Revised FLAG Register

section and added Table 2a and Charge Pump section. 1, 4, 7, 8–12, 19, 20

3 6/10 Introduced the MAX13326. Updated the Electrical Characteristics table

and added new Typical Operating Characteristics graphs. 1, 4, 5, 7

4 9/12 Corrected slave addresses in Table 18 17

5 4/13 Corrected bits D[7:6] in Table 3 10