M48T58-70PC1TR - STMicroelectronics, Inc.

June 2011 Doc ID 2412 Rev 8 1/33

M48T58

M48T58Y

5.0 V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM

Features

■Integrated, ultra low power SRAM, real-time

clock, power-fail control circuit and battery

■BYTEWIDE™ RAM-like clock access

■BCD coded year, month, day, date, hours,

minutes, and seconds

■Frequency test output for real-time clock

■Automatic power-fail chip deselect and WRITE

protection

■WRITE protect voltages

(VPFD = power-fail deselect voltage):

–M48T58: V

CC = 4.75 to 5.5 V;

4.5 V ≤ VPFD ≤ 4.75 V

–M48T58Y: V

CC = 4.5 to 5.5 V;

4.2 V ≤ VPFD ≤ 4.5 V

■Self-contained battery and crystal in the

CAPHAT™ DIP package

■Packaging includes a 28-lead SOIC and

SNAPHAT® top (to be ordered separately)

■SOIC package provides direct connection for a

snaphat housing containing the battery and

crystal

■Pin and function compatible with JEDEC

standard 8 Kb x 8 SRAMs

■RoHS compliant

– Lead-free second level interconnect

PCDIP28

Battery/crystal

CAPHAT™

SNAPHAT®

Battery/crystal

SOH28

www.st.com

Contents M48T58, M48T58Y
2/33 Doc ID 2412 Rev 8
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE mode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data retention mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
3 Stopping and starting the oscillator   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
4 Calibrating the clock  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
5 Battery low flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
6 Century bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
7 VCC noise and negative going transients  . . . . . . . . . . . . . . . . . . . . . . . . .  20
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Part numbering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

M48T58, M48T58Y List of tables
Doc ID 2412 Rev 8 3/33
List of tables
Table 1. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. READ mode AC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. WRITE mode AC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Register map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Capacitance  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Power down/up trip points DC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data  . . . . . . . . . . . . . 25
Table 13. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®, package mech. 
data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package mech. data . . . . . 27
Table 15. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package mech. data . . . . 28
Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. SNAPHAT® battery table  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

List of figures M48T58, M48T58Y
4/33 Doc ID 2412 Rev 8
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Chip enable controlled, WRITE AC waveforms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 25
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®, package outline . . . 26
Figure 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, pack. outline . . . . . . . . . . . 27
Figure 16. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package outline. . . . . . . . 28
Figure 17. Recycling symbols  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

M48T58, M48T58Y Description

Doc ID 2412 Rev 8 5/33

1 Description

The M48T58/Y TIMEKEEPER® RAM is a 8 Kb x 8 non-volatile static RAM and real-time

clock. The monolithic chip is available in two special packages to provide a highly integrated

battery-backed memory and real-time clock solution.

The M48T58/Y is a non-volatile pin and function equivalent to any JEDEC standard

8b Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,

providing the non-volatility of PROMs without any requirement for special WRITE timing or

limitations on the number of WRITEs that can be performed.

The 28-pin, 600 mil DIP CAPHAT™ houses the M48T58/Y silicon with a quartz crystal and a

long life lithium button cell in a single package.

The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct

connection to a separate SNAPHAT® housing containing the battery and crystal. The

unique design allows the SNAPHAT battery package to be mounted on top of the SOIC

package after the completion of the surface mount process. Insertion of the SNAPHAT

housing after reflow prevents potential battery and crystal damage due to the high

temperatures required for device surface-mounting. The SNAPHAT housing is keyed to

prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in

plastic anti-static tubes or in tape & reel form.

For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28-

BR12SH”.

Figure 1. Logic diagram

AI01374B

A0-A12

DQ0-DQ7

VCC

M48T58

M48T58Y

VSS

E1 FT

Description M48T58, M48T58Y

6/33 Doc ID 2412 Rev 8

Table 1. Signal names

Figure 2. DIP connections

Figure 3. SOIC connections

A0-A12 Address inputs

DQ0-DQ7 Data inputs / outputs

FT Frequency test output (open drain)

E1 Chip enable 1

E2 Chip enable 2

GOutput enable

WWRITE enable

VCC Supply voltage

VSS Ground

DQ0

A10

DQ7

A11

DQ5DQ1

DQ2

DQ3VSS

DQ4

DQ6

A12

FT VCC

AI01375B

M48T58

M48T58Y

AI01376B

DQ0

A10

DQ7

A11

DQ5DQ1

DQ2

DQ3VSS

DQ4

DQ6

A12

FT VCC

M48T58Y

M48T58, M48T58Y Description

Doc ID 2412 Rev 8 7/33

Figure 4. Block diagram

AI01377C

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

VCC VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

8 x 8 BiPORT

SRAM ARRAY

8184 x 8

SRAM ARRAY

A0-A12

DQ0-DQ7

POWER

Operation modes M48T58, M48T58Y

8/33 Doc ID 2412 Rev 8

2 Operation modes

As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock

oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are

interconnected at the upper eight memory locations to provide user accessible

BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock

locations contain the century, year, month, date, day, hour, minute, and second in 24 hour

BCD format (except for the century). Corrections for 28, 29 (leap year - valid until 2100), 30,

and 31 day months are made automatically. Byte 1FF8h is the clock control register. This

byte controls user access to the clock information and also stores the clock calibration

setting.

The eight clock bytes are not the actual clock counters themselves; they are memory

locations consisting of BiPORT™ READ/write memory cells. The M48T58/Y includes a

clock control circuit which updates the clock bytes with current information once per second.

The information can be accessed by the user in the same manner as any other location in

the static memory array.

The M48T58/Y also has its own power-fail detect circuit. The control circuitry constantly

monitors the single 5 V supply for an out-of-tolerance condition. When VCC is out of

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

midst of unpredictable system operation brought on by low VCC. As VCC falls below the

battery backup switchover voltage (VSO), the control circuitry connects the battery which

maintains data and clock operation until valid power returns.

Table 2. Operating modes

Note: X = VIH or VIL; VSO = Battery backup switchover voltage.

Mode VCC E1 E2 G WDQ0-DQ7 Power

Deselect

4.75 to 5.5 V

4.5 to 5.5 V

VIH XXXHigh Z Standby

Deselect X VIL X X High Z Standby

WRITE VIL VIH XV

IL DIN Active

READ VIL VIH VIL VIH DOUT Active

READ VIL VIH VIH VIH High Z Active

Deselect VSO to VPFD

(min)(1)

1. See Table 11 on page 24 for details.

X X X X High Z CMOS standby

Deselect ≤ VSO(1) X X X X High Z Battery backup mode

M48T58, M48T58Y READ mode

Doc ID 2412 Rev 8 9/33

3 READ mode

The M48T58/Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip enable

1) is low, and E2 (chip enable 2) is high. The unique address specified by the 13 address

inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be

available at the data I/O pins within address access time (tAVQV) after the last address input

signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1,

E2 and G access times are not met, valid data will be available after the latter of the chip

enable access times (tE1LQV or tE2HQV) or output enable access time (tGLQV).

The state of the eight three-state data I/O signals is controlled by E1, E2 and G. If the

outputs are activated before tAVQV, the data lines will be driven to an indeterminate state

until tAVQV. If the address inputs are changed while E1, E2 and G remain active, output data

will remain valid for output data hold time (tAXQX) but will go indeterminate until the next

address access.

Figure 5. READ mode AC waveforms

Note: WRITE enable (W) = high.

AI00962

tAVAV

tAVQV tAXQX

tE1LQV

tE1LQX

tE1HQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A12

DQ0-DQ7

tE2HQV

tE2HQX

VALID

tE2LQZ

READ mode M48T58, M48T58Y

10/33 Doc ID 2412 Rev 8

Table 3. READ mode AC characteristics

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where

noted).

M48T58/Y

Unit

Min Max

tAVAV READ cycle time 70 ns

tAVQV Address valid to output valid 70 ns

tE1LQV Chip enable 1 low to output valid 70 ns

tE2HQV Chip enable 2 high to output valid 70 ns

tGLQV Output enable low to output valid 35 ns

tE1LQX(2)

2. CL = 5 pF.

Chip enable 1 low to output transition 5 ns

tE2HQX(2) Chip enable 2 high to output transition 5 ns

tGLQX(2) Output enable low to output transition 5 ns

tE1HQZ(2) Chip enable 1 high to output Hi-Z 25 ns

tE2LQZ(2) Chip enable 2 low to output Hi-Z 25 ns

tGHQZ(2) Output enable high to output Hi-Z 25 ns

tAXQX Address transition to output transition 10 ns

M48T58, M48T58Y WRITE mode

Doc ID 2412 Rev 8 11/33

4 WRITE mode

The M48T58/Y is in the WRITE mode whenever W and E1 are low and E2 is high. The start

of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge

of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2.

The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low

for a minimum of tE1HAX or tE2LAX from chip enable or tWHAX from WRITE enable prior to the

initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of

WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to

avoid bus contention; although, if the output bus has been activated by a low on E1 and G

and a high on E2, a low on W will disable the outputs tWLQZ after W falls.

Figure 6. WRITE enable controlled, WRITE AC waveform

AI00963

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A12

DQ0-DQ7

VALID

tAVWH

tAVE1L

tAVE2H

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

WRITE mode M48T58, M48T58Y

12/33 Doc ID 2412 Rev 8

Figure 7. Chip enable controlled, WRITE AC waveforms

AI00964B

tAVAV

tE1HAX

tDVE1H

tDVE2L

A0-A12

DQ0-DQ7

VALID

tAVE1H

tAVE1L

tAVWL

tAVE2L

tE1LE1H

tE2LAX

tAVE2H tE2HE2L

tE1HDX

tE2LDX

DATA INPUT

M48T58, M48T58Y WRITE mode

Doc ID 2412 Rev 8 13/33

Table 4. WRITE mode AC characteristics

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where

noted).

M48T58/Y

Unit

Min Max

tAVAV WRITE cycle time 70 ns

tAVWL Address valid to WRITE enable low 0 ns

tAVE1L Address valid to chip enable 1 low 0 ns

tAVE2H Address valid to chip enable 2 high 0 ns

tWLWH WRITE enable pulse width 50 ns

tE1LE1H Chip enable 1 low to chip enable 1 high 55 ns

tE2HE2L Chip enable 2 high to chip enable 2 low 55 ns

tWHAX WRITE enable high to address transition 0 ns

tE1HAX Chip enable 1 high to address transition 0 ns

tE2LAX Chip enable 2 low to address transition 0 ns

tDVWH Input valid to WRITE enable high 30 ns

tDVE1H Input valid to chip enable 1 high 30 ns

tDVE2L Input valid to chip enable 2 low 30 ns

tWHDX WRITE enable high to input transition 5 ns

tE1HDX Chip enable 1 high to input transition 5 ns

tE2LDX Chip enable 2 low to input transition 5 ns

tWLQZ(2)(3)

2. CL = 5 pF.

3. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance

state.

Write enable low to output Hi-Z 25 ns

tAVWH Address valid to WRITE enable high 60 ns

tAVE1H Address valid to chip enable 1 high 60 ns

tAVE2L Address valid to chip enable 2 low 60 ns

tWHQX(2)(3) WRITE enable high to output transition 5 ns

Data retention mode M48T58, M48T58Y

14/33 Doc ID 2412 Rev 8

5 Data retention mode

With valid VCC applied, the M48T58/Y operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write

protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs

become high impedance, and all inputs are treated as “don't care.”

Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the

user can be assured the memory will be in a write protected state, provided the VCC fall time

is not less than tF

. The M48T58/Y may respond to transient noise spikes on VCC that reach

into the deselect window during the time the device is sampling VCC. Therefore, decoupling

of the power supply lines is recommended.

When VCC drops below VSO, the control circuit switches power to the internal battery which

preserves data and powers the clock. The internal button cell will maintain data in the

M48T58/Y for an accumulated period of at least 7 years when VCC is less than VSO. As

system power returns and VCC rises above VSO, the battery is disconnected, and the power

supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min)

plus trec (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent

inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume

trec after VCC exceeds VPFD (max).

For more information on battery storage life refer to the application note AN1012.

M48T58, M48T58Y Clock operations

Doc ID 2412 Rev 8 15/33

6 Clock operations

6.1 Reading the clock

Updates to the TIMEKEEPER® registers (see Ta b l e 5 ) should be halted before clock data is

read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM

array are only data registers and not the actual clock counters, so updating the registers can

be halted without disturbing the clock itself.

Updating is halted when a '1' is written to the READ bit, D6 in the control register 1FF8h. As

long as a '1' remains in that position, updating is halted.

After a halt is issued, the registers reflect the count; that is, the day, date, and the time that

were current at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an

update in progress. Updating is within a second after the bit is reset to a '0.'

6.2 Setting the clock

Bit D7 of the control register (1FF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the

READ bit, halts updates to the TIMEKEEPER® registers. The user can then load them with

the correct day, date, and time data in 24-hour BCD format (see Ta b l e 5 ). Resetting the

WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual

TIMEKEEPER counters and allows normal operation to resume. The bits marked as '0' in

Table 5 on page 16 must be written to '0' to allow for normal TIMEKEEPER and RAM

operation. After the WRITE bit is reset, the next clock update will occur within one second.

See the application note AN923 “TIMEKEEPER Rolling Into the 21st Century” for

information on century rollover.

6.3 Stopping and starting the oscillator

The oscillator may be stopped at any time. If the device is going to spend a significant

amount of time on the shelf, the oscillator can be turned off to minimize current drain on the

battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the

oscillator. The M48T58/Y is shipped from STMicroelectronics with the STOP bit set to a '1.'

When reset to a '0,' the M48T58/Y oscillator starts within 1 second.

Clock operations M48T58, M48T58Y

16/33 Doc ID 2412 Rev 8

Table 5. Register map

Keys:

S = SIGN bit

FT = FREQUENCY TEST bit

R = READ bit

W = WRITE bit

ST = STOP bit

0 = Must be set to '0'

BLE = Battery low enable bit

BL = Battery low bit (read only)

CEB = Century enable bit

CB = Century bit

Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century

(dependent upon the initial value set).

When CEB is set to '0,' CB will not toggle. The WRITE bit does not need to be set to write to

CEB.

6.4 Calibrating the clock

The M48T58/Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768

Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency

error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits

properly set, the accuracy of each M48T58/Y improves to better than +1/–2 ppm at 25°C.

The oscillation rate of any crystal changes with temperature (see Figure 8 on page 18).

Most clock chips compensate for crystal frequency and temperature shift error with

cumbersome “trim” capacitors. The M48T58/Y design, however, employs periodic counter

correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit

at the divide by 256 stage, as shown in Figure 9 on page 18. The number of times pulses

are blanked (subtracted, negative calibration) or split (added, positive calibration) depends

upon the value loaded into the five calibration bits found in the control register. Adding

counts speeds the clock up, subtracting counts slows the clock down.

The calibration byte occupies the five lower order bits (D4-D0) in the control register 1FF8h.

These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the

Address

Data Function/range

BCD format

D7 D6 D5 D4 D3 D2 D1 D0

1FFFh 10 Years Year Year 00-99

1FFEh 0 0 0 10 M Month Month 01-12

1FFDh BLE BL 10 date Date Date 01-31

1FFCh 0 FT CEB CB 0 Day Century/day 0-1/1-7

1FFBh 0 0 10 hours Hours Hours 00-23

1FFAh 0 10 minutes Minutes Minutes 00-59

1FF9h ST 10 seconds Seconds Seconds 00-59

1FF8h W R S Calibration Control

M48T58, M48T58Y Clock operations

Doc ID 2412 Rev 8 17/33

sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs

within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one

second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is

loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator

cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of

adjustment per calibration step in the calibration register. Assuming that the oscillator is in

fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would

represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –

2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M48T58/Y may

require. The first involves simply setting the clock, letting it run for a month and comparing it

to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows

the designer to give the end user the ability to calibrate his clock as his environment may

require, even after the final product is packaged in a non-user serviceable enclosure. All the

designer has to do is provide a simple utility that accesses the calibration byte.

The second approach is better suited to a manufacturing environment, and involves the use

of some test equipment. When the frequency test (FT) bit (D6 in the day register) is set to a

'1,' and D7 of the seconds register is a '0' (oscillator running), The frequency test (pin 1) will

toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator

frequency shift at the test temperature. For example, a reading of 512.01024 Hz would

indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into

the calibration byte for correction.

The frequency test pin is an open drain output which requires a pull-up resistor for proper

operation. A 500-10 kΩ resistor is recommended in order to control the rise time.

For more information on calibration, see application note AN934, “TIMEKEEPER®

calibration.”

Clock operations M48T58, M48T58Y

18/33 Doc ID 2412 Rev 8

Figure 8. Crystal accuracy across temperature

Figure 9. Clock calibration

AI02124

-80

-60

-100

-40

-20

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

ΔF= -0.038 (T - T0)2 ± 10%

ppm

T0 = 25 °C

ppm

°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M48T58, M48T58Y Clock operations

Doc ID 2412 Rev 8 19/33

6.5 Battery low flag

The M48T58/Y automatically performs periodic battery voltage monitoring upon power-up.

The battery low flag (BL), bit D6 of the flags register 1FFDh, will be asserted high if the

internal or SNAPHAT® battery is found to be less than approximately 2.5 V and the battery

low enable (BLE) bit has been previously set to '1.' The BL flag will remain active until

completion of battery replacement and subsequent battery low monitoring tests.

If a battery low is generated during a power-up sequence, this indicates that the battery

voltage is below 2.5 V (approximately), which may be insufficient to maintain data integrity.

Data should be considered suspect and verified as correct. A fresh battery should be

installed.

The SNAPHAT top may be replaced while VCC is applied to the device.

Note: This will cause the clock to lose time during the interval the SNAPHAT® battery/crystal top is

disconnected.

Note: Battery monitoring is a useful technique only when performed periodically. The M48T58/Y

only monitors the battery when a nominal VCC is applied to the device. Thus applications

which require extensive durations in the battery back-up mode should be powered-up

periodically (at least once every few months) in order for this technique to be beneficial.

Additionally, if a battery low is indicated, data integrity should be verified upon power-up via

a checksum or other technique.

6.6 Century bit

Bit D5 and D4 of clock register 1FFCh contain the CENTURY ENABLE bit (CEB) and the

CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or

from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'

CB will not toggle.

Note: The WRITE bit must be set in order to write to the CENTURY bit.

Clock operations M48T58, M48T58Y

20/33 Doc ID 2412 Rev 8

6.7 VCC noise and negative going transients

ICC transients, including those produced by output switching, can produce voltage

fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if

capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the

bypass capacitors will be released as low going spikes are generated or energy will be

absorbed when overshoots occur. A bypass capacitor value of 0.1 µF (as shown in

Figure 10) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can

generate negative voltage spikes on VCC that drive it to values below VSS by as much as

one volt. These negative spikes can cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage spikes, it is recommended to connect a

Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode

1N5817 is recommended for through hole and MBRS120T3 is recommended for surface

mount.

Figure 10. Supply voltage protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

M48T58, M48T58Y Maximum ratings

Doc ID 2412 Rev 8 21/33

7 Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 6. Absolute maximum ratings

Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup

mode.

Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT® sockets.

Symbol Parameter Value Unit

TAAmbient operating temperature 0 to 70 °C

TSTG Storage temperature (VCC off, oscillator off) –40 to 85 °C

TSLD(1)(2)(3)

1. For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds.

Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of

wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat

damage to the batteries.

2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid

damaging the crystal.

3. For SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (the time above

255°C must not exceed 30 seconds).

Lead solder temperature for 10 seconds 260 °C

VIO Input or output voltages –0.3 to 7 V

VCC Supply voltage –0.3 to 7 V

IOOutput current 20 mA

PDPower dissipation 1 W

DC and AC parameters M48T58, M48T58Y

22/33 Doc ID 2412 Rev 8

8 DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and

AC characteristics of the device. The parameters in the following DC and AC characteristic

tables are derived from tests performed under the measurement conditions listed in Ta bl e 7 .

Designers should check that the operating conditions in their projects match the

measurement conditions when using the quoted parameters.

Table 7. Operating and AC measurement conditions

Note: Output Hi-Z is defined as the point where data is no longer driven.

Figure 11. AC measurement load circuit

Table 8. Capacitance

Parameter M48T58 M48T58Y Unit

Supply voltage (VCC) 4.75 to 5.5 4.5 to 5.5 V

Ambient operating temperature (TA) 0 to 70 0 to 70 °C

Load capacitance (CL)100100pF

Input rise and fall times ≤ 5 ≤ 5ns

Input pulse voltages 0 to 3 0 to 3 V

Input and output timing ref. voltages 1.5 1.5 V

Symbol Parameter(1)(2)

1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.

2. At 25 °C, f = 1 MHz.

Min Max Unit

CIN Input capacitance - 10 pF

COUT(3)

3. Outputs deselected.

Output capacitance - 10 pF

AI01030

OUT

CL = 100pF or 5pF

CL includes JIG capacitance

1.9kΩ

DEVICE

UNDER

TEST

1kΩ

M48T58, M48T58Y DC and AC parameters

Doc ID 2412 Rev 8 23/33

Table 9. DC characteristics

Figure 12. Power down/up mode AC waveforms

Symbol Parameter Test condition(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).

M48T58 M48T58Y

Unit

Min Max Min Max

ILI Input leakage current 0 V ≤ VIN ≤ VCC ±1 ±1 µA

ILO(2)

2. Outputs deselected.

Output leakage current 0 V ≤ VOUT ≤ VCC ±1 ±1 µA

ICC Supply current Outputs open 50 50 mA

ICC1 Supply current (standby) TTL E1 = VIH

E2 = VIO

33mA

ICC2

Supply current (standby)

CMOS

E1 = VCC – 0.2 V

E2 = VSS + 0.2 V 33mA

VIL Input low voltage –0.3 0.8 –0.3 0.8 V

VIH Input high voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V

VOL

Output low voltage IOL = 2.1 mA 0.4 0.4

Output low voltage (FT)(3)

3. The FT pin is open drain.

IOL = 10 mA 0.4 0.4 V

VOH Output high voltage IOH = –1 mA 2.4 2.4 V

AI01168C

VCC

INPUTS

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tFB

tPD

tRB

tDR

VALID VALID

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

trec

DC and AC parameters M48T58, M48T58Y

24/33 Doc ID 2412 Rev 8

Table 10. Power down/up AC characteristics

Table 11. Power down/up trip points DC characteristics

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where

noted).

Min Max Unit

tPD E1 or W at VIH or E2 at VIL before power down 0 µs

tF(2)

2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring

until 200 µs after VCC passes VPFD (min).

VPFD (max) to VPFD (min) VCC fall time 300 µs

tFB(3)

3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

VPFD (min) to VSS VCC fall time M48T58 10 µs

M48T58Y 10 µs

tRVPFD (min) to VPFD (max) VCC rise time 10 µs

tRB VSS to VPFD (min) VCC rise time 1 µs

trec VPFD (max) to inputs recognized 40 200 ms

Symbol Parameter(1)(2)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where

noted).

2. All voltages referenced to VSS.

Min Typ Max Unit

VPFD Power-fail deselect voltage M48T58 4.5 4.6 4.75 V

M48T58Y 4.2 4.35 4.5 V

VSO Battery backup switchover voltage 3.0 V

tDR(3)

3. At 25 °C, VCC = 0 V.

Expected data retention time 7 Years

M48T58, M48T58Y Package mechanical data

Doc ID 2412 Rev 8 25/33

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline

Note: Drawing is not to scale.

Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data

PCDIP

B1 B e1

Symb

mm inches

Typ Min Max Typ Min Max

A 8.89 9.65 0.350 0.380

A1 0.38 0.76 0.015 0.030

A2 8.38 8.89 0.330 0.350

B 0.38 0.53 0.015 0.021

B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012

D 39.37 39.88 1.550 1.570

E 17.83 18.34 0.702 0.722

e1 2.29 2.79 0.090 0.110

e3 33.02 1.3

eA 15.24 16.00 0.600 0.630

L 3.05 3.81 0.120 0.150

N28 28

Package mechanical data M48T58, M48T58Y

26/33 Doc ID 2412 Rev 8

Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®,

package outline

Note: Drawing is not to scale.

SOH-A

LA1 a

Table 13. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®, package

mech. data

Symb

mm inches

Typ Min Max Typ Min Max

A3.050.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e1.27– –0.050– –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

a 0°8° 0°8°

N28 28

CP 0.10 0.004

M48T58, M48T58Y Package mechanical data

Doc ID 2412 Rev 8 27/33

Figure 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, pack. outline

Note: Drawing is not to scale.

SHTK-A

A1 A

Table 14. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package mech.

data

Symb

mm inches

Typ Min Max Typ Min Max

A9.780.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

Package mechanical data M48T58, M48T58Y

28/33 Doc ID 2412 Rev 8

Figure 16. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package

outline

Note: Drawing is not to scale.

SHTK-A

A1 A

Table 15. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package

mech. data

Symb

mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

M48T58, M48T58Y Part numbering

Doc ID 2412 Rev 8 29/33

10 Part numbering

Table 16. Ordering information scheme

Caution: Do not place the SNAPHAT® battery package “M4TXX-BR12SH” in conductive foam as it

will drain the lithium button-cell battery.

For other options, or for more information on any aspect of this device, please contact the

ST sales office nearest you.

Example: M48T 58 –70 MH 1 E

Device type

M48T

Supply voltage and write protect voltage

58(1) = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V

1. The M48T58 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.

58Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V

Speed

–70 = 70 ns

Package

PC = PCDIP28

MH(2) = SOH28

2. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under

the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see

Table 17).

Temperature range

1 = 0 to 70°C

Shipping method

For SOH28:

blank = Tubes (not for new design - use E)

E = Lead-free package (ECOPACK®), tubes

F = Lead-free package (ECOPACK®), tape & reel

TR = Tape & reel (not for new design - use F)

For PCDIP28:

blank = Tubes

Part numbering M48T58, M48T58Y

30/33 Doc ID 2412 Rev 8

Table 17. SNAPHAT® battery table

Part number Description Package

M4T28-BR12SH Lithium battery (48 mAh) SNAPHAT®SH

M4T32-BR12SH Lithium battery (120 mAh) SNAPHAT®SH

M48T58, M48T58Y Environmental information

Doc ID 2412 Rev 8 31/33

11 Environmental information

Figure 17. Recycling symbols

This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)

button cell battery fully encapsulated in the final product.

Recycle or dispose of batteries in accordance with the battery manufacturer's instructions

and local/national disposal and recycling regulations.

Revision history M48T58, M48T58Y
32/33 Doc ID 2412 Rev 8
12 Revision history
Table 18. Document revision history
         
Date Revision Changes
Jul-1999 1 First issue
27-Jul-2000 1.1 Century bit and battery low flag paragraphs added; power down/up AC 
characteristics table and waveforms changed (Ta bl e 1 0, Figure 12)
04-Jun-2001 2 Reformatted; temperature information added (Ta b le 9 , 3, 4, 10, 11)
31-Jul-2001 2.1 Formatting changes from recent document review findings
20-May-2002 2.2 Modify reflow time and temperature footnotes (Ta bl e 6 )
01-Apr-2003 3 v2.2 template applied; test condition updated (Ta b l e 1 1 )
17-Jul-2003 3.1 Update “battery low flag” information
02-Apr-2004 4 Reformatted; update lead-free packaging information (Ta b l e 6 , 16)
30-Aug-2007 5 Reformatted; added lead-free second level interconnect information to 
cover page and Section 9: Package mechanical data; updated Ta b le 9 .
24-Mar-2009 6 UpdatedTa b le 6 , Section 9: Package mechanical data; added Section 11: 
Environmental information; minor reformatting.
02-Aug-2010 7 Reformatted document; updated Section 7, Ta bl e 12 .
07-Jun-2011 8 Updated footnote 1 of Table 6: Absolute maximum ratings; updated 
Section 11: Environmental information.

M48T58, M48T58Y

Doc ID 2412 Rev 8 33/33

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