Document No. U17260EJ3V1UD00 (3rd edition)
Date Published August 2005 N CP(K)
Printed in Japan
2004
µ
PD78F0531
µ
PD78F0532
µ
PD78F0533
µ
PD78F0534
µ
PD78F0535
µ
PD78F0536
µ
PD78F0537
µ
PD78F0537D
78K0/KE2
8-Bit Single-Chip Microcontrollers
Preliminary User’s Manual
The
µ
PD78F0537D has an on-chip debug function.
Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function
has been used, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics
does not accept complaints concerning this product.
Preliminary User’s Manual U17260EJ3V1UD
2
[MEMO]
Preliminary User’s Manual U17260EJ3V1UD 3
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
Preliminary User’s Manual U17260EJ3V1UD
4
EEPROM is a trademark of NEC Electronics Corporation.
Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products,
customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
Electronics product before using it in a particular application.
•
•
•
•
•
•
•
M5D 02. 11-1
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio and
visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
Preliminary User’s Manual U17260EJ3V1UD 5
Regional Information
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
J05.6
N
EC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
• Succursale Française
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-265 40 10
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 87 200
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
Preliminary User’s Manual U17260EJ3V1UD
6
INTRODUCTION
Readers This manual is intended for user engineers who wish to understand the functions of the
78K0/KE2 and design and develop application systems and programs for these devices.
The target products are as follows.
78K0/KE2:
µ
PD78F0531, 78F0532, 78F0533, 78F0534, 78F0535, 78F0536, 78F0537,
78F0537D
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The 78K0/KE2 manual is separated into two parts: this manual and the instructions
edition (common to the 78K/0 Series).
78K0/KE2
User’s Manual
(This Manual)
78K/0 Series
User’s Manual
Instructions
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• Electrical specifications (target)
• CPU functions
• Instruction set
• Explanation of each instruction
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark shows major
revised points.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a
reserved word in the RA78K0, and is defined as an sfr variable using the
#pragma sfr directive in the CC78K0.
• To check the details of a register when you know the register name:
→ See APPENDIX C REGISTER INDEX.
• To know details of the 78K/0 Series instructions:
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
Preliminary User’s Manual U17260EJ3V1UD 7
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
... ×××× or ××××B
Decimal
... ××××
Hexadecimal
... ××××H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
78K0/KE2 User’s Manual This manual
78K/0 Series Instructions User’s Manual U12326E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
Operation U17199E
Language U17198E
RA78K0 Ver. 3.80 Assembler Package
Structured Assembly Language U17197E
Operation U17201E CC78K0 Ver. 3.70 C Compiler
Language U17200E
Operation U17246E SM+ System Simulator
External Part User Open Interface
Specifications
U17247E
ID78K0-QB Ver. 2.90 Integrated Debugger Operation U17437E
PM+ Ver. 5.20 U16934E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name Document No.
QB-78K0KX2 In-Circuit Emulator U17341E
QB-78K0MINI On-Chip Debug Emulator U17029E
Documents Related to Flash Memory Programming
Document Name Document No.
PG-FP4 Flash Memory Programmer User’s Manual U15260E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Preliminary User’s Manual U17260EJ3V1UD
8
Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Preliminary User’s Manual U17260EJ3V1UD 9
CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 17
1.1 Features .................................................................................................................................... 17
1.2 Applications ............................................................................................................................. 18
1.3 Ordering Information ............................................................................................................... 19
1.4 Pin Configuration (Top View).................................................................................................. 23
1.5 78K0/Kx2 Series Lineup .......................................................................................................... 26
1.6 Block Diagram.......................................................................................................................... 29
1.7 Outline of Functions ................................................................................................................ 30
CHAPTER 2 PIN FUNCTIONS............................................................................................................... 32
2.1 Pin Function List...................................................................................................................... 32
2.2 Description of Pin Functions.................................................................................................. 36
2.2.1 P00 to P06 (port 0).....................................................................................................................36
2.2.2 P10 to P17 (port 1).....................................................................................................................37
2.2.3 P20 to P27 (port 2).....................................................................................................................38
2.2.4 P30 to P33 (port 3).....................................................................................................................38
2.2.5 P40 to P43 (port 4).....................................................................................................................39
2.2.6 P50 to P53 (port 5).....................................................................................................................39
2.2.7 P60 to P63 (port 6).....................................................................................................................39
2.2.8 P70 to P77 (port 7).....................................................................................................................39
2.2.9 P120 to P124 (port 12)...............................................................................................................40
2.2.10 P130 (port 13) ............................................................................................................................40
2.2.11 P140, P141 (port 14)..................................................................................................................41
2.2.12 AVREF .........................................................................................................................................41
2.2.13 AVSS ...........................................................................................................................................41
2.2.14 RESET .......................................................................................................................................41
2.2.15 REGC.........................................................................................................................................41
2.2.16 VDD and EVDD .............................................................................................................................42
2.2.17 VSS and EVSS .............................................................................................................................42
2.2.18 FLMD0 .......................................................................................................................................42
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins....................................... 43
CHAPTER 3 CPU ARCHITECTURE...................................................................................................... 47
3.1 Memory Space.......................................................................................................................... 47
3.1.1 Internal program memory space ................................................................................................56
3.1.2 Memory bank (
µ
PD78F0536, 78F0537, and 78F0537D only)....................................................58
3.1.3 Internal data memory space.......................................................................................................58
3.1.4 Special function register (SFR) area ..........................................................................................59
3.1.5 Data memory addressing ...........................................................................................................59
3.2 Processor Registers ................................................................................................................ 67
3.2.1 Control registers.........................................................................................................................67
3.2.2 General-purpose registers .........................................................................................................71
3.2.3 Special function registers (SFRs)...............................................................................................72
Preliminary User’s Manual U17260EJ3V1UD
10
3.3 Instruction Address Addressing ............................................................................................ 77
3.3.1 Relative addressing................................................................................................................... 77
3.3.2 Immediate addressing ............................................................................................................... 78
3.3.3 Table indirect addressing .......................................................................................................... 79
3.3.4 Register addressing .................................................................................................................. 79
3.4 Operand Address Addressing ................................................................................................ 80
3.4.1 Implied addressing .................................................................................................................... 80
3.4.2 Register addressing .................................................................................................................. 81
3.4.3 Direct addressing ...................................................................................................................... 82
3.4.4 Short direct addressing ............................................................................................................. 83
3.4.5 Special function register (SFR) addressing ............................................................................... 84
3.4.6 Register indirect addressing...................................................................................................... 85
3.4.7 Based addressing...................................................................................................................... 86
3.4.8 Based indexed addressing ........................................................................................................ 87
3.4.9 Stack addressing....................................................................................................................... 88
CHAPTER 4 MEMORY BANK SELECT FUNCTION
(
µ
PD78F0536, 78F0537, AND 78F0537D ONLY) ......................................................... 89
4.1 Memory Bank............................................................................................................................ 89
4.2 Memory Bank Select Register (BANK)................................................................................... 90
4.3 Selecting Memory Bank........................................................................................................... 91
4.3.1 Referencing values between memory banks............................................................................. 91
4.3.2 Branching instruction between memory banks.......................................................................... 93
4.3.3 Subroutine call between memory banks.................................................................................... 95
4.3.4 Instruction branch to bank area by interrupt ..............................................................................97
CHAPTER 5 PORT FUNCTIONS ........................................................................................................... 99
5.1 Port Functions.......................................................................................................................... 99
5.2 Port Configuration ................................................................................................................. 101
5.2.1 Port 0........................................................................................................................................102
5.2.2 Port 1........................................................................................................................................108
5.2.3 Port 2........................................................................................................................................113
5.2.4 Port 3........................................................................................................................................114
5.2.5 Port 4........................................................................................................................................116
5.2.6 Port 5........................................................................................................................................117
5.2.7 Port 6........................................................................................................................................118
5.2.8 Port 7........................................................................................................................................120
5.2.9 Port 12......................................................................................................................................121
5.2.10 Port 13......................................................................................................................................123
5.2.11 Port 14......................................................................................................................................124
5.3 Registers Controlling Port Function .................................................................................... 125
5.4 Port Function Operations...................................................................................................... 130
5.4.1 Writing to I/O port .....................................................................................................................130
5.4.2 Reading from I/O port...............................................................................................................130
5.4.3 Operations on I/O port..............................................................................................................130
5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function....... 131
CHAPTER 6 CLOCK GENERATOR .................................................................................................... 134
Preliminary User’s Manual U17260EJ3V1UD 11
6.1 Functions of Clock Generator .............................................................................................. 134
6.2 Configuration of Clock Generator........................................................................................ 135
6.3 Registers Controlling Clock Generator ............................................................................... 137
6.4 System Clock Oscillator........................................................................................................ 146
6.4.1 X1 oscillator .............................................................................................................................146
6.4.2 XT1 oscillator ...........................................................................................................................146
6.4.3 When subsystem clock is not used ..........................................................................................149
6.4.4 Internal high-speed oscillator ...................................................................................................149
6.4.5 Internal low-speed oscillator.....................................................................................................149
6.4.6 Prescaler..................................................................................................................................149
6.5 Clock Generator Operation................................................................................................... 150
6.6 Controlling Clock ................................................................................................................... 153
6.6.1 Controlling high-speed system clock........................................................................................153
6.6.2 Example of controlling internal high-speed oscillation clock.....................................................156
6.6.3 Example of controlling subsystem clock...................................................................................158
6.6.4 Example of controlling internal low-speed oscillation clock ......................................................160
6.6.5 Clocks supplied to CPU and peripheral hardware....................................................................160
6.6.6 CPU clock status transition diagram ........................................................................................161
6.6.7 Condition before changing CPU clock and processing after changing CPU clock ...................166
6.6.8 Time required for switchover of CPU clock and main system clock .........................................167
6.6.9 Conditions before clock oscillation is stopped..........................................................................168
6.6.10 Peripheral hardware and source clocks ...................................................................................169
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 ........................................................ 170
7.1 Functions of 16-Bit Timer/Event Counters 00 and 01 ........................................................ 170
7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01.................................................. 171
7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 ......................................... 176
7.4 Operation of 16-Bit Timer/Event Counters 00 and 01 ........................................................ 188
7.4.1 Interval timer operation ............................................................................................................188
7.4.2 Square wave output operation .................................................................................................191
7.4.3 External event counter operation .............................................................................................194
7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input....................................197
7.4.5 Free-running timer operation....................................................................................................213
7.4.6 PPG output operation...............................................................................................................222
7.4.7 One-shot pulse output operation..............................................................................................225
7.4.8 Pulse width measurement operation........................................................................................230
7.5 Special Use of TM0n .............................................................................................................. 239
7.5.1 Rewriting CR01n during TM0n operation .................................................................................239
7.5.2 Setting LVS0n and LVR0n .......................................................................................................239
7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01......................................................... 241
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 .......................................................... 245
8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 .......................................................... 245
8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51.................................................... 245
8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ........................................... 248
8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 ........................................................ 253
8.4.1 Operation as interval timer .......................................................................................................253
8.4.2 Operation as external event counter ........................................................................................255
Preliminary User’s Manual U17260EJ3V1UD
12
8.4.3 Square-wave output operation .................................................................................................256
8.4.4 PWM output operation..............................................................................................................257
8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51........................................................... 261
CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 262
9.1 Functions of 8-Bit Timers H0 and H1 ................................................................................... 262
9.2 Configuration of 8-Bit Timers H0 and H1............................................................................. 262
9.3 Registers Controlling 8-Bit Timers H0 and H1 .................................................................... 266
9.4 Operation of 8-Bit Timers H0 and H1 ................................................................................... 271
9.4.1 Operation as interval timer/square-wave output.......................................................................271
9.4.2 Operation as PWM output ........................................................................................................274
9.4.3 Carrier generator operation (8-bit timer H1 only)......................................................................280
CHAPTER 10 WATCH TIMER.............................................................................................................. 287
10.1 Functions of Watch Timer ..................................................................................................... 287
10.2 Configuration of Watch Timer............................................................................................... 288
10.3 Register Controlling Watch Timer........................................................................................ 289
10.4 Watch Timer Operations........................................................................................................ 291
10.4.1 Watch timer operation ..............................................................................................................291
10.4.2 Interval timer operation.............................................................................................................291
10.5 Cautions for Watch Timer ..................................................................................................... 292
CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 293
11.1 Functions of Watchdog Timer .............................................................................................. 293
11.2 Configuration of Watchdog Timer........................................................................................ 294
11.3 Register Controlling Watchdog Timer ................................................................................. 295
11.4 Operation of Watchdog Timer............................................................................................... 296
11.4.1 Controlling operation of watchdog timer ...................................................................................296
11.4.2 Setting overflow time of watchdog timer...................................................................................297
11.4.3 Setting window open period of watchdog timer ........................................................................298
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 300
12.1 Functions of Clock Output/Buzzer Output Controller........................................................ 300
12.2 Configuration of Clock Output/Buzzer Output Controller ................................................. 301
12.3 Registers Controlling Clock Output/Buzzer Output Controller......................................... 301
12.4 Operations of Clock Output/Buzzer Output Controller ...................................................... 303
12.4.1 Operation as clock output.........................................................................................................303
12.4.2 Operation as buzzer output ......................................................................................................303
CHAPTER 13 A/D CONVERTER ......................................................................................................... 304
13.1 Function of A/D Converter .................................................................................................... 304
13.2 Configuration of A/D Converter ............................................................................................ 305
13.3 Registers Used in A/D Converter.......................................................................................... 307
13.4 A/D Converter Operations ..................................................................................................... 315
13.4.1 Basic operations of A/D converter............................................................................................315
13.4.2 Input voltage and conversion results ........................................................................................317
Preliminary User’s Manual U17260EJ3V1UD 13
13.4.3 A/D converter operation mode .................................................................................................318
13.5 How to Read A/D Converter Characteristics Table ............................................................ 320
13.6 Cautions for A/D Converter................................................................................................... 322
CHAPTER 14 SERIAL INTERFACE UART0 ...................................................................................... 326
14.1 Functions of Serial Interface UART0 ................................................................................... 326
14.2 Configuration of Serial Interface UART0 ............................................................................. 327
14.3 Registers Controlling Serial Interface UART0 .................................................................... 330
14.4 Operation of Serial Interface UART0.................................................................................... 335
14.4.1 Operation stop mode................................................................................................................335
14.4.2 Asynchronous serial interface (UART) mode ...........................................................................336
14.4.3 Dedicated baud rate generator ................................................................................................342
CHAPTER 15 SERIAL INTERFACE UART6 ...................................................................................... 347
15.1 Functions of Serial Interface UART6 ................................................................................... 347
15.2 Configuration of Serial Interface UART6 ............................................................................. 351
15.3 Registers Controlling Serial Interface UART6 .................................................................... 354
15.4 Operation of Serial Interface UART6.................................................................................... 363
15.4.1 Operation stop mode................................................................................................................363
15.4.2 Asynchronous serial interface (UART) mode ...........................................................................364
15.4.3 Dedicated baud rate generator ................................................................................................377
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11................................................................ 384
16.1 Functions of Serial Interfaces CSI10 and CSI11................................................................. 384
16.2 Configuration of Serial Interfaces CSI10 and CSI11 .......................................................... 385
16.3 Registers Controlling Serial Interfaces CSI10 and CSI11.................................................. 388
16.4 Operation of Serial Interfaces CSI10 and CSI11 ................................................................. 393
16.4.1 Operation stop mode................................................................................................................393
16.4.2 3-wire serial I/O mode..............................................................................................................394
CHAPTER 17 SERIAL INTERFACE IIC0 ........................................................................................... 406
17.1 Functions of Serial Interface IIC0......................................................................................... 406
17.2 Configuration of Serial Interface IIC0 .................................................................................. 409
17.3 Registers to Control Serial Interface IIC0............................................................................ 412
17.4 I2C Bus Mode Functions........................................................................................................ 425
17.4.1 Pin configuration ......................................................................................................................425
17.5 I2C Bus Definitions and Control Methods............................................................................ 426
17.5.1 Start conditions ........................................................................................................................426
17.5.2 Addresses ................................................................................................................................427
17.5.3 Transfer direction specification ................................................................................................427
17.5.4 Acknowledge (ACK).................................................................................................................428
17.5.5 Stop condition ..........................................................................................................................429
17.5.6 Wait..........................................................................................................................................430
17.5.7 Canceling wait..........................................................................................................................432
17.5.8 Interrupt request (INTIIC0) generation timing and wait control.................................................432
17.5.9 Address match detection method.............................................................................................433
17.5.10 Error detection .........................................................................................................................433
Preliminary User’s Manual U17260EJ3V1UD
14
17.5.11 Extension code.........................................................................................................................434
17.5.12 Arbitration.................................................................................................................................435
17.5.13 Wakeup function.......................................................................................................................436
17.5.14 Communication reservation......................................................................................................437
17.5.15 Other cautions ..........................................................................................................................440
17.5.16 Communication operations.......................................................................................................442
17.5.17 Timing of I2C interrupt request (INTIIC0) occurrence................................................................449
17.6 Timing Charts ......................................................................................................................... 470
CHAPTER 18 MULTIPLIER/DIVIDER
(
µ
PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) .................... 477
18.1 Functions of Multiplier/Divider ............................................................................................. 477
18.2 Configuration of Multiplier/Divider ....................................................................................... 477
18.3 Register Controlling Multiplier/Divider ................................................................................ 481
18.4 Operations of Multiplier/Divider............................................................................................ 482
18.4.1 Multiplication operation.............................................................................................................482
18.4.2 Division operation.....................................................................................................................484
CHAPTER 19 INTERRUPT FUNCTIONS ............................................................................................ 486
19.1 Interrupt Function Types....................................................................................................... 486
19.2 Interrupt Sources and Configuration ................................................................................... 486
19.3 Registers Controlling Interrupt Functions .......................................................................... 491
19.4 Interrupt Servicing Operations ............................................................................................. 499
19.4.1 Maskable interrupt acknowledgement ......................................................................................499
19.4.2 Software interrupt request acknowledgement ..........................................................................501
19.4.3 Multiple interrupt servicing........................................................................................................502
19.4.4 Interrupt request hold ...............................................................................................................505
CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 506
20.1 Functions of Key Interrupt .................................................................................................... 506
20.2 Configuration of Key Interrupt.............................................................................................. 506
20.3 Register Controlling Key Interrupt ....................................................................................... 507
CHAPTER 21 STANDBY FUNCTION .................................................................................................. 508
21.1 Standby Function and Configuration................................................................................... 508
21.1.1 Standby function.......................................................................................................................508
21.1.2 Registers controlling standby function......................................................................................508
21.2 Standby Function Operation................................................................................................. 511
21.2.1 HALT mode ..............................................................................................................................511
21.2.2 STOP mode .............................................................................................................................516
CHAPTER 22 RESET FUNCTION........................................................................................................ 521
22.1 Register for Confirming Reset Source................................................................................. 529
CHAPTER 23 POWER-ON-CLEAR CIRCUIT...................................................................................... 530
23.1 Functions of Power-on-Clear Circuit ................................................................................... 530
Preliminary User’s Manual U17260EJ3V1UD 15
23.2 Configuration of Power-on-Clear Circuit............................................................................. 531
23.3 Operation of Power-on-Clear Circuit ................................................................................... 531
23.4 Cautions for Power-on-Clear Circuit.................................................................................... 534
CHAPTER 24 LOW-VOLTAGE DETECTOR ....................................................................................... 536
24.1 Functions of Low-Voltage Detector ..................................................................................... 536
24.2 Configuration of Low-Voltage Detector............................................................................... 536
24.3 Registers Controlling Low-Voltage Detector ...................................................................... 537
24.4 Operation of Low-Voltage Detector ..................................................................................... 540
24.4.1 When used as reset .................................................................................................................541
24.4.2 When used as interrupt ............................................................................................................546
24.5 Cautions for Low-Voltage Detector...................................................................................... 551
CHAPTER 25 OPTION BYTE............................................................................................................... 554
25.1 Functions of Option Bytes.................................................................................................... 554
25.2 Format of Option Byte ........................................................................................................... 555
CHAPTER 26 FLASH MEMORY.......................................................................................................... 558
26.1 Internal Memory Size Switching Register ........................................................................... 558
26.2 Internal Expansion RAM Size Switching Register.............................................................. 560
26.3 Writing with Flash Programmer ........................................................................................... 561
26.4 Programming Environment................................................................................................... 564
26.5 Communication Mode ........................................................................................................... 564
26.6 Handling of Pins on Board.................................................................................................... 566
26.6.1 FLMD0 pin ...............................................................................................................................566
26.6.2 Serial interface pins..................................................................................................................566
26.6.3 RESET pin ...............................................................................................................................568
26.6.4 Port pins...................................................................................................................................568
26.6.5 REGC pin.................................................................................................................................568
26.6.6 Other signal pins ......................................................................................................................568
26.6.7 Power supply ...........................................................................................................................568
26.7 Programming Method............................................................................................................ 569
26.7.1 Controlling flash memory .........................................................................................................569
26.7.2 Flash memory programming mode ..........................................................................................569
26.7.3 Selecting communication mode ...............................................................................................570
26.7.4 Communication commands......................................................................................................571
26.8 Security Settings.................................................................................................................... 572
26.9 Flash Memory Programming by Self-Programming........................................................... 574
26.9.1 Boot swap function...................................................................................................................576
CHAPTER 27 ON-CHIP DEBUG FUNCTION (
µ
PD78F0537D ONLY) ............................................ 578
27.1 On-Chip Debug Security ID................................................................................................... 579
CHAPTER 28 INSTRUCTION SET ...................................................................................................... 580
28.1 Conventions Used in Operation List.................................................................................... 580
28.1.1 Operand identifiers and specification methods ........................................................................580
Preliminary User’s Manual U17260EJ3V1UD
16
28.1.2 Description of operation column...............................................................................................581
28.1.3 Description of flag operation column ........................................................................................581
28.2 Operation List ......................................................................................................................... 582
28.3 Instructions Listed by Addressing Type ............................................................................. 590
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET).............................................................. 593
CHAPTER 30 PACKAGE DRAWINGS ................................................................................................ 612
CHAPTER 31 CAUTIONS FOR WAIT................................................................................................. 617
31.1 Cautions for Wait.................................................................................................................... 617
31.2 Peripheral Hardware That Generates Wait .......................................................................... 618
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 619
A.1 Software Package .................................................................................................................. 622
A.2 Language Processing Software............................................................................................ 622
A.3 Control Software .................................................................................................................... 623
A.4 Flash Memory Writing Tools ................................................................................................. 623
A.5 Debugging Tools (Hardware) ................................................................................................ 624
A.5.1 When using in-circuit emulator QB-78K0KX2...........................................................................624
A.5.2 When using on-chip debug emulator QB-78K0MINI.................................................................625
A.6 Debugging Tools (Software) ................................................................................................. 625
APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 626
APPENDIX C REGISTER INDEX ......................................................................................................... 628
C.1 Register Index (In Alphabetical Order with Respect to Register Names) ........................ 628
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ....................... 632
APPENDIX D REVISION HISTORY ..................................................................................................... 636
D.1 Major Revisions in This Edition............................................................................................ 636
D.2 Revisions History up to Previous Edition ........................................................................... 643
Preliminary User’s Manual U17260EJ3V1UD 17
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.1
µ
s: @ 20 MHz operation with high-
speed system clock) to ultra low-speed (122
µ
s: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
Data Memory Item
Part Number
Program Memory
(ROM) Internal High-Speed RAMNote Internal Expansion RAMNote
µ
PD78F0531 16 KB 768 bytes
µ
PD78F0532 24 KB
µ
PD78F0533 32 KB
−
µ
PD78F0534 48 KB 1 KB
µ
PD78F0535 60 KB 2 KB
µ
PD78F0536 96 KB 4 KB
µ
PD78F0537, 78F0537D
Flash memoryNote
128 KB
1 KB
6 KB
Note The internal flash memory, internal high-speed RAM capacities, and internal expansion RAM capacities
can be changed using the internal memory size switching register (IMS) and the internal expansion RAM
size switching register (IXS). For IMS and IXS, see 26.1 Memory Size Switching Register and 26.2
Internal Expansion RAM Size Switching Register.
{ On-chip single-power-supply flash memory
{ Self-programming (with boot swap function)
{ On-chip debug function (
µ
PD78F0537D only)Note
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ On-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock)
{ On-chip multiplier/divider (16 bits × 16 bits, 32 bits / 16 bits)
(
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only)
{ On-chip key interrupt function
{ On-chip clock output/buzzer output controller
{ I/O ports: 55 (N-ch open drain: 4)
Note The
µ
PD78F0537D has an on-chip debug function. Do not use this product for mass production because its
reliability cannot be guaranteed after the on-chip debug function has been used, from the viewpoint of the
restriction on the number of times the flash memory can be rewritten. NEC Electronics does not accept any
complaint about this product.
CHAPTER 1 OUTLINE
Preliminary User’s Manual U17260EJ3V1UD
18
{ Timer
µ
PD78F0531, 78F0532, 78F0533: 7 channels
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D: 8 channels
• 16-bit timer/event counter: 2 channelsNote
• 8-bit timer/event counter: 2 channels
• 8-bit timer: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
Note
µ
PD78F0531, 78F0532, 78F0533: 1 channel
{ Serial interface
µ
PD78F0531, 78F0532, 78F0533: 3 channels
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D: 4 channels
• UART (LIN (Local Interconnect Network)-bus supported: 1 channel
• CSI/UARTNote1: 1 channel
• CSI Note2: 1 channel
• I
2C: 1 channel
Notes 1. Select either of the functions of these alternate-function pins.
2.
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only
{ 10-bit resolution A/D converter (AVREF = 2.3 to 5.5 V): 8 channels
{ Power supply voltage: VDD = 1.8 to 5.5 V
{ Operating ambient temperature:
• T
A = −40 to +85°C: (T), (S), (R) products
• TA = −40 to +125°C: (T2) product
1.2 Applications
{ Automotive equipment ((A), (A1), (A2) grade products, under development)
• System control for body electricals (power windows, keyless entry reception, etc.)
• Sub-microcontrollers for control
{ Car audio
{ AV equipment, home audio
{ PC peripheral equipment (keyboards, etc.)
{ Household electrical appliances
• Air conditioners
• Microwave ovens, electric rice cookers
{ Industrial equipment
• Pumps
• Vending machines
• FA (Factory Automation)
CHAPTER 1 OUTLINE
Preliminary User’s Manual U1260EJ3V1UD 19
1.3 Ordering Information
• Flash memory version (1/4)
Part Number Package
µ
PD78F0531GB(T)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0531GB(T2)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0531GB(S)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0531GB(R)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0531GC(T)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0531GC(T2)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0531GC(S)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0531GC(R)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0531GK(T)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0531GK(T2)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0531GK(S)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0531GK(R)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0531GA(T)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0531GA(T2)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0531GA(S)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0531GA(R)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0531FC(T)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0531FC(S)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0531FC(R)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0532GB(T)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0532GB(T2)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0532GB(S)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0532GB(R)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0532GC(T)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0532GC(T2)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0532GC(S)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0532GC(R)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0532GK(T)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0532GK(T2)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0532GK(S)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0532GK(R)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0532GA(T)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0532GA(T2)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0532GA(S)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0532GA(R)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0532FC(T)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0532FC(S)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0532FC(R)-AA1-A 64-pin plastic FLGA (5x5)
CHAPTER 1 OUTLINE
Preliminary User’s Manual U17260EJ3V1UD
20
• Flash memory version (2/4)
Part Number Package
µ
PD78F0533GB(T)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0533GB(T2)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0533GB(S)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0533GB(R)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0533GC(T)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0533GC(T2)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0533GC(S)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0533GC(R)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0533GK(T)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0533GK(T2)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0533GK(S)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0533GK(R)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0533GA(T)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0533GA(T2)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0533GA(S)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0533GA(R)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0533FC(T)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0533FC(S)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0533FC(R)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0534GB(T)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0534GB(T2)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0534GB(S)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0534GB(R)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0534GC(T)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0534GC(T2)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0534GC(S)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0534GC(R)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0534GK(T)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0534GK(T2)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0534GK(S)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0534GK(R)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0534GA(T)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0534GA(T2)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0534GA(S)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0534GA(R)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0534FC(T)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0534FC(S)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0534FC(R)-AA1-A 64-pin plastic FLGA (5x5)
CHAPTER 1 OUTLINE
Preliminary User’s Manual U1260EJ3V1UD 21
• Flash memory version (3/4)
Part Number Package
µ
PD78F0535GB(T)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0535GB(T2)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0535GB(S)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0535GB(R)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0535GC(T)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0535GC(T2)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0535GC(S)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0535GC(R)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0535GK(T)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0535GK(T2)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0535GK(S)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0535GK(R)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0535GA(T)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0535GA(T2)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0535GA(S)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0535GA(R)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0535FC(T)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0535FC(S)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0535FC(R)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0536GB(T)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0536GB(T2)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0536GB(S)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0536GB(R)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0536GC(T)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0536GC(T2)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0536GC(S)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0536GC(R)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0536GK(T)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0536GK(T2)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0536GK(S)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0536GK(R)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0536GA(T)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0536GA(T2)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0536GA(S)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0536GA(R)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0536FC(T)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0536FC(S)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0536FC(R)-AA1-A 64-pin plastic FLGA (5x5)
CHAPTER 1 OUTLINE
Preliminary User’s Manual U17260EJ3V1UD
22
• Flash memory version (4/4)
Part Number Package
µ
PD78F0537GB(T)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0537GB(T2)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0537GB(S)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0537GB(R)-UEU-A 64-pin plastic LQFP (10x10)
µ
PD78F0537GC(T)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0537GC(T2)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0537GC(S)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0537GC(R)-UBS-A 64-pin plastic LQFP (14x14)
µ
PD78F0537GK(T)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0537GK(T2)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0537GK(S)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0537GK(R)-UET-A 64-pin plastic LQFP (12x12)
µ
PD78F0537GA(T)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0537GA(T2)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0537GA(S)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0537GA(R)-9EV-A 64-pin plastic TQFP (7x7)
µ
PD78F0537FC(T)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0537FC(S)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0537FC(R)-AA1-A 64-pin plastic FLGA (5x5)
µ
PD78F0537DGB(T)-UEU-ANote 64-pin plastic LQFP (10x10)
µ
PD78F0537DGC(T)-UBS-ANote 64-pin plastic LQFP (14x14)
µ
PD78F0537DGK(T)-UET-ANote 64-pin plastic LQFP (12x12)
µ
PD78F0537DGA(T)-9EV-ANote 64-pin plastic TQFP (7x7)
µ
PD78F0537DFC(T)-AA1-ANote 64-pin plastic FLGA (5x5)
Note The
µ
PD78F0537D has an on-chip debug function. Do not use this product for mass production, because
its reliability cannot be guaranteed after the on-chip debug function has been used, with respect to the
number of times the flash memory can be rewritten. NEC Electronics does not accept complaints about this
product.
Remark Products with -A at the end of the part number are lead-free products.
The standard quality versions of this product are classified by production process as follows.
(T), (T2): General
(S): Individual contract
(R): For automobile accessories
CHAPTER 1 OUTLINE
Preliminary User’s Manual U1260EJ3V1UD 23
1.4 Pin Configuration (Top View)
• 64-pin plastic LQFP (10 × 10)
• 64-pin plastic LQFP (14 × 14)
• 64-pin plastic LQFP (12 × 12)
• 64-pin plastic TQFP (7 × 7)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P140/PCL/INTP6
P141/BUZ/INTP7
P00/TI000
P01/TI010/TO00
P02/SO11
Note2
P03/SI11
Note2
P04/SCK11
Note2
P130
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P60/SCL0
P61/SDA0
P62/EXSCL0
P63
P33/TI51/TO51/INTP4
P77/KR7
P76/KR6
P75/KR5
P74/KR4
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P06/TO01
Note2
/TI011
Note2
P05/SSI11
Note2
/TI001
Note2
P32/INTP3/OCD1B
Note1
AV
SS
AV
REF
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P30/INTP1
P53
P52
P51
P50
P31/INTP2/OCD1A
Note1
P120/INTP0/EXLVI
P43
P42
P41
P40
RESET
P124/XT2/EXCLKS
P123/XT1
FLMD0
P122/X2/EXCLK/OCD0B
Note1
P121/X1/OCD0A
Note1
REGC
V
SS
EV
SS
V
DD
EV
DD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Notes 1.
µ
PD78F0537D (product with on-chip debug function) only
2.
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only
Cautions 1. Make AVSS the same potential as VSS.
2. Connect the REGC pin to VSS via a capacitor (0.47
µ
F: target).
3. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset.
CHAPTER 1 OUTLINE
Preliminary User’s Manual U17260EJ3V1UD
24
• 64-pin plastic FLGA (5 × 5)
Top View Bottom View
Index mark
1
2
HG F E DC BA
3
4
5
6
7
8
HGFEDCBA
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
A1 AVSS C1 P24/ANI4 E1 P130 G1 P141/BUZ/INTP7
A2 AVREF C2 P23/ANI3 E2 P20/ANI0 G2 P140/PCL/INTP6
A3 P11/SI10/RxD0 C3 P27/ANI7 E3 P03/SI11 Note2 G3 P43
A4 P13/TxD6 C4 P10/SCK10/TxD0 E4 P42 G4 RESET
A5 P16/TOH1/INTP5 C5 P17/TI50/TO50 E5 P77/KR7 G5 REGC
A6 P53 C6 P30/INTP1 E6 P33/TI51/TO51/INTP4 G6 VSS
A7 P51 C7 P31/INTP2/
OCD1A Note1
E7 P74/KR4 G7 VDD
A8 P32/INTP3/
OCD1B Note1
C8 P06 /TO01 Note2/
TI011 Note2
E8 P76/KR6 G8 P61/SDA0
B1 P25/ANI5 D1 P21/ANI1 F1 P01/TI010/TO00 H1 P120/INTP0/EXLVI
B2 P26/ANI6 D2 P22/ANI2 F2 P00/TI000 H2 P124/XT2/EXCLKS
B3 P12/SO10 D3 P04/SCK11 Note2 F3 P02/SO11 Note2 H3 P123/XT1
B4 P15/TOH0 D4 P72/KR2 F4 P41 H4 FLMD0
B5 P14/RxD6 D5 P70/KR0 F5 P40 H5 P122/X2/EXCLK
/OCD0B Note1
B6 P52 D6 P71/KR1 F6 P60/SCL0 H6 P121/X1/OCD0A Note1
B7 P50 D7 P75/KR5 F7 P62/EXSCL0 H7 EVSS
B8 P05/SSI11 Note2/
TI001 Note2
D8 P73/KR3 F8 P63 H8 EVDD
Notes 1.
µ
PD78F0537D (product with on-chip debug function) only
2.
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only
Cautions 1. Make AVSS the same potential as VSS.
2. Connect the REGC pin to VSS via a capacitor (0.47
µ
F: target).
3. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset.
CHAPTER 1 OUTLINE
Preliminary User’s Manual U1260EJ3V1UD 25
Pin Identification
ANI0 to ANI7: Analog input
AVREF: Analog reference voltage
AVSS: Analog ground
BUZ: Buzzer output
EVDD: Power supply for port
EVSS: Ground for port
EXCLK: External clock input
(main system clock)
EXCLKS: External clock input
(subsystem clock)
EXLVI: External potential input
for low-voltage detector
EXSCL0: External serial clock input
FLMD0: Flash programming mode
INTP0 to INTP7: External interrupt input
KR0 to KR7: Key return
OCD0A Note1,
OCD0B Note1,
OCD1A Note1,
OCD1B Note1: On chip debug input/output
P00 to P06: Port 0
P10 to P17: Port 1
P20 to P27: Port 2
P30 to P33: Port 3
P40 to P43: Port 4
P50 to P53: Port 5
P60 to P63: Port 6
P70 to P77: Port 7
P120 to P124: Port 12
P130: Port 13
P140, P141: Port 14
PCL: Programmable clock output
REGC Regulator capacitance
RESET: Reset
RxD0, RxD6: Receive data
SCK10, SCK11 Note2,
SCL0: Serial clock input/output
SDA0: Serial data input/output
SI10, SI11 Note2: Serial data input
SO10, SO11 Note2: Serial data output
SSI11 Note2: Serial interface chip select input
TI000, TI010,
TI001 Note2, TI011 Note2,
TI50, TI51: Timer input
TO00, TO01 Note2,
TO50, TO51,
TOH0, TOH1: Timer output
TxD0, TxD6: Transmit data
VDD: Power supply
VSS: Ground
X1, X2: Crystal oscillator (main system clock)
XT1, XT2: Crystal oscillator (subsystem clock)
Notes 1.
µ
PD78F0537D (product with on-chip debug function) only
2.
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only
