BU-61590D5-110 - Data Device Corporation (DDC)

DESCRIPTION

DDC's BU-61590 BC/RT/MT

Universal Advanced Communication

Engine (ACE) terminal comprises a

complete integrated interface between

a host processor and a MIL-STD-

1553, STANAG 3838, or McAir bus.

The BU-61590 integrates a dual uni-

versal McAir transceiver, protocol,

memory management and processor

interface logic, and 4K words of inter-

nal buffered RAM in either a 78-pin

DIP or flat pack package.

This dual universal tr ansceiv er pro vides

a sinusoidal waveform for full compli-

ance with 1553A, 1553B, and McAir

A3818, A5232, and A5690 standards.

To minimize board space and "glue"

logic, the Universal ACE terminals

provide the ultimate flexibility in inter-

facing to a host processor and inter-

nal/exter nal RAM.

The BU-61590 provides complete

multiprotocol support of MIL-STD-

1553A, 1553B Notice 2, McAir A3818,

A5232, and A5690, General

Dynamics 16PP303, Grumman

SPG151A, and STANA G 3838 (includ-

ing EFAbus).The advanced functional

architecture of the ACE ter minals pro-

vides software compatibility to DDC's

previous AIM series hybrids. In addi-

tion, the ACE Terminals incor porate a

multiplicity of architectural enhance-

ments allowing fle xib le operation while

off-loading the host processor, ensur-

ing data consistency, and supporting

bulk data transfers.

The BU-61590 may be operated at

either 12 or 16 MHz.Options allow f or

a hardwired or programmable RT

address.

The BU-61590 operates over the full

military temperature range of -55 to

+125°C. Available screened to MIL-

PRF-38534, the terminals are ideal

for demanding military and industrial

processor-to-1553 applications.

FEATURES

•

Fully Integrated Terminal

•

Dual Universal Transceiver

Satisfies McAir and 1553A/B

•

Multiprotocol Supports:

MIL-STD-1553A and B Notice 2

McAir A3818, A5232, & A5690

General Dynamics 16PP303

(F16) Grumman SPG151A

•

4K x 16 Internal RAM

•

Flexible Processor/Memory

Interface

•

Automatic BC Retries

•

Programmable BC Gap Times

•

BC Frame Auto-Repeat

•

Flexible RT Data Buffering

•

Programmable Illegalization

•

Selective Message Monitor

•

Simultaneous RT/Monitor Mode

TRANSCEIVER

CH. A

TRANSCEIVER

CH. B

DUAL

ENCODER/DECODER,

MULTIPROTOCOL

AND

MEMORY

MANAGEMENT

RT ADDRESS

4K X 16

SHARED

RAM

ADDRESS BUS

PROCESSOR

AND

MEMORY

INTERFACE

LOGIC

DATA BUS D15-D0

A15-A0

DATA

BUFFERS

ADDRESS

BUFFERS

PROCESSOR

DATA BUS

PROCESSOR

ADDRESS BUS

MISCELLANEOUS

INCMD

CLK_IN, TAG_CLK, BC/MT_ENA, TX_INH_A, TX_INH_B,

MSTCLR, SSFLAG/EXT_TRG, ILLEGAL, RT_AD_LAT

RTAD4-RTAD0, RTADP

TRANSPARENT/BUFFERED, STRBD, SELECT,

RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,

MSB/LSB/DTGRT, INT_ACK

IOEN, MEMENA-OUT, READYD

ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,

8/16-BIT/DTREQ, POLARITY_SEL/DTACK

INT

PROCESSOR

AND

MEMORY

CONTROL

INTERRUPT

REQUEST

TX/RX_A

TX/RX_B

BU-61590 BLOCK DIAGRAM

BU-61590

MIL-STD-1553A/B AND McAIR BC/RT/MT,

ADVANCED COMMUNICATION ENGINE (ACE)

PARAMETER MIN TYP MAX

BU-61590 SERIES SPECIFICATIONS UNITS

ABSOLUTE MAXIMUM RATINGS

Supply Voltage

nLogic +5 V

nTransceiver +5 V

nTransceiver +V

nTransceiver -V

Logic

nVoltage Input Range

-0.3

-0.5

-0.3

+0.3

-0.3

7.0

+18.0

-18.0

VCC+0.3

RECEIVER

Differential Input Resistance (Note 1)

Differential Input Capacitance (Note1)

Threshold Voltage, Transformer

Coupled, Measured on Stub

Common Mode Voltage (Note 2)

610

0.860

kOhm

Vp-p

Vpeak

TRANSMlTTER

Differential Output Voltage

nDirect Coupled Across 35 Ohms,

Measured on Bus

nTransformer Coupled, Measured

on Stub

Output Noise, Differential (Direct

Coupled)

Output Offset Voltage, Direct

Coupled Across 35 Ohms

Rise/F all Time

-90

280

300

Vp-p

mVp-p, diff

nsec

LOGIC

VIH

VlL

IIH (VCC=5.5 V, VIN=5.0 V)

IIH (VCC=5.5 V, VIN=2.4 V)

nSSFLAG/EXT_TRIG

nAll Other Inputs

IIL (VCC=5.5 V, VIN=0 V)

nSSFLAG/EXT_TRIG

nAll Other Inputs

VOH (VCC=4.5 V, VIH=2.4 V, VIL=0.7

V, lOH=max)

VOL (VCC=4.5 V, VIH=2.4 V, VlL=0.7

V, IOL=max)

IOL

n(DB0-DB15, A0-A15,

MEMOE/ADDR_LAT,

MEMWR/ZEROWAIT,

DTREQ 16/8, DTACK/POLARI

TY_SEL

nINCMD, INT, MEMENA_OUT,

READYD, IOEN

IOH

n(DB0-DB15, A0-A15,

MEMOE/ADDR_LAT,

MEMWR/ZEROWAIT,

DTREQ/16/8, DTACK/POLARI-

TY_SEL)

nINCMD, INT, MEMENA_OUT,

READYD, IOEN

2.0

-10

-692

-346

-794

-397

2.4

6.4

3.2

0.8

-84

-42

-100

-50

0.4

-6.4

-3.2

µA

BU-61590 SERIES SPECIFICATIONS (contd)

PARAMETER MIN TYP MAX UNITS

n-V (-12V to -15V)

• Idle

• 25% Duty Cycle

• 50% Duty Cycle

• 100% Dutv Cycle

134

112

165

POWER DISSIPATION

Total Hybrid

nIdle

n25% Duty Cycle

n50% Duty Cycle

n100% Duty Cycle

Hottest Die

nIdle

n25% Duty Cycle

n50% Duty Cycle

n100% Dutv Cycle

1.31

1.81

2.28

3.24

0.045

0.095

0.205

2.50

2.97

3.45

4.40

0.072

0.143

0.287

CLOCK INPUT

Frequency

nNominal Value (programmable)

• default

• option

nLong Term Tolerance

• 1553A Compliance

• 1553B Compliance

nShort Term Tolerance 1 second

• 1553A Compliance

• 1553B Compliance

nDuty Cycle

• 16MHz

• 12MHz 33

16.0

12.0

0.01

0.1

0.001

0.01

MHz

17.5

21.5

49.5

127

2.5

9.5

18.5

22.5

50.5

128

668

19.5

23.5

51.5

129

µs

THERMAL

Thermal Resistance Junction-to-

Case Hottest Die (θJC)

Operating Junction Temperature

Storage Temperature

Lead Temperature (soldering 10 sec-

onds)

-55

-65

67.23

160

150

+300

°C/W

°C

PHYSICAL CHARACTERISTICS

Size

n78-pin DIP, Flat Pack

Weight

n78-pin DIP. Flat Pack 1.0

(29)

(mm)

(g)

2.1 x 1.8 x 0.210

(53.34 x 45.72 x 5.33)

1553 MESSAGE TIMING

RT Response Time

(mid-parity to mid-sync)

Completion of CPU Write (BC Start-

to-Star t of First BC Message)

BC Intermessage Gap (Note 2)

BC/RT/MT Response Timeout(Note 3)

n18.5 nominal

n22.5 nominal

n50.5 nominal

n128.0 nominal

Trasnmitter W atchdog Timeout

Notes:

1. Specifications include both transmitter and receiver (tied together internally).

Measurement of impedance is directly between pins TX/RX A(B) and TX/RX

A(B) of the BU-61590X5 hybrid. Assuming the connection of all power and

ground inputs to the hybrid. The specifications are applicable for both unpow-

ered and powered conditions.The specifications assume a 2 volt rms balanced

differential, sinusoidal input.The applicable frequency range is 75 kHz to 1

MHz. Minimum resistance and maximum capacitance parameters are guaran-

teed, but not tested, over the operating range.

2.Typical value for minimum intermessage gap time. Under software conlrol, may

be lengthened to (65,535 µs minus message time), in increments of 1 µs.

3. Software programmable (4 options). Includes RT-to-RT Timeout (Mid-Parity of

Transmit Command to Mid-Sync of Transmitting RT Status).

POWER SUPPLY REQUIREMENTS

Voltages/Tolerances

n+5 V (Logic)

n+5 V (CH. A CH. B)

n+V (CH. A CH. B)

n-V (CH. A CH. B)

Current Drain (Total Hybrid)

n+5 V

n+V (+12 V to +15 V)

• Idle

• 25% Duty Cycle

• 50% Duty Cycle

• 100% Dutv Cycle

4.5

11.4

15.75 95

134

5.5

15.75

-11.4

190

112

165

1.800 MAX

(45.72)

1.500

(38.1)

1.800 (45.72) INDEX

DENOTES

PIN 1

NOTES:

LEAD CLUSTER TO BE LOCATED WITH

±0.005 (±0.127) OF CASE CENTER LINE.

CERAMIC PACKAGE KOVAR COVER.

3. DIMENSIONS ARE IN INCHES (mm).

2.100 MAX

(53.34)

1.900 (48.26)

0.210

MAX

(5.33)

0.100 TYP (2.54)

0.250 ±0.010

(6.35 ±0.25)

PIN NUMBERS FOR

REFERENCE ONLY

1.650

(41.91)

0.018 ±0.002 DIA TYP

(0.46 ±0.05)

41 77

SEE DETAIL "A" 0.050 TYP (1.27)

DETAIL "A"

BU-61590DX, 78-PIN DIP PACKAGE, MECHANICAL OUTLINE

BU-61590 PIN LISTING (78-PIN DIP OR FLAT PACK)

PIN NAME PIN NAME PIN NAME

1TX/RX-A 27 A00 53 D01

2TX/RX-A 28 DTGRT/MSB/LSB 54 D02

3GNDA 29 SSFLAG/EXT_TRIG 55 D03

4TX_INH_A 30 MEMENA_OUT 56 D04

5SELECT 31 MEMOE/ADDR_LAT 57 D05

6STRBD 32 MEMWR/ZERO_WAIT 58 D06

7MEM_REG 33 DTREQ/16/8 59 D07

8RD/WR 34 DTACK/POLARITY_SEL 60 D08

9MSTCLR 35 MEMENA_IN/TRIGGER_SEL 61 D09

10 A15 36 ILLEGAL 62 D10

11 A14 37 TX/RX-B 63 D11

12 A13 38 TX/RX-B 64 D12

13 A12 39 GNDB 65 D13

14 A11 40 +5 VB 66 D14

15 A10 41 -15 VB 67 D15

16 A09 42 +15 VB 68 TAG_CLK

17 A08 43 CLOCK_IN 69 TRANSPARENT/BUFFERED

18 LOGIC GND 44 RT_AD_LAT 70 INT

19 +5 V LOGIC 45 RTAD0 71 READYD

20 A07 46 RTAD1 72 IOEN

21 A06 47 RTAD2 73 INT_ACK

22 A05 48 RTAD3 74 BC/MT_ENA

23 A04 49 RTAD4 75 TX_INH_B

24 A03 50 RTADP 76 +5 VA

25 A02 51 INCMD 77 -15 A

26 A01 52 D00 78 +15 A

38 EQ. SP. @

0.050 = 1.90

TOL NONCUM

(1.27 = 48.26)

0.400 MIN TYP

(10.16)

0.050 TYP

(1.27)

0.100 ±0.010 TYP

(2.54 ±0.25)

0.210 MAX (5.33)

39 40

178

1.800 MAX

(45.72)

NOTES:

LEAD CLUSTER TO BE LOCATED WITH

±0.005 (±0.13) OF CASE CENTER LINE.

CERAMIC PACKAGE KOVAR COVER.

3.DIMENSIONS ARE IN INCHES (mm).

0.018 ±0.002 TYP

(0.46 ±0.05)

SEE DETAIL "A"

DETAIL "A"

PN 1 DENOTED

BY INDEX TAB

ON LEAD BRAZE

2.100 MAX

(53.34)

0.010 ±0.002 TYP

(0.25 ±0.05)

PIN NUMBERS FOR

REFERENCE ONLY

FIGURE 3. BU-61590FX, 78-PIN FLAT PACK PACKAGE, MECHANICAL OUTLINE

ORDERING INFORMATION

BU-61590XX-XX0X

Supplemental Process Requirements:

S = Pre-Cap Source Inspection

L = Pull Test

Q = Pull Test and Pre-Cap Inspection

K = One Lot Date Code

W = One Lot Date Code and PreCap Source

Y = One Lot Date Code and 100% Pull Test

Z = One Lot Date Code, PreCap Source and 100% Pull Test

Blank = None of the Above

Process Requirements:

0 = Standard DDC Processing, no Burn-In

1 = MIL-PRF-38534 Compliant

2 = B*

3 = MIL-PRF-38534 Compliant with PIND Testing

4 = MIL-PRF-38534 Compliant with Solder Dip

5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip

6 = B* with PIND Testing

7 = B* with Solder Dip

8 = B* with PIND Testing and Solder Dip

9 = Standard DDC Processing with Solder Dip, no Bur n-In

Temperature Grade/Data Requirements:

1 = -55°C to +125°C

2 = -40°C to +85°C

3 = 0°C to +70°C

4 = -55°C to +125°C with Var iables Test Data

5 = -40°C to +85°C with Var iables Test Data

8 = 0°C to +70°C with Var iables Test Data

V oltage T ransceiver Option:

5 = +5/+15/-15 V Sinusoidal (McAir)

Package:

D = DIP

F = Flat Pack

Product T ype:

61590 = 78-Pin BC/RT/MT with 4K RAM

*Standard DDC Processing with burn-in and full temperature test.

NOTES

PRINTED IN THE U.S.A.

C-(ABR)-02/99-500

ILC DATA DEVICE CORPORATION

REGISTERED TO ISO 9001

FILE NO. A5976

The information in this data sheet is believed to be accurate; however, no responsibility is

assumed by Data Device Cor poration for its use, and no license or rights are

granted by implication or otherwise in connection therewith.

Specifications are subject to change without notice.

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