1
DESCRIPTION
The CAT5269 is two digitally programmable
potentiometers (DPPs™) integrated with control logic
and 18 bytes of NVRAM memory. Each DPP consists of
a series of resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper
outputs with CMOS switches. A separate 8-bit control
register (WCR) independently controls the wiper tap
switches for each DPP. Associated with each wiper
control register are four 8-bit non-volatile memory data
registers (DR) used for storing up to four wiper settings.
Writing to the wiper control register or any of the
CAT5269
Dual Digitally Programmable Potentiometers (DPP™)
with 256 Taps and 2-wire Interface
FEATURES
■ Two linear taper digitally programmable poten-
tiometers
■256 resistor taps per potentiometer
■End to end resistance 50kΩΩ
ΩΩ
Ω or 100kΩΩ
ΩΩ
Ω
■Potentiometer control and memory access via
2-wire interface (I2C like)
■Low wiper resistance, typically 100ΩΩ
ΩΩ
Ω
■Nonvolatile memory storage for up to four
wiper settings for each potentiometer
■Automatic recall of saved wiper settings at
power up
■2.5 to 6.0 volt operation
■Standby current less than 1 µA
■1,000,000 nonvolatile WRITE cycles
■100 year nonvolatile memory data retention
■24-lead SOIC and TSSOP packages
■Industrial temperature range
PIN CONFIGURATION FUNCTIONAL DIAGRAM
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice Document No. 2123, Rev. B
non-volatile data registers is via a 2-wire serial bus. On
power-up, the contents of the first data register (DR0)
for each of the four potentiometers is automatically
loaded into its respective wiper control registers.
The CAT5269 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40˚C to 85˚C industrial
operating temperature range and offered in a 24-lead
SOIC and TSSOP packages.
SOIC Package (J, W)
TSSOP Package (U, Y)
H
A
L
O
G
E
N
F
R
E
E
TM
L
E
A
D
F
R
E
E
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
NC
A0
NC
NC
NC
NC
V
R
R
R
A2
WP
A3
SCL
NC
NC
NC
NC
GND
R
R
R
A1
SDA
CAT
5269
CC
W0
H0
W1
H1
L1
L0
R
H0
W0
W1
H1
R
R
L0 L1
R
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
2-WIRE BUS
INTERFACE
CONTROL
LOGIC
SCL
SDA
WP
A0
A1
A2
A3
R
R
2
CAT5269
Document No. 2123, Rev. B
PIN DESCRIPTION
Pin
(SOIC) Name Function
1 NC No Connect
2 A0 Device Address, LSB
3 NC No Connect
4 NC No Connect
5 NC No Connect
6 NC No Connect
7 VCC Supply Voltage
8R
L0 Low Reference Terminal for Potentiometer 0
9R
H0 High Reference Terminal for Potentiometer 0
10 RW0 Wiper Terminal for Potentiometer 0
11 A2 Device Address
12 WP Write Protection
13 SDA Serial Data Input/Output
14 A1 Device Address
15 RL1 Low Reference Terminal for Potentiometer 1
16 RH1 High Reference Terminal for Potentiometer 1
17 RW1 Wiper Terminal for Potentiometer 1
18 GND Ground
19 NC No Connect
20 NC No Connect
21 NC No Connect
22 NC No Connect
23 SCL Bus Serial Clock
24 A3 Device Address
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT5269 serial clock input pin is used to
clock all data transfers into or out of the device.
SDA: Serial Data
The CAT5269 bidirectional serial data pin is
used to transfer data into and out of the device.
The SDA pin is an open drain output and can be
wire-Ored with the other open drain or open
collector I/Os.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with
the address input in order to initiate communica-
tion with the CAT5269.
RH, RL: Resistor End Points
The two sets of RH and RL pins are equivalent
to the terminal connections on a mechanical
potentiometer.
RW: Wiper
The RW pins are equivalent to the wiper terminal
of a mechanical potentiometer.
WPWP
WPWP
WP: Write Protect Input
The WP pin when tied low prevents non-volatile
writes to the data registers (change of wiper
control register is allowed) and when tied high or
left floating normal read/write operations are
allowed. See Write Protection on page 7 for
more details.
DEVICE OPERATION
The CAT5269 is two resistor arrays integrated with a 2-wire serial interface, two 8-bit wiper control registers and eight
8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements connected in
series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and
RL). The tap positions between and at the ends of the series resistors are connected to the output wiper terminals
(RW)by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper control register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also,
the device can be instructed to operate in an "increment/decrement" mode.
3
CAT5269
Document No. 2123, Rev. B
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on any Pin with
Respect toVSS(1)(2) ................ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs)............ 300°C
Wiper Current.................................................... +6mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = RTOT / 255 or (RH - RL) / 255, single pot
(5) n = 0, 1, 2, ..., 255
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Recommended Operating Conditions:
VCC = +2.5V to +6.0V
Temperature Min Max
Industrial -40°C85°C
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
RPOT Potentiometer Resistance (100KΩ) 100 kΩ
RPOT Potentiometer Resistance (50KΩ) 50 kΩ
Potentiometer Resistance +20 %
Tolerance
RPOT Matching 1 %
Power Rating 50 mW 25°C, each pot
IWWiper Current +3 mA
RWWiper Resistance 200 300 ΩIW = +3mA @ VCC = 3V
RWWiper Resistance 100 150 ΩIW = +3mA @ VCC = 5V
VTERM Voltage on any RH or RL Pin VSS VCC VV
SS = 0V
VNNoise nV/√Hz (1)
Resolution 0.4 %
Absolute Linearity (2) +1 LSB (4) Rw(n)(actual)-R(n)(expected)(5)
Relative Linearity (3) +0.2 LSB (4) Rw(n+1)-[Rw(n)+LSB](5)
Temperature Coefficient of +300 ppm/˚C (1)
TCRPOT RPOT
TCRATIO Ratiometric Temp. Coefficient 20 ppm/˚C (1)
CH/CL/CWPotentiometer Capacitances 10/10/25 pF (1)
fc Frequency Response 0.4 MHz RPOT = 50KΩ(1)
4
CAT5269
Document No. 2123, Rev. B
CAPACITANCE
TA = 25˚C, f = 1.0 MHz, VCC = 5V
Symbol Test Max. Units Conditions
CI/O(1) Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN(1) Input Capacitance (A0, A1, A2, A3, SCL, WP)6 pF V
IN = 0V
2.5V-6.0V
Symbol Parameter Min. Max. Units
fSCL Clock Frequency 400 kHz
TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 200 ns
tAA SLC Low to SDA Data Out and ACK Out 1 µs
tBUF(1) Time the bus must be free before a new transmission can start 1.2 µs
tHD:STA Start Condition Hold Time 0.6 µs
tLOW Clock Low Period 1.2 µs
tHIGH Clock High Period 0.6 µs
tSU:STA Start Condition SetupTime (for a Repeated Start Condition) 0.6 µs
tHD:DAT Data in Hold Time 0 ns
tSU:DAT Data in Setup Time 50 ns
tR(1) SDA and SCL Rise Time 0.3 µs
tF(1) SDA and SCL Fall Time 300 ns
tSU:STO Stop Condition Setup Time 0.6 µs
tDH Data Out Hold Time 100 ns
A.C. CHARACTERISTICS
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +6.0V, unless otherwise specified.
Symbol Parameter Min Max Units Test Conditions
ICC1 Power Supply Current 1 mA fSCL = 400 KHz, SDA Open
VCC = 6 V, Input = GND
ICC2 Power Supply Current 5 mA fSCK = 400 KHz, SDA Open
Non-volatile WRITE VCC = 6 V, Input = GND
ISB Standby Current (VCC = 5.0V) 5 µAV
IN = GND or VCC, SDA Open
ILI Input Leakage Current 10 µAV
IN = GND to VCC
ILO Output Leakage Current 10 µAV
OUT = GND to VCC
VIL Input Low Voltage -1 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 1.0 V
VOL1 Output Low Voltage (VCC = 3.0V) 0.4 V IOL = 3 mA
VOL2 Output Low Voltage (VCC = 1.8V) 0.5 V IOL = 1.5 mA
5
CAT5269
Document No. 2123, Rev. B
POWER UP TIMING (1)(2)
Symbol Parameter Max. Units
tPUR Power-up to Read Operation 1 ms
tPUW Power-up to Write Operation 1 ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tFtLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA tDH
Figure 1. Bus Timing
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
NEND(1) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
TDR(1) Data Retention 100 Years MIL-STD-883, Test Method 1008
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1) Latch-Up 100 mA JEDEC Standard 17
XDCP TIMING
Symbol Parameter Min Max Units
tWRPO Wiper Response Time After Power Supply Stable 5 10 µs
tWRL Wiper Response Time After Instruction Issued 5 10 µs
WRITE CYCLE LIMITS
Symbol Parameter Max. Units
tWR Write Cycle Time 5 ms
6
CAT5269
Document No. 2123, Rev. B
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
CAT5269 will be considered a slave device in all
applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5269 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address of
the particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
0101 for the CAT5269 (see Figure 5). The next four
significant bits (A3, A2, A1, A0) are the device address
bits and define which device the Master is accessing. Up
to sixteen devices may be individually addressed by the
system. Typically, +5V and ground are hard-wired to
these pins to establish the device's address.
After the Master sends a START condition and the slave
address byte, the CAT5269 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT5269 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
8-bit byte.
When the CAT5269 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT5269 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
WRITE OPERATIONS
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the
requested operation of CAT5269. The instruction byte
consist of a four-bit opcode followed by two register
selection bits and two pot selection bits. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the selected register.
The CAT5269 acknowledges once more and the Master
generates the STOP condition, at which time if a non-
volatile data register is being selected, the device begins
an internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will not
respond to any request from the Master device.
tWR
STOP
CONDITION START
CONDITION ADDRESS
ACK8TH BIT
BYTE n
SCL
SDA
Figure 2. Write Cycle Timing
7
CAT5269
Document No. 2123, Rev. B
ACKNOWLEDGE
1
START
SCL FROM
MASTER 89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 4. Acknowledge Condition
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
the CAT5269 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address. If the
CAT5269 is still busy with the write operation, no ACK
will be returned. If the CAT5269 has completed the write
operation, an ACK will be returned and the host can then
proceed with the next instruction operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile
data registers. If the WP pin is tied to LOW, the data
registers are protected and become read only. Similarly,
the WP pin going low after start will interrupt a non-
volatile write to data registers, while the WP pin going
low after an internal write cycle has stated will have no
effect on any write operation (see also CAT5409 or
CAT5259). The CAT5269 will accept both slave
addresses and instructions, but the data registers are
protected from programming by the device’s failure to
send an acknowledge after data is received.
Figure 5. Slave Address Bits
01 0 1 A3A2A1A0
CAT5269
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 3. Start/Stop Condition
START CONDITION
SDA
STOP CONDITION
SCL
8
CAT5269
Document No. 2123, Rev. B
INSTRUCTION AND REGISTER
DESCRIPTION
SLAVE ADDRESS BYTE
The first byte sent to the CAT5269 from the master/
processor is called the Slave/DPP Address Byte. The
most significant four bits of the slave address are a
device type identifier. These bits for the CAT5269 are
fixed at 0101[B] (refer to Table 1).
The next four bits, A3 - A0, are the internal slave address
and must match the physical device address which is
defined by the state of the A3 - A0 input pins for the
CAT5269 to successfully continue the command
sequence. Only the device which slave address matches
the incoming device address sent by the master executes
the instruction. The A3 - A0 inputs can be actively driven
by CMOS input signals or tied to VCC or VSS.
INSTRUCTION BYTE
The next byte sent to the CAT5269 contains the instruction
and register pointer information. The four most significant
bits used provide the instruction opcode I3 - I0. The R1
and R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits
point to one of two Wiper Control Registers. The format
is shown in Table 2.
Table 1. Identification Byte Format
ID3 ID2 ID1 ID0 A3 A2 A1 A0
0101
(MSB) (LSB)
Device Type
Identifier Slave Address
Table 2. Instruction Byte Format
I3 I2 I1 I0 R1 R0 P1 P0
(MSB) (LSB)
Instruction Data Register WCR/Pot Selection
Opcode Selection
Data Register Selected R1 R0
DR0 0 0
DR1 0 1
Data Register Selection
Figure 6. Write Timing
5020 FHD F08
S
A
C
K
A
C
K
DR1 WCRDATA
S
T
O
P
P
BUS A CTIVITY :
MASTER
SDA LINE
S
T
A
R
T
A
C
K
SLAVE/DPP
ADDRESS
INSTRUCTION
BYTE
Fixed Variable op code
Register
Address Pot1 WCR
Address
9
CAT5269
Document No. 2123, Rev. B
Table 3. Instruction Set
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The CAT5269 contains two 8-bit Wiper Control Registers,
one for each potentiometer. The Wiper Control Register
output is decoded to select one of 256 switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written by the host via Write Wiper
Control Register instruction; it may be written by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction, it can be
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register
zero (DR0) upon power-up.
The Wiper Control Register is a volatile register that
loses its contents when the CAT5269 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
Data Registers (DR)
Each potentiometer has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data Registers
is a non-volatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as standard memory locations for system
parameters or user preference data.
INSTRUCTIONS
Four of the nine instructions are three bytes in length.
These instructions are:
—Read Wiper Control Register - read the current
wiper position of the selected potentiometer in the WCR
—Write Wiper Control Register - change current
wiper position in the WCR of the selected potentiometer
—Read Data Register - read the contents of the
selected Data Register
—Write Data Register - write a new value to the
selected Data Register
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
Note: 1/0 = data is one or zero
Instruction
Instruction Set
OperationI3 I2 I1 I0 R1 R0 WCR1/
P1
Read Wiper Control
Register 100100 1/0 1/0Read the contents of the Wiper Control
Register pointed to by P1-P0
Write Wiper Control Register 101000 1/0 1/0Write new value to the Wiper Control
Register pointed to by P1-P0
Read Data Register 10111/01/01/0 1/0Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Write Data Register 11001/01/01/0 1/0Write new value to the Data Register
pointed to by P1-P0 and R1-R0
XFR Data Register to Wiper
Control Register 11011/01/01/0 1/0Transfer the contents of the Data Register
pointed to by P1-P0 and R1-R0 to its
associated Wiper Control Register
XFR Wiper Control Register
to Data Register 11101/01/01/0 1/0Transfer the contents of the Wiper Control
Register pointed to by P1-P0 to the Data
Register pointed to by R1-R0
Gang XFR Data Registers
to Wiper Control Registers 00011/01/0 0 0 Transfer the contents of the Data Registers
pointed to by R1-R0 of both pots to their
respective Wiper Control Registers
Gang XFR Wiper Control
Registers to Data Register 10001/01/0 0 0 Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of both pots
Increment/Decrement Wiper
Control Register 001000 1/0 1/0Enable Increment/decrement of the Control
Latch pointed to by P1-P0
WCR0/
P0
10
CAT5269
Document No. 2123, Rev. B
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be delayed
by tWR. A transfer from the WCR (current wiper position),
to a Data Register is a write to non-volatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the two potentiometers and one of
its associated registers; or the transfer can occur between
both potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5269; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
—XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
—XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated
Data Register.
—Gang XFR Data Register to Wiper
Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
—Gang XFR Wiper Counter Register to
Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 9
and 10). The Increment/Decrement command is differ-
ent from the other commands. Once the command is
issued and the CAT5269 has responded with an ac-
knowledge, the master can clock the selected wiper up
and/or down in one segment steps; thereby providing a
fine tuning capability to the host. For each SCL clock
pulse (tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the RH terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the RL terminal.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
Figure 8. Three-Byte Instruction Sequence
Figure 9. Increment/Decrement Instruction Sequence
I3 I2 I1 I0
ID3 ID2 ID1ID0
Device ID Internal Instruction
Opcode
Address Data
Register
Address
Pot/WCR
Address
S
T
A
R
T
0101
A2 A1 A0 A
C
K
R0 P1 P0 A
C
K
SDA
S
T
O
P
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
R1
A3
S
T
A
R
T
0101
A2 A0 A
C
K
I2 I1 I0 R1 R0 P1 A
C
K
SDA
S
T
O
P
ID3 ID2 ID1 ID0 P0
Device ID Internal Instruction
Opcode
Address Register
Address Pot/WCR
Address
A1
A3 I3
I3 I2 I1 I0 R1 R0
ID3 ID2
ID1
ID0
Device ID Internal Instruction
Opcode
Address Data
Register
Address
Pot/WCR
Address WCR[7:0]
or
Data Register D[7:0]
S
T
A
R
T
0101
A2 A1 A0 A
C
K
P1 P0 A
C
K
SDA
S
T
O
P
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A3
11
CAT5269
Document No. 2123, Rev. B
Figure 10. Increment/Decrement Timing Limits
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
Write Wiper Control Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
DEVICE ADDRESSES INSTRUCTION DATA
0 101AAAA 100100PP 76 5 4 3 210
3210 10
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
DEVICE ADDRESS INSTRUCTION DATA
0101AAAA 101000PP 76 5 43 210
3210 10
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
DEVICE ADDRESS INSTRUCTION DATA
0 101AAAA 1011RRPP 76 5 4 3 210
3210 1010
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
DEVICE ADDRESS INSTRUCTION DATA
0101AAAA 1100RRPP 76 5 43 210
3210 1010
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
SCL
SDA
RW
INC/DEC
Command
Issued
Voltage Out
tWRL
12
CAT5269
Document No. 2123, Rev. B
Gang Transfer Wiper Control Register (WCR) to Data Register (DR)
INSTRUCTION FORMAT (continued)
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESS INSTRUCTION
0101AAAA 1110RRPP
3210 1010
S
T
A
R
T
A
C
K
A
C
K
S
T
O
P
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESS INSTRUCTION
0101AAAA 1101RRPP
3210 1010
S
T
A
R
T
A
C
K
A
C
K
S
T
O
P
Increment (I)/Decrement (D) Wiper Control Register (WCR)
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
DEVICE ADDRESS INSTRUCTION
0101AAAA 0001RR00
3210 10
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
Gang Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESS INSTRUCTION
0 101AAAA 1000RR00
3210 10
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
DEVICE ADDRESS INSTRUCTION DATA
0101AAAA 001000PP II II
3210 10 // //
DD DD
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
• • •
13
CAT5269
Document No. 2123, Rev. B
Notes:
(1) The device used in the above example is a CAT5269JI00-TE13 (SOIC, Industrial Temperature, 100K Ohm, Tape & Reel)
ORDERING INFORMATION
24-LEAD 300 MIL WIDE SOIC (J, W)
0.2914 (7.40)
0.2992 (7.60) 0.394 (10.00)
0.419 (10.65)
0.0926 (2.35)
0.1043 (2.65)
0.0040 (0.10)
0.0118 (0.30)
0.050 (1.27) BSC 0.013 (0.33)
0.020 (0.51)
0—8
0.0091 (0.23)
0.0125 (0.32)
0.010 (0.25)
0.029 (0.75) X 45
0.016 (0.40)
0.050 (1.27)
0.5985 (15.20)
0.6141 (15.60)
PACKAGING INFORMATION
U: TSSOP
Y: TSSOP (Lead free, Halogen free)
Package Information shown in inches (mm).
14
CAT5269
Document No. 2123, Rev. B
6.4
(0.9)
7.8 + 0.1
4.4 + 0.1
PIN #1 INDENT.
-A-
-B-
0.2 C B A
3.2
ALL LEAD TIPS
7.72 TYP
4.16 TYP
(1.78 TYP)
0.42 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
0.10 + 0.05 TYP
0.19 - 0.30 TYP
1.1 MAX TYP 0.1 C
ALL LEAD TIPS
-C-
0.65 TYP
0.3 M A B S C S
SEE DETAIL A
0.09 - 0.20 TYP
0.6+0.1 SEATING PLANE
GAGE PLANE
0.25
0
o
- 8
o
DETAIL A
PACKAGING INFORMATION CON'T
24 Lead TSSOP (U)
Package Information shown in mm.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #: 2123
Revison: B
Issue date: 5/6/04
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Date Rev. Reason
11/18/2003 A Initial issue
5/6/2004 B Added TSSOP package in all areas
Updated Functional Diagram
Updated Pin Descriptions
Updated notes in Absolute Max Ratings
Updated Potentiometer Characteristics table
Updated DC Characteristics table
Added XDCP Timing table
Updated Write Cycle LImits table
Changed Figure 3 drawing to Start/Stop Condition from
Start/Stop Timing
Changed Figure 4 title to Acknowlege Condition (from Acknowlege Timing)
Updated Table 3 Gang XFR Operation information
Corrected Instruction Format for Gang Transfer Data Register (DR)
to Wiper Control Register (WCR)
REVISION HISTORY
