LTC2946 Wide Range I2C Power, Charge and Energy Monitor FEATURES n n n n n n n n n n n n n n n DESCRIPTION Rail-to-Rail Input Range: 0V to 100V Wide Input Supply Range: 2.7V to 100V Shunt Regulator for Supplies >100V ADC with Less Than 0.4% Total Unadjusted Error 12-Bit Resolution for Current and Voltages 1% Accurate Power and Energy Measurements 0.6% Accurate Current and Charge Measurements Additional ADC Input Monitors an External Voltage Internal 5% or External Time Bases Continuous Scan and Snapshot Modes Stores Minimum and Maximum Values Alerts When Limits Exceeded Split SDA Pin Eases Opto-Isolation Shutdown Mode with IQ < 40A Available in 4mm x 3mm DFN and 16-Lead MSOP Packages APPLICATIONS n n n Telecom Infrastructure Industrial Equipment General Purpose Energy Measurement The LTC(R)2946 is a rail-to-rail system monitor that measures current, voltage, power, charge and energy. It features an operating range of 2.7V to 100V and includes a shunt regulator for supplies above 100V. The current measurement common mode range of 0V to 100V is independent of the input supply. A 12-bit ADC measures load current, input voltage and an auxiliary external voltage. Load current and internally calculated power are integrated over an external clock or crystal or internal oscillator time base for charge and energy. An accurate time base allows the LTC2946 to provide measurement accuracy of better than 0.6% for charge and 1% for power and energy. Minimum and maximum values are stored and an overrange alert with programmable thresholds minimizes the need for software polling. Data is reported via a standard I2C interface. The LTC2946 I2C interface includes separate data input and output pins for use with standard or opto-isolated I2C connections. The LTC2946-1 has an inverted data output for use with inverting opto-isolator configurations. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Wide Range Power, Charge and Energy Monitor with Onboard ADC and I2C 0.02 SENSE+ VDD 0.1F NINE I2C ADDRESSES ACCUMULATION ENABLE OPTIONAL CRYSTAL TIMEBASE SENSE- GPIO3 INTVCC SCL ADR1 SDAI ADR0 GND 0.10 TO LOAD LTC2946 I2C INTERFACE SDAO MEASURED VOLTAGE ADIN GPIO2 GPIO1 CLKIN CLKOUT 0.05 ALERT GENERAL PURPOSE OUTPUT ADC TUE (%) VIN 4V TO 100V ADC Total Unadjusted Error (ADIN) 0 -0.05 -0.10 0 2946 TA01a 1024 2048 CODE 3072 4096 2946 TA01b 2946fa For more information www.linear.com/LTC2946 1 LTC2946 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) VDD Voltage............................................... -0.3V to 100V SENSE+ Voltage............................................-1V to 100V SENSE- Voltage......-1V or SENSE+ - 1V to SENSE+ + 1V INTVCC Voltage (Note 3)....................-0.3V to Lesser of 5.8V, VDD + 0.3V ADR1, ADR0, ADIN, SDAO, SDAO, GPIO1 TO GPIO3 Voltages........................................................ -0.3V to 7V CLKOUT Voltage.........................-0.3V to INTVCC + 0.3V CLKIN Voltage............................................ -0.3V to 5.5V INTVCC Clamp Current............................................35mA SCL, SDAI Voltages (Note 4)...................... -0.3V to 5.9V SCL, SDAI Clamp Current.........................................5mA Operating Temperature Range LTC2946C................................................. 0C to 70C LTC2946I..............................................-40C to 85C LTC2946H........................................... -40C to 125C LTC2946MP....................................... -55C TO 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) MS Package Only............................................... 300C PIN CONFIGURATION LTC2946 TOP VIEW VDD 1 INTVCC 2 GPIO1 3 GPIO2 4 GPIO3 5 SDAO 6 SDAI 7 SCL 8 16 SENSE + 15 SENSE - 17 GND TOP VIEW 14 ADR1 13 ADIN 12 ADR0 11 GND 10 CLKOUT 9 CLKIN VDD INTVCC GPIO1 GPIO2 GPIO3 SDAO SDAI SCL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SENSE + SENSE - ADR1 ADIN ADR0 GND CLKOUT CLKIN MS PACKAGE 16-LEAD PLASTIC MSOP DE PACKAGE 16-LEAD (4mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 120C/W TJMAX = 125C, JA = 43C/W, E PAD GND SOLDERED DOWN EXPOSED PAD (PIN 17) IS GND, PCB GND CONNECTION IS OPTIONAL LTC2946-1 TOP VIEW VDD 1 INTVCC 2 GPIO1 3 GPIO2 4 GPIO3 5 SDAO 6 SDAI 7 SCL 8 TOP VIEW 16 SENSE + 15 SENSE - 17 GND VDD INTVCC GPIO1 GPIO2 GPIO3 SDAO SDAI SCL 14 ADR1 13 ADIN 12 ADR0 11 GND 10 CLKOUT 9 CLKIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SENSE + SENSE - ADR1 ADIN ADR0 GND CLKOUT CLKIN MS PACKAGE 16-LEAD PLASTIC MSOP DE PACKAGE 16-LEAD (4mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 120C/W TJMAX = 125C, JA = 43C/W, E PAD GND SOLDERED DOWN EXPOSED PAD (PIN 17) IS GND, PCB GND CONNECTION IS OPTIONAL 2946fa 2 For more information www.linear.com/LTC2946 LTC2946 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING LTC2946CDE#PBF LTC2946CDE#TRPBF 2946 LTC2946IDE#PBF LTC2946IDE#TRPBF 2946 LTC2946HDE#PBF LTC2946HDE#TRPBF 2946 LTC2946CDE-1#PBF LTC2946CDE-1#TRPBF 29461 LTC2946IDE-1#PBF LTC2946IDE-1#TRPBF 29461 LTC2946HDE-1#PBF LTC2946HDE-1#TRPBF 29461 LTC2946CMS#PBF LTC2946CMS#TRPBF 2946 LTC2946IMS#PBF LTC2946IMS#TRPBF 2946 LTC2946HMS#PBF LTC2946HMS#TRPBF 2946 LTC2946MPMS#PBF LTC2946MPMS#TRPBF 2946 LTC2946CMS-1#PBF LTC2946CMS-1#TRPBF 29461 LTC2946IMS-1#PBF LTC2946IMS-1#TRPBF 29461 LTC2946HMS-1#PBF LTC2946HMS-1#TRPBF 29461 LTC2946MPMS-1#PBF LTC2946MPMS-1#TRPBF 29461 Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. PACKAGE DESCRIPTION 16-Lead (4mm x 3mm) Plastic DFN 16-Lead (4mm x 3mm) Plastic DFN 16-Lead (4mm x 3mm) Plastic DFN 16-Lead (4mm x 3mm) Plastic DFN 16-Lead (4mm x 3mm) Plastic DFN 16-Lead (4mm x 3mm) Plastic DFN 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP TEMPERATURE RANGE 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C -55C to 125C 0C to 70C -40C to 85C -40C to 125C -55C to 125C For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD is from 4V to 100V, unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VDD VDD Input Supply Voltage l 4 100 V VCC INTVCC Input Supply Voltage l 2.7 5.8 V IDD VDD Supply Current ICC INTVCC Supply Current 1.3 40 1.0 40 mA A mA A VCC(LDO) VDD = 48V, INTVCC Open Shutdown INTVCC = VDD = 5V Shutdown l l 0.9 15 0.7 15 INTVCC Linear Regulator Voltage 8V < VDD < 100V, ILOAD = 0mA l VCC(LDO) INTVCC Linear Regulator Load Regulation 8V < VDD < 100V, ILOAD = 0mA to 10mA l VCCZ Shunt Regulator Voltage at INTVCC VDD = 48V, ICC = 1mA l VCCZ Shunt Regulator Load Regulation VDD = 48V, ICC = 1mA to 35mA l VCC(UVL) INTVCC Supply Undervoltage Lockout INTVCC Rising, VDD = INTVCC l 2.3 VDD(UVL) VDD Supply Undervoltage Lockout VDD Rising, INTVCC Open l VDDI2C(RST) VDD I2C Logic Reset VDD Falling, INTVCC Open l VCCI2C(RST) INTVCC I2C Logic Reset INTVCC Falling, VDD = INTVCC l ISENSE+(HI) 48V SENSE + Input Current ISENSE-(HI) 48V SENSE - Input Current ISENSE+(LO) 0V SENSE + Source Current SENSE+, SENSE -, VDD = 48V Shutdown SENSE +, SENSE -, VDD = 48V Shutdown SENSE +, SENSE - = 0V, VDD = 48V Shutdown l l 4.4 5.8 5 5.4 V 100 200 mV 6.3 6.7 V 250 mV 2.6 2.69 V 2.4 2.8 3 1.7 2.1 V 1.7 2.1 V V SENSE Inputs l l l l l l 100 150 1 20 1 -10 -1 A A A A A A 2946fa For more information www.linear.com/LTC2946 3 LTC2946 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD is from 4V to 100V, unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS ISENSE(LO)- 0V SENSE - Source Current SENSE +, SENSE - = 0V, VDD = 48V MIN Shutdown l l TYP MAX -5 -1 UNITS A A ADC (SENSE+, SENSE- = 0V, 100V) (Note 5) RES Resolution (No missing codes) (Note 7) l TUE Total Unadjusted Error (Note 6) l l l l l l VFS Full-Scale Voltage LSB LSB Step Size VOS Offset Error INL Integral Nonlinearity Transition Noise (Note 7) tCONV Conversion Time (Snapshot Mode) RADIN ADIN Input Resistance SENSE (C-, I-Grade) SENSE (H-, MP-Grade) SENSE+, VDD (C-, I-Grade) SENSE+, VDD (H-, MP-Grade) ADIN (C-, I-Grade) ADIN (H-, MP-Grade) SENSE (C-, I-Grade) SENSE (H-, MP-Grade) SENSE+, VDD (C-, I-Grade) SENSE+, VDD (H-, MP-Grade) ADIN (C-, I-Grade) ADIN (H-, MP-Grade) SENSE SENSE +, VDD ADIN SENSE (C-, I-Grade) SENSE (H-, MP-Grade) SENSE +, VDD ADIN SENSE SENSE +, VDD ADIN SENSE SENSE +, VDD ADIN SENSE SENSE +, VDD, ADIN VDD = 48V, ADIN = 3V l l l l l l 12 101.8 101.7 102 101.9 2.042 2.04 Bits 102.4 102.4 102.4 102.4 2.048 2.048 25 25 0.5 2.1 3.1 1.5 1.1 2.5 2 2 l l l l l l l l 62.4 31.2 3 1.2 0.3 10 65.6 32.8 10 1 l l 0.6 0.7 0.4 0.5 0.3 0.4 103 103.1 102.8 102.9 2.054 2.056 68.8 34.4 % % % % % % mV mV V V V V V mV mV LSB LSB LSB LSB LSB LSB LSB VRMS mVRMS VRMS ms ms M CLKIN, CLKOUT, GPIO VCLKIN(TH) CLKIN Input Threshold l 0.7 fCLKIN(MAX) Maximum CLKIN Frequency l 25 1.3 V ICLKIN(IN) CLKIN Input Current VCLKIN = 5V l 5 10 A ICLKOUT CLKOUT Output Current VCLKIN = 0V, VCLKOUT = 0V l -70 -100 -130 A VGPIO(TH) GPIO Input Threshold VGPIO Rising l 1.06 1.22 1.32 V MHz VGPIO(HYST) GPIO Input Hysteresis VGPIO(OL) GPIO Output Low Voltage IGPIO = 8mA l 0.15 36 0.4 mV V IGPIO(IN) GPIO Input Leakage Current VGPIO = 5V l 0 1 A 2.7 V I2C Interface (VDD = 48V) VADR(H) ADR0, ADR1 Input High Threshold VADR(L) ADR0, ADR1 Input Low Threshold IADR(IN) ADR0, ADR1 Input Current IADR(IN,Z) Allowable Leakage When Open VOD(OL) SDAO, SDAO, Output Low Voltage ISDA,SCL(IN) SDAI, SDAO, SDAO, SCL Input Current ADR0, ADR1 = 0V, 3V l 1.9 2.4 l 0.3 0.6 0.9 V l 13 A l 7 A ISDAO, ISDAO = 8mA l 0.15 0.4 V SDAI, SDAO, SDAO, SCL = 5V l 0 1 A 2946fa 4 For more information www.linear.com/LTC2946 LTC2946 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD is from 4V to 100V, unless otherwise noted. (Note 2) SYMBOL PARAMETER VSDA,SCL(TH) SDAI, SCL Input Threshold CONDITIONS VSDA,SCL(CL) SDAI, SCL Clamp Voltage ISDAI, ISCL = 3mA MIN TYP MAX l 1.5 1.8 2.1 UNITS V l 5.9 6.4 6.9 V 400 I2C Interface Timing fSCL(MAX) Maximum SCL Clock Frequency l tLOW SCL LOW Period l 0.65 1.3 s tHIGH SCL HIGH Period l 50 600 ns tBUF(MIN) l 0.12 1.3 s l 140 600 ns l 30 600 ns tSU,STO(MIN) Bus Free Time Between STOP/START Condition Hold Time After (Repeated) START Condition Repeated START Condition Setup Time STOP Condition Setup Time l 30 600 ns tHD,DATI(MIN) Data Hold Time Input l -100 0 ns tHD,DATO(MIN) Data Hold Time Output l tSU,DAT(MIN) Data Setup Time l tSP(MAX) Maximum Suppressed Spike Pulse Width l tRST Stuck Bus Reset Time l CX SCL, SDAI Input Capacitance (Note 7) tHD,STA(MIN) tSU,STA(MIN) SCL or SDAI Held Low kHz 300 600 900 ns 30 100 ns 50 110 250 ns 25 33 5 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive. All voltages are referenced to ground, unless otherwise noted. Note 3: An internal shunt regulator limits the INTVCC pin to a minimum of 5.8V. Driving this pin to voltages beyond 5.8V may damage the part. This pin can be safely tied to higher voltages through a resistor that limits the current below 35mA. ms 10 pF Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of 5.9V. Driving these pins to voltages beyond the clamp may damage the part. The pins can be safely tied to higher voltages through resistors that limit the current below 5mA. Note 5: SENSE is defined as VSENSE+ - VSENSE - Note 6: TUE = (ACTUAL CODE - IDEAL CODE)/4096 * 100% where IDEAL CODE is derived from a straight line passing through Code 0 at 0V and theoretical code of 4096 at VFS. Note 7: Guaranteed by design and not subject to test. TYPICAL PERFORMANCE CHARACTERISTICS SUPPLY CURRENT (A) 900 900 800 700 26 SHUTDOWN 22 20 INTVCC Load Regulation 5.2 NORMAL 800 NORMAL 24 INTVCC Supply Current 700 INTVCC VOLTAGE (V) VDD Supply Current SUPPLY CURRENT (A) 1000 600 30 25 SHUTDOWN 5.1 5.0 4.9 20 0 20 40 60 80 VDD SUPPLY VOLTAGE (V) 100 2946 G01 15 2 3 4 5 INTVCC SUPPLY VOLTAGE (V) 6 2946 G02 4.8 0 2 4 6 LOAD CURRENT (mA) 8 10 2946 G03 2946fa For more information www.linear.com/LTC2946 5 LTC2946 TYPICAL PERFORMANCE CHARACTERISTICS INTVCC Shunt Regulator Load Regulation 5.5 6.40 5.0 6.35 SENSE Input Current 100 4.5 4.0 SENSE CURRENT (A) 80 INTVCC VOLTAGE (V) INTVCC OUTPUT VOLTAGE (V) INTVCC Line Regulation 6.30 6.25 SENSE+ 60 40 20 SENSE - 0 3.5 0 20 40 60 80 VDD SUPPLY VOLTAGE (V) 6.20 100 0 2946 G04 10 20 30 INTVCC SHUNT CURRENT (mA) -20 40 3.0 6.6 2.5 6.5 2.0 6.4 20 2946 G05 SCL/SDAI Loaded Clamp Voltage vs Load Current ADR Voltage with Current Source or Sink 0 40 60 SENSE VOLTAGE (V) 80 100 2946 G06 GPIO, SDAO, SDAO Loaded Output Low Voltage vs Load Current 0.4 1.5 1.0 VOD(OL) (V) VSDA,SCL(CL) (V) VADR (V) 0.3 6.3 0.2 6.2 0.1 0.5 6.1 0 -10 -5 0 5 IADR (A) 6.0 0.01 10 0.10 1.00 ILOAD (mA) 2946 G07 ADC Total Unadjusted Error (ADIN) 0 10.00 2 4 6 IOD (mA) 8 10 2946 G09 ADC Differential Nonlinearity (ADIN) ADC Integral Nonlinearity (ADIN) 0.10 0 2946 G08 0.3 0.3 0.2 0.2 0 0.1 ADC DNL (LSB) ADC INL (LSB) ADC TUE (%) 0.05 0 0.1 0 -0.1 -0.1 -0.2 -0.2 -0.05 -0.10 0 1024 2048 CODE 3072 4096 -0.3 0 1024 2048 CODE 3072 4096 2946 G11 -0.3 0 1024 2048 CODE 3072 4096 2946 G12 2946 G10 2946fa 6 For more information www.linear.com/LTC2946 LTC2946 TYPICAL PERFORMANCE CHARACTERISTICS ADC Total Unadjusted Error (SENSE) ADC Differential Nonlinearity (SENSE) ADC Integral Nonlinearity (SENSE) 0.2 0.3 0.3 0.2 0.2 0 ADC DNL (LSB) ADC INL (LSB) ADC TUE (%) 0.1 0.1 0 0.1 0 -0.1 -0.1 -0.2 -0.2 -0.1 -0.2 0 1024 2048 CODE 3072 -0.3 4096 0 1024 2048 3072 4096 CODE -0.3 0 1024 2048 3072 CODE 2946 G14 4096 2946 G15 2946 G13 254.4 6 254.3 254.2 4 2 0 25 50 75 100 TEMPERATURE (C) 125 CALIBRATION ON -2 -50 0 -25 25 50 75 100 TEMPERATURE (C) 2946 G16 100 1000 80 950 900 5 10 15 fCLKIN (MHz) CALIBRATION OFF 2 CALIBRATION ON -2 0 50 75 25 COMMON MODE VOLTAGE (V) 100 2946 G18 ADC Conversion Time over Internal Clock Frequency 1050 0 125 2946 G17 VDD Supply Current over CLKIN Frequency 850 4 0 CONVERSION TIME (ms) -25 INITIAL CALIBRATION DONE AT VCM = 48V NO CALIBRATION THEREAFTER 6 CALIBRATION OFF 0 254.1 8 OFFSET DRIFT (LSB) OFFSET DRIFT (LSB) 8 254.0 -50 Current Sense Amplifier Offset Drift Over Input Common Mode Current Sense Amplifier Offset Drift Over Temperature 254.5 SUPPLY CURRENT (A) INTERNAL CLOCK FREQUENCY (kHz) Internal Clock Frequency Over Temperature 20 25 SNAPSHOT MEASUREMENT OF ADIN 60 40 20 100 2946 G19 150 200 250 300 350 INTERNAL CLOCK FREQUENCY (kHz) 400 2946 G20 2946fa For more information www.linear.com/LTC2946 7 LTC2946 PIN FUNCTIONS ADIN: ADC Input. The onboard ADC measures voltages between 0V and 2.048V with respect to GND or INTVCC. Tie to ground if unused. See Table 3 in the Applications Information section for details. ADR1, ADR0: I2C Device Address Inputs. Connecting these pins to INTVCC, GND, or leaving the pins open configures one of nine possible addresses. See Table 1 in the Applications Information section for details. CLKIN: Clock Input. Connect to ground to use the internal 5% clock. For improved accuracy, connect to an external crystal oscillator circuit or drive with an external clock. CLKOUT: Clock Output. Connect to an external crystal oscillator circuit. Leave open if unused. EXPOSED PAD: Exposed Pad may be left open or connected to device ground. For best thermal performance, connect to a large PCB area. GND: Device Ground. GPIO1: General Purpose Input/Output (Open Drain). Configurable to general purpose output or input. Tie to ground if unused. See Table 9 in the Applications Information section for details. GPIO2: General Purpose Input/Output (Open Drain). Configurable to general purpose output, input or accumulation enable (ACC) to gate internal accumulators. Tie to ground if unused. See Table 9 in the Applications Information section for details. GPIO3: General Purpose Input/Output (Open Drain). Configurable to general purpose output, input or ALERT. As ALERT, it is pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by setting the corresponding bit in the ALERT registers, as shown in Tables 5 and 8. Tie to ground if unused. See Table 9 in the Applications Information section for details. INTVCC: Internal Low Voltage Supply Input/Output. This pin is used to power internal circuitry. It can be configured as a direct input for a low voltage supply, as a linear regulator from a higher voltage supply connected to VDD, or as a shunt regulator. Connect this pin directly to a 2.7V to 5.8V supply if available. When INTVCC is powered from an external supply, short the VDD pin to INTVCC. If VDD is connected to a 4V to 100V supply, INTVCC becomes the 5V output of an internal series regulator that can supply up to 10mA to external circuitry. For even higher supply voltages, or if a floating topology is desired, INTVCC can be used as a 6.3V shunt regulator. Connect the supply to INTVCC through a resistor or current source that limits the shunt regulator current to less than 35mA. An undervoltage lockout circuit disables the ADC when the voltage at this pin drops below 2.5V. Connect a bypass capacitor of 0.1F or greater from this pin to ground. If an external load is present, for loop stability use a bypass capacitor of 0.22F or greater. SCL: I2C Bus Clock Input. Data at the SDAI pin is shifted in or out on rising edges of SCL. This pin is driven by an open-collector output from a master controller. An external pull-up resistor or current source is required and can be placed between SCL and VDD or INTVCC. The voltage at SCL is internally clamped to 6.4V typically. 2946fa 8 For more information www.linear.com/LTC2946 LTC2946 PIN FUNCTIONS SDAI: I2C Bus Data Input. Used for shifting in address, command or data bits. This pin is driven by an opencollector output from a master controller. An external pull-up resistor or current source is required and can be placed between SDAI and VDD or INTVCC. The voltage at SDAI is internally clamped to 6.4V typically. Tie to SDAO for normal I2C operation. SDAO: LTC2946 Only. I2C Bus Data Output. Open-drain output used for sending data back to the master controller or acknowledging a write operation. An external pull-up resistor or current source is required. Tie to SDAI for normal I2C operation. SDAO: LTC2946-1 Only. Inverted I2C Bus Data Output. Open-drain output used for sending data back to the master controller or acknowledging a write operation. Data is inverted for convenience of opto-isolation. An external pull-up resistor or current source is required. The LTC2946-1 cannot be used in nonisolated I2C applications without additional components. SENSE+: Supply Voltage and Current Sense Input. Used as a supply and current sense input for internal current sense amplifier. The voltage at this pin is monitored by the onboard ADC with a full-scale input range of 102.4V. See Figure 20 for recommended Kelvin connection. SENSE-: Current Sense Input. Connect an external sense resistor between SENSE + and SENSE -. The differential voltage between SENSE + and SENSE - is monitored by the onboard ADC with a full-scale sense voltage of 102.4mV. VDD: High Voltage Supply Input. This pin powers an internal series regulator with input voltages ranging from 4V to 100V and produces 5V at INTVCC when VDD is above 8V. Connect a bypass capacitor of 0.1F or greater from this pin to ground if an external load is present on the INTVCC pin. The onboard 12-bit ADC can be configured to monitor the voltage at VDD with a full-scale input range of 102.4V. 2946fa For more information www.linear.com/LTC2946 9 LTC2946 BLOCK DIAGRAM 6 SENSE - + 8 SDAI SCL 12 ADR0 14 ADR1 DECODER 6.4V 6.4V - 15 7 SDAO/SDAO LTC2946/ LTC2946-1 20X I2C 2 GPIO3 5 VDD INTVCC VREF 2.048V 5V LDO 6.3V 735k 735k VOLTAGE 12 ADC + 1 - 16 + - SENSE + 1.22V 1.22V GPIO2 4 CURRENT POWER TIME COUNTER CHARGE 15k ENERGY + 15k - 13 ADIN 1.22V GPIO1 3 OSC GND 11 CLKIN 9 CLKOUT 10 2946BD TIMING DIAGRAM SDA tSU,DAT tHD,DATO tHD,DATI tSU,STA tSP tHD,STA tSP tBUF tSU,STO 2946 TD SCL tHD,STA REPEATED START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION 2946fa 10 For more information www.linear.com/LTC2946 LTC2946 OPERATION The LTC2946 accurately monitors current, voltage and power of any supply rail from 0V to 100V. An internal linear regulator allows the LTC2946 to operate directly from a 4V to 100V rail, or from an external supply voltage between 2.7V and 5.8V. Quiescent current is less than 1.3mA in normal operation. Enabling shutdown mode via the I2C interface reduces the quiescent current to below 40A. The onboard 12-bit analog-to-digital converter (ADC) runs either continuously or on demand using snapshot mode. There are seven continuous scan modes that can be selected via I2C. These modes configure the ADC to repeatedly measure the differential voltage between SENSE + and SENSE - (full-scale 102.4mV), the voltage at SENSE + or VDD pin (full-scale 102.4V) and the voltage applied to ADIN pin (full-scale 2.048V) at internally set duty cycles. See the Applications Information section for more details. The conversion results are stored in onboard registers. In snapshot mode, the LTC2946 performs a single measurement of one selected voltage or current. A status bit in the STATUS2 register monitors the ADC's conversion progress; when complete, the conversion result is stored in the corresponding data registers. The GPIO1 to GPIO3 pins are general purpose inputs or general purpose open-drain outputs. GPIO2 may also be configured as an enabling input for the accumulators. Similarly, GPIO3 may be configured as an ALERT output. Onboard logic stores the minimum and maximum values for each ADC measurement, calculates power data by digitally multiplying the stored current and voltage data, and optionally triggers an alert by pulling the GPIO3 pin low when the ADC measured value falls outside the programmed window thresholds. The LTC2946 includes accumulators that integrate the measured current and power over time to produce charge and energy values. The accumulators integrate at a rate determined either with an internal trimmed 5% clock, a precision clock generated from an external crystal, or an external clock. The accumulators can be preset with a value and optionally generate an alert when they overflow. The LTC2946 includes an I2C interface to access the onboard data registers and to program the alert threshold, configuration and control registers. Two three-state pins, ADR1 and ADR0, are decoded to allow nine device addresses (see Table 1). The SDA pin is split into SDAI (input) and SDAO (output, LTC2946) or SDAO (output, LTC2946-1) to facilitate opto-isolation. Tie SDAI and SDAO together for normal, nonisolated I2C operation. APPLICATIONS INFORMATION The LTC2946 offers a compact and complete solution for high and low side power monitoring with integrated energy and charge accumulators. With an input common mode range of 0V to 100V and a wide input supply operating voltage range from 2.7V to 100V, this device is ideal for a wide variety of power management applications including automotive, industrial and telecom infrastructure. The basic application circuit shown in Figure 1 provides monitoring of high side current with a 0.02 resistor (5.12A full-scale), input voltage (102.4V full-scale) and an external voltage (2.048V full-scale), all using an internal 12-bit ADC. RSNS 0.02 VIN 4V TO 100V SENSE+ VDD C2 0.1F 3.3V VOUT SENSE- ADIN VADIN R2 2k R3 2k VDD INTVCC SCL SCL ADR1 SDAI SDA LTC2946 SDAO ALERT GPIO3 ADR0 3.3V GND ACCUMULATE R1 2k INT R4 2k GPIO1 GPIO2 CLKIN P GND GP OUTPUT 2946 F01 CLKOUT X1 C3 33pF X1: ABLS-4.000MHZ-B2-T C4 33pF Figure 1. High Side Power, Energy and Charge Monitor Using the LTC2946 2946fa For more information www.linear.com/LTC2946 11 LTC2946 APPLICATIONS INFORMATION Data Converter, Multiplier and Accumulator The LTC2946 features an onboard, 12-bit ADC that inherently averages input signal and noise over the conversion time window. The differential voltage between SENSE + and SENSE - (SENSE) is monitored with 25V/ LSB resolution (102.4mV full-scale) to allow accurate measurement of the load current across very low value shunt resistors. The supply voltage at VDD or SENSE + is directly measured with 25mV/LSB resolution (102.4V full-scale). The voltage at the uncommitted ADIN pin can also be measured with 0.5mV/LSB resolution (2.048V fullscale) to allow monitoring of an arbitrary external voltage. The supply voltage data is derived from VDD, SENSE + or ADIN depending on the external application circuit. SENSE + is selected by default as it is normally connected to the supply voltage as shown in Figure 4 (4a to 4c) and Figure 5b. In negative supply voltage systems, such as shown in Figure 5d, VDD is used to measure the supply voltage at GND with respect to the device ground. For positive and negative supply voltages of more than 100V, as shown in Figure 5a and Figure 5c, external resistors can be used to divide down the voltage for ADIN to measure the supply voltage. CA[4:3] in the CTRLA register select between VDD, SENSE + and ADIN for supply voltage data. More details can be found in Table 3. A 24-bit power value is generated by digitally multiplying the 12-bit load current data with the 12-bit supply voltage data. 1LSB of power is 1LSB of voltage multiplied by 1LSB of SENSE (current). The result is held in the three adjacent POWER registers (Table 2). During conversions, the data converter's input is multiplexed to measure four voltages: SENSE, the current sense amplifier's offset, VDD or VSENSE+, and VADIN at various duty cycle by configuring CA[6:5] and CA[2:0] in the CTRLA register (Table 3). Some configurations are shown in Figure 2 (2a to 2c) to illustrate the various conversion timing sequences. In Figure 2a, it is shown that upon power-up or after an I2C write transaction to the CTRLA register the ADC will first measure the current sense amplifier's offset (calibration) and again after every other conversion which can be either VADIN, the supply voltage (VDD or VSENSE+) or the load current (SENSE). Figure 2b shows periodic calibration performed every 16 conversions. In Figure 2c a more specific configuration is shown where the ADC periodically calibrates the current sense amplifier with other voltages sequenced for conversions in between. Two factors need to be considered when selecting between these configurations: 1. Presence of load current harmonics in sync with the windows when the ADC is not sampling the current. The user can improve measurement accuracy of the load current signal with such harmonics by selecting a higher duty cycle for SENSE. For most complete coverage, the ADC can be configured to continuously measure the current by setting CA[2:0] to 110. 2. Increasing the duty cycle for current measurement will result in less frequent updates of the current sense amplifier's offset and the supply voltage values, hence the amount they drift with respect to time and temperature determines the best configuration to use. An on-demand update can also be done with a single I2C write transaction to the CTRLA register, which will command new measurements of the current sense amplifier's offset and the supply voltage. The results will be used for offset calibration and for providing the voltage value for the multiplier. For example, if CA[6:5] is set to code 11, and CA[2:0] is set to 110, a new offset and voltage values will be produced two ADC conversions after the I2C write transaction. The ADC will continuously measure the current thereafter. The timing diagram shown in Figure 2d illustrates the sequence in which the power and accumulator data are generated following conversions in the default configuration. At t1, the ADC has just finished a conversion of the current (SENSE) signal. The time counter is incremented by one count while the new current data at t1 is added to the charge accumulator. A new power value is generated by multiplying I(t1) with the previous voltage (VIN) data that is then added to the energy accumulator. From t1 to t3, the systematic offset of the current sense amplifier is measured and stored. The ADC then performs a conversion on VIN. A calibration is done again at t4 before the ADC converts SENSE. The charge and energy accumulators are incremented at t2, t3, t4, t5, t6 and t7, with current and power data from time t1. The timer counter will keep track 2946fa 12 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION of the number of accumulations that have occurred. At t8, new current and power data becomes available and these values are added to the charge and energy accumulators. For other CA configurations, the charge and energy accumulators behave similarly; during calibration and when not measuring current the last current value will be used for accumulation and calculation of power. A 12-bit digital word corresponding to each measured voltage is stored in two adjacent registers out of the six total ADC data registers (SENSE MSB/LSB, VIN MSB/ LSB, and ADIN MSB/LSB), with the eight MSBs in the first register and the four LSBs in the second (see Table 2). The lowest 4 bits in the LSB registers are set to 0. These data registers are updated immediately following the corresponding ADC conversion. The 4-byte time counter keeps track of the elapsed time during which current and power measurements have been added to the charge and energy accumulators, respectively. At 16.395ms per count it will keep counts up to 2.23 years (see Table 15). Dividing the energy/charge by the time in the timer will yield the average power/current over the time interval in the timer. The charge accumulator is a 36-bit register with the most significant 32-bits accessible, hence one charge bit is equivalent to one timer tick of 16 (24) counts of current. Similarly, the energy accumulator is a 48-bit register with the most significant 32-bits accessible, hence one energy bit is equivalent to one timer tick of 65536 (216) counts of power. With current and power at full-scale the charge and energy accumulators are capable of storing 3.2 days of data which translates to several months at nominal current and power levels. POWER-UP OR CTRLA WRITTEN CAL MEAS CAL MEAS (2a) Current Sense Amplifier Calibrated Every Conversion, CA[6:5] = 00 POWER-UP OR CTRLA WRITTEN MEAS N=1 CAL MEAS N=2 MEAS N=3 MEAS N = 16 MEAS N=1 CAL MEAS N=2 (2b) Current Sense Amplifier Calibrated Every 16 Conversions, CA[6:5] = 01 POWER-UP OR CTRLA WRITTEN MEAS ADIN N=1 CAL MEAS V N=2 MEAS I N=3 MEAS I N = 128 MEAS I N = 129 CAL MEAS I N = 256 MEAS ADIN N=1 CAL (2c) The ADC Conversion Sequence for CA[6:5] = 10 and CA[2:0] = 101 NEW POWER = P(t1) NEW CURRENT= I(t1) POWER = P(t1) CURRENT= I(t1) MEAS I POWER = P(t1) CURRENT= I(t1) CAL 16.4ms t1 POWER = P(t1) CURRENT= I(t1) MEAS V 16.4ms t2 POWER = P(t1) CURRENT= I(t1) POWER = P(t1) CURRENT= I(t1) NEW POWER = P(t8) NEW CURRENT= I(t8) MEAS I CAL CAL 16.4ms t3 POWER = P(t1) CURRENT= I(t1) 16.4ms t4 16.4ms t5 16.4ms t6 16.4ms t7 t8 2946 F02 (2d) Default ADC Conversion Sequence Figure 2 2946fa For more information www.linear.com/LTC2946 13 LTC2946 APPLICATIONS INFORMATION Since the accumulators contain multiple bytes of data, a single page read transaction of the accumulators is required to ensure the data is coherent. All the accumulators are writable, allowing them to be preloaded with given values. The LTC2946 can then be configured to generate an overflow alert after a specified amount of energy or charge has been delivered or when a preset amount of time has elapsed. A snapshot mode is also included which makes a measurement of a single selected voltage (either SENSE, VDD or VSENSE+, or VADIN). To make a snapshot measurement, write the 2-bit code of the desired ADC channel to CA[4:3] and code 111 to CA[2:0] using a write byte command to the CTRLA register. When the write byte command is completed, the ADC converts the selected voltage and the busy bit S2[3] in the STATUS2 register (see Table 10) will be set to indicate that the conversion is in progress. After completing the conversion, the ADC will halt and the busy bit will reset to indicate that the data is ready. An alert may be generated at the end of a snapshot conversion by setting bit AL2[7] in the ALERT2 register (Table 8). To make another snapshot measurement, rewrite the CTRLA register. In snapshot mode, the POWER registers, time counters, charge and energy accumulators are not refreshed. Crystal Oscillator/External Clock Accurately measuring energy/charge by integrating power/ current requires a precise integration period. The on-chip clock of the LTC2946 is trimmed to within 5%. To enable timekeeping with the on-chip clock, tie CLKIN to GND and leave CLKOUT open. For better accuracy, a crystal oscillator or resonator may be connected to the CLKIN and CLKOUT pins, as shown in Figure 1. Alternately, an external clock between 1MHz and 25MHz may be applied to CLKIN with CLKOUT left unconnected. The clock frequency at CLKIN is divided by 4x the value in the CLK_DIV register (see Table 13) to generate an internal clock with targeted frequency of 250kHz for the data converter's delta-sigma modulator. With an external clock or crystal, the sampling frequency of the ADC can be adjusted by configuring the CLK_DIV register (Register 43h). Limit the sampling clock to between 100kHz and 400kHz and at least 20kHz above or below fIN. The delta-sigma ADC provides inherent averaging of the input signal such that an anti-aliasing filter is not required in most applications. However, noise ripple (fIN) occurring at integer multiples of the modulator sampling frequency (fS) can still pose problems. Figure 3 shows how the sampling frequency as a function of the input frequency affects the amount of error. When fS = fIN, in the worst case the input signal may be sampled entirely at its peak fS = 0.9 * fIN tIN tS fS = 1.1 * fIN tIN tS fS = fIN tIN tS 0s 10s 20s 30s 40s 50s 60s 70s 80s 90s 100s 2946 F03 Figure 3. Waveforms Showing the Effect of Aliasing 2946fa 14 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION recommended for optimal transient performance. Note that operation with high VDD voltages can result in significant power dissipation, and care is required to ensure that the maximum operating junction temperature stays below 125C. For improved thermal resistance, use the DFN package and solder the exposed pad to a large copper region on the PCB. (or trough) resulting in an average output value of VPEAK (or VTROUGH). The actual average value of the input is 1/2 * (VPEAK - VTROUGH). Slightly adjusting the sampling frequency will remove the error as samples representative of the entire waveform are averaged over the conversion period. This is illustrated in the waveforms corresponding to fS = 0.9fIN and fS = 1.1fIN. The input can be seen to get sampled at multiple instances between the peak and trough. Averaging sufficient number of samples will then yield the correct result. Figure 4a shows the LTC2946 being used to monitor an input supply that ranges from 4V to 100V. No secondary supply is needed since VDD can be connected directly to the input supply. If the LTC2946 is used to monitor an input supply of 0V to 100V, it can derive power from a wide range secondary supply connected to the VDD pin as shown in Figure 4b. The SENSE +/ - pins can be biased independently of the part's supply voltage. Alternatively, if a low voltage supply is present it can be connected to the INTVCC pin, as shown in Figure 4c, to minimize onchip power dissipation. When INTVCC is powered from a secondary supply, connect VDD to INTVCC. Flexible Power Supply to LTC2946 The LTC2946 can be externally configured to derive power from a wide range of supplies. The LTC2946 includes an onboard linear regulator to power the low voltage internal circuitry connected to the INTVCC pin from high VDD voltages. The linear regulator operates with VDD voltages from 4V to 100V, and a shunt regulator is available for voltages above 100V. The linear regulator produces a 5V output capable of supplying 10mA at the INTVCC pin when VDD is greater than 8V. The regulator is disabled when the junction temperature rises above 150C, and the output is protected against accidental shorts. Bypass capacitors of 0.1F, or greater, at both the VDD and INTVCC pins are RSNS VIN 4V TO 100V SENSE+ VOUT RSNS VIN 0V TO 100V SENSE+ SENSE- 4V TO 100V VDD VOUT RSNS VIN 0V TO 100V SENSE- SENSE+ 2.7V TO 5.9V VDD INTVCC C2 LTC2946 INTVCC VDD GND GND GND 2946 F04b 2946 F04a (4a) LTC2946 Derives Power from the Supply Being Monitored VOUT SENSE- INTVCC LTC2946 LTC2946 C2 For supply voltages above 100V, the shunt regulator at INTVCC can be used in both high and low side configurations to provide power to the LTC2946 through an external shunt resistor, RSHUNT. Figure 5a shows a high side power (4b) LTC2946 Derives Power from a Wide Range Secondary Supply 2946 F04c (4c) LTC2946 Derives Power from a Low Voltage Secondary Supply Figure 4 2946fa For more information www.linear.com/LTC2946 15 LTC2946 APPLICATIONS INFORMATION monitor with an input monitoring range beyond 100V in a high side shunt regulator configuration. The device ground is separated from ground through RSHUNT and clamped at 6.3V below the input supply. Note that due to the different ground levels, the I2C signals from the part need to be level shifted for communication with other ground referenced components. The bus voltage is measured with a resistor string connected to ADIN. Set CA[7] in the CTRLA register so that the ADC measures ADIN with reference to INTVCC instead of GND. The measurement range at ADIN is then from INTVCC to INTVCC - 2.048V. Figure 5b shows a high side rail-to-rail power monitor which derives power from a secondary supply greater than 100V. The voltage at INTVCC is clamped at 6.3V above ground in a low side shunt regulator configuration to power the part. In low side power monitors, the device RSNS VIN >100V SENSE+ R1 ground and the current sense inputs are connected to the negative terminal of the input supply as shown in Figure 5c. The low side shunt regulator configuration allows operation with input supplies above 100V by clamping the voltage at INTVCC. RSHUNT should be sized according to the following equation: VS(MAX) - VCCZ(MIN) ICC(ABSMAX) VS(MAX) - 5.8V 35mA RSHUNT VOUT LTC2946 >100V 1mA + ILOAD(MAX) RSNS SENSE+ RSHUNT VOUT SENSE- INTVCC LTC2946 GND C2 (1) ICC(MAX)+ ILOAD(MAX) VS(MIN) - 6.7V VIN 0V TO 100V SENSE- ADIN R2 VS(MIN) - VCCZ(MAX) where VS(MAX) and VS(MIN) are the operating maximum and minimum limits of the supply. ILOAD(MAX) is the maximum external current load that is connected to the shunt regulator. The shunt resistor must also be rated to safely INTVCC VDD RSHUNT C2 VDD 2946 F05a GND RSHUNT 2946 F05b (5a) LTC2946 Derives Power Through a High Side Shunt Regulator (5b) LTC2946 Derives Power Through a Low Side Shunt Regulator in a High Side Current Sense Topology GND RSHUNT GND VDD INTVCC R1 C2 INTVCC VDD GND LTC2946 GND ADIN R2 > -100V LTC2946 C2 SENSE - SENSE+ RSNS SENSE- 2946 F05c VNEG (-4V TO -100V) VOUT (5c) LTC2946 Derives Power Through a Low Side Shunt Regulator in a Low Side Current Sense Topology SENSE+ RSNS 2946 F05d VOUT (5d) LTC2946 Derives Power from the Supply Monitored in a Low Side Current Sense Topology Figure 5 2946fa 16 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION dissipate the worst-case power. As an example, consider the -48V telecom system where the supply operates from -36V to -72V and the shunt regulator is used to supply an external load up to 4mA. RSHUNT needs to be between 1.9k and 5.9k according to the previous equation, and for reduced power dissipation, a larger resistance is advantageous. The worst-case power dissipated in an RSHUNT of 5.36k is calculated to be 0.8W. Three 0.5W rated 1.8k resistors in series would suffice for this example. If the supply input is below 100V, the shunt resistor is not required and VDD can be connected to GND of the supply as shown in Figure 5d. Supply Undervoltage Lockout During power-up, the internal I2C logic and the ADC are enabled when either VDD or INTVCC rises above its undervoltage lockout threshold. During power-down, the ADC is disabled when VDD and INTVCC fall below their respective undervoltage lockout thresholds. The internal I2C logic is reset when VDD and INTVCC fall below their respective I2C reset thresholds. Shutdown Mode The LTC2946 includes a low quiescent current shutdown mode, controlled by bit CB[6] in the CTRLB register (Table 4). Setting CB[6] puts the part in shutdown mode, powering down the ADC, internal reference and onboard linear regulator. The internal I2C bus remains active, and although the ADR1 and ADR0 pins are disabled, the device will retain the most recently programmed I2C bus address. All onboard registers retain their contents and can be accessed through the I2C interface. To re-enable ADC conversions, reset bit CB[6] in the CTRLB register. The analog circuitry will power up and all registers will retain their contents. The onboard linear regulator is disabled in shutdown mode to conserve power. If the onboard linear regulator is used to power external I2C bus related circuitry such as optocouplers or pull-ups, I2C communication will be lost when the part is shut down. The LTC2946 would then have to be reset by cycling its power to come out of shutdown. If low IQ mode is not required, ensure bit CB[6] in the CTRLB register is masked off during software development. It is recommended that external regulators be used in such applications if powering down the LTC2946 is desirable. As an added layer of protection against this scenario, bit CB[4] in the CTRLB register can be set during system configuration to enable the LTC2946 to automatically exit shutdown mode when the I2C lines are low for more than 33ms (which can be a result of accidental shutdown of the LTC2946's linear regulator powering the I2C). The user can elect to be alerted of this event by setting bit AL2[3] in the ALERT2 register (Table 8). Quiescent current drops below 40A in shutdown mode with the internal regulator disabled. Configuring the GPIO Pins The LTC2946 has three GPIO pins configurable through the GPIO_CFG register (Table 9) to be used as general purpose input/output pins. As general purpose inputs, GPIO1 through GPIO3 can be either active HIGH or LOW. In addition, GPIO2 can also be used as an accumulation enable input by writing bits CB[3:2] = [10] to allow integration of the time counter, charge and energy accumulators. GPIO1 through GPIO3 have comparators monitoring the voltage on these pins with a threshold of 1.22V, the results of which may be read from bits S2[6:4] in the STATUS2 register, as shown in Table 10. An alert may be generated when GPIO1 or GPIO2 are active as inputs by setting bits AL2[6] and AL2[5], respectively, in the ALERT2 register. GPIO1-3 can be pulled low as general purpose outputs, which are otherwise high impedance. GPIO3 is by default an ALERT output that pulls low when an alert event is present. To pull GPIO3 (ALERT) low in the absence of an alert event, set GC[7] of the GPIO3_CTRL register (Table 12). Clearing this bit will release the GPIO3 (ALERT). GC[7] does not have an effect on GPIO3 if it is not configured as an ALERT output. Likewise, GC[6] does not affect GPIO3 if it is not configured as a general purpose output. GC[7] is set whenever an alert event occurs irrespective of GPIO3's configuration. Reset GC[7] before reconfiguring GPIO3 to ALERT. 2946fa For more information www.linear.com/LTC2946 17 LTC2946 APPLICATIONS INFORMATION I2C Reset The accumulators can be programmed to reset themselves after the host reads the last byte (3Fh) of the accumulator data by writing bits CB[1:0] to [01] in the CTRLB register (Table 4). This feature removes the need to issue a reset command after polling the LTC2946 for accumulated data. The accumulators will continue to accumulate after the reset. To reset the accumulators without such read command, write bits CB[1:0] to [10]. The accumulators will stay reset if CB[1:0] = [10]. All registers are reset when CB[1:0] = [11], and these bits will then auto-reset to [00]. The ADC sequencing configuration is preserved through the I2C reset, regardless of the CTRLA register having reset. To change the sequencing configuration after such resets, rewrite the CTRLA register. Storing Minimum and Maximum Values The LTC2946 compares each measurement including the calculated power with the stored values in the respective MIN and MAX registers for each parameter (Table 2). If the new conversion is beyond the stored minimum or maximum values, the MIN or MAX registers are updated with the new values. The MIN and MAX of the registers are refreshed at the end of their respective ADC conversions in continuous scan modes and snapshot mode. They are also refreshed if the ADC registers are written via the I2C bus with values beyond the stored values. To initiate a new peak hold cycle, write all 1's to the MIN registers and all 0's to the MAX registers via the I2C bus. These registers will be updated when the next respective ADC conversion is done. The LTC2946 also includes MIN and MAX threshold registers (Table 2) for the measured parameters including the MEASURED DATA THRESHOLD DATA calculated power. At power-up, the maximum thresholds are set to all 1's, and minimum thresholds are set to all 0's, effectively disabling them. The thresholds can be reprogrammed to any desired value via the I2C bus. Fault Alert and Resetting Faults As soon as a measured quantity falls below the minimum threshold or exceeds the maximum threshold, the LTC2946 sets the corresponding flag in the STATUS1 (Table 6) register and latches it into the FAULT1 (Table 7) register (see Figure 6). Other events such as GPIO state change, stuck bus wake-up and accumulator overflow have their present status in the STATUS2 (Table 10) register and any fault is latched in the FAULT2 (Table 11) register. The GPIO3 pin is pulled low if the appropriate bit in the ALERT1 (Table 5) and ALERT2 (Table 8) registers is set and it is configured as ALERT output. More details on the alert behavior can be found in the Alert Response Protocol section. An active fault indication can be reset by writing zeros to the corresponding FAULT register bits or setting bit CB[5] in the CTRLB register. If bit CB[5] is set, reading the FAULT1 or FAULT2 register will cause the corresponding register to reset. All FAULT register bits are also cleared if the VDD and INTVCC fall below their respective I2C logic reset threshold. Note that faults that are still present, as indicated in the STATUS1 and STATUS2 registers, will immediately reappear. When accumulators (time, charge and energy) overflow, the corresponding bits in the STATUS2 register are set and will stay set. The accumulator overflow bits in the FAULT2 register will reappear after they have been cleared via I2C since the STATUS2 register continues to indicate overflow faults. STATUS DIGITAL COMPARATOR LOGIC LATCH FAULT ALERT RESET ENA_ALERT_RESPONSE 2946 F06 Figure 6. LTC2946 Fault Alert Generation Blocks 2946fa 18 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION If it is necessary to clear accumulator overflow fault(s), the recommended procedure is: 1. Read the accumulators 2. Store these values in an external memory 3. Issue a reset to the accumulators by writing bits CB[1:0] to [10]. Then disable reset by writing bits CB[1:0] to [00]. 4. Write the stored values back to the accumulators Steps 2 and 4 can be skipped if there is no need to continue the accumulation from present values. SDA a6 - a0 SCL I2C Interface The LTC2946 includes an I2C/SMBus-compatible interface to provide access to the onboard registers. Figure 6 shows a general data transfer format using the I2C bus. The LTC2946 is a read/write slave device and supports the SMBus read byte, write byte, read word and write word protocols. The LTC2946 also supports extended read and write commands that allow reading or writing more than two bytes of data. When using the read/write word or extended read and write commands, the bus master issues an initial register address and the internal register address b7 - b0 1-7 8 9 1-7 b7 - b0 8 9 1-7 8 9 S P START CONDITION ADDRESS R/W ACK DATA ACK DATA STOP CONDITION ACK 2946 F06 Figure 7. General Data Transfer Over I2C S ADDRESS W A COMMAND 1 1 0 a3:a0 0 0 X X b5:b0 FROM MASTER TO SLAVE FROM SLAVE TO MASTER A DATA A P 0 b7:b0 0 2946 F08 A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) S W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION ADDRESS W A COMMAND 1 1 0 a3:a0 0 0 X X b5:b0 A DATA COMMAND X X b5:b0 A DATA A DATA A P 0 b7:b0 0 b7:b0 0 2946 F09 Figure 8. LTC2946 Serial Bus SDA Write Byte Protocol S ADDRESS W A 1 1 0 a3:a0 0 0 Figure 9. LTC2946 Serial Bus SDA Write Word Protocol A DATA A ... DATA 0 b7:b0 0 b7:b0 0 ... b7:b0 0 A P S ADDRESS W A COMMAND 1 1 0 a3:a0 0 0 X X b5:b0 A S ADDRESS 0 1 1 0 a3:a0 1 0 b7:b0 1 2946 F10 2946 F11 Figure 10. LTC2946 Serial Bus SDA Write Page Protocol S ADDRESS W A COMMAND 1 1 0 a3:a0 0 0 X X b5:b0 R A DATA A P Figure 11. LTC2946 Serial Bus SDA Read Byte Protocol A S ADDRESS 0 1 1 0 a3:a0 1 0 b7:b0 0 b7:b0 1 R A DATA A DATA A P 2946 F12 Figure 12. LTC2946 Serial Bus SDA Read Word Protocol S ADDRESS W A COMMAND 1 1 0 a3:a0 0 0 X X b5:b0 A S ADDRESS R A DATA A DATA ... DATA A P 0 1 1 0 a3:a0 1 0 b7:b0 0 b7:b0 ... b7:b0 1 2946 F13 Figure 13. LTC2946 Serial Bus SDA Read Page Protocol Protocol 2946fa For more information www.linear.com/LTC2946 19 LTC2946 APPLICATIONS INFORMATION pointer automatically increments by 1 after each byte of data is read or written. After the register address reaches 43h, it will roll over to 00h and continue incrementing. A STOP condition resets the register address pointer to 00h. The data formats for the above commands are shown in Figure 7 through Figure 13. Note that only the read byte command is available to the E7 and E8 (MFR_SPECIAL_ID) registers (Table 2). I2C Device Addressing Nine distinct I2C bus addresses are configurable using the three-state pins ADR0 and ADR1, as shown in Table 1. ADR0 and ADR1 should be tied to INTVCC, to GND, or left floating (NC) to configure the lower four address bits. During low power shutdown, the address select state is latched into memory powered from standby supply. Address bits a6, a5 and a4 are permanently set to 110b and the least significant bit is the R/W bit. In addition, all LTC2946 devices will respond to a common mass write address 1100_110b; this allows the bus master to write to several LTC2946s simultaneously, regardless of their individual address settings. The LTC2946 will also respond to the standard ARA address 0001_100b if the GPIO3 (ALERT) pin is asserted. See the Alert Response Protocol section for more details. The LTC2946 will not respond to the ARA address if no alerts are pending. START and STOP Conditions When the I2C bus is idle, both SCL and SDA are in the HIGH state. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL stays high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from LOW to high while SCL stays high. The bus is then free for another transmission. Stuck-Bus Reset The LTC2946 I2C interface features a stuck-bus reset timer to prevent it from holding the bus lines low indefinitely if the SCL signal is interrupted during a transfer. The timer starts when either SCL or SDAI is low, and resets when both SCL and SDAI are pulled high. If either SCL or SDAI are low for over 33ms, the stuck-bus timer will expire, and the internal I2C interface and the SDAO pin pull-down logic will be reset to release the bus. Normal communication will resume at the next START command. Acknowledge The acknowledge signal is used for handshaking between the master and the slave to indicate that the last byte of data was received. The master always releases the SDA line during the acknowledge clock pulse. The LTC2946 will pull the SDA line low on the 9th clock cycle to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA high, then the master can abort the transmission by generating a STOP condition. When the master is receiving data from the slave, the master must acknowledge the slave by pulling down the SDA line during the 9th clock pulse to indicate receipt of a data byte. After the last byte has been received by the master, it will leave the SDA line high (not acknowledge) and issue a STOP condition to terminate the transmission. Write Protocol The master begins a write operation with a START condition followed by the seven-bit slave address and the R/W bit set to zero. After the addressed LTC2946 acknowledges the address byte, the master then sends a command byte that indicates which internal register the master wishes to write. The LTC2946 acknowledges this and then latches the lower six bits of the command byte into its internal register address pointer. The master then delivers the data byte and the LTC2946 acknowledges once more and writes the data into the internal register pointed to by the register address pointer. If the master continues sending additional data bytes with a write word or extended write command, the additional data bytes will be acknowledged by the LTC2946, the register address pointer will automatically increment by one, and data will be written as previously stated. The write operation terminates and the register address pointer resets to 00h when the master sends a STOP condition. Read Protocol The master begins a read operation with a START condition followed by the 7-bit slave address and the R/W bit set to zero. After the addressed LTC2946 acknowledges 2946fa 20 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION the address byte, the master then sends a command byte that indicates which internal register the master wishes to read. The LTC2946 acknowledges this and then latches the lower six bits of the command byte into its internal register address pointer. The master then sends a repeated START condition followed by the same 7-bit address with the R/W bit now set to 1. The LTC2946 acknowledges and sends the contents of the requested register. The transmission terminates when the master sends a STOP condition. If the master acknowledges the transmitted data byte, as in a read word command, the LTC2946 will send the contents of the next register. If the master keeps acknowledging, the LTC2946 will keep incrementing the register address pointer and sending out data bytes. The read operation terminates and the register address pointer resets to 00h when the master sends a STOP condition. Alert Response Protocol When any of the fault bits in the FAULT1 and FAULT2 register are set, a bus alert is generated if the appropriate bit in the ALERT1 or ALERT2 register has been set and GPIO3 is configured as an ALERT output. This allows the bus master to select which faults will generate alerts. At power-up, both ALERT registers are cleared (no alerts enabled) and the GPIO3 (ALERT) pin is high. If an alert is enabled, the corresponding fault causes the GPIO3 (ALERT) pin to pull low. The bus master responds to the alert in accordance with the SMBus alert response protocol by broadcasting the alert response address 0001_100b, and the LTC2946 replies with its own address and releases its GPIO3 (ALERT) pin, as shown in Figure 14. The GPIO3 (ALERT) line is also released if CB[7] is set and the LTC2946 is addressed (see Table 4) by any message. The GPIO3 (ALERT) signal is not pulled low again until the FLT registers indicate a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate additional alerts until the associated FLT register bits have been cleared. ALERT S RESPONSE R A ADDRESS 0001100 1 0 DEVICE ADDRESS a7:a0 If two or more LTC2946s on the same bus are generating alerts when the ARA is broadcast, the bus master will repeat the alert response protocol until the GPIO3 (ALERT) line is released. Standard I2C arbitration causes the device with the highest priority (lowest address) to reply first and the device with the lowest priority (highest address) to reply last. Opto-Isolating the I2C Bus Opto-isolating a standard I2C device is complicated by the bidirectional SDA pin. The LTC2946/LTC2946-1 minimize this problem by splitting the standard I2C SDA line into SDAI (input) and SDAO (output, LTC2946) or SDAO (inverted output, LTC2946-1). The SCL is an input-only pin and does not require special circuitry to isolate. For conventional nonisolated I2C applications, use the LTC2946 and tie the SDAI and SDAO pins together to form a standard I2C SDA pin. Low speed isolated interfaces that use standard opendrain opto-isolators can use the LTC2946 with the SDAI and SDAO pins separated, as shown in Figure 15. Connect SDAI to the output of the incoming opto-isolator with a pull-up resistor to INTVCC or a local 5V supply; connect SDAO to the cathode of the outgoing opto-isolator with a current-limiting resistor in series with the anode. The input and output must be connected together on the isolated side of the bus to allow the LTC2946 to participate in I2C arbitration. Note that maximum I2C bus speed will generally be limited by the speed of the opto-couplers used in this application. The shunt regulators can supply up to 34mA of current to drive opto-isolator and pull-up resistors, as shown in Figure 16 and Figure 17. For identical SDAI/SCL pull-up resistors the maximum load is: 1 2 ILOAD(MAX) = VCCZ(MAX) * + R5 R4 (2) 1 2 ILOAD(MAX) = 6.7V * + R5 R4 A P RSHUNT can then be calculated using Equation 1. Note that both LTC2946 and LTC2946-1 can be used in the shunt 1 2946 F14 Figure 14. LTC2946 Serial Bus SDA Alert Response Protocol 2946fa For more information www.linear.com/LTC2946 21 LTC2946 APPLICATIONS INFORMATION 3.3V 5V R4 10k R5 10k R6 0.82k R7 0.47k R8 0.47k R10 2k VDD SCL LTC2946 SCL SDAI P MOCD207M SDA GND SDAO 2946 F15 GND 1/2 MOCD207M Figure 15. Opto-Isolation of a 10kHz I2C Interface Between LTC2946 and Microcontroller GND RSHUNT 3.3V R4 1k R5 10k R6 0.47k R7 10k SDAI INTVCC VDD VDD LTC2946 VEE C2 1F P 1/2 MOCD207M SDA GND GND SENSE- VEE SDAO SENSE+ 1/2 MOCD207M 2946 F16 VOUT RSNS 0.02 Figure 16. Low Speed 10kHz Opto-Isolators Powered from Low Side Shunt Regulator (SCL Omitted for Clarity) RSNS 0.02 VIN SENSE+ 3.3V SENSE- R4 1k R5 10k R6 1k R7 10k SDAI INTVCC VDD VDD LTC2946-1 C2 1F P 1/2 MOCD207M SDA SDAO GND GND 1/2 MOCD207M 2946 F17 RSHUNT Figure 17. Low Speed 10kHz Opto-Isolators Powered from High Side Shunt Regulator (SCL Omitted for Clarity) 22 For more information www.linear.com/LTC2946 2946fa LTC2946 APPLICATIONS INFORMATION regulator applications mentioned. Figure 18 shows an alternate connection for use with low speed opto-couplers and the LTC2946-1. This circuit uses a limited-current pull-up on the internally clamped SDAI pin and clamps the SDAO pin with the input diode of the outgoing optoisolator, removing the need to use INTVCC for biasing in the absence of an auxiliary low voltage supply. For proper clamping: VS(MAX) - VSDA,SCL(MIN) ISDA,SCL(MAX) VS(MAX) - 5.9V 5mA R4 R4 VS(MAX) - VSDA,SCL(MAX) ISDA,SCL(MIN) The LTC2946-1 must be used in this application to ensure that the SDAO signal polarity is correct. The LTC2946-1 can also be used with high speed optocouplers with push-pull outputs and inverted logic as shown in Figure 19. The incoming opto-isolator draws power from the INTVCC, and the data output is connected directly to the SDAI pin with no pull-up required. Ensure the current drawn does not exceed the 10mA maximum capability of the INTVCC pin. The SDAO pin is connected to the cathode of the outgoing opto-coupler with a current limiting resistor connected back to INTVCC. An additional discrete N-channel MOSFET is required at the output of the outgoing opto-coupler to provide the open-drain pulldown that the I2C bus requires. Finally, the input of the incoming opto-isolator is connected back to the output as in the low speed case. (3) VS(MAX) - 6.9V 0.5mA As an example, a supply that operates from 36V to 72V would require the value of R4 to be between 13k and 58k. 3.3V VIN 48V R4 20k R5 5.6k R6 0.47k R7 2k SDAI VDD LTC2946-1 P 1/2 MOCD207M SDAO GND SDA GND 1/2 MOCD207M 2946 F18 Figure 18. Opto-Isolation of a 1.5kHz I2C Interface Between LTC2946-1 and Microcontroller (SCL Omitted for Clarity) VIN 48V C1 1F VDD INTVCC C2 1F R5 2k 1/2 ACPL-064L* 3.3V VCC LTC2946-1 Q1 GND SDAO BS170 R6 2k R7 2k VDD VCC GND P ISO_SDA SDAI GND 1/2 ACPL-064L* SDA GND 2946 F19 *CMOS OUTPUT Figure 19. Opto-Isolation of a I2C Interface with Low Power, High Speed Opto-Couplers (SCL Omitted for Clarity) 2946fa For more information www.linear.com/LTC2946 23 LTC2946 APPLICATIONS INFORMATION Layout Considerations Design Example A Kelvin connection between the sense resistor RSNS and the LTC2946 is recommended to achieve accurate current sensing (Figure 20). The recommended minimum trace width for 1oz copper foil is 0.02" per amp to ensure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is preferred. Note that 1oz copper exhibits a sheet resistance of about 530 per square. In very high current applications where the sense resistor can dissipate significant power, the PCB layout should include good thermal management techniques such as extra vias and wide metal area. Given a 20m sense resistor, calculate the weight value per LSB for the current, power, charge and energy registers: The crystal oscillator's clock amplitude is sensitive to parasitics such as stray capacitance on the CLKOUT pin and coupling between the CLKIN and CLKOUT pins. It is recommended that the CLKIN and CLKOUT traces from the LTC2946 to the crystal oscillator network be as short as practical with the load capacitors placed next to the crystal, as shown in Figure 21. To minimize stray capacitances, avoid large ground planes and digital signals near the crystal network. Current = 25V/LSB/RSNS = 1.25mA/LSB Voltage = 25mV/LSB (SENSE+/ VDD is sensing the voltage) Power = 1.25mA/LSB * 25mV/LSB = 31.25W/LSB = 16.39543ms/LSB (default configuration Time 250kHz target frequency) Charge = 1.25mA/LSB * 16 * 16.384ms/LSB = 327.9086C/LSB Energy = 31.25W * 65536 * 16.39543ms = 33.578mJ/LSB RSNS TO LOAD SENSE - SENSE+ VIN 1 16 2 15 3 14 1 16 4 2 15 5 3 14 17 13 X1 12 6 11 12 7 10 CLKOUT 6 11 8 7 10 8 9 4 5 17 13 2946 F20 9 CLKIN C4 GND C3 2946 F21 Figure 20. Recommended Layout for Kelvin Connection Figure 21. Recommended Layout for Crystal Oscillator 2946fa 24 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION Table 1. LTC2946 Device Addressing DESCRIPTION HEX DEVICE ADDRESS h LTC2946 ADDRESS PINS BINARY DEVICE ADDRESS a6 a5 a4 a3 a2 a1 a0 R/W ADR1 ADR0 Mass Write CC 1 1 0 0 1 1 0 0 X X Alert Response 19 0 0 0 1 1 0 0 1 X X 0 CE 1 1 0 0 1 1 1 X H L 1 D0 1 1 0 1 0 0 0 X NC H 2 D2 1 1 0 1 0 0 1 X H H 3 D4 1 1 0 1 0 1 0 X NC NC 4 D6 1 1 0 1 0 1 1 X NC L 5 D8 1 1 0 1 1 0 0 X L H 6 DA 1 1 0 1 1 0 1 X H NC 7 DC 1 1 0 1 1 1 0 X L NC 8 DE 1 1 0 1 1 1 1 X L L Table 2. LTC2946 Register Addresses and Contents REGISTER ADDR 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah REGISTER NAME CTRLA CTRLB ALERT1 STATUS1 FAULT1 POWER MSB2 POWER MSB1 POWER LSB MAX POWER MSB2 MAX POWER MSB1 MAX POWER LSB MIN POWER MSB2 MIN POWER MSB1 MIN POWER LSB MAX POWER THRESHOLD MSB2 MAX POWER THRESHOLD MSB1 MAX POWER THRESHOLD LSB MIN POWER THRESHOLD MSB2 MIN POWER THRESHOLD MSB1 MIN POWER THRESHOLD LSB SENSE MSB SENSE LSB MAX SENSE MSB MAX SENSE LSB MIN SENSE MSB MIN SENSE LSB MAX SENSE THRESHOLD MSB READ/WRITE R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION Operation Control Register A Operation Control Register B Selects Which Primary Faults Generate Alerts Primary Status Information Primary Fault Log Power MSB2 Data Power MSB1 Data Power LSB Data Maximum Power MSB2 Data Maximum Power MSB1 Data Maximum Power LSB Data Minimum Power MSB2 Data Minimum Power MSB1 Data Minimum Power LSB Data Maximum POWER Threshold MSB2 to Generate Alert Maximum POWER Threshold MSB1 to Generate Alert Maximum POWER Threshold LSB to Generate Alert Minimum POWER Threshold MSB2 to Generate Alert Minimum POWER Threshold MSB1 to Generate Alert Minimum POWER Threshold LSB to Generate Alert SENSE MSB Data SENSE LSB Data Maximum SENSE MSB Data Maximum SENSE LSB Data Minimum SENSE MSB Data Minimum SENSE LSB Data Maximum SENSE Threshold MSB to Generate Alert DEFAULT 18h 00h 00h 00h 00h XXh XXh XXh 00h 00h 00h FFh FFh FFh FFh FFh FFh 00h 00h 00h XXh X0h 00h 00h FFh F0h FFh 2946fa For more information www.linear.com/LTC2946 25 LTC2946 APPLICATIONS INFORMATION 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h E7h E8h MAX SENSE THRESHOLD LSB MIN SENSE THRESHOLD MSB MIN SENSE THRESHOLD LSB VIN MSB VIN LSB MAX VIN MSB MAX VIN LSB MIN VIN MSB MIN VIN LSB MAX VIN THRESHOLD MSB MAX VIN THRESHOLD LSB MIN VIN THRESHOLD MSB MIN VIN THRESHOLD LSB ADIN MSB ADIN LSB MAX ADIN MSB MAX ADIN LSB MIN ADIN MSB MIN ADIN LSB MAX ADIN THRESHOLD MSB MAX ADIN THRESHOLD LSB MIN ADIN THRESHOLD MSB MIN ADIN THRESHOLD LSB ALERT2 GPIO_CFG TIME COUNTER MSB3 TIME COUNTER MSB2 TIME COUNTER MSB1 TIME COUNTER LSB CHARGE MSB3 CHARGE MSB2 CHARGE MSB1 CHARGE LSB ENERGY MSB3 ENERGY MSB2 ENERGY MSB1 ENERGY LSB STATUS2 FAULT2 GPIO3_CTRL CLK_DIV MFR_SPECIAL_ ID MSB MFR_SPECIAL_ID LSB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R R Maximum SENSE Threshold LSB to Generate Alert Minimum SENSE Threshold MSB to Generate Alert Minimum SENSE Threshold LSB to Generate Alert ADC VIN MSB Data ADC VIN LSB Data Maximum VIN MSB Data Maximum VIN LSB Data Minimum VIN MSB Data Minimum VIN LSB Data Maximum VIN Threshold MSB to Generate Alert Maximum VIN Threshold LSB to Generate Alert Minimum VIN Threshold MSB to Generate Alert Minimum VIN Threshold LSB to Generate Alert ADIN MSB Data ADIN LSB Data Maximum ADIN MSB Data Maximum ADIN LSB Data Minimum ADIN MSB Data Minimum ADIN LSB Data Maximum ADIN Threshold MSB to Generate Alert Maximum ADIN Threshold LSB to Generate Alert Minimum ADIN Threshold MSB to Generate Alert Minimum ADIN Threshold LSB to Generate Alert Selects Which Secondary Faults Generate Alerts GPIO Configuration Time Counter MSB Data3 Time Counter MSB Data2 Time Counter MSB Data1 Time Counter LSB Data Charge MSB Data3 Charge MSB Data2 Charge MSB Data1 Charge LSB Data Energy MSB Data3 Energy MSB Data2 Energy MSB Data1 Energy LSB Data Secondary Status Information Secondary Fault Log GPIO3 Control Command Clock Divider Command Manufacturer Special ID MSB Data Manufacturer Special ID LSB Data F0h 00h 00h XXh X0h 00h 00h FFh F0h FFh F0h 00h 00h XXh X0h 00h 00h FFh F0h FFh F0h 00h 00h 00h 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h 00h 04h 60h 01h 2946fa 26 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION Table 3. CTRLA Register (00h): Read/Write BIT REGISTER NAME OPERATION DEFAULT ADIN Configuration [1] = ADIN Measured with Respect to INTVCC [0] = ADIN Measured with Respect to GND 0 CA[6:5] Offset Calibration Configuration Offset Calibration [11] = 1st Power-Up or Use Last Calibrated Result [10] = Once Every 128 Conversions [01] = Once Every 16 Conversions [00] = Every Conversion 00 CA[4 :3] Voltage Selection [11] = SENSE+ [10] = ADIN [01] = VDD [00] = SENSE** 11 CA[2 :0] Channel Configuration [111] = [110] = [101] = [100] = [011] = [010] = [001] = [000] = 000 CA[7] Snapshot Mode (Channel Defined by CA[4:3]). No Power, Energy or Charge Data Generated Voltage Measurement Once Followed by Current Measurement Indefinitely* ADIN, Voltage, Current Measurement at 1/256, 1/256 and 254/256 Duty Cycle, Respectively* ADIN, Voltage, Current Measurement at 1/32, 1/32 and 30/32 Duty Cycle, Respectively* Alternate ADIN, Voltage and Current Measurement* Voltage, Current Measurement at 1/128 and 127/128 Duty Cycle, Respectively* Voltage, Current Measurement at 1/16 and 15/16 Duty Cycle, Respectively* Alternate Voltage, Current Measurement* *Voltage defined by CA[4:3] in polling modes. **If SENSE (00) is selected and the channel configuration is other than snapshot mode (111) the voltage data is always the value in the VIN register prior to the mode change. It is recommended that SENSE be avoided when polling modes are used. Table 4. CTRLB Register (01h): Read/Write BIT REGISTER NAME OPERATION DEFAULT CB[7] ALERT Clear Enable Clear ALERT if Device is Addressed by the Master [1] = Enable [0] = Disable 0 CB[6] Shutdown [1] = Shutdown [0] = Power-Up 0 CB[5] Cleared on Read Control FAULT Registers Cleared on Read [1] = Cleared on Read [0] = Registers Not Affected by Reading 0 CB[4] Stuck Bus Timeout Auto Wake-Up Allows Part to Exit Shutdown Mode When Stuck-Bus Timer Is Reached [1] = Enable [0] = Disable 0 CB[3:2] Enable Accumulation [11] = Reserved [10] = Follows ACC State (GPIO2, See Table 9) ACC High, Accumulate ACC Low, No Accumulate [01] = No Accumulate [00] = Accumulate 00 CB[1:0] Auto-Reset Mode/Reset [11] = Reset All Registers [10] = Reset Accumulator (Time Counter, Charge and Energy) Registers [01] = Enable Auto-Reset [00] = Disable Auto-Reset 00 2946fa For more information www.linear.com/LTC2946 27 LTC2946 APPLICATIONS INFORMATION Table 5. ALERT1 Register (02h): Read/Write BIT REGISTER NAME AL1[7] Maximum POWER Alert OPERATION Enables Alert When POWER > Maximum POWER Threshold [1] = Enable Alert [0] = Disable Alert Enables Alert When POWER < Minimum POWER Threshold [1] = Enable Alert [0] = Disable Alert Enables Alert When ISENSE > Maximum ISENSE Threshold [1] = Enable Alert [0] = Disable Alert Enables Alert When ISENSE < Minimum ISENSE Threshold [1] = Enable Alert [0] = Disable Alert DEFAULT 0 AL1[6] Minimum POWER Alert AL1[5] Maximum ISENSE Alert AL1[4] Minimum ISENSE Alert AL1[3] Maximum VIN Alert Enables Alert When VIN > Maximum VIN Threshold [1] = Enable Alert [0] = Disable Alert 0 AL1[2] Minimum VIN Alert Enables Alert When VIN < Minimum VIN Threshold [1] = Enable Alert [0] = Disable Alert 0 AL1[1] Maximum ADIN Alert Enables Alert When ADIN > Maximum ADIN Threshold [1] = Enable Alert [0] = Disable Alert 0 AL1[0] Minimum ADIN Alert Enables Alert When ADIN < Minimum ADIN Threshold [1] = Enable Alert [0] = Disable Alert 0 Table 6. STATUS1 Register (03h): Read BIT REGISTER NAME S1[7] POWER Overvalue S1[6] POWER Undervalue S1[5] ISENSE Overvalue S1[4] ISENSE Undervalue S1[3] VIN Overvalue S1[2] VIN Undervalue S1[1] ADIN Overvalue S1[0] ADIN Undervalue OPERATION POWER > Maximum POWER Threshold [1] = POWER Overvalue [0] = POWER Not Overvalue POWER < Minimum POWER Threshold [1] = POWER Undervalue [0] = POWER Not Undervalue ISENSE > Maximum ISENSE Threshold [1] = ISENSE Overvalue [0] = ISENSE Not Overvalue ISENSE < Minimum ISENSE Threshold [1] = ISENSE Undervalue [0] = ISENSE Not Undervalue 0 0 0 DEFAULT 0 0 0 0 VIN > Maximum VIN Threshold [1] = VIN Overvalue [0] = VIN Not Overvalue VIN < Minimum VIN Threshold [1] = VIN Undervalue [0] = VIN Not Undervalue 0 ADIN > Maximum ADIN Threshold [1] = ADIN Overvalue [0] = ADIN Not Overvalue ADIN < Minimum ADIN Threshold [1] = ADIN Undervalue [0] = ADIN Not Undervalue 0 0 0 2946fa 28 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION Table 7. FAULT1 Register (04h): Read/Write BIT REGISTER NAME OPERATION DEFAULT F1[7] POWER Overvalue Fault POWER > Maximum POWER Threshold [1] = POWER Overvalue Fault Occurred [0] = No POWER Overvalue Fault Occurred 0 F1[6] POWER Undervalue Fault POWER < Minimum POWER Threshold [1] = POWER Undervalue Fault Occurred [0] = No POWER Undervalue Fault Occurred 0 F1[5] ISENSE Overvalue Fault ISENSE > Maximum ISENSE Threshold [1] = ISENSE Overvalue Fault Occurred [0] = No ISENSE Overvalue Fault Occurred 0 F1[4] ISENSE Undervalue Fault ISENSE < Minimum ISENSE Threshold [1] = ISENSE Undervalue Fault Occurred [0] = No ISENSE Undervalue Fault Occurred 0 F1[3] VIN Overvalue Fault VIN > Maximum VIN Threshold [1] = VIN Overvalue Fault Occurred [0] = No VIN Overvalue Fault Occurred 0 F1[2] VIN Undervalue Fault VIN < Minimum VIN Threshold [1] = VIN Undervalue Fault Occurred [0] = No VIN Undervalue Fault Occurred 0 F1[1] ADIN Overvalue Fault ADIN > Maximum ADIN Threshold [1] = ADIN Overvalue Fault Occurred [0] = No ADIN Overvalue Fault Occurred 0 F1[0] ADIN Undervalue Fault ADIN < Minimum ADIN Threshold [1] = ADIN Undervalue Fault Occurred [0] = No ADIN Undervalue Fault Occurred 0 Table 8. ALERT2 Register (32h): Read/Write BIT REGISTER NAME OPERATION DEFAULT AL2[7] ADC Conversion Done Alert Alert When ADC Finishes a Conversion [1] = Enable [0] = Disable 0 AL2[6] GPIO1 Input Alert Alert if GPIO1 Is Low When GP[7:6] = [01] (GPIO1 Input Active Low), or GPIO1 Is High When GP[7:6] = [00] (GPIO1 Input Active High) [1] = Enable Alert [0] = Disable Alert 0 AL2[5] GPIO2 Input Alert Alert if GPIO2 Is Low When GP[5:4] = [01] (GPIO2 Input Active Low), or GPIO2 Is High When GP[5:4] = [00] (GPIO2 Input Active High) [1] = Enable Alert [0] = Disable Alert 0 AL2[4] Reserved AL2[3] Stuck-Bus Timeout Wake-Up Alert Alert if Part Exits Shutdown Mode After Stuck-Bus Timer Expires with CB[4] = 1 [1] = Enable Alert [0] = Disable Alert 0 AL2[2] Energy Overflow Alert Alert if Energy Register Overflow [1] = Enable Alert [0] = Disable Alert 0 0 2946fa For more information www.linear.com/LTC2946 29 LTC2946 APPLICATIONS INFORMATION AL2[1] Charge Overflow Alert Alert if Charge Register Overflow [1] = Enable Alert [0] = Disable Alert 0 AL2[0] Time Counter Overflow Alert Alert if Time Counter Register Overflow [1] = Enable Alert [0] = Disable Alert 0 Table 9. GPIO_CFG Register (33h): Read/Write BIT REGISTER NAME OPERATION DEFAULT GP[7:6] GPIO1 Configure [11] = General Purpose Input, Active High [10] = General Purpose Input, Active Low [01] = General Purpose Output, Hi-Z [00] = General Purpose Output, Pulls Low 00 GP[5:4] GPIO2 Configure [11] = General Purpose Input, Active High [10] = General Purpose Input, Active Low [01] = General Purpose Output, GPIO = GP[1] [00] = Accumulate Input 00 GP[3:2] GPIO3 Configure [11] = General Purpose Input, Active High [10] = General Purpose Input, Active Low [01] = General Purpose Output, See Register 42h (Table 12) [00] = ALERT Output 00 GP[1] GPIO2 Output [1] = Pulls Low [0] = Hi-Z 0 GP[0] Reserved 0 2946fa 30 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION Table 10. STATUS2 Register (40h): Read BIT NAME S2[7] Reserved S2[6] GPIO1 State S2[5] S2[4] GPIO2 State GPIO3 State OPERATION DEFAULT 0 GP[7] GP[6] Function GPIO State 1 0 GPIO1 Input = Active Low [1] = GPIO1 Low [0] = GPIO1 High 1 1 GPIO1 Input = Active High [1] = GPIO1 High [0] = GPIO1 Low GP[5] GP[4] Function GPIO State 0 0 GPIO2 Input = ACC [1] = ACC High [0] = ACC Low 1 0 GPIO2 Input = Active Low [1] = GPIO2 Low [0] = GPIO2 High 1 1 GPIO2 Input = Active High [1] = GPIO2 High [0] = GPIO2 Low GP[3] GP[2] Function GPIO State 1 0 GPIO3 Input = Active Low [1] = GPIO3 Low [0] = GPIO3 High 1 1 GPIO3 Input = Active High [1] = GPIO3 High [0] = GPIO3 Low 0 0 0 S2[3] ADC Busy in Snapshot Mode 0 S2[2] Energy Register Overflow Energy Register Overflow [1] = Energy Register Overflow [0] = Energy Register Not Overflow 0 S2[1] Charge Register Overflow Charge Register Overflow [1] = Charge Register Overflow [0] = Charge Register Not Overflow 0 S2[0] Time Counter Register Overflow Time Counter Register Overflow [1] = Time Counter Register Overflow [0] = Time Counter Register Not Overflow 0 2946fa For more information www.linear.com/LTC2946 31 LTC2946 APPLICATIONS INFORMATION Table 11. FAULT2 Register (41h): Read/Write BIT REGISTER NAME OPERATION DEFAULT F2[7] Reserved 1 F2[6] GPIO1 Input Fault Indicates GPIO1 Was at Active Level as a General Purpose Input [1] = GPIO1 Input Was Active [0] = GPIO1 Input Was Inactive 0 F2[5] GPIO2 Input Fault Indicates GPIO2 Was at Active Level as a General Purpose Input [1] = GPIO2 Input Was Active [0] = GPIO2 Input Was Inactive 0 F2[4] GPIO3 Input Fault Indicates GPIO3 Was at Active Level as a General Purpose Input [1] = GPIO3 Input Was Active [0] = GPIO3 Input Was Inactive 0 F2[3] Stuck-Bus Timeout Wake-Up Fault With CB[4] = 1 [1] = Part Exited Shutdown Mode After Stuck-Bus Timer Expired [0] = No Stuck Bus Timeout Wake-Up Fault Occurred 0 F2[2] Energy Register Overflow Fault Energy Register Overflow [1] = Energy Register Overflow Fault [0] = No Energy Overflow Fault 0 F2[1] Charge Register Overflow Fault Charge Register Overflow [1] = Charge Register Overflow Fault [0] = No Charge Overflow Fault 0 F2[0] Time Counter Register Overflow Fault Time Counter Register Overflow [1] = Time Counter Register Overflow Fault [0] = No Time Counter Overflow Fault 0 Table 12. GPIO3_CTRL Register (42h): Read/Write BIT REGISTER NAME OPERATION DEFAULT GC[7] Alert Generated If GPIO3 is configured as ALERT output, it pulls low when alert is generated. Otherwise, this bit does not have an effect on GPIO3. This bit is set when an alert is generated or a 1 is written. To clear this bit, write 0 via I2C. 0 GC[6] GPIO3 Pull-Down Control Controls GPIO3 as a General Purpose Output [1] = GPIO3 Pulls Low [0] = GPIO3 Hi-Z This bit does not have effect on GPIO3 if it is configured otherwise. 0 Reserved Read Only GC[5:0] 00000b Table 13. CLK_DIV Register (43h): Read/Write BIT REGISTER NAME OPERATION CD[7:5] Reserved Read Only CD[4:0] Clock Divider Integer Input clock frequency at CLKIN is divided by 4x of this integer to produce the target 250kHz system clock. DEFAULT 000b 00100b 2946fa 32 For more information www.linear.com/LTC2946 LTC2946 APPLICATIONS INFORMATION Table 14. Register Data Format: Read/Write BIT (7) BIT (6) BIT (5) BIT (4) BIT (3) BIT (2) BIT (1) BIT (0) ADC, Min/Max ADC, Min/Max ADC Threshold MSB REGISTER Data (11) Data (10) Data (9) Data (8) Data (7) Data (6) Data (5) Data (4) ADC, Min/Max ADC, Min/Max ADC Threshold LSB Data (3) Data (2) Data (1) Data (0) Read as 0 Read as 0 Read as 0 Read as 0 Power, Min/Max Power, Min/ Max Power Threshold MSB2 Data (23) Data (22) Data (21) Data (20) Data (19) Data (18) Data (17) Data (16) Power, Min/Max Power, Min/ Max Power Threshold MSB1 Data (15) Data (14) Data (13) Data (12) Data (11) Data (10) Data (9) Data (8) Power, Min/Max Power, Min/ Max Power Threshold LSB Data (7) Data (6) Data (5) Data (4) Data (3) Data (2) Data (1) Data (0) Time Counter, Charge, Energy MSB3 Data (31) Data (30) Data (29) Data (28) Data (27) Data (26) Data (25) Data (24) Time Counter, Charge, Energy MSB2 Data (23) Data (22) Data (21) Data (20) Data (19) Data (18) Data (17) Data (16) Time Counter, Charge, Energy MSB1 Data (15) Data (14) Data (13) Data (12) Data (11) Data (10) Data (9) Data (8) Time Counter, Charge, Energy LSB Data (7) Data (6) Data (5) Data (4) Data (3) Data (2) Data (1) Data (0) MFR_SPECIAL_ID MSB Data (15) Data (14) Data (13) Data (12) Data (11) Data (10) Data (9) Data (8) MFR_SPECIAL_ID LSB Data (7) Data (6) Data (5) Data (4) Data (3) Data (2) Data (1) Data (0) Table 15. Time per LSB of Timer Register CA[6:5] SEE TABLE 3 CA[2:0] SEE TABLE 3 XX 110 4098.5 11 011 4099.75 010, 101 4098.5098 001, 100 4098.5806 000 4099.3333 10 01 00 Time / LSB = N * N 011 4099.7355 010, 101 4098.5097 001, 100 4098.5800 000 4099.3549 011 4099.6429 010, 101 4098.5092 001, 100 4098.5758 000 4099.2692 011 4099 010, 101 4098.5049 001, 100 4098.5397 000 4098.8571 4 *CLK _DIV fCLKIN or N * 4s if internal clock used. 2946fa For more information www.linear.com/LTC2946 33 LTC2946 TYPICAL APPLICATIONS Bidirectional Power Monitor with Energy and Charge Monitor in Forward Path RSNS 0.2 VIN 2.7V TO 5.8V SENSE+ ADIN ADR1 LTC2946 R2 2k SCL SCL SDAI SDA ALERT GPIO3 VDD P INT 3.3V GND GND R4 2k GPIO1 GPIO2 CLKIN R3 2k SDAO ADR0 ACCUMULATE R1 2k SENSE- INTVCC VDD C2 0.1F 3.3V VOUT 0.5A 2946 TA10 GP OUTPUT CLKOUT C3 X1 33pF C4 33pF X1: ABLS-4.000MHz-B2-T POWER FOR REVERSE PATH = CODEADIN x CODEVDD TO BE PERFORMED BY P CA[7] = 1, SEE TABLE 3 Power, Charge and Energy Monitoring in -48V System Using Low Side Sensing (1.5kHz I2C Interface) -48V RTN C1 1F C2 0.1F R6 12.1k R12 12.1k NC R1 20k R3 1k R2 20k 3.3V VEE VEE R5 681k R4 1k VDD R7 0.47k INTVCC ADR1 GPIO1 R8 0.47k R9 10k R10 10k R11 10k VDD SCL LTC2946 GPIO2 SCL SDAI CLKOUT VEE CLKIN GND SDA ADIN SDAO INT ADR0 ALERT GPIO3 SENSE - VEE -48V INPUT NC = NO CONNECT P MOCD207M SENSE+ RSNS 0.02 GND 2946 TA03 MOCD207M VOUT CA[4:3] = 01, SEE TABLE 3 2946fa 34 For more information www.linear.com/LTC2946 LTC2946 TYPICAL APPLICATIONS Dual Power, Charge and Energy Monitor Using Single Opto-Coupler for Galvanic Isolation and Blocking Diodes for Data Retention When Either Supply Fails V5VGEN RSNS1 0.02 VIN1 24V D1 BAT54 C1 1F SENSE + VDD VOUT1 SENSE- R5 3.9 GPIO2 GPIO3 C2 0.1F ADIN SDAO ADR0 SCL VIN1 R13 100k GREEN R14 4.7k GPO2A GREEN: VIN1 OK GP01A GP02A V5VGEN R6 4.7k GPO1A LTC2946 GPIO1 INTVCC VIN1 R5 100k RED RED: VIN1 OVERLOAD 3.3V V5VGEN R6 1k R7 1k HCPL-063L R8 0.47k R9 0.47k R10 10k R11 10k R12 10k VCC VDD SCL ADR1 P SDAI GND CLKIN CLKOUT X1 C5 33pF GND KEEP SHORT! C6 33pF V5VGEN C4 0.22F VIN2 48V D2 BAT54 SENSE + LTC2946 INTVCC R1 33.2k ADR1 ADIN R2 18.2k 3.3V VCC VOUT2 SDA CLKIN INT ALERT GND GND 2946 TA07 SDAI SCL V5VGEN SDAO C3 0.1F R4 HCPL-063L 1k SENSE- VDD C4 1F R3 1k RSNS2 0.02 R15 100k GPIO3 ADR0 GPIO1 GP01B GND GPIO2 GP02B CLKOUT NC GPO1B VIN2 V5VGEN R16 10k GREEN GREEN: VIN2 OK R17 100k GP02B VIN2 R18 10k RED RED: VIN2 OVERLOAD X1: ABLS-4.000MHz-B2-T GPO1A, GPO2A, GPO1B AND GPO2B ARE CONTROLLED BY MICROPROCESSOR WRITING COMMANDS TO LTC2946s VIA I2C 2946fa For more information www.linear.com/LTC2946 35 LTC2946 TYPICAL APPLICATIONS Power, Charge and Energy Monitor in -48V Harsh Environment Using INTVCC Shunt Regulator to Tolerate 200V Transients -48V RTN RSHUNT 2 x 5k IN SERIES R5 732k R12 100 Q1 PZTA42 D1 1N4148WS C2 1F VDD R1 1k INTVCC ADR1 C1 1F R4 1k R3 0.47k VEE R7 0.47k R8 0.47k R9 1k R10 1k R11 10k VCC VDD SCL LTC2946 SCL P SDAI ADIN R6 15k R2 1k 3.3V GND GPIO1 FAN ON OUTPUT CLKIN GPIO2 TEMP MONITOR INPUT C3, 33pF SDA GND ADR0 HCPL-063L V EE 3.3V VCC SDAO X1 C4, 33pF INT CLKOUT GPIO3 SENSE - VEE -48V INPUT ALERT GND GND SENSE+ 2946 TA05 HCPL-063L VOUT RSNS 0.02 X1: ABLS-4.000MHz-B2-T CA[4:3] = 10, SEE TABLE 3 Power, Charge and Energy Monitor for Main Supply and Power Monitor for Secondary Supply with Single LTC2946 RSNS1 0.02 VIN1 0V TO 100V SENSE+ VOUT1 5A SENSE- CLKOUT ADR0 GND CLKIN C2 0.1F ACCUMULATE LTC2946 R1 2k NC R3 2k VDD SCL SCL SDA ALERT 3.3V INT R4 2k VDD GPIO1 INTVCC P SDAO GPIO3 GPIO2 R2 2k SDAI ADR1 VIN2 2.7V TO 5.8V 3.3V GND GP OUTPUT 2946 TA06 ADIN RSNS 0.25 VOUT2 0.5A (8-BIT) CA[7] = 1, SEE TABLE 3 POWER FOR SECONDARY SUPPLY = CODEADIN x CODEVDD. TO BE PERFORMED BY P 2946fa 36 For more information www.linear.com/LTC2946 LTC2946 TYPICAL APPLICATIONS 6V to 300V High Side Power, Charge and Energy Monitor RSNS 0.02 VIN SENSE + VDD Z1* 5.1V C1 0.1F R1 5.1k VOUT 3.3V SENSE- INTVCC C2 1F R4 2k LTC2946-1 GPIO1 SCL GPIO2 SDAI FGND R3 2k R9 1k R10 1k VCC VDD P SDA GND ACPL-064L CLKOUT FGND 3.3V VCC ADR1 M2 BS170 SDAO ADR0 CLKIN R8 0.47k SCL ADIN R2 750k R7 0.47k GPIO3 GND INT ALERT GND GND 2946 TA07 ACPL-064L FGND Q1 2N3904 M3 BSP135 R5 10k R11 100 Q2 MMBT6520L R6 10k M1 BSP135 Q3 2N3904 CA[7] = 1, CA[4:3] = 10, SEE TABLE 3 * DDZ9689, DIODES, INC. 2946fa For more information www.linear.com/LTC2946 37 LTC2946 TYPICAL APPLICATIONS 12V, 50A Power, Charge and Energy Monitor RSNS 0.002, 5W VIN 12V SENSE+ VOUT 50A SENSE- VDD R3 2k VDD SCL ADR1 SDAI SDA LTC2946 P SDAO ALERT GPIO3 INT 3.3V GND V+ V+ OUT DIVA LTC6930-8.00 DIVB R2 2k SCL ADR0 C3 0.22F R1 2k VADIN ADIN INTVCC C2 0.1F ACCUMULATE 3.3V GPIO2 GPIO1 CLKIN CLKOUT R4 2k GND 2946 TA08 GP OUTPUT NC DIVC GND GND Wide Range -4V to -500V Negative Power, Charge and Energy Monitor (10kHz I2C Interface) RTN M1 BSP135 R5 750k R13 10k R4 1k Z1 4.7V CLKOUT R6 750k R1 2k R3 1k VDD 3.3V C1 0.1F R2 2k VEE R7 0.47k R8 0.47k R9 10k R10 10k R11 10k VDD SCL GPIO1 LTC2946 GPIO2 SCL SDAI P ADIN VEE CLKIN MOCD207M GND R12 6.04k SDA ADR1 SDAO INT ADR0 C2 0.1F ALERT GPIO3 INTVCC SENSE - SENSE+ VEE RSNS 0.02 GND 2946 TA09 MOCD207M VOUT CA[4:3] = 10, SEE TABLE 3 2946fa 38 For more information www.linear.com/LTC2946 LTC2946 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE Package 16-Lead Plastic DFN (4mm x 3mm) (Reference LTC DWG # 05-08-1732 Rev O) 0.70 0.05 3.30 0.05 3.60 0.05 2.20 0.05 1.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) R = 0.05 TYP 9 R = 0.115 TYP 0.40 0.10 16 3.30 0.10 3.00 0.10 (2 SIDES) 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER PIN 1 TOP MARK (SEE NOTE 6) (DE16) DFN 0806 REV O 8 0.200 REF 1 0.23 0.05 0.45 BSC 0.75 0.05 3.15 REF 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2946fa For more information www.linear.com/LTC2946 39 LTC2946 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev A) 0.889 0.127 (.035 .005) 5.10 (.201) MIN 3.20 - 3.45 (.126 - .136) 4.039 0.102 (.159 .004) (NOTE 3) 0.50 (.0197) BSC 0.305 0.038 (.0120 .0015) TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL "A" 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) 0 - 6 TYP 0.280 0.076 (.011 .003) REF 16151413121110 9 GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 0.17 - 0.27 (.007 - .011) TYP 1234567 8 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 0.0508 (.004 .002) MSOP (MS16) 0213 REV A 2946fa 40 For more information www.linear.com/LTC2946 LTC2946 REVISION HISTORY REV DATE DESCRIPTION A 03/15 Changed Y-axis of Typical Applications graph. PAGE NUMBER Corrected ISENSE(LO) - Conditions. Corrected RSHUNT equation. 1 4 16 2946fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC2946 41 LTC2946 TYPICAL APPLICATION Rail-to-Rail Power, Charge and Energy Monitor RSNS 0.02 VIN 0V TO 100V SENSE+ 2.7V TO 5.8V SENSE- R1 2k VADIN ADIN VDD R2 2k R3 2k VDD INTVCC SCL SCL ADR1 SDAI SDA C2 0.1F LTC2946 P SDAO ALERT GPIO3 ADR0 3.3V GND ACCUMULATE 3.3V VOUT INT R4 2k GPIO2 GPIO1 CLKIN CLKOUT X1 C3 33pF C4 33pF GND GP OUTPUT 2946 TA02 X1: ABLS-4.000MHz-B2-T RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT(R)2940 Power and Current Monitor 4-Quadrant Multiplication, 5% Power Accuracy, 4V to 80V Operation LTC2941 I2C Battery Gas Gauge 2.7V to 5.5V Operation, 1% Charge Accuracy LTC2942 I2C Battery Gas Gauge 2.7V to 5.5V Operation, 1% Charge, Voltage and Temperature LTC2943 High Voltage Battery Gas Gauge 3.6V to 20V Operation, 1% Charge, Voltage, Current and Temperature LTC2945 Wide Range I2C Power Monitor 0V to 80V Operation, 12-Bit ADC with 0.75% TUE LTC2990 Quad I2C Temperature, Voltage and Current Monitor 3V to 5.5V Operation, 14-Bit ADC LTC4150 Coulomb Counter/Battery Gas Gauge 2.7V to 8.5V Operation, Voltage-to-Frequency Converter LTC4151 High Voltage I2C Current and Voltage Monitor 7V to 80V Operation, 12-Bit Resolution with 1.25% TUE LTC4215 Single Channel, Hot SwapTM Controller with I2C Monitoring 8-Bit ADC, Adjustable Current Limit and Inrush, 2.9V to 15V Operation LTC4222 Dual Channel, Hot Swap Controller with I2C Monitoring 10-Bit ADC, Adjustable Current Limit and Inrush, 2.9V to 29V Operation LTC4260 Positive High Voltage Hot Swap Controller with I2C Monitoring 8-Bit ADC, Adjustable Current Limit and Inrush, 8.5V to 80V Operation LTC4261 Negative High Voltage Hot Swap Controller with I2C Monitoring 10-Bit ADC, Floating Topology, Adjustable Inrush 2946fa 42 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2946 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2946 LT 0315 REV A * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014