1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Low Voltage ORing FET Controller
ISL6146
The ISL6146 represents a family of ORing MOSFET controllers
capable of ORing voltages from 1V to 18V. Together with suitably
sized N-channel power MOSFETs, the ISL6146 increases power
distribution efficiency when replacing a power ORing diode in high
current applications. It provides gate drive voltage for the
MOSFET(s) with a fully integrated charge pump.
The ISL6146 allows users to adjust with external resistor(s) the
VOUT - VIN trip point, which adjusts the control sensitivity to system
power supply noise. An open drain FAULT pin will indicate if a
conditional or FET fault has occurred.
The ISL6146A and ISL6146B are optimized for very low voltage
operation, down to 1V with an additional independent bias of 3V
or greater.
The ISL6146C provides a voltage compliant mode of operation
down to 3V with programmable Undervoltage Lock Out and
Overvoltage Protection threshold levels
The ISL6146D and ISL6146E are like the ISL6146A and ISL6146B
respectively but do not have conduction state reporting via the
fault output.
Features
• ORing Down to 1V and Up to 20V with ISL6146A, ISL6146B,
ISL6146D and ISL6146E
• Programmable Voltage Compliant Operation with ISL6146C
• VIN Hot Swap Transient Protection Rating to +24V
• High Speed Comparator Provides Fast <0.3µs Turn-off in
Response to Shorts on Sourcing Supply
• Fastest Reverse Current Fault Isolation with 6A Turn-off
Current
• Very Smooth Switching Transition
• Internal Charge Pump to Drive N-channel MOSFET
•User Programmable V
IN - VOUT Vth for Noise Immunity
• Open Drain FAULT Output with Delay
- Short between any two of the ORing FET Terminals
- GATE Voltage and Excessive FET VDS
- Power-Good Indicator (ISL6146C)
• MSOP and DFN Package Options
Applications
• N+1 Industrial and Telecom Power Distribution Systems
• Uninterruptable Power Supplies
• Low Voltage Processor and Memory
•Storage and Datacom Systems
TABLE 1. KEY DIFFERENCES BETWEEN PARTS IN FAMILY
PART NUMBER KEY DIFFERENCES
ISL6146A Separate BIAS and VIN with Active High Enable
ISL6146B Separate BIAS and VIN with Active Low Enable
ISL6146C VIN with OVP/UVLO Inputs
ISL6146D ISL6146A wo Conduction Monitor & Reporting
ISL6146E ISL6146B wo Conduction Monitor & Reporting
FIGURE 1. TYPICAL APPLICATION FIGURE 2. ISL6146 GATE HIGH CURRENT PULL-DOWN
VIN GATE VOUT
GND
ADJ
+
-
+
VOUT
+
-
+C
O
M
M
O
N
P
O
W
E
R
B
U
S
Q1
ISL6146B FLT
BIAS
VOLTAGE
DC/DC
VOLTAGE
DC/DC
EN
(3V - 20V)
(3V - 20V)
Q2
C
O
M
M
O
N
P
O
W
E
R
B
U
S
VIN GATE VOUT
GND
ADJ
ISL6146B FLT
BIAS
EN
GATE FAST OFF, ~200ns FALL TIME
~70ns FROM 20V TO 12.6V ACROSS 57nF
GATE OUTPUT SINKING ~ 6A
July 12, 2012
FN7667.2
ISL6146
2FN7667.2
July 12, 2012
Block Diagram
Pin Configuration
ISL6146
(8 LD MSOP/DFN)
TOP VIEW
+
+
VIN
VOUT
ADJ
FLT
GATE
BIAS
4A
8mA
HIGH SPEED
COMPARATOR
Q-PUMP
VDS FORWARD
REGULATOR
REVERSE DETECTION
COMPARATOR
ENABLE
+
FAULT DIAGNOSTIC
1. VIN - VOUT > 570mV
2. GATE - VIN < 220mV (A,B,C only)
3. TEMP > +150°C
4. VBIAS < POR (ISL6146A/B/D/E)
5. VIN OR VOUT < POR (ISL6146C)
+
-
+
-
19mV
57mV
* Connected to BIAS on ISL6146A/B/D/E
*
Connected to VOUT on ISL6146C
ENABLE
+
-VREF
EN/EN
ISL6146A/B/D/E +
-VREF
OVP
ISL6146C
EN
UVLO
+
+
6. VIN < VOUT
7. Gate to Drain and Gate to Source Shorts
ISL6146A, ISL6146B, ISL6146D, ISL6146E ISL6146C
VIN
GATE
FAULT
VOUT
ADJ
EN ISL6146A
BIAS
GND
EN ISL6146B
1
2
3
4
8
7
6
5
VIN
GATE
FAULT
VOUT
ADJ
GND
UVLO
OVP
1
2
3
4
8
7
6
5
EPAD on DFN only, connect to GND
Pin Descriptions
MSOP/
DFN SYMBOL DESCRIPTION
1 GATE Gate Drive output to the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn-on time is typically
<1ms. Allows active control of external N-Channel FET gate to perform ORing function.
The GATE drive is between VIN + 7V at VIN = 3.3V and VIN +12V at VIN = 18V.
2 VIN Connected to the sourcing supply side (ORing MOSFET Source), this pin serves as the sense pin to determine the OR’d supply
voltage. The ORing MOSFET will be turned off when VIN becomes lower than VOUT by a value more than the externally set
threshold or the defaulted internal threshold. Range: 0V to 24V
3
ISL6146A
ISL6146B
BIAS Primary bias pin. Connected to an independent voltage supply greater than or equal to 3V and greater than VIN.
Range: 3.0 to 24V
3
ISL6146C
UVLO Programmable UVLO protection to prevent premature turn-on prior to VIN being adequately biased. Range: 0V to 24V
4
ISL6146A
EN Active high enable input to turn on the FET. Internally pulled low to GND through 2M.
Range: 0V to 24V
4
ISL6146B
EN Active low enable input to turn on the FET. Internally pulled high to BIAS through 2M. Range: 0 to 24V
ISL6146
3FN7667.2
July 12, 2012
4
ISL6146C
OVP Programmable OV protection to prevent continued operation when the monitored voltage is too high. A back-to-back FET
configuration must be employed to implement the OVP capability. Range: 0V to 24V
5 GND Chip ground reference.
6FAULT
Open-Drain pull-down fault indicating output with internal on chip filtering (TFLT). The ISL6146 fault detection circuitry pulls
down this pin to GND as it detects a fault or to a disabled input (EN = ‘0’ or EN = ‘1’).
Different types of faults and their detection mechanisms are discussed in more detail on page 16. These faults include:
a. GATE is OFF (GATE < VIN+0.2V) when enabled [this condition is not reported on the ISL6146D and ISL6146E]
b. VIN-VOUT > 0.57V when ON.
c. FET G-D or G-S or D-S shorts.
d. VIN < PORL2H
e. VIN < VOUT
f. Over-Temperature
Range: 0 to VOUT
7 ADJ Resistor programmable VIN - VOUT Voltage Threshold (Vth) of the High Speed Comparator. This pin is either directly connected
to VOUT or can be connected through a 5k to 100k resistor to GND. Allows for adjusting the voltage difference threshold to
prevent unintended turn-off of the pass FET due to normal system voltage fluctuations.
Range: 0.4 to VOUT
8 VOUT The second sensing node for external FET control and connected to the Load side (ORing MOSFET Drain). This is the common
connection point for multiple paralleled supplies. VOUT is compared to VIN to determine when the ORing FET has to be turned
off. Range: 0V to 24V
PAD Thermal
Pad
Connect to GND
Pin Descriptions (Continued)
MSOP/
DFN SYMBOL DESCRIPTION
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6146AFUZ 6146A -40 to +125 8 Ld MSOP M8.118
ISL6146AFRZ 46AF -40 to +125 8 Ld 3x3 DFN L8.3x3J
ISL6146BFUZ 6146B -40 to +125 8 Ld MSOP M8.118
ISL6146BFRZ 46BF -40 to +125 8 Ld 3x3 DFN L8.3x3J
ISL6146CFUZ 6146C -40 to +125 8 Ld MSOP M8.118
ISL6146CFRZ 46CF -40 to +125 8 Ld 3x3 DFN L8.3x3J
ISL6146DFUZ 6146D -40 to +125 8 Ld MSOP M8.118
ISL6146DFRZ 46DF -40 to +125 8 Ld 3x3 DFN L8.3x3J
ISL6146EFUZ 6146E -40 to +125 8 Ld MSOP M8.118
ISL6146EFRZ 46EF -40 to +125 8 Ld 3x3 DFN L8.3x3J
ISL6146AEVAL1Z ISL6146A Evaluation Board
ISL6146BEVAL1Z ISL6146B Evaluation Board
ISL6146CEVAL1Z ISL6146C Evaluation Board
ISL6146DEVAL1Z ISL6146D Evaluation Board
ISL6146EEVAL1Z ISL6146E Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6146. For more information on MSL please see techbrief TB363.
ISL6146
4FN7667.2
July 12, 2012
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-Up Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Typical Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
ISL6146 Evaluation Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Description and Use of the Evaluation Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L8.3x3J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
M8.118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ISL6146
5FN7667.2
July 12, 2012
Absolute Maximum Ratings Thermal Information
BIAS, VIN, VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 40V
EN, EN, UVLO, OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
ADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 250V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
MSOP Package (Notes 4, 7) . . . . . . . . . . . . 140 41
DFN Package (Notes 5, 6) . . . . . . . . . . . . . . 46 5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Bias Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3V to +20V
OR’d Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1V to BIAS
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center
Electrical Specifications VCC = BIAS = 12V, unless otherwise stated. TA= +25°C to +85°C. Boldface limits apply over the operating
temperature range, -40°C to +125°C.
SYMBOL PARAMETERS TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
BIAS
PORL2H POR Rising BIAS Rising, GATE Rising 1.9 2.5 2.95 V
PORHYS POR Hysteresis 189 mV
IBIAS_en_18 ISL6146A/B/D/E BIAS Current BIAS, VIN = 18V, ADJ, VOUT = 16.98V, enabled 3.6 5 mA
IVIN_en_18 ISL6146A/B/D/E VIN Current BIAS, VIN = 18V, ADJ, VOUT = 16.98V, enabled 25 40 µA
IVIN_en_18 ISL6146C VIN Current VIN = 18V, ADJ, VOUT = 16.98V, enabled 3 4.5 mA
IVOUT_en_18 ISL6146A/B/D/E VOUT Current BIAS, VIN = 18V, VOUT = 16.98V, enabled 14 20 µA
VOUT_en_18 ISL6146C VOUT Current VIN = 18V, VOUT = 16.98V, enabled 400 500 µA
IBIAS_den_18 ISL6146A/B/D/E BIAS Current BIAS, VIN = 18V, ADJ, VOUT = 16.98V, disabled 1.7 3 mA
IVIN_den_18 ISL6146A/B/D/E VIN Current BIAS, VIN = 18V, ADJ, VOUT = 16.98V, disabled 27 37 µA
IVIN_den_18 ISL6146C VIN Current VIN = 18V, ADJ, VOUT = 16.98V, disabled 1.3 1.5 mA
IVOUT_den_18 ISL6146A/B/D/E VOUT Current BIAS, VIN = 18V, VOUT = 16.98V, disabled 14 20 µA
IVOUT_den_18 ISL6146C VOUT Current VIN = 18V, VOUT = 16.98V, disabled 385 500 µA
tBIAS2GTE BIAS to GATE Delay BIAS > PORL2H to GATE Rising 150 210 µs
GATE
VGH_3 Charge Pump Voltage VIN, BIAS = 3V VIN - VOUT > VFWD_VR VIN+5V VIN +7V VIN+10.5V V
VGH_12 Charge Pump Voltage VIN, BIAS = 12V VIN - VOUT > VFWD_VR VIN+9V VIN +10V VIN+17.5V V
VGH_18 Charge Pump Voltage VIN, BIAS = 18V VIN - VOUT > VFWD_VR VIN+9V VIN +10V VIN+18V V
VGL Low Voltage Level VIN - VOUT < 0V 0 0.1 V
IPDL Low Pull-Down Current VIN = 12V, VOUT = 12.2V ADJ = 11V 58.4 13 mA
IPDH High Pull-Down Current VIN falling from 12V to 10V in 2µs 3.5 6.5 A
ISL6146
6FN7667.2
July 12, 2012
ttoff Fast Turn-off Time VIN = VBIAS = 12V, VGATE = 18V to 10V,
CGATE = 57nF
65 130 ns
ttoffs Slow Turn-off Time VIN = VBIAS = 12V, VGATE = 18V to 10V,
CGATE = 57nF
58 80 µs
ION Turn-On Current BIAS = 12V, VG = 0V 1 mA
BIAS = 12V, VG = 20V 0.15 mA
VVG_FLTr GATE to VIN Rising Fault Voltage GATE > VIN, enabled, FLT output is high.
(Does not apply to ISL6146D and ISL6146E)
320 440 560 mV
VVG_FLTf GATE to VIN Falling Fault Voltage GATE > VIN, enabled, FLT output is low.
(Does not apply to ISL6146D and ISL6146E)
140 220 300 mV
CONTROL AND REGULATION I/O
VRr Reverse Voltage Detection
Rising VOUT Threshold
VOUT rising 35 57 79 mV
VRf Reverse Voltage Detection
Falling VOUT Threshold
VOUT falling 10 30 51 mV
tRs Reverse Voltage Detection Response
Time
10 µs
VFWD_VR Amplifier Forward Voltage Regulation ISL6146 controls voltage across FET VDS to
VFWD_VR during static forward operation at loads
resulting in Id*rDS(ON) < VFWD_VR
11 19 28 mV
VOS_HS HS Comparator Input Offset Voltage -14 0.7 14 mV
VTH(HS5k) ADJ Adjust Threshold with 5k to GND RADJ = 5k to GND 0.57 0.8 1.1 V
VTH(HS100k) ADJ Adjust Threshold with 100k to GND RADJ = 100k to GND 10 40 95 mV
tHSpd HS Comparator Response Time VOUT > VIN, 1ns transition, 5V differential 170 ns
VFWD_FLT VIN to VOUT Forward Fault Voltage VIN > VOUT, GATE is fully on, FLT output is low 330 450 570 mV
VFWD_FLT_HYS VIN to VOUT Forward Fault Voltage
Hysteresis
VIN > VOUT, GATE is fully on, FLT output is high 44 mV
FAULT OUTPUT
IFLT_SINK FAULT Sink Current BIAS = 18V FAULT = 0.5V, VIN < VOUT, VGATE = VGL 59mA
IFLT_LEAK FAULT Leakage Current FAULT = “VFLT_H”, VIN > VOUT, VGATE = VIN + VGQP 0.04 10 µA
tFLT_L2H FAULT Low to High Delay GATE = VGQP to FAULT output is high 10 23 µs
tFLT_H2L FAULT High to Low Delay GATE = VIN to FAULT output is low 1.7 3µs
ENABLE UVLO/OVP/ADJ INPUTS
VthRa ISL6146A/D EN Rising Vth 580 606 631 mV
VthR_hysa ISL6146A/D EN Vth Hysteresis -90 mV
VthFb ISL6146B/E EN Falling Vth 580 606 631 mV
VthF_hysb ISL6146B/E EN Vth Hysteresis +90 mV
VthFc ISL6146C OVP Falling Vth 580 606 631 mV
VthF_hysc ISL6146C OVP Vth Hysteresis +90 mV
VthRc ISL6146C UVLO Rising Vth 580 606 631 mV
VthR_hysc ISL6146C UVLO Vth Hysteresis -90 mV
Electrical Specifications VCC = BIAS = 12V, unless otherwise stated. TA= +25°C to +85°C. Boldface limits apply over the operating
temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETERS TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
ISL6146
7FN7667.2
July 12, 2012
tEN2GTER EN/UVLO Rising to GATE Rising Delay 10 12 µs
EN/OVP Falling to GATE Rising Delay 9 12 µs
tEN2GTEF EN/UVLO Falling to GATE Falling Delay 2 4µs
EN/OVP Rising to GATE Falling Delay 2 4µs
Ren_h ENABLE Pull-Down Resistor ISL6146A 2 M
Ren_l ENABLE Pull-Up Resistor ISL6146B 2 M
Vadj ADJ Pin Voltage RADJ 5k to 100k0.4 V
Radj ADJ Pull-Up Resistor Internal ADJ Pull-up Resistor to VOUT 3.85 M
OTS Over-Temperature Sense Fault signals in operation 140 °C
OTSHYS Over-Temperature Sense Hysteresis 20 °C
HTS High Temperature Sense Fault signals upon enabling 125 °C
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications VCC = BIAS = 12V, unless otherwise stated. TA= +25°C to +85°C. Boldface limits apply over the operating
temperature range, -40°C to +125°C. (Continued)
SYMBOL PARAMETERS TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
ISL6146
8FN7667.2
July 12, 2012
Typical Performance Curves
FIGURE 3. ISL6146A/B/D/E BIAS AND ISL6146C VIN CURRENT vs
TEMPERATURE
FIGURE 4. ISL6146A/B/C/D/E VIN AND VOUT CURRENT vs
TEMPERATURE
FIGURE 5. GATE VOLTAGE vs TEMPERATURE FIGURE 6. POR Vth RISING AND FALLING VOLTAGE
FIGURE 7. ISL6146A/D EN Vth vs TEMPERATURE FIGURE 8. ISL6146B/E EN Vth vs TEMPERATURE
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-40 25 85 125
TEMPERATURE (°C)
IBIAS/IVIN CURRENT (mA)
18V DISABLED
12V DISABLED
3V DISABLED
18V ENABLED
12V ENABLED
3V ENABLED
TEMPERATURE (°C)
40
35
30
25
20
15
10 -40 25 85 125
18V DISABLED
12V DISABLED
3V DISABLED
VIN/VOUT CURRENT (mA)
VOUT CURRENT
VIN CURRENT
3V ENABLED
18V ENABLED
12V ENABLED
0
5
10
15
20
25
30
35
-40 25 85 125
TEMPERATURE (°C)
HARD ON GATE VOLTAGE (V)
BIAS = 3V
BIAS = 12V
BIAS = 18V
TEMPERATURE (°C)
VPOR Vth (V)
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
-40 25 85 125
POR Vth FALLING
POR Vth RISING
0.40
0.45
0.50
0.55
0.60
0.65
0.70
-40 25 85 125
TEMPERATURE (°C)
EN Vth (V)
EN ASSERT RISING Vth
EN DEASSERT FALLING Vth
TEMPERATURE (°C)
EN Vth (V)
0.54
0.56
0.58
0.60
0.62
0.64
0.66
0.68
0.70
0.72
0.74
-40 25 85 125
EN DEASSERT RISING Vth
EN ASSERT FALLING Vth
ISL6146
9FN7667.2
July 12, 2012
FIGURE 9. ISL6146C UVLO/OVP Vth vs TEMPERATURE FIGURE 10. GATE TURN-ON CURRENT VIN = 12V
FIGURE 11. GATE HARD TURN-OFF CURRENT FIGURE 12. GATE SLOW TURN-OFF CURRENT
FIGURE 13. INCREASING REVERSE VOLTAGE DETECTION Vth FIGURE 14. REVERSE VOLTAGE RESPONSE TIME
Typical Performance Curves (Continued)
TEMPERATURE (°C)
OVP AND UVLO Vth (mV)
450
500
550
600
650
700
750
-40 25 85 125
UVLO FALLING
UVLO RISING AND OVP FALLING
OVP RISING
TEMPERATURE (°C)
GATE TURN-ON CURRENT (mA)
0.1
0.3
0.5
0.7
0.9
1.1
1.3
-40 25 85 125
VG = 0V
TEMPERATURE (°C)
GATE PULL-DOWN CURRENT (A)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
-4025 85125
TEMPERATURE (°C)
GATE PULL-DOWN CURRENT (mA)
0
1
2
3
4
5
6
7
8
9
10
-40 25 85 125
TEMPERATURE (°C)
REVERSE DETECTION VOLTAGE (mV)
52.0
52.5
53.0
53.5
54.0
54.5
55.0
55.5
56.0
-40 25 85 125
TEMPERATURE (°C)
RESPONSE TIME (µs)
15
20
25
30
35
40
45
-4025 85125
ISL6146
10 FN7667.2
July 12, 2012
FIGURE 15. HIGH SPEED COMPARATOR OFFSET VOLTAGE FIGURE 16. VHIGH SPEED COMPARATOR RESPONSE TIME
FIGURE 17. HS COMPARATOR ADJUSTABLE Vth FIGURE 18. EN/EN/OVP/UVLO Vth DELTA vs BIAS VOLTAGE
NORMALIZED TO BIAS = 12V
FIGURE 19. FORWARD VOLTAGE REGULATION FIGURE 20. VIN TO VOUT FORWARD FAULT VOLTAGE
Typical Performance Curves (Continued)
TEMPERATURE (°C)
OFFSET VOLTAGE (mV)
-3
-2
-1
0
1
2
3
-40 25 85 125
TEMPERATURE (°C)
RESPONSE TIME (ns)
100
120
140
160
180
200
220
240
260
280
300
-40 25 85 125
0
100
200
300
400
500
600
700
800
900
-40 25 85 125
TEMPERATURE (°C)
HS COMP ADJUST VTH (mV)
RADJ TO GND = 5k
RADJ TO GND = 100k
BIAS VOLTAGE (V)
RELATIVE %
0.993
0.994
0.995
0.996
0.997
0.998
0.999
1.000
1.001
1.002
31218
TEMPERATURE (°C)
VIN TO VOUT FWD VOLTAGE REG (mV)
19.0
19.2
19.4
19.6
19.8
20.0
20.2
20.4
20.6
20.8
21.0
-40 25 85 125
TEMPERATURE (°C)
VIN - VOUT FAULT VTH (mV)
420
425
430
435
440
445
450
455
460
465
-40 25 85 125
ISL6146
11 FN7667.2
July 12, 2012
FIGURE 21. ISL6146C SLOW RAMP CONNECT 12V ORing FIGURE 22. ISL6146C SLOW RAMP DISCONNECT 12V ORing
FIGURE 23. ISL6146C HOT SWAP CONNECT 12V ORing FIGURE 24. ISL6146C HOT DISCONNECT 12V ORing
FIGURE 25. ISL6146A/D EN/ISL6146C UVLO TO GATE ON DELAY FIGURE 26. ISL6146A/D EN/ISL6146C UVLO TO GATE OFF DELAY
Typical Performance Curves (Continued)
GATE1 GATE 2
IIN1 IIN2
GATE1
GATE 2
IIN1
IIN2
GATE1 GATE 2
IIN1
IIN2
GATE1
GATE 2
IIN1
IIN2
GATE
EN/UVLO
EN/UVLO
GATE
ISL6146
12 FN7667.2
July 12, 2012
FIGURE 27. ISL6146B/E EN TO GATE ON DELAY FIGURE 28. ISL6146B/E EN TO GATE OFF DELAY
FIGURE 29. ISL6146C OVP TO GATE ON DELAY FIGURE 30. ISL6146C OVP TO GATE OFF DELAY
FIGURE 31. ISL6146C RISING VIN, UVLO AND OVP FUNCTION FIGURE 32. ISL6146C FALLING, VIN OVP AND UVLO FUNCTION
Typical Performance Curves (Continued)
EN
GATE
EN
GATE
OVP GATE
OVP GATE
GATE
VIN
VIN RISING THROUGH BOTH THE PROGRAMMED UVLO
AND OVP LEVELS. GATE TURNS-ON AS VIN EXCEEDS 10V
THEN TURNS-OFF AS VIN EX C E ED S 15V
GATE VIN
VIN FALLING THROUGH BOTH THE PROGRAMMED OVP
AND UVLO LEVELS. GATE TURNS-ON AS VIN > 13V THEN
TURNS-OFF AS VIN > 8.3V
ISL6146
13 FN7667.2
July 12, 2012
FIGURE 33. BACK-TO-BACK FET TURN_ON DETAIL FIGURE 34. ISL6146 RISING POR Vth
FIGURE 35. FAST GATE TURN-OFF WITH 57nF GATE FIGURE 36. RESPONSE TO VIN SHORTED TO GND WITH ADJ
SHORTED TO VOUT
FIGURE 37. RESPONSE TO VIN SHORTED TO GND WITH
ADJ 5kΩ TO GND
FIGURE 38. RESPONSE TO VIN SHORTED TO GND WITH
ADJ 100kΩ TO GND
Typical Performance Curves (Continued)
GATE
VIN
VOUT
GATE
VIN
VOUT
VIN
GATE
VIN RISING TO <2.5V WHEN
GATE BECOMES ACTIVE
GATE FAST OFF, ~200ns FALL TIME
~70ns FROM 20V TO 12.6V ACROSS 57nF
GATE OUTPUT SINKING ~ 6A
VOUT
GATE1
VIN1 SHORTED
TO GND
GATE2
HIGH SPEED COMPARATOR Vth = VOS(HS)
VOUT
GATE1
VIN1 SHORTED
TO GND
GATE2
HIGH SPEED COMPARATOR Vth = 800mV
VOUT
GATE1
VIN1 SHORTED
TO GND
GATE2
HIGH SPEED COMPARATOR Vth = 40mV
ISL6146
14 FN7667.2
July 12, 2012
FIGURE 39. VIN HOT SWAPPED TO GATE WITH BIAS = 12V NO LOAD FIGURE 40. FAULT ASSERTING VIN TO VOUT > VFWD_FLT
FIGURE 41. HIGH SPEED COMPARATOR OFFSET VOLTAGE
DISTRIBUTION
FIGURE 42. FOWARD REGULATION VOTLAGE DISTRIBUTION
FIGURE 43. REVERSE DETECTION RISING VOLTAGE DISTRIBUTION FIGURE 44. FAST RAMP REVERSE PROTECTION TIMING DIAGRAM
Typical Performance Curves (Continued)
VIN
GATE
VIN - VOUT
FLT
VIN
VOUT
HS COMP ADJUST VTH (mV)
% OF DISTRIBUTION
0
5
10
15
20
25
30
35
-101234567
0
5
10
15
20
25
30
35
40
17 18 19 20 21 22
% OF DISTRIBUTION
VFWD_VR (mV)
0
5
10
15
20
25
30
35
40
50 52 54 56 58 60 62 64 66 68
VRr (mV)
% OF DISTRIBUTION
VDS0V
+
VR
20V
12.6V
VGATE
tHSpd
tOFF
VBIAS = VIN = 12V
ISL6146
15 FN7667.2
July 12, 2012
FIGURE 45. ISL6146A FLT RESPONSE TO NON-CONDUCTION FIGURE 46. ISL6146D FLT RESPONSE TO NON-CONDUCTION
Typical Performance Curves (Continued)
FLT
GATE
VIN
VIN
GATE
FLT
ISL6146
16 FN7667.2
July 12, 2012
Functional Description
Functional Overview
In a redundant power distribution system, similar potential and
parallel power supplies each contribute to the load current
through various active and passive current sharing schemes.
Typically ORing power diodes are used to protect against reverse
current flow in the event that one of the power supplies falls
below the common bus voltage or develops a catastrophic
failure. However, using a discrete ORing diode solution has some
significant drawbacks. The primary downside is the increased
power dissipation loss in the ORing diodes as system power
requirements increase. At the lowest voltages where the ISL6146
is designed for use, the voltage distribution losses across an
ORing diode can be a significant percentage, in some cases
approaching 70%. Another disadvantage when using an ORing
diode is failure to detect a shorted or opened current path, which
jeopardizes system power availability and reliability. An open
diode may reduce the system to a single point of failure while a
shorted diode eliminates the system’s power protection.
Using an active ORing FET controller, such as the ISL6146, helps
with these potential issues. The use of a low on-resistance FET as
the ORing component allows for a more efficient system design
as the voltage across the FET is much lower than that across a
forward biased diode. Additionally, the ISL6146 has a dedicated
fault (FAULT) output pin that indicates when there is a conditional
or FET fault short providing the diagnostic capability that a diode
is unable to.
The ISL6146 is designed to OR together voltages as low as 1V
when supplied with a separate bias supply of 3V or greater.
Otherwise, the ISL6146 is designed to be biased from and OR
voltages across the 3V to 20V nominal supply range.
In a single FET configuration as voltage is first applied to a VIN
pin, the FET body diode conducts providing all the ISL6146s
connected on a common bus circuit, bias via the VOUT pins. As
individual power supply voltages ramp up in excess of the rising
POR threshold, the ISL6146’s internal charge pump activates to
provide a floating gate drive voltage for the external N-channel
ORing MOSFET, thus turning the FETs on once VIN > VOUT. The
ISL6146 continuously monitors the drain and source of the
ORing FET and provides a reverse voltage (N-channel MOSFET
VOUT - VIN) detection threshold (VR) that, when exceeded,
indicates a reverse current condition. Once this threshold is
exceeded, the ISL6146 turns off the ORing FET by pulling down
the GATE pin to GND. The ISL6146 also provides high speed VOUT
> VIN transient protection as in the case of a catastrophic VIN
failure. The ISL6146 additionally provides for adjustment of the
VIN - VOUT reverse voltage Vth(VR Vth) via the ADJ pin of the
ISL6146 with an external resistor to GND. This allows adjusting
the VIN - VOUT voltage threshold level to compensate for normal
system voltage fluctuations, thus eliminating unnecessary
reaction by the ISL6146.
The total VIN - VOUT VR Vth is the sum of both the internal offset
and the external programmed VR Vth.
In the event of a VOUT > VIN condition, the ISL6146 responds
either with a high or low current pull-down on the GATE pin
depending on whether the High Speed comparator (HSCOMP)
has been activated or not. The HSCOMP determines if the VR
occurred within 1s, by continuously monitoring the FET VDS and
if so, the high pull-down current is used to turn off the ORing FET.
In the event of a falling VIN transition in <1s, (i.e., a catastrophic
failure of the power source) the HSCOMP protects the common
bus from the individual faulted power supply short by turning off
the shorted supply’s ORing MOSFET in less than 300ns, ensuring
the integrity of the common bus voltage from reverse current to
the damaged supply.
Once the correct VIN > VOUT relationship is established again, the
ISL6146 again turns on the FET.
The FAULT pin is an open drain, active low output indicating that
a fault or specific condition has occurred, these include:
• GATE is OFF (GATE < VIN+0.2V). Lack of conduction, not a fault,
just not on. ISL6146D and ISL6146E do not respond to this
condition
• Faults resulting in VIN - VOUT > 0.57V when ON
• An open FET resulting in body diode conduction
• Excessive current through FET
• FET Faults monitored and reported include
- G-D, gate unable to drive to Q-pump voltage
- G-S, gate unable to drive to Q-pump voltage
- D-S shorts, when GATE is OFF VDS < 2V
-V
IN < POR
- Missing VIN
-V
IN shorted to GND
On the ISL6146C version, a conditional fault is also signalled if
the VIN is not within the programmed UVLO and OVP levels.
The ISL6146 has an on-chip over-temperature fault threshold of
~+140°C with a 20°C hysteresis. Although the ISL6146 itself
produces little heat, it senses the environment in which it is,
likely including a close by FET.
The ISL6146A/D and ISL6146B/E are functional variants with an
enabling input of either polarity. This feature is used when the
need to interrupt the current path via signaling is necessary. This
is accomplished by implementing two FETs in series so that there
is a body diode positioned to block current in either direction.
This functionality is considered an additional enhancement to
the ORing diode it replaces.
The ISL6146C employs the use of a programmable Undervoltage
Lock Out (UVLO) and a programmable Overvoltage Protection
(OVP) input. This allows the GATE to only turn-on when the
monitored voltage is between the programmed lower and upper
levels. This application would use the back-to-back FET
configuration. In the event that the current path does not need to
be interrupted then the EN, UVLO and OVP inputs can all be
overridden.
The ISL6146D and ISL6146E are variants of the ISL6146A and
ISL6146B respectively, the difference being the former do not
respond to a nonconduction condition (when enabled and VIN >
VOUT, the GATE is not on) unlike the latter that do signal a fault.
ISL6146
17 FN7667.2
July 12, 2012
Applications Information
Power-Up Considerations
BIAS AND VIN CONSTRAINTS
Upon power-up when the VIN supply is separate from the BIAS
supply, the BIAS voltage must be greater or equal to the VIN
voltage at all times.
When using a single supply for both the ISL6146 bias and the
ORing supply, the VIN and BIAS pins can be configured with a low
value resistor between the two pins to provide some isolation and
decoupling to support the chip bias even as the OR’d supply
experiences voltage droops and surges. Although not necessary
to do so, it is a best design practice for particularly noisy
environments.
FET TO IC LAYOUT RECOMMENDATIONS
Connections from the FET(s) to the ISL6146 VIN and VOUT pins
must be Kelvin in nature and as close to the FET drain and source
PCB pads as possible to eliminate any trace resistance errors
that can occur with high currents. This connection placement is
most critical to providing the most accurate voltage sensing
particularly when the back-to-back FET configuration is used.
Likewise, connections from OVP, UVLO and ADJ are also critical to
optimize accuracy.
ADJUSTING THE HS COMPARATOR REVERSE VOLTAGE
THRESHOLD
The ISL6146 allows adjustment of the HS Comparator reverse
voltage detection threshold (VR Vth), the difference in VOUT - VIN.
There are two valid ADJ pin configurations:
1. ADJ connected to VOUT: This makes the HS comparator
threshold equal to the intrinsic error in the HS comparator
input. This is the default condition and the most likely used
configuration.
2. A single resistor is connected from ADJ pin to ground:
Making the HS comparator threshold = VOUT - 4k/RADJ.
So, for a 100k REXT, HS Comparator threshold = 40mV below
VOUT and for a 5k REXT HS comparator threshold = ~ 800mV
below VOUT.
The recommended resistor range is 5k to 100k for this
voltage adjustment.
At power-up, the HS comparator threshold is default set to the
internal device error first, and then released to the user
programmed threshold after the related circuits are ready. It
takes ~20s for the circuit to switch from the default setting to
the user programmed threshold after a POR startup.
The current out of the ADJ pin with a resistor to GND is equal to
0.4V/REXT.
BACK-TO-BACK FET CONFIGURATION
When using the back-to-back FET configuration, the FET choice
must be such that the voltage across both FETs at full current
loading be less than the minimum forward voltage fault
threshold of 400mV to avoid unintended fault notification.
In this configuration, it may be tempting to use the enable inputs
to force a path by switching between the two as opposed to
having both paths on, and having the higher voltage source
provide current. The problem with that is the timing of the FETs
on and off, so that excessive VOUT voltage droop is not introduced
if the turn-off happens faster, or before the (or a slower) turn-on
momentarily leaves the load with an inadequate power
connection.
Typical Applications Circuits
There are four basic configurations that the ISL6146 can be
used in:
1. For voltages >3V where the BIAS and VIN are common
2. For a very low ORing voltage, <3V operation, BIAS >3V
3. For a voltage window compliant operation and,
4. For a signaled operation where the current path is controlled
by an input signal or minimum voltage condition.
Each of these configurations can be tailored for the High Speed
Comparator (HS COMP) reverse threshold via the ADJ input being
connected either to VOUT or to GND via a resistor as previously
explained. Additionally, the voltage window is adjustable for both
a minimum and maximum operating voltage via the UVLO and
OVP inputs and a resistor divider also explained earlier. Also,
soft-start and turn-on and turn-off characteristics can be tailored
to suit.
The three evaluation platforms provided demonstrate the four
basic configurations and provide for the additional tailoring of
the various performance characteristics.
VIN GATE VOUT
GND
ADJ
VER Y LOW
+
-
+C
O
M
M
O
N
P
O
W
E
R
B
U
S
Q1
VIN GATE VOUT
GND
ADJ
+
-
+C
O
M
M
O
N
P
O
W
E
R
B
U
S
ISL6146A
ISL6146A
FLT
FLT
BIAS
BIAS
DC - DC
VOLTAGE
BIAS
VOLTAGE
>3V
EN
EN
(1V-3V)
Q2
FIGURE 47. LOW VOLTAGE APPLICATION DIAGRAM
VER Y LOW
DC - DC
VOLTAGE
(1V-3V)
ISL6146
18 FN7667.2
July 12, 2012
The Figure 1 circuit shown on page 1 is the basic circuit used for
ORing voltages >3V to 20V.
The ISL6146A application shown in Figure 47 is the configuration
for ORing very low voltages of 1V to 3V. Additionally, this
application shows the utilization of the ADJ input with a single
resistor tied to GND. This provides the user a programmable level
of VOUT > VIN before the High Speed (HS) Comparator is activated
and the GATE output is pulled down to allow for normal voltage
fluctuations in the system.
Notice that in both of these circuits, the EN or EN inputs are
defaulted to enabled and have no current path on/off control.
Failure to do so correctly will result in only body diode conduction
and a resulting fault indication.
The VIN and VOUT to FET and GND to ADJ connections are drawn
to emphasize the Kelvin connection necessary to correctly
monitor the voltage across the FET, and for the VR Vth monitor to
eliminate any stray resistance effects.
The ISL6146C application shown in Figure 48 is limited to the 3V
to 20V VIN range and must implement the back-to-back FET
configuration to utilize the UVLO and OVP inputs and capabilities.
As the VIN voltage rises above the minimum programmed
voltage, the related ORing FETs will turn on and stay on until
either the minimum voltage requirement is no longer met or the
VIN voltage exceeds its programmed maximum. The minimum
and maximum programmed voltage levels are done with the
resistor divider on the UVLO and OVP pins. These levels should be
programmed to take into account conduction path losses to the
load in addition to the IC operational constraints.
When using the back-to-back FET configuration, the user must
chose FETs to ensure (2rDS(ON) + PCB IR) ILOAD <0.5V to avoid
tripping the VIN - VOUT > 0.5V when ON fault.
The application diagram in Figure 49 shows the ISL6146A or
ISL6146B utilizing the EN or EN pin as a signalled input to open
or close the conduction path from power supply to load. This
feature can be implemented on ORing 1V to 20V but is shown for
ORing <3V.
The enable input signaling can be simultaneous across the N+1
number of ISL6146s used.
Although not needed for thermal relief, connect the DFN EPAD
to GND.
SWITCH-OVER CIRCUITS
Switch over applications are different than ORing applications in
that, the former are looking for the presence of or a condition of
a preferred supply in order to switch to it. Whereas true ORing
consists of a redundant N+1 configuration with no preferred
source.
The following 2 circuits are simple single ISL6146 switchover
circuits optimized for situations particular to the VBATT and VEXT
voltages relative to each other. Figure 50 shows an ISL6146B
switchover circuit where VEXT, when present, is the preferred
source and VBATT could be lesser or greater than VEXT. This circuit
senses the presence of the preferred voltage supply to a
programmable threshold level that when exceeded, VEXT is
passed to the output as VBATT is disconnected from the output.
R1 & R2 program the VEXT level that must be preset for the
preferred voltage to be passed to the output.
Q3 is necessary if VBATT can ever exceed VEXT to prevent current
from flowing into VEXT when present. The body diode of Q3
prevents that when Q1 is on regardless of the VBATT voltage.
Q2
Q1
GND
+
-
+
C
O
M
M
O
N
P
O
W
E
R
B
U
S
+
-
+
C
O
M
M
O
N
P
O
W
E
R
B
U
S
VOLTAGE
DC - DC
VOLTAGE
DC - DC
3V-20V
3V-20V
VOUT
ADJ
ISL6146C FLT
UVLO
OVP
VIN GATE
Q4
Q3
GND
VIN GATE VOUT
ADJ
ISL6146C FLT
UVLO
OVP
FIGURE 48. TYPICAL ISL6146C APPLICATION DIAGRAM
Q2
Q1
GND
+
-
+
C
O
M
M
O
N
P
O
W
E
R
B
U
S
+
-
+
C
O
M
M
O
N
P
O
W
E
R
B
U
S
DC - DC
VOLTAGE
(1V-BIAS)
VOUT
ADJ
ISL6146A/B FLT
BIAS
VIN GATE
Q4
Q3
GND
VIN GATE VOUT
ADJ
ISL6146A/B FLT
BIAS
VERY LOW
DC - DC
VOLTAGE
(1V-BIAS)
VERY LOW
EN/EN ENABLED
SIGNALED
WHEN
DISTRIBUTED
VOLTAGE
>3V
EN/EN ENABLED
SIGNALED
WHEN
FIGURE 49. CONTROLLED ON/OFF APPLICATION DIAGRAM
ISL6146
19 FN7667.2
July 12, 2012
The ISL6146 bias is pulled from the common drain node to
ensure an always adequate bias from either source when the
other is absent
Figure 51 shows operational scope shots of the above circuit.
All of the scope shots were taken with a 5A load and 100µF of
bulk load capacitance.
Figure 52 is a ISL6146A switchover circuit to use where the
preferred VEXT source is always greater than the VBATT. Because
this is so, there is no need for a 3rd FET for blocking as in
Figure 50. Additionally, the preferred VEXT source when present
or at a programmed minimum threshold voltage via R1 and R2
divider will turn on Q2/turn-off Q1 but when absent or not
minimally adequate, will do the opposite. In this circuit, with the
ISL6146A not connected to the battery, and thus no constant IVIN
load on it, which allows for longer battery life.
Bias voltage is pulled from the common output to ensure an
always adequate IC bias from either source.
FIGURE 50. ISL6146B EXTERNAL SWITCHOVER SCHEMATIC
FIGURE 51. EXTERNAL SUPPLY < BATT SUPPLY CONNECTED
FIGURE 52. EXTERNAL SUPPLY < BATT SUPPLY DISCONNECTED
VIN GATE VOUT
GND
ADJ
ISL6146B
FLT
BIAS
EN
Q2
Q1
SWITCHED
OUTPUT
VEXT
3.3V - 24V
VBATT
3.3V-20V
Q3
R1
R2
R3
Use when VBATT > VEXT
Q3 disconnects VBATT from
output when GATE is off.
BATT SUPPLY
EXT SUPPLY
VOUT
GATE
BATT SUPPLY
EXT SUPPLY
VOUT
GATE
FIGURE 53. ISL6146A EXTERNAL SWITCHOVER SCHEMATIC
FIGURE 54. EXTERNAL SUPPLY > BATT SUPPLY CONNECTED
VIN GATE VOUT
GND
ADJ
ISL6146A
FLT
BIAS
EN
Q2
Q1
SWITCHED
OUTPUT
VBATT
VEXT
R1
R2
Use when VBATT < VEXT
BATT SUPPLY
EXT SUPPLY VOUT
GATE
ISL6146
20 FN7667.2
July 12, 2012
ISL6146 Evaluation Platforms
Description and Use of the Evaluation Boards
The three ISL6146 evaluation boards are used to demonstrate
the four application configurations discussed earlier. All the
boards have ADJ shorted to VOUT with the PCB layout having the
component footprints to insert a resistor of choice between ADJ
and GND to adjust the HS COMP Vth. Likewise, the VIN is
connected to BIAS but these can be separated to provide an
adequate BIAS voltage when ORing <3V supplies or if providing a
separate from VIN voltage to BIAS.
The ISL6146AEVAL1Z, ISL6146DEVAL1Z are configured to have
a 8.5V minimum turn-on threshold with a 1.2V hysteresis.
The ISL6146BEVAL1Z, ISL6146EEVAL1Z are configured as a
minimally featured maximum performance ORing FET controller
for 3V to 20V.
The ISL6146CEVAL1Z is configured to operate with a 10.8V lower
turn on threshold and 14.9V upper turn-off threshold.
All five boards are equipped with 50A capable FETs for high
current evaluations and with a minimum of VIN and VOUT bulk
capacitance likely to be found in any power system design.
After determining the BIAS source along with VIN voltage criteria
and configuring the evaluation board if necessary, for the
application to be evaluated the board is ready for power.
Apply the BIAS voltage first (via the test points labeled BIAS), if
separate from VIN, then the VIN voltage. Monitor the provided
test points for device performance with current loads up to 50A.
Figures 56 through 61 illustrate the three ISL6146 evaluation
boards for the three typical applications in photograph and
schematic form.
FIGURE 55. EXTERNAL SUPPLY > BATT SUPPLY DISCONNECTED
BATT SUPPLY EXT SUPPLY
VOUT
GATE
FIGURE 56. ISL6146AEVAL1Z,
ISL6146DEVAL1Z PHOTOGRAPH FIGURE 57. ISL6146AEVAL1Z, ISL6146DEVAL1Z SCHEMATIC
ISL6146
21 FN7667.2
July 12, 2012
FIGURE 58. ISL6146BEVAL1Z,
ISL6146EEVAL1Z PHOTOGRAPH FIGURE 59. ISL6146BEVAL1Z, ISL6146EEVAL1Z SCHEMATIC
FIGURE 60. ISL6146CEVAL1Z PHOTOGRAPH FIGURE 61. ISL6146CEVAL1Z SCHEMATIC (UVLO AND OVP TEST POINT LABELS ARE SWAPPED)
ISL6146
22 FN7667.2
July 12, 2012
TABLE 2. ISL6146xEVALZ BOM
REFERENCE DESIGNATOR VALUE DESCRIPTION MANUFACTURER PART NUMBER
ISL6146AEVAL1Z
U1, U2 ISL6146A ORing FET Controller Intersil ISL6146AFUZ
Q1, Q2, Q11, Q12 30V, 50A FET Various
R1, 11 66.5kRES, SMD, 0603, 1% Generic
R2, R12, R6, R16 4.99kRES, SMD, 0603, 1% Generic
R3, R13 10RES, SMD, 0603, 1% Generic
R4, R14 0RES, SMD, 0603, 1% Generic
R5, R15 DNP RES, SMD, 0603, 1% Generic
R7, R17 10kRES, SMD, 0603, 1% Generic
C1, C11, C5 C15 100µF Alum. Elect SMD Cap Generic
C2, C3, C12 C13 1µF CAP, SMD, 0603, 50V, 10% Generic
C4, C14 DNP CAP, SMD, 0603, 50V, 10% Generic
TPx Test Point Generic
Jx Banana Jack Generic
ISL6146BEVAL1Z
U1, U2 ISL6146B ORing FET Controller Intersil ISL6146BFUZ
Q1, Q11 30V, 50A FET Various
R4, R14 4.99kRES, SMD, 0603, 1% Generic
R1, R10 10RES, SMD, 0603, 1% Generic
R2, R12 0RES, SMD, 0603, 1% Generic
R3, R13 DNP RES, SMD, 0603, 1% Generic
R5, R15 10kRES, SMD, 0603, 1% Generic
C1, C11, C5 C15 100µF ALum. Elect SMD Cap Generic
C2, C3, C12 C13 1µF CAP, SMD, 0603, 50V, 10% Generic
C4, C14 DNP CAP, SMD, 0603, 50V, 10% Generic
TPx Test Point Generic
Jx Banana Jack Generic
ISL6146CEVAL1Z
U1, U2 ISL6146C ORing FET Controller Intersil ISL6146CFUZ
Q1, Q2, Q11, Q12 30V, 50A FET Various
R1, 11 93.1kRES, SMD, 0603, 1% Generic
R2, R12 1.4kRES, SMD, 0603, 1% Generic
R3, R13 4.53kRES, SMD, 0603, 1% Generic
R4, R14 0RES, SMD, 0603, 1% Generic
R5, R15 DNP RES, SMD, 0603, 1% Generic
R6, R16 4.99kRES, SMD, 0603, 1% Generic
R7, R17 10kRES, SMD, 0603, 1% Generic
C1, C11, C3 C13 100µF ALum. Elect SMD Cap Generic
C2, C12 1µF CAP, SMD, 0603, 50V, 10% Generic
TPx Test Point Generic
Jx Banana Jack Generic
ISL6146DEVAL1Z
U1, U2 ISL6146D ORing FET Controller Intersil ISL6146DFUZ
Q1, Q2, Q11, Q12 30V, 50A FET Various
ISL6146
23 FN7667.2
July 12, 2012
R1, 11 66.5kRES, SMD, 0603, 1% Generic
R2, R12, R6, R16 4.99kRES, SMD, 0603, 1% Generic
R3, R13 10RES, SMD, 0603, 1% Generic
R4, R14 0RES, SMD, 0603, 1% Generic
R5, R15 DNP RES, SMD, 0603, 1% Generic
R7, R17 10kRES, SMD, 0603, 1% Generic
C1, C11, C5 C15 100µF Alum. Elect SMD Cap Generic
C2, C3, C12 C13 1µF CAP, SMD, 0603, 50V, 10% Generic
C4, C14 DNP CAP, SMD, 0603, 50V, 10% Generic
TPx Test Point Generic
Jx Banana Jack Generic
ISL6146EEVAL1Z
U1, U2 ISL6146E ORing FET Controller Intersil ISL6146EFUZ
Q1, Q11 30V, 50A FET Various
R4, R14 4.99kRES, SMD, 0603, 1% Generic
R1, R10 10RES, SMD, 0603, 1% Generic
R2, R12 0RES, SMD, 0603, 1% Generic
R3, R13 DNP RES, SMD, 0603, 1% Generic
R5, R15 10kRES, SMD, 0603, 1% Generic
C1, C11, C5 C15 100µF ALum. Elect SMD Cap Generic
C2, C3, C12 C13 1µF CAP, SMD, 0603, 50V, 10% Generic
C4, C14 DNP CAP, SMD, 0603, 50V, 10% Generic
TPx Test Point Generic
Jx Banana Jack Generic
TABLE 2. ISL6146xEVALZ BOM (Continued)
REFERENCE DESIGNATOR VALUE DESCRIPTION MANUFACTURER PART NUMBER
ISL6146
24
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7667.2
July 12, 2012
For additional products, see www.intersil.com/product_tree
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL6146
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE REVISION CHANGE
June 18, 2012 FN7667.2 Added ISL6146D and ISL6146E. References to these products added throughout the datasheet. Added Figures
45 & 46 to illustrate the fault differences between ISL6146A/B and ISL6146D/E. Moved Figure 50 and revised
the related text on page 19 before the evaluation board section. Added Figures 51 - 55 and related text on
page 19 to page 20.
February 27, 2012 FN7667.1 Removed note “MSOP packaged parts to be released soon” from “Ordering Information” on page 3. Added
FIgures 42 & 43 on page 14.
December 16, 2011 FN7667.0 Initial Release
ISL6146
25 FN7667.2
July 12, 2012
Package Outline Drawing
L8.3x3J
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0 9/09
located within the zone indicated. The pin #1 identifier may be
Unless otherwise spec ifie d, tolera nc e : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
C0 . 2 REF
0 . 05 MAX.
0 . 00 MIN.
5
3.00 AB
3.00
(4X) 0.15
6
PIN 1
INDEX AREA PIN #1 INDEX AREA
6X 0.65
1.64 +0.10/ - 0.15
8
1
8X 0.400 ± 0.10
6
Max 1.00
SEE DETAIL "X"
0.08
0.10
C
C
C
( 2.80 )
(1.64)
( 8 X 0.30)
( 8X 0.60)
( 2.38 )
( 1.95)
2.38 0.10
8X 0.30 AMC B
4
2X 1.950
+0.10/ - 0.15
(6x 0.65)
4
5
PIN 1
ISL6146
26 FN7667.2
July 12, 2012
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
DETAIL "X"
SIDE VIEW 2
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
PIN# 1 ID
0.25 - 0.36
DETAIL "X"
0.10 ± 0.05
(4.40)
(3.00)
(5.80)
H
C
1.10 MAX
0.09 - 0.20
3°±3°
GAUGE
PLANE 0.25
0.95 REF
0.55 ± 0.15
B
0.08 C A-B D
3.0±0.05
12
8
0.85±010
SEATING PLANE
A
0.65 BSC
3.0±0.05 4.9±0.15
(0.40)
(1.40)
(0.65)
D
5
5
SIDE VIEW 1
Dimensioning and tolerancing conform to JEDEC MO-187-AA
Plastic interlead protrusions of 0.15mm max per side are not
Dimensions in ( ) are for reference only.
Dimensions are measured at Datum Plane "H".
Plastic or metal protrusions of 0.15mm max per side are not
Dimensions are in millimeters.
3.
4.
5.
6.
NOTES:
1.
2. and AMSEY14.5m-1994.
included.
included.
0.10C
M
