LTC6994-1/LTC6994-2
1
699412fb
Typical applicaTion
FeaTures DescripTion
TimerBlox: Delay Block/
Debouncer
The LT C
®
6994 is a programmable delay block with a
range of 1µs to 33.6 seconds. The LTC6994 is part of
the TimerBlox
®
family of versatile silicon timing devices.
A single resistor, RSET
, programs an internal master os-
cillator frequency, setting the LTC6994’s time base. The
input-to-output delay is determined by this master oscil-
lator and an internal clock divider, NDIV
, programmable
to eight settings from 1 to 221:
tDELAY =
N
DIV
•R
SET
50k
Ω
•1µs, NDIV = 1, 8, 64,...,221
The output (OUT) follows the input (IN) after delaying
the rising and/or falling transitions. The LTC6994-1 will
delay the rising or falling edge. The LTC6994-2 will delay
both transitions, and adds the option to invert the output.
DEVICE DELAY FUNCTION
LTC6994-1 or
LTC6994-2 or
The LTC6994 also offers the ability to dynamically adjust
the delay time via a separate control voltage.
For easy configuration of the LTC6994, download the
TimerBlox Designer tool at www.linear.com/timerblox.
Noise Discriminator
applicaTions
n Delay Range: 1µs to 33.6 Seconds
n Configured with 1 to 3 Resistors
n Delay Max Error:
– <2.3% for Delay > 512µs
– <3.4% for Delay of 8µs to 512µs
– <5.1% for Delay of 1µs to 8µs
n Delay One or Both Rising/Falling Edges
n 2.25V to 5.5V Single Supply Operation
n 70µA Supply Current at 10µs Delay
n 500µs Start-Up Time
n CMOS Output Driver Sources/Sinks 20mA
n –55°C to 125°C Operating Temperature Range
n Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN
n Noise Discriminators/Pulse Qualifiers
n Delay Matching
n Switch Debouncing
n High Vibration, High Acceleration Environments
n Portable and Battery-Powered Equipment
L, LT , LT C , LT M , Linear Technology, TimerBlox and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
699412 TA01a
LTC6994-2
OUT
V+
DIV
IN
GND
SET
RSET
75k
3.3V
0.1µF
NOISY
INPUT
QUALIFIED
OUTPUT IN
2V/DIV
OUT
2V/DIV
20µs/DIV 699412 TA01b
1.5µs1.5µs
LTC6994-1/LTC6994-2
2
699412fb
absoluTe MaxiMuM raTings
Supply Voltage (V+) to GND ........................................6V
Maximum Voltage on Any Pin
.................................. (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)
Operating Temperature Range (Note 2)
LTC6994C ............................................ –40°C to 85°C
LTC6994I .............................................–40°C to 85°C
LTC6994H .......................................... –40°C to 125°C
LTC6994MP ....................................... –55°C to 125°C
(Note 1)
orDer inForMaTion
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6994CDCB-1#TRMPBF LTC6994CDCB-1#TRPBF LFCT 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC6994IDCB-1#TRMPBF LTC6994IDCB-1#TRPBF LFCT 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC6994HDCB-1#TRMPBF LTC6994HDCB-1#TRPBF LFCT 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LTC6994CDCB-2#TRMPBF LTC6994CDCB-2#TRPBF LFCW 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC6994IDCB-2#TRMPBF LTC6994IDCB-2#TRPBF LFCW 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC6994HDCB-2#TRMPBF LTC6994HDCB-2#TRPBF LFCW 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LTC6994CS6-1#TRMPBF LTC6994CS6-1#TRPBF LTFCV 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6994IS6-1#TRMPBF LTC6994IS6-1#TRPBF LTFCV 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6994HS6-1#TRMPBF LTC6994HS6-1#TRPBF LTFCV 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6994MPS6-1#TRMPBF LTC6994MPS6-1#TRPBF LTFCV 6-Lead Plastic TSOT-23 –55°C to 125°C
LTC6994CS6-2#TRMPBF LTC6994CS6-2#TRPBF LTFCX 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6994IS6-2#TRMPBF LTC6994IS6-2#TRPBF LTFCX 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6994HS6-2#TRMPBF LTC6994HS6-2#TRPBF LTFCX 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6994MPS6-2#TRMPBF LTC6994MPS6-2#TRPBF LTFCX 6-Lead Plastic TSOT-23 –55°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LT C Marketing for parts specified with wider operating temperature ranges.
Consult LT C Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
TOP VIEW
OUT
GND
IN
V+
DIV
SET
DCB PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
4
5
7
6
3
2
1
TJMAX = 150°C, θJA = 64°C/W, θJC = 10.6°C/W
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
IN 1
GND 2
SET 3
6 OUT
5 V+
4 DIV
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W
pin conFiguraTion
Specified Temperature Range (Note 3)
LTC6994C ................................................ 0°C to 70°C
LTC6994I .............................................–40°C to 85°C
LTC6994H .......................................... –40°C to 125°C
LTC6994MP ....................................... –55°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
S6 Package ....................................................... 300°C
LTC6994-1/LTC6994-2
3
699412fb
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDELAY Delay Time 1µ 33.55 sec
∆tDELAY Delay Accuracy (Note 4) NDIV ≥ 512
l
±1.7 ±2.3
±3.0
%
%
8 ≤ NDIV ≤ 64
l
±2.4 ±3.4
±4.4
%
%
NDIV = 1
l
±3.8 ±5.1
±6.2
%
%
∆tDELAY/∆T Delay Drift Over Temperature NDIV ≥ 512
NDIV ≤ 64
l
l
±0.006
±0.008
%/°C
%/°C
Delay Change With Supply NDIV ≥ 512 V+ = 4.5V to 5.5V
V+ = 2.25V to 4.5V
l
l
–0.6
–0.4
–0.2
–0.1
%
%
8 ≤ NDIV ≤ 64 V+ = 4.5V to 5.5V
V+ = 2.7V to 4.5V
V+ = 2.25V to 2.7V
l
l
l
–0.9
–0.7
–1.1
–0.2
–0.2
–0.1
0.4
0.9
%
%
%
Delay Jitter (Note 10) NDIV = 1 V+ = 5.5V
V+ = 2.25V
1.0
0.5
%P-P
%P-P
NDIV = 8 0.20 %P-P
NDIV = 64 0.05 %P-P
NDIV = 512 0.20 %P-P
NDIV = 4096 0.03 %P-P
tSDelay Change Settling Time (Note 9) tMASTER = tDELAY/NDIV 6 • tMASTER µs
Power Supply
V+Operating Supply Voltage Range l2.25 5.5 V
Power-On Reset Voltage l1.95 V
IS(IDLE) Supply Current (Idle) RL = ∞, RSET = 50k, NDIV ≤ 64 V+ = 5.5V
V+ = 2.25V
l
l
165
125
200
160
µA
µA
RL = ∞, RSET = 50k, NDIV ≥ 512 V+ = 5.5V
V+ = 2.25V
l
l
135
105
175
140
µA
µA
RL = ∞, RSET = 800k, NDIV ≤ 64 V+ = 5.5V
V+ = 2.25V
l
l
70
60
110
95
µA
µA
RL = ∞, RSET = 800k, NDIV ≥ 512 V+ = 5.5V
V+ = 2.25V
l
l
65
55
100
90
µA
µA
Analog Inputs
VSET Voltage at SET Pin l0.97 1.00 1.03 V
∆VSET/∆T VSET Drift Over Temperature l±75 µV/°C
RSET Frequency-Setting Resistor l50 800 kΩ
VDIV DIV Pin Voltage l0 V+V
∆VDIV/∆V+DIV Pin Valid Code Range (Note 5) Deviation from Ideal
VDIV/V+ = (DIVCODE + 0.5)/16
l±1.5 %
DIV Pin Input Current l±10 nA
LTC6994-1/LTC6994-2
4
699412fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6994C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6994C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6994C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6994I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6994H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6994MP is
guaranteed to meet specified performance from –55°C to 125°C.
Note 4: Delay accuracy is defined as the deviation from the tDELAY
equation, assuming RSET is used to program the delay.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital I/O
IN Pin Input Capacitance 2.5 pF
IN Pin Input Current IN = 0V to V+±10 nA
VIH High Level IN Pin Input Voltage (Note 6) l0.7 • V+V
VIL Low Level IN Pin Input Voltage (Note 6) l0.3 • V+V
IOUT(MAX) Output Current V+ = 2.7V to 5.5V ±20 mA
VOH High Level Output Voltage (Note 7) V+ = 5.5V IOUT = –1mA
IOUT = –16mA
l
l
5.45
4.84
5.48
5.15
V
V
V+ = 3.3V IOUT = –1mA
IOUT = –10mA
l
l
3.24
2.75
3.27
2.99
V
V
V+ = 2.25V IOUT = –1mA
IOUT = –8mA
l
l
2.17
1.58
2.21
1.88
V
V
VOL Low Level Output Voltage (Note 7) V+ = 5.5V IOUT = 1mA
IOUT = 16mA
l
l
0.02
0.26
0.04
0.54
V
V
V+ = 3.3V IOUT = 1mA
IOUT = 10mA
l
l
0.03
0.22
0.05
0.46
V
V
V+ = 2.25V IOUT = 1mA
IOUT = 8mA
l
l
0.03
0.26
0.07
0.54
V
V
tPD Propagation Delay V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
10
14
24
ns
ns
ns
tWIDTH Minimum Recognized Input Pulse Width V+ = 3.3V 5 ns
trOutput Rise Time (Note 8) V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.1
1.7
2.7
ns
ns
ns
tfOutput Fall Time (Note 8) V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.0
1.6
2.4
ns
ns
ns
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: The IN pin has hysteresis to accommodate slow rising or falling
signals. The threshold voltages are proportional to V+. Typical values can
be estimated at any supply voltage using:
VIN(RISING) ≈ 0.55 • V+ + 185mV and VIN(FALLING) ≈ 0.48 • V+ – 155mV
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
within ±1% of the final delay after a 0.5× or 2× change in ISET
.
Note 10: Jitter is the ratio of the deviation of the programmed delay to the
mean of the delay. This specification is based on characterization and is
not 100% tested.
LTC6994-1/LTC6994-2
5
699412fb
Typical perForMance characTerisTics
Delay Drift vs Temperature
(NDIV ≥ 512)
Delay Drift vs Temperature
(NDIV ≤ 64)
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Delay Drift vs Temperature
(NDIV ≤ 64)
Delay Drift vs Supply Voltage
(NDIV = 1)
Delay Drift vs Supply Voltage
(NDIV = 1)
TEMPERATURE (°C)
–50
DRIFT (%)
0.5
1.0
1.5
25 75
699412 G01
0
–0.5
–25 0 50 100 125
–1.0
–1.5
RSET = 50k
3 PARTS
TEMPERATURE (°C)
–50
DRIFT (%)
0.5
1.0
1.5
25 75
699412 G02
0
–0.5
–25 0 50 100 125
–1.0
–1.5
RSET = 200k
3 PARTS
Delay Drift vs Temperature
(NDIV ≤ 64)
TEMPERATURE (°C)
–50
DRIFT (%)
0.5
1.0
1.5
25 75
699412 G03
0
–0.5
–25 0 50 100 125
–1.0
–1.5
RSET = 800k
3 PARTS
TEMPERATURE (°C)
–50
DRIFT (%)
0.5
1.0
1.5
25 75
699412 G04
0
–0.5
–25 0 50 100 125
–1.0
–1.5
RSET = 50k
3 PARTS
Delay Drift vs Temperature
(NDIV ≥ 512)
TEMPERATURE (°C)
–50
DRIFT (%)
0.5
1.0
1.5
25 75
699412 G05
0
–0.5
–25 0 50 100 125
–1.0
–1.5
RSET = 200k
3 PARTS
Delay Drift vs Temperature
(NDIV ≥ 512)
TEMPERATURE (°C)
–50
DRIFT (%)
0.5
1.0
1.5
25 75
699412 G06
0
–0.5
–25 0 50 100 125
–1.0
–1.5
RSET = 800k
3 PARTS
SUPPLY (V)
2
–1.0
DRIFT (%)
–0.8
–0.4
–0.2
0
1.0
0.4
34
699412 G07
–0.6
0.6
0.8
0.2
56
RSET = 50k
RSET = 200k
RSET = 800k
RISING EDGE DELAY
REFERENCED TO V+ = 4V
SUPPLY (V)
2
–1.0
DRIFT (%)
–0.8
–0.4
–0.2
0
1.0
0.4
34
699412 G08
–0.6
0.6
0.8
0.2
56
RSET = 50k
RSET = 200k
RSET = 800k
FALLING EDGE DELAY
REFERENCED TO V+ = 4V
Delay Drift vs Supply Voltage
(NDIV > 1)
SUPPLY (V)
2
–1.0
DRIFT (%)
–0.8
–0.4
–0.2
0
1.0
0.4
34
699412 G09
–0.6
0.6
0.8
0.2
56
RSET = 50k, NDIV = 8
RSET = 50k TO 800k, NDIV ≥ 512
RSET = 800k, NDIV = 8
REFERENCED TO V+ = 4V
LTC6994-1/LTC6994-2
6
699412fb
VSET Drift vs ISET VSET Drift vs Supply Voltage VSET vs Temperature
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Delay Error vs RSET (NDIV = 1)
Delay Error vs RSET (NDIV =1) Delay Error vs DIVCODE
ISET (µA)
0
–1.0
0
0.4
0.2
0.6
0.8
1.0
10 15 20
–0.4
–0.2
–0.6
–0.8
5
699412 G16
VSET (mV)
REFERENCED TO ISET = 10µA
SUPPLY (V)
2
–1.0
0
0.4
0.2
0.6
0.8
1.0
456
–0.4
–0.2
–0.6
–0.8
3
699412 G17
DRIFT (mV)
REFERENCED TO V+ = 4V
TEMPERATURE (°C)
–50
0.980
1.000
1.010
1.005
1.015
1.020
0 25 50 100 125
0.995
0.990
0.985
–25 75
699412 G18
V
SET
(V)
3 PARTS
RSET (kΩ)
50
–5
ERROR (%)
–3
–1
1
3
100 800400200
699412 G10
5
–4
–2
0
2
4
RISING EDGE DELAY
3 PARTS
Delay Error vs RSET
(8 ≤ NDIV ≤ 64)
RSET (kΩ)
50
–5
ERROR (%)
–3
–1
1
3
100 800400200
699412 G11
–4
–2
0
2
4
3 PARTS
Delay Error vs RSET (NDIV ≥ 512)
RSET (kΩ)
50
–5
–3
–1
1
3
100 800400200
699412 G12
5
–4
–2
0
2
4
3 PARTS
RSET (kΩ)
50
–5
ERROR (%)
–3
–1
1
3
100 800400200
699412 G13
–4
–2
0
2
4
FALLING EDGE DELAY
3 PARTS
DIVCODE
0
ERROR (%)
1
3
2468
699412 G14
–1
–3
0
2
4
5
–2
–4
–5 10 12 14
LTC6994-1
RSET = 50k
3 PARTS
RISING EDGE
DELAY
FALLING EDGE
DELAY
Delay Error vs DIVCODE
DIVCODE
0
ERROR (%)
1
3
2468
699412 G15
–1
–3
0
2
4
5
–2
–4
–5 10 12 14
LTC6994-1
RSET = 800k
3 PARTS
RISING EDGE
DELAY
FALLING EDGE
DELAY
LTC6994-1/LTC6994-2
7
699412fb
Typical perForMance characTerisTics
Typical VSET Distribution
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
VSET (V)
0.98
0
100
50
150
200
250
0.996 1.004 1.012 1.02
0.988
699412 G19
NUMBER OF UNITS
2 LOTS
DFN AND SOT-23
1274 UNITS
Supply Current vs TemperatureSupply Current vs Supply Voltage
Supply Current vs IN Pin Voltage Supply Current vs tDELAY (5V) Supply Current vs tDELAY (2.5V)
tDELAY (ms)
50
POWER SUPPLY CURRENT (µA)
100
150
200
250
0.001 0.1 1 100
699412 G23
0
0.01 10
ACTIVE
IDLE
V+ = 5V
CLOAD = 5pF
RLOAD = ∞
ACTIVE CURRENT MEASURED
USING LTC6994-1 WITH
fIN = 1/(2 • tDELAY)
÷1
÷8
tDELAY (ms)
50
POWER SUPPLY CURRENT (µA)
100
150
200
250
0.001 0.1 1 100
699412 G24
0
0.01 10
ACTIVE
IDLE
V+ = 2.5V
CLOAD = 5pF
RLOAD = ∞
÷1 ÷8
ACTIVE CURRENT MEASURED
USING LTC6994-1 WITH
fIN = 1/(2 • tDELAY)
SUPPLY VOLTAGE (V)
2
0
POWER SUPPLY CURRENT (µA)
50
100
150
200
250
300
3 4 5 6
699412 G20
LTC6994-1
IS(ACTIVE) MEASURED
WITH fIN = 1/(2 • tDELAY)
RSET = 50k,
÷1, ACTIVE
RSET = 100k, ÷8, ACTIVE
RSET = 100k, ÷8, IDLE
RSET = 800k, ÷512
RSET = 50k,
÷1, IDLE
CLOAD = 5pF
RLOAD = ∞
TEMPERATURE (°C)
–50 –25
0
POWER SUPPLY CURRENT (µA)
50
100
150
200
250
0 25 50 75 100 125
699412 G21
RSET = 100k, ÷8, ACTIVE
RSET = 50k, ÷1, ACTIVE
RSET = 100k, ÷8, IDLE
RSET = 50k, ÷1, IDLE
RSET = 800k, ÷512
LTC6994-1
IS(ACTIVE) MEASURED
WITH fIN = 1/(2 • tDELAY)
CLOAD = 5pF
RLOAD = ∞
VIN/V+ (V/V)
0
POWER SUPPLY CURRENT (µA)
150
200
250
0.8
699412 G22
100
50
00.2 0.4 0.6 1.0
5V
IN FALLING
5V
IN RISING
3.3V
IN RISING
3.3V
IN FALLING
CLOAD = 5pF
RLOAD = ∞
Peak-to-Peak Jitter vs tDELAY
IN Threshold Voltage
vs Supply Voltage Typical ISET Current Limit vs V+
SUPPLY VOLTAGE (V)
IN PIN VOLTAGE (V)
699412 G25
3.5
1.0
2.0
3.0
0.5
1.5
2.5
02 43 5 6
POSITIVE GOING
NEGATIVE GOING
tDELAY (ms)
0.4
JITTER (%P-P)
0.8
1.2
0.2
0.6
1.0
0.001 0.1 1 10 100
699412 G26
0
0.01
÷1, 5.5V
÷8, 5.5V
÷1, 2.25V
÷8, 2.25V ÷64
÷512
÷4096
PEAK-TO-PEAK
tDELAY VARIATION
MEASURED OVER
30s INTERVALS
SUPPLY VOLTAGE (V)
ISET (µA)
699412 G27
1000
400
800
200
600
02 43 5 6
SET PIN SHORTED TO GND
LTC6994-1/LTC6994-2
8
699412fb
Output Resistance
vs Supply Voltage
Input Propagation Delay (tPD)
vs Supply Voltage
Rise and Fall Time
vs Supply Voltage
SUPPLY VOLTAGE (V)
RISE/FALL TIME (ns)
699412 G29
3.0
1.5
2.5
1.0
0.5
2.0
02 43 5 6
CLOAD = 5pF
tRISE
tFALL
SUPPLY VOLTAGE (V)
OUTPUT RESISTANCE (Ω)
699412 G30
50
25
20
35
45
5
10
15
30
40
02 43 5 6
OUTPUT SOURCING CURRENT
OUTPUT SINKING CURRENT
SUPPLY VOLTAGE (V)
2
PROPAGATION DELAY (ns)
10
15
6
699412 G28
5
0345
25
20
CLOAD = 5pF
Start-Up, RSET = 800k
(LTC6994-1)
Start-Up, RSET = 50k
(LTC6994-2, POL = 1)
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
V+
2V/DIV
IN
2V/DIV
OUT
2V/DIV
V+ = 2.5V 1ms/DIV 699412 G31
7.2ms V+
2V/DIV
IN
2V/DIV
OUT
2V/DIV
V+ = 2.5V 100µs/DIV 699412 G32
500µs
LTC6994-1/LTC6994-2
9
699412fb
pin FuncTions
(DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup-
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1µF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. The DIV pin voltage (VDIV) is internally converted
into a 4-bit result (DIVCODE). VDIV may be generated by
a resistor divider between V+ and GND. Use 1% resistors
to ensure an accurate result. The DIV pin and resistors
should be shielded from the OUT pin or any other traces
that have fast edges. Limit the capacitance on the DIV pin
to less than 100pF so that VDIV settles quickly. The MSB
of DIVCODE (POL) selects the delay functionality. For the
LTC6994-1, POL = 0 will delay the rising transition and
POL = 1 will delay the falling transition. For the LTC6994-
2, both transitions are delayed so POL = 1 can be used
to invert the output.
SET (Pin 3/Pin 3): Delay Setting Input. The voltage on the
SET pin (VSET) is regulated to 1V above GND. The amount
of current sourced from the SET pin (ISET) programs the
master oscillator frequency. The ISET current range is
1.25µA to 20µA. The delayed output transition will be not
occur if ISET drops below approximately 500nA. Once ISET
increases above 500nA the delayed edge will transition.
A resistor connected between SET and GND is the most
accurate way to set the delay. For best performance, use
a precision metal or thin film resistor of 0.5% or better
tolerance and 50ppm/°C or better temperature coefficient.
For lower accuracy applications an inexpensive 1% thick
film resistor may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
IN (Pin 4/Pin 1): Logic Input. Depending on the version and
POL bit setting, rising or falling edges on IN will propagate
to OUT after a programmable delay. The LTC6994-1 will
delay only the rising or falling edge. The LTC6994-2 will
delay both edges.
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground
plane for best performance.
OUT (Pin 6/Pin 6): Output. The OUT pin swings from
GND to V+ with an output resistance of approximately
30Ω. When driving an LED or other low impedance load
a series output resistor should be used to limit source/
sink current to 20mA.
699412 PF
LTC6994
IN
GND
SET
OUT
V+
DIV
C1
0.1µF
RSET R2
R1
V+
V+
LTC6994-1/LTC6994-2
10
699412fb
block DiagraM
(S6 package pin numbers shown)
699412 BD
PROGRAMMABLE DIVIDER
÷1, 8, 64, 512, 4096,
215, 218, 221
MASTER OSCILLATOR
POR
DIGITAL
FILTER
4-BIT A/D
CONVERTER
POL
R1
R2
DIV
V+
OUT
5
4
IN
1
6
HALT OSCILLATOR
IF ISET < 500nA
MCLK
+
–
ISET
ISET
VSET = 1V
+
–
1V
3 22
GND
SET
RSET
INPUT
BUFFER
tMASTER = •
1µs
50kΩ
VSET
ISET
OUTPUT
POLARITY
(LTC6994-2)
EDGE-
CONTROLLED
DELAY
LOGIC
LTC6994-1/LTC6994-2
11
699412fb
operaTion
The LTC6994 is built around a master oscillator with a 1µs
minimum period. The oscillator is controlled by the SET
pin current (ISET) and voltage (VSET), with a 1µs/50kΩ
conversion factor that is accurate to ±1.7% under typical
conditions.
tMASTER =1µs
50kΩ
•VSET
ISET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the input-to-output
delay. The simplest way to generate ISET is to connect a
resistor (RSET) between SET and GND, such that ISET =
VSET/RSET
. The master oscillator equation reduces to:
tMASTER =1µs •RSET
50kΩ
From this equation, it is clear that VSET drift will not affect
the input-to-output delay when using a single program
resistor (RSET). Error sources are limited to RSET toler-
ance and the inherent accuracy ∆tDELAY of the LTC6994.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25µA and 20µA).
When the input makes a transition that will be delayed
(as determined by the part version and POL bit setting),
the master oscillator is enabled to time the delay. When
the desired duration is reached, the output is allowed to
transition.
The LTC6994 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
512, 4096, 215, 218 or 221. This extends the delay duration
by those same factors. The divider ratio NDIV is set by a
resistor divider attached to the DIV pin.
tDELAY =NDIV
50kΩ
•VSET
ISET
•1µs
With RSET in place of VSET/ISET the equation reduces to:
tDELAY =NDIV •RSET
50kΩ
•1µs
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit A/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6994:
1. DIVCODE determines the frequency divider setting,
NDIV
.
2. The DIVCODE MSB is the POL bit, and configures a
different polarity setting on the two versions.
a. LTC6994-1: POL selects rising or falling-edge delays.
POL = 0 will delay rising-edge transitions. POL = 1
will delay falling-edge transitions.
b. LTC6994-2: POL selects the output inversion.
POL = 1 inverts the output signal.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
699412 F01
LTC6994
V+
DIV
GND
R1
R2
2.25V TO 5.5V
Figure 1. Simple Technique for Setting DIVCODE
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIV and POL values for the recommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects)
2. The driving impedance (R1||R2) does not exceed 500kΩ.
LTC6994-1/LTC6994-2
12
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operaTion
Table 1. DIVCODE Programming
DIVCODE POL NDIV Recommended tDELAY R1 (k) R2 (k) VDIV/V+
0 0 1 1µs to 16µs Open Short ≤ 0.03125 ±0.015
1 0 8 8µs to 128µs 976 102 0.09375 ±0.015
2 0 64 64µs to 1.024ms 976 182 0.15625 ±0.015
3 0 512 512µs to 8.192ms 1000 280 0.21875 ±0.015
4 0 4,096 4.096ms to 65.54ms 1000 392 0.28125 ±0.015
5 0 32,768 32.77ms to 524.3ms 1000 523 0.34375 ±0.015
6 0 262,144 262.1ms to 4.194sec 1000 681 0.40625 ±0.015
7 0 2,097,152 2.097sec to 33.55sec 1000 887 0.46875 ±0.015
8 1 2,097,152 2.097sec to 33.55sec 887 1000 0.53125 ±0.015
9 1 262,144 262.1ms to 4.194sec 681 1000 0.59375 ±0.015
10 1 32,768 32.77ms to 524.3ms 523 1000 0.65625 ±0.015
11 1 4,096 4.096ms to 65.54ms 392 1000 0.71875 ±0.015
12 1 512 512µs to 8.192ms 280 1000 0.78125 ±0.015
13 1 64 64µs to 1.024ms 182 976 0.84375 ±0.015
14 1 8 8µs to 128µs 102 976 0.90625 ±0.015
15 1 1 1µs to 16µs Short Open ≥ 0.96875 ±0.015
Figure 2. Delay Range and POL Bit vs DIVCODE
If the voltage is generated by other means (i.e., the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
VDIV
V+=DIVCODE +0.5
16 ±1.5%
For example, if the supply is 3.3V and the desired DIVCODE
is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing
that NDIV is symmetric around the DIVCODE midpoint.
0.5•V+
t
DELAY
(ms)
699412 F02
1000
10000
100
10
1
0.001
0.1
0.01
INCREASING VDIV
V+
0V
POL BIT = 0
0
1
2
3
4
5
6
7 8
9
10
11
12
13
14
15
POL BIT = 1
LTC6994-1/LTC6994-2
13
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operaTion
Figure 3. Rising-Edge Delayed Timing Diagram (LTC6994-1, POL = 0)
Figure 4. Falling-Edge Delayed Timing Diagram (LTC6994-1, POL = 1)
Edge-Controlled Delay
The LTC6994 is a programmable delay or pulse qualifier.
It can perform noise filtering, which distinguishes it from
a delay line (which simply delays all input transitions).
When the voltage on the LTC6994 input pin (IN) transitions
low or high, the LTC6994 can delay the corresponding
output transition by any time from 1µs to 33.6 seconds.
LTC6994-1 Functionality
Figures 3 details the basic operation of the LTC6994-1 when
configured to delay rising edge transitions (POL = 0). A
rising edge on the IN pin initiates the timing. OUT remains
low for the duration of tDELAY
. If IN stays high then OUT
will transition high after this time. If the input doesn’t
remain high long enough for OUT to transition high then
the timing will restart on each successive rising edge. In
this way, the LTC6994-1 can serve as a pulse qualifier,
filtering out noisy or short signals.
On a falling edge at the input, the output will follow im-
mediately (after a short propagation delay tPD).Note that
the output pulse width may be extremely short if IN falls
immediately after OUT rises.
Figure 4 details the operation of the LTC6994-1 when
configured to delay falling edges (POL = 1).
IN
OUT
tDELAY
tPD tPD
tDELAY tDELAY
tPD
699412 F03
t
WIDTH
tPD
tPD tPD
IN
OUT
tDELAY
tPD
tDELAY
tPD tPD
tPD tPD tPD
t
WIDTH
tDELAY
699412 F04
LTC6994-1/LTC6994-2
14
699412fb
operaTion
LTC6994-2 Functionality
Figures 5 details the basic operation of the LTC6994-2
when configured for noninverting operation (POL = 0). As
before, a rising edge on the IN pin initiates the timing and,
if IN remains high, OUT will transition high after tDELAY
.
Unlike the LTC6994-1, falling edges are delayed in the same
way. When IN transitions low, OUT will follow after tDELAY
.
If the input doesn’t remain high or low long enough for
OUT to follow, the timing will restart on the next transition.
Also unlike the LTC6994-1, the output pulse width can
never be less than tDELAY
. Therefore, the LTC6994-2 can
generate pulses with a defined minimum width.
Figure 6 details the operation of the LTC6994-2 when the
output is inverted (POL = 1).
Figure 5. Both Edges Delayed Timing Diagram (LTC6994-2, POL = 0)
Figure 6. Both Edges Delayed (Inverting) Timing Diagram (LTC6994-2, POL = 1)
IN
OUT
tDELAY
tPD
tPD
tPD
t
WIDTH
tPD
tDELAY
tPD
tDELAY tDELAY
699412 F05
IN
OUT
tDELAY
tPD
tPD tPD tPD tPD
t
WIDTH
tDELAY tDELAY tDELAY
699412 F06
LTC6994-1/LTC6994-2
15
699412fb
operaTion
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6994 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
tDIVCODE = 16 • (∆DIVCODE + 6) • tMASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. How-
ever, if the delay timing is active during the transition, the
actual delay can take on a value between the two settings.
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, tSTART
. The OUT pin
is held low during this time and the IN pin has no control
over the output. The typical value for tSTART ranges from
0.5ms to 8ms depending on the master oscillator frequency
(independent of NDIV):
tSTART(TYP) = 500 • tMASTER
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the LTC6994 can respond
to an input. The start-up time may increase if the supply
or DIV pin voltages are not stable. For this reason, it is
recommended to minimize the capacitance on the DIV
pin so it will properly track V+. Less than 100pF will not
extend the start-up time.
At the end of tSTART the DIVCODE and IN pin settings are
recognized, and the state of the IN pin is transferred to the
output (without additional delay). If IN is high at the end of
tSTART, OUT will go high. Otherwise OUT will remain low.
The LTC6994-2 with POL = 1 is the exception because it
inverts the signal. At this point, the LTC6994 is ready to
respond to rising/falling edges on the input.
DIV
500mV/DIV
IN
2V/DIV
OUT
2V/DIV
LTC6994-1
V+ = 3.3V
RSET = 200k
500µs/DIV 699412 F07a
512µs
256µs
4µs
Figure 7a. DIVCODE Change from 0 to 2
DIV
500mV/DIV
IN
2V/DIV
OUT
2V/DIV
LTC6994-1
V+ = 3.3V
RSET = 200k
500µs/DIV 699412 F07b
256µs 4µs
512µs
Figure 7b. DIVCODE Change from 2 to 0
IN
V+
OUT
tSTART
(IN IGNORED)
tPD
699412 F08
IF IN = 1 AT END OF tSTART*
IF IN = 0 AT END OF tSTART*
*LTC6994-2 WITH POL = 1 INVERTS THE OUTPUT
Figure 8. Start-Up Timing Diagram
LTC6994-1/LTC6994-2
16
699412fb
applicaTions inForMaTion
Basic Operation
The simplest and most accurate method to program the
LTC6994 is to use a single resistor, RSET
, between the SET
and GND pins. The design procedure is a 3-step process.
Alternatively, Linear Technology offers the easy-to-use
TimerBlox Designer tool to quickly design any LTC6994
based circuit. Download the free TimerBlox Designer
software at www.linear.com/timerblox.
Step 1: Select the LTC6994 Version and POL Bit
Setting.
Choose LTC6994-1 to delay one (rising or falling) input
transition. The POL bit then defines which edge is to be
delayed. POL = 0 delays rising edges. POL = 1 delays
falling edges.
Choose LTC6994-2 to delay rising and falling edges. Set
POL = 0 for normal operation, or POL = 1 to invert the
output.
Step 2: Select the NDIV Frequency Divider Value.
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
NDIV value. For a given delay time (tDELAY), NDIV should
be selected to be within the following range:
tDELAY
16µs ≤NDIV ≤tDELAY
1µs
(1)
To minimize supply current, choose the lowest NDIV value.
However, in some cases a higher value for NDIV will provide
better accuracy (see Electrical Characteristics).
Table 1 can also be used to select the appropriate NDIV
values for the desired tDELAY
.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 3: Calculate and Select RSET
.
The final step is to calculate the correct value for RSET
using the following equation:
RSET =50k
1µs •tDELAY
NDIV
(2)
Select the standard resistor value closest to the calculated
value.
Example: Design a circuit to delay falling edges by
tDELAY = 100µs with minimum power consumption.
Step 1: Select the LTC6994 Version and POL Bit
Setting.
To delay negative transitions, choose the LTC6994-1 with
POL = 1.
Step 2: Select the NDIV Frequency Divider Value.
Choose an NDIV value that meets the requirements of
Equation (1), using tDELAY = 100µs:
6.25 ≤ NDIV ≤ 100
Potential settings for NDIV include 8 and 64. NDIV = 8 is
the best choice, as it minimizes supply current by us-
ing a large RSET resistor. POL = 1 and NDIV = 8 requires
DIVCODE = 14. Using Table 1, choose R1 = 102k and R2
= 976k values to program DIVCODE = 14.
Step 3: Select RSET
.
Calculate the correct value for RSET using Equation (2).
RSET =50k
1µs •100µs
8=625k
Since 625k is not available as a standard 1% resistor,
substitute 619k if a –0.97% shift in tDELAY is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
The completed design is shown in Figure 9.
Figure 9. 100µs Negative-Edge Delay
LTC6994-1
IN
GND
SET
OUT
V+
DIV
R1
102k
0.1µF
DIVCODE = 14
699412 F09
2.25V TO 5.5V
R2
976k
RSET
625k
LTC6994-1/LTC6994-2
17
699412fb
applicaTions inForMaTion
Voltage-Controlled Delay
With one additional resistor, the LTC6994 output delay
can be manipulated by an external voltage. As shown in
Figure 10, voltage VCTRL sources/sinks a current through
RMOD to vary the ISET current, which in turn modulates
the delay as described in Equation (3):
tDELAY =NDIV •RMOD
50kΩ
•1µs
1+RMOD
RSET
–VCTRL
VSET
(3)
Digital Delay Control
The control voltage can be generated by a DAC (digital-to-
analog converter), resulting in a digitally-controlled delay.
Many DACs allow for the use of an external reference. If
such a DAC is used to provide the VCTRL voltage, the VSET
dependency can be eliminated by buffering VSET and using
it as the DAC’s reference voltage, as shown in Figure 11.
The DAC’s output voltage now tracks any VSET variation
and eliminates it as an error source. The SET pin cannot be
tied directly to the reference input of the DAC because the
current drawn by the DAC’s REF input would affect the delay.
ISET Extremes (Master Oscillator Frequency Extremes)
When operating with ISET outside of the recommended
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The oscillator will still function with reduced accuracy for
ISET < 1.25µA. At approximately 500nA, the oscillator will
stop. Under this condition, the delay timing can still be
initiated, but will not terminate until ISET increases and
the master oscillator starts again.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
LTC6994
IN
GND
SET
OUT
V+
DIV
R1
C1
0.1µF
699412 F10
V+
R2
RSET
RMOD
VCTRL
699412 F11
LTC6994
IN
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
V+
RMOD
RSET
–
+
V+
1/2
LTC6078
LTC1659
V+
0.1µF
VCC REF
GND
VOUT
µP
DIN
CLK
CS/LD
NDIV • RMOD
50kΩ
tDELAY =
DIN = 0 TO 4095
•
–
1+ RMOD
RSET
DIN
4096
1µs
0.1µF
Figure 10. Voltage-Controlled Delay
Figure 11. Digitally Controlled Delay
LTC6994-1/LTC6994-2
18
699412fb
applicaTions inForMaTion
Settling Time
Following a 2× or 0.5× step change in ISET
, the out-
put delay takes approximately six master clock cycles
(6 • tMASTER) to settle to within 1% of the final value.
An example is shown in Figure 12, using the circuit in
Figure 10.
Figure 12. Typical Settling Time
VCTRL
2V/DIV
IN
5V/DIV
OUT
5V/DIV
DELAY
2µs/DIV
LTC6994-1
V+ = 3.3V
DIVCODE = 0
RSET = 200k
RMOD = 464k
tOUT = 3µs AND 6µs
20µs/DIV 699412 F12
Coupling Error
The current sourced by the SET pin is used to bias the
internal master oscillator. The LTC6994 responds to
changes in ISET almost immediately, which provides excel-
lent settling time. However, this fast response also makes
the SET pin sensitive to coupling from digital signals, such
as the IN input.
Even an excellent layout will allow some coupling between
IN and SET. Additional error is included in the specified
accuracy for NDIV = 1 to account for this. Figure 13 shows
that ÷1 supply variation is dependent on coupling from
rising or falling inputs.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
IN (or any other fast-edge, wide-swing signal).
SUPPLY (V)
2
–1.0
0
0.4
0.2
0.6
0.8
1.0
456
–0.4
–0.2
–0.6
–0.8
3
699412 F13
DRIFT (%)
FALLING EDGE DELAY
RISING EDGE DELAY
RSET = 50k
NDIV = 1
Figure 13. Delay Drift vs Supply Voltage
LTC6994-1/LTC6994-2
19
699412fb
Power Supply Current
The Electrical Characteristics table specifies the supply
current while the part is idle (waiting for an input transi-
tion). IS(IDLE) varies with the programmed tDELAY and the
supply voltage, as described by the equations in Table 2,
valid for both the LTC6994-1 and LTC6994-2.
Table 2. Approximate Idle Supply Current Equations
CONDITION TYPICAL IS(IDLE)
NDIV ≤ 64
V+•NDIV •7pF +4pF
( )
tDELAY
+V+
500kΩ+2.2•ISET +50µA
NDIV ≥ 512
V+•NDIV •7pF
tDELAY
+V+
500kΩ+1.8 •ISET +50µA
When an input transition starts the delay timing circuity,
the instantaneous supply current increases to IS(ACTIVE).
IS(ACTIVE) = IS(IDLE) + ∆IS(ACTIVE)
applicaTions inForMaTion
∆IS(ACTIVE) can be estimated using the equations in Table 3,
assuming a periodic input with frequency fIN. The equa-
tions assume the input pulse width is greater than tDELAY;
otherwise, the output will not transition (and the increase
in supply current will be less).
Table 3. Active Increase in Supply Current
CONDITION DEVICE TYPICAL ∆IS(ACTIVE)*
NDIV ≤ 64 LTC6994-1 fIN • V+ • (NDIV • 5pF + 18pF + CLOAD)
LTC6994-2 fIN • V+ • (NDIV • 10pF + 22pF + CLOAD)
NDIV ≥ 512 Either Version fIN • V+ • CLOAD
*Ignoring resistive loads (assumes RLOAD = ∞)
Figures 14 and 15 show how the supply current increases
from IS(IDLE) as the input frequency increases. At higher
NDIV settings, the increase in active current is smaller.
fIN • tDELAY
“IDLE”
POWER SUPPLY CURRENT (µA)
150
200
250
0.8
699412 F14
100
50
00.2 0.4 0.6 1.0
÷1, RSET = 50k ÷8, RSET = 50k
÷1, RSET = 100k
÷1, RSET = 800k
V+ = 3.3V
INPUT PULSE WIDTH = 1.1 • tDELAY
CLOAD = 5pF
RLOAD = ∞
fIN • tDELAY
“IDLE”
POWER SUPPLY CURRENT (µA)
150
200
250
0.4
699412 F15
100
50
00.1 0.2 0.3 0.5
÷1, RSET = 50k
÷8, RSET = 50k
÷1, RSET = 100k
÷1, RSET = 800k
V+ = 3.3V
fIN < 1/(2 • tDELAY) TO ALLOW RISING AND
FALLING DELAYS TO REACH THE OUTPUT
CLOAD = 5pF
RLOAD = ∞
Figure 14. IS(ACTIVE) vs Input Frequency, LTC6994-1 Figure 15. IS(ACTIVE) vs Input Frequency, LTC6994-2
LTC6994-1/LTC6994-2
20
699412fb
699412 F16
LTC6994
IN
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
RSET
V+
V+
DIV
SET
OUT
GND
IN
C1R1
R2
V+
RSET
DCB PACKAGE
IN
GND
SET
OUT
V+
DIV
R2
V+
RSET
TSOT-23 PACKAGE
R1
C1
applicaTions inForMaTion
Figure 16. Supply Bypassing and PCB Layout
Supply Bypassing and PCB Layout Guidelines
The LTC6994 is an accurate monostable multivibrator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance is
easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 16 shows example PCB layouts for both the SOT-23
and DCB packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6994. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and make
a direct, short connection. The SET pin is a current sum-
ming node and currents injected into this pin directly
modulate the output delay. Having a short connection
minimizes the exposure to signal pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
LTC6994-1/LTC6994-2
21
699412fb
Typical applicaTions
Delayed One-Shot
LTC6994-1
OUT
V+
DIV
IN
GND
SET
604k
IN
OUT
5V
0.1µF
IN
699412 TA02
LTC6993-1
tRISE_DELAY = 50ms
DELAY
50ms DELAY SHOT
SHOT
10ms
tONESHOT = 10ms
OUT
V+
DIV
TRIG
GND
SET
121k
5V
0.1µF
DELAYED PULSE OUT
1M
392k
Pulse Stretcher
LTC6994-1
OUT
V+
DIV
IN
GND
SET
tMIN = 1ms
OUTPUT PULSE DURATION = tPULSE_IN + 1ms
V+
0.1µF
976k
699412 TA03
787k
OUTIN
IN
OUT tMIN
182k
tMIN
LTC6994-2
OUT
V+
DIV
IN
GND
SET
t = 100ms
OUTPUT GOES TO SAME FINAL LEVEL OF INPUT
AFTER STABLE FOR 100ms
V+
STABLECHATTER
OR
STABLECHATTER
0.1µF
523k
699412 TA04
154k
OUT
V+
1M
V+OR
Switch/Relay Debouncer
LTC6994-1/LTC6994-2
22
699412fb
Typical applicaTions
Edge Chatter Filter
699412 TA05
LTC6994-2
OUT
V+
DIV
IN
GND
SET
499k 10µs
INPUT MUST BE STABLE FOR AT LEAST 10µs
NORMAL NOISY EDGES
IN
OUT
10µs 10µs 10µs 10µs
V+
0.1µF
IN OUT
Crossover Gate—Break-Before-Make Interval Timer
LTC6994-1
OUT
V+
DIV
IN
GND
SET
787k tDELAY = 1ms
V+
V+
V+
V+
VLOAD
OFF
GND
1ms OFF INTERVAL
AT EACH TRANSITION
OFF
OFF
V+
0.1µF
IN
LOAD
LOW
LOAD
HIGH
FALLING
DELAYED
RISING
DELAYED
100k
100k
P
TP0610
N
2N7000
699412 TA06
100k
LTC6994-1
OUT
V+
DIV
IN
GND
SET
tDELAY = 1ms
0.1µF
442k
LOAD
VLOAD
IN
V+/2
100k
787k
LTC6994-1/LTC6994-2
23
699412fb
package DescripTion
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
3.00 ±0.10
(2 SIDES)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 ±0.10
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB6) DFN 0405
0.25 ± 0.05
0.50 BSC
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
0.25 ± 0.05
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)
2.15 ±0.05
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC6994-1/LTC6994-2
24
699412fb
package DescripTion
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302 REV B
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC6994-1/LTC6994-2
25
699412fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 7/11 Revised the Description section.
Added text to Basic Operation paragraph in the Applications Information section.
1
16
B 1/12 Added MP-Grade.
Corrected sizing of the Typical Performance Characteristics curves G31 and G32.
1, 2, 4
8
LTC6994-1/LTC6994-2
26
699412fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 0112 REV B • PRINTED IN USA
Press-and-Hold (0.3s to 4s) Delay Timer
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC1799 1MHz to 33MHz ThinSOT Silicon Oscillator Wide Frequency Range
LTC6900 1MHz to 20MHz ThinSOT Silicon Oscillator Low Power, Wide Frequency Range
LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 35µA at 400kHz
LTC6930 Fixed Frequency Oscillator, 32.768kHz to 8.192MHz 0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
LTC6990 TimerBlox: Voltage-Controlled Silicon Oscillator Fixed-Frequency or Voltage-Controlled Operation
LTC6991 TimerBlox: Resettable Low Frequency Oscillator Clock Periods up to 9.5 hours
LTC6992 TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) Simple PWM with Wide Frequency Range
LTC6993 TimerBlox: Monostable Pulse Generator (One-Shot) Resistor-Programmable Pulse Width of 1µs to 34s
LTC6994-1
OUT
V+
DIV
IN
GND
SET
RSET
576k
DELAY
HOLD
IN
OUT
IN
OUT
tDELAY ≅ 3s
BOUNCE
V+
0.1µF
1M
OUT
V+
100k
681k
LTC6994-1
ACTIVE HIGH ACTIVE LOW
OUT
V+
DIV
IN
GND
SET
RSET
576k
HOLD
DELAY
tDELAY ≅ 3s
BOUNCE
RSET (kΩ) = 190 • tDELAY (SECONDS)
V+
0.1µF
1M
699412 TA07
OUT
V+
100k
681k