QuadPort™ Datapath Switching Element (DSE) Family
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Cypress Semiconductor Corporation •3901 North First Street •San Jose •CA 95134 •408-943-2600
Document #: 38-06065 Rev. ** Revised August 2, 2002
Features
• The QuadPort™ Dat apath Switching Element (DSE)
allows four independent ports of access for data path
management and switching.
• Synchronous pipelined device
—128K x 40 (5 Mb) CY7C0452V18
—64K x 40 (2 Mb) CY7C0451V18
—32K x 40 (1 Mb) CY7C0450V18
—128K x 20 (2 Mb) CY7C0431V18
—64K x 20 (1 Mb) CY7C0430V18
• Clock operation up to 167 MHz
• High Bandwidth up to 27 Gbps
• LVTTL and SSTL2 I/O standard for I/O
• LVPECL differential clock inputs
• Impedance matching on data outputs
• Simple array partitioning (except CY7C0452V18)
—Internal mask register for burst counter control
—Counter-Interrupt flags to indicate terminal count
—Block Retransmit Capability
—Counter and mask register readback on address
lines
• Dual Chip Enables on all ports for easy depth expansion
(except CY7C0452V18)
• Separate byte select controls on all ports
• BGA package (676 balls, 27 x 27 mm, 1.0 mm pitch)
• Commercial and Industrial temperature ranges
• IEEE 1149.1 JTAG boundary scan
• 1.8V Suppl y Voltage
—Active = 1300 mA (maximum)
—Standby = 500 mA (maximum)
QuadPort DSE Applications
BUFFERED SWITCH
PORT 1
PORT 2
PORT 3
PORT 4
REDUNDANT DATA MIRR OR
PORT 1 PORT 3
PORT 4
PORT 2
DATA PATH AGGREGATOR
PORT 1
PORT 2
PORT 3
PORT 4
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 2 of 51
Pin Configuration
676 Ball Grid Array (BGA) (CY7C0451V18)[1]
Note:
1. B Following a Pin name represents an active LOW signal. For example, B0B P1 = B0 P1.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
AVSS AIO
P1 RWB
P1 VDD
CVDD
CVDD
A
P1
VDD
A
P1
VDD VDD VDD
A
P1
VDD
A
P1
VDD
A
P1
VDD
A
P1
VDD
A
P4
VDD
A
P4
VDD
A
P4
VDD
A
P4
VDD VDD VDD
A
P4
VDD
A
P4
VDD
CVDD
CRWB
P4 AIO
P4 VSS A
BDIO
P1 B2B
P1 B3B
P1 MKL
DB
P1
RETX
B
P1
CN-
TRDB
P1
WRP
0B
P1
VDD VDD CNTI
NTB
P1
A2
P1 A7
P1 A12
P1 A12
P4 A7
P4 A2
P4 CNTI
NTB
P4
VDD VDD WRP
0B
P4
CN-
TRDB
P4
RETX
B
P4
MKL
DB
P4
B3B
P4 B2B
P4 DIO
P4 B
CB0B
P1 B1B
P1 CE1
P1 CE0B
P1 CN-
TRST
B
P1
CNTL
DB
P1
CNTI
NCB
P1
MKR
DB
P1
NC INTB
P1 A3
P1 A8
P1 A13
P1 A13
P4 A8
P4 A3
P4 INTB
P4 NC MKR
DB
P4
CNTI
NCB
P4
CNTL
DB
P4
CN-
TRST
B
P4
CE0B
P4 CE1
P4 B1B
P4 B0B
P4 C
DVDD
Q
P1
DQ0
P1 DQ1
P1 DQ2
P1 DQ3
P1 DQ4
P1 VSS TRST NC REA
DYB
P1
A4
P1 A9
P1 A14
P1 A14
P4 A9
P4 A4
P4 REA
DYB
P4
NC NC VSS DQ4
P4 DQ3
P4 DQ2
P4 DQ1
P4 DQ0
P4 VDD
Q
P4 D
EVDD
Q
P1
DQ5
P1 DQ6
P1 DQ7
P1 DQ8
P1 DQ9
P1 VSS TMS TDI A0
P1 A5
P1 A10
P1 A15
P1 A15
P4 A10
P4 A5
P4 A0
P4 NC VSS VSS DQ9
P4 DQ8
P4 DQ7
P4 DQ6
P4 DQ5
P4 VDD
Q
P4 E
FVDD
Q
P1
DQ10
P1 DQ11
P1 DQ12
P1 DQ13
P1 DQ14
P1 VSS TCK TDO A1
P1 A6
P1 A11
P1 NC NC A11
P4 A6
P4 A1
P4 VSS VSS VSS DQ14
P4 DQ13
P4 DQ12
P4 DQ11
P4 DQ10
P4 VDD
Q
P4 F
GVDD
Q
P1
DQ15
P1 DQ16
P1 DQ17
P1 DQ18
P1 DQ19
P1 VSS NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQ19
P4 DQ18
P4 DQ17
P4 DQ16
P4 DQ15
P4 VDD
Q
P4 G
HVDD VDD VDD
CZQ
P1 OEB
P1 C+
P1 VSS VSS VSS REFA
P1 REFA
P1 REFA
P1 REFA
P1 REFA
P4 REFA
P4 REFA
P4 REFA
P4 VSS VSS VSS C+
P4 OEB
P4 ZQ
P4 VDD
CVDD VDD H
JVDD VDD VDD
Q
P1
VDD DOFF
B
P1
C-
P1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C-
P4 DOFF
B
P4
VDD VDD
Q
P4
VDD VDD J
KVDD
Q
P1
DQ20
P1 DQ21
P1 DQ22
P1 DQ23
P1 DQ24
P1 VSS REF
Q
P1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF
Q
P4
VSS DQ24
P4 DQ23
P4 DQ22
P4 DQ21
P4 DQ20
P4 VDD
Q
P4 K
LVDD
Q
P1
DQ25
P1 DQ26
P1 DQ27
P1 DQ28
P1 DQ29
P1 VSS REF
Q
P1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF
Q
P4
VSS DQ29
P4 DQ28
P4 DQ27
P4 DQ26
P4 DQ25
P4 VDD
Q
P4 L
MVDD
Q
P1
DQ30
P1 DQ31
P1 DQ32
P1 DQ33
P1 DQ34
P1 VSS REF
Q
P1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF
Q
P4
VSS DQ34
P4 DQ33
P4 DQ32
P4 DQ31
P4 DQ30
P4 VDD
Q
P4 M
NVDD
Q
P1
DQ35
P1 DQ36
P1 DQ37
P1 DQ38
P1 DQ39
P1 VSS REF
Q
P1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF
Q
P4
VSS DQ39
P4 DQ38
P4 DQ37
P4 DQ36
P4 DQ35
P4 VDD
Q
P4 N
PVDD
Q
P2
DQ35
P2 DQ36
P2 DQ37
P2 DQ38
P2 DQ39
P2 VSS REF
Q
P2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF
Q
P3
VSS DQ39
P3 DQ38
P3 DQ37
P3 DQ36
P3 DQ35
P3 VDD
Q
P3 P
RVDD
Q
P2
DQ30
P2 DQ31
P2 DQ32
P2 DQ33
P2 DQ34
P2 VSS REF
Q
P2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF
Q
P3
VSS DQ34
P3 DQ33
P3 DQ32
P3 DQ31
P3 DQ30
P3 VDD
Q
P3 R
TVDD
Q
P2
DQ25
P2 DQ26
P2 DQ27
P2 DQ28
P2 DQ29
P2 VSS REF
Q
P2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF
Q
P3
VSS DQ29
P3 DQ28
P3 DQ27
P3 DQ26
P3 DQ25
P3 VDD
Q
P3 T
UVDD
Q
P2
DQ20
P2 DQ21
P2 DQ22
P2 DQ23
P2 DQ24
P2 VSS REF
Q
P2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS REF
Q
P3
VSS DQ24
P3 DQ23
P3 DQ22
P3 DQ21
P3 DQ20
P3 VDD
Q
P3 U
VVDD VDD VDD
Q
P2
VDD DOFF
B
P2
C-
P2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C-
P3 DOFF
B
P3
VDD VDD
Q
P3
VDD VDD V
WVDD VDD VDD
CZQ
P2 OEB
P2 C+
P2 VSS VSS VSS REFA
P2 REFA
P2 REFA
P2 REFA
P2 REFA
P3 REFA
P3 REFA
P3 REFA
P3 VSS VSS VSS C+
P3 OEB
P3 ZQ
P3 VDD
CVDD VDD W
YVDD
Q
P2
DQ15
P2 DQ16
P2 DQ17
P2 DQ18
P2 DQ19
P2 VSS MRS
TB VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQ19
P3 DQ18
P3 DQ17
P3 DQ16
P3 DQ15
P3 VDD
Q
P3 Y
AA VDD
Q
P2
DQ10
P2 DQ11
P2 DQ12
P2 DQ13
P2 DQ14
P2 VSS NC NC A1
P2 A6
P2 A11
P2 NC NC A11
P3 A6
P3 A1
P3 VSS VSS VSS DQ14
P3 DQ13
P3 DQ12
P3 DQ11
P3 DQ10
P3 VDD
Q
P3 AA
AB VDD
Q
P2
DQ5
P2 DQ6
P2 DQ7
P2 DQ8
P2 DQ9
P2 VSS NC NC A0
P2 A5
P2 A10
P2 A15
P2 A15
P3 A10
P3 A5
P3 A0
P3 VSS VSS VSS DQ9
P3 DQ8
P3 DQ7
P3 DQ6
P3 DQ5
P3 VDD
Q
P3 AB
AC VDD
Q
P2
DQ0
P2 DQ1
P2 DQ2
P2 DQ3
P2 DQ4
P2 VSS NC NC REA
DYB
P2
A4
P2 A9
P2 A14
P2 A14
P3 A9
P3 A4
P3 REA
DYB
P3
NC VSS VSS DQ4
P3 DQ3
P3 DQ2
P3 DQ1
P3 DQ0
P3 VDD
Q
P3 AC
AD B0B
P2 B1B
P2 CE1
P2 CE0B
P2 CN-
TRST
B
P2
CNTL
DB
P2
CNTI
NCB
P2
MKR
DB
P2
NC INTB
P2 A3
P2 A8
P2 A13
P2 A13
P3 A8
P3 A3
P3 INTB
P3 NC MKR
DB
P3
CNTI
NCB
P3
CNTL
DB
P3
CN-
TRST
B
P3
CE0B
P3 CE1
P3 B1B
P3 B0B
P3 AD
AE DIO
P2 B2B
P2 B3B
P2 MKL
DB
P2
RETX
B
P2
CN-
TRDB
P2
WRP
0B
P2
VDD VDD CNTI
NTB
P2
A2
P2 A7
P2 A12
P2 A12
P3 A7
P3 A2
P3 CNTI
NTB
P3
VDD VDD WRP
0B
P3
CN-
TRDB
P3
RETX
B
P3
MKL
DB
P3
B3B
P3 B2B
P3 DIO
P3 AE
AF VSS AIO
P2 RWB
P2 VDD
CVDD
CVDD
A
P2
VDD
A
P2
VDD VDD VDD
A
P2
VDD
A
P2
VDD
A
P2
VDD
A
P2
VDD
A
P3
VDD
A
P3
VDD
A
P3
VDD
A
P3
VDD VDD VDD
A
P3
VDD
A
P3
VDD
CVDD
CRWB
P3 AIO
P3 VSS AF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 3 of 51
Table 1. 676 BGA Pin Table (CY7C0451V18)
VSSPIN CY7C0451V18
A1 VSS
A2 AIO P1
A3 RWB P1
A4 VDDC
A5 VDDC
A6 VDDA P1
A7 VDDA P1
A8 VDD
A9 VDD
A10 VDDA P1
A11 VDDA P1
A12 VDDA P1
A13 VDDA P1
A14 VDDA P4
A15 VDDA P4
A16 VDDA P4
A17 VDDA P4
A18 VDD
A19 VDD
A20 VDDA P4
A21 VDDA P4
A22 VDDC
A23 VDDC
A24 RWB P4
A25 AIO P4
A26 VSS
B1 DIO P1
B2 B2B P1
B3 B3B P1
B4 MKLDB P1
B5 RETXB P1
B6 CNTRDB P1
B7 WRP0B P1
B8 VDD
B9 VDD
B10 CNTINTB P1
B11 A2 P1
B12 A7 P1
B13 A12 P1
B14 A12 P4
B15 A7 P4
B16 A2 P4
B17 CNTINTB P4
B18 VDD
B19 VDD
B20 WRP0B P4
B21 CNTRDB P4
B22 RETXB P4
B23 MKLDB P4
B24 B3B P4
B25 B2B P4
B26 DIO P4
C1 B0B P1
C2 B1B P1
C3 CE1 P1
C4 CE0B P1
C5 CNTRSTB P1
C6 CNTL DB P1
C7 CNTINCB P1
C8 MKRDB P1
C9 NC
C10 INTB P1
C11 A3 P1
C12 A8 P1
C13 A13 P1
C14 A13 P4
C15 A8 P4
C16 A3 P4
C17 INTB P4
C18 NC
C19 MKRDB P4
C20 CNTINCB P4
C21 CNTLDB P4
C22 CNTRSTB P4
C23 CE0B P4
C24 CE1 P4
C25 B1B P4
C26 B0B P4
D1 VDDQ P1
D2 DQ0 P1
D3 DQ1 P1
D4 DQ2 P1
D5 DQ3 P1
D6 DQ4 P1
D7 VSS
D8 TRST
D9 NC
D10 READYB P1
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 4 of 51
D11 A 4 P 1
D12 A9 P1
D13 A14 P1
D14 A14 P4
D15 A9 P4
D16 A4 P4
D17 READYB P4
D18 NC
D19 NC
D20 VSS
D21 DQ4 P4
D22 DQ3 P4
D23 DQ2 P4
D24 DQ1 P4
D25 DQ0 P4
D26 VDDQ P4
E1 VDDQ P1
E2 DQ5 P1
E3 DQ6 P1
E4 DQ7 P1
E5 DQ8 P1
E6 DQ9 P1
E7 VSS
E8 TMS
E9 TDI
E10 A0 P4
E11 A5 P1
E12 A10 P1
E13 A15 P1
E14 A15 P4
E15 A10 P4
E16 A5 P4
E17 A0 P1
E18 NC
E19 VSS
E20 VSS
E21 DQ9 P4
E22 DQ8 P4
E23 DQ7 P4
E24 DQ6 P4
E25 DQ5 P4
E26 VDDQ P4
F1 VDDQ P1
F2 DQ10 P1
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18 F3 DQ11 P1
F4 DQ12 P1
F5 DQ13 P1
F6 DQ14 P1
F7 VSS
F8 TCK
F9 TDO
F10 A1 P1
F11 A6 P1
F12 A11 P1
F13 NC
F14 NC
F15 A11 P4
F16 A6 P4
F17 A1 P4
F18 VSS
F19 VSS
F20 VSS
F21 DQ 14 P4
F22 DQ13 P4
F23 DQ12 P4
F24 DQ11 P4
F25 DQ10 P4
F26 VDDQ P4
G1 VDDQ P1
G2 DQ15 P1
G3 DQ16 P1
G4 DQ17 P1
G5 DQ18 P1
G6 DQ19 P1
G7 VSS
G8 NC
G9 VSS
G10 VSS
G11 VSS
G12 VSS
G13 VSS
G14 VSS
G15 VSS
G16 VSS
G17 VSS
G18 VSS
G19 VSS
G20 VSS
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 5 of 51
G21 DQ19 P4
G22 DQ18 P4
G23 DQ17 P4
G24 DQ16 P4
G25 DQ15 P4
G26 VDDQ P4
H1 VDD
H2 VDD
H3 VDDC
H4 ZQ P1
H5 OEB P1
H6 C+ P1
H7 VSS
H8 VSS
H9 VSS
H10 VREFA P1
H11 VRE FA P1
H12 VREFA P1
H13 VREFA P1
H14 VREFA P4
H15 VREFA P4
H16 VREFA P4
H17 VREFA P4
H18 VSS
H19 VSS
H20 VSS
H21 C+ P4
H22 OEB P4
H23 ZQ P4
H24 VDDC
H25 VDD
H26 VDD
J1 VDD
J2 VDD
J3 VDDQ P1
J4 VDD
J5 DOFFB P1
J6 C– P1
J7 VSS
J8 VSS
J9 VSS
J10 VSS
J11 VSS
J12 VSS
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18 J13 VSS
J14 VSS
J15 VSS
J16 VSS
J17 VSS
J18 VSS
J19 VSS
J20 VSS
J21 C– P4
J22 DOFFB P4
J23 VDD
J24 VDDQ P4
J25 VDD
J26 VDD
K1 VDD1 P1
K2 DQ20 P1
K3 DQ21 P1
K4 DQ22 P1
K5 DQ23 P1
K6 DQ24 P1
K7 VSS
K8 VREFQ P1
K9 VSS
K10 VSS
K11 VSS
K12 VSS
K13 VSS
K14 VSS
K15 VSS
K16 VSS
K17 VSS
K18 VSS
K19 VREFQ P4
K20 VSS
K21 DQ24 P4
K22 DQ23 P4
K23 DQ22 P4
K24 DQ21 P4
K25 DQ20 P4
K26 VDDQ P4
L1 VDDQ P1
L2 DQ25 P1
L3 DQ26 P1
L4 DQ27 P1
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 6 of 51
L5 DQ28 P1
L6 DQ29 P1
L7 VSS
L8 VREFQ P1
L9 VSS
L10 VSS
L11 VSS
L12 VSS
L13 VSS
L14 VSS
L15 VSS
L16 VSS
L17 VSS
L18 VSS
L19 VREFQ P4
L20 VSS
L21 DQ29 P4
L22 DQ28 P4
L23 DQ27 P4
L24 DQ26 P4
L25 DQ25 P4
L26 VDDQ P4
M1 VDDQ P1
M2 DQ30 P1
M3 DQ31 P1
M4 DQ32 P1
M5 DQ33 P1
M6 DQ34 P1
M7 VSS
M8 VREFQ P1
M9 VSS
M10 VSS
M11 VSS
M12 VSS
M13 VSS
M14 VSS
M15 VSS
M16 VSS
M17 VSS
M18 VSS
M19 VREFQ P 4
M20 VSS
M21 DQ34 P4
M22 DQ33 P4
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18 M23 DQ32 P4
M24 DQ31 P4
M25 DQ30 P4
M26 VDDQ P4
N1 VDDQ P1
N2 DQ35 P1
N3 DQ36 P1
N4 DQ37 P1
N5 DQ38 P1
N6 DQ39 P1
N7 VSS
N8 VREFQ P1
N9 VSS
N10 VSS
N11 VSS
N12 VSS
N13 VSS
N14 VSS
N15 VSS
N16 VSS
N17 VSS
N18 VSS
N19 VREFQ P4
N20 VSS
N21 DQ39 P4
N22 DQ38 P4
N23 DQ37 P4
N24 DQ36 P4
N25 DQ35 P4
N26 VDDQ P4
P1 VDDQ P2
P2 DQ35 P2
P3 DQ36 P2
P4 DQ37 P2
P5 DQ38 P2
P6 DQ39 P2
P7 VSS
P8 VREFQ P2
P9 VSS
P10 VSS
P11 VSS
P12 VSS
P13 VSS
P14 VSS
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 7 of 51
P15 VSS
P16 VSS
P17 VSS
P18 VSS
P19 VREFQ P3
P20 VSS
P21 DQ39 P3
P22 DQ38 P3
P23 DQ37 P3
P24 DQ36 P3
P25 DQ35 P3
P26 VDDQ P3
R1 VDDQ P2
R2 DQ30 P2
R3 DQ31 P2
R4 DQ32 P2
R5 DQ33 P2
R6 DQ34 P2
R7 VSS
R8 VREFQ P2
R9 VSS
R10 VSS
R11 VSS
R12 VSS
R13 VSS
R14 VSS
R15 VSS
R16 VSS
R17 VSS
R18 VSS
R19 VREFQ P3
R20 VSS
R21 DQ34 P3
R22 DQ33 P3
R23 DQ32 P3
R24 DQ31 P3
R25 DQ30 P3
R26 VDDQ P3
T1 VDDQ P2
T2 DQ25 P2
T3 DQ26 P2
T4 DQ27 P2
T5 DQ28 P2
T6 DQ29 P2
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18 T7 VSSVSS
T8 VREFQ P2
T9 VSS
T10 VSS
T11 VSS
T12 VSS
T13 VSS
T14 VSS
T15 VSS
T16 VSS
T17 VSS
T18 VSS
T19 VREFQ P3
T20 VSS
T21 DQ29 P3
T22 DQ28 P3
T23 DQ27 P3
T24 DQ26 P3
T25 DQ25 P3
T26 VDDQ P3
U1 VDDQ P2
U2 DQ20 P2
U3 DQ21 P2
U4 DQ22 P2
U5 DQ23 P2
U6 DQ24 P2
U7 VSS
U8 VREFQ P2
U9 VSS
U10 VSS
U11 VSS
U12 VSS
U13 VSS
U14 VSS
U15 VSS
U16 VSS
U17 VSS
U18 VSS
U19 VREFQ P3
U20 VSS
U21 DQ24 P3
U22 DQ23 P3
U23 DQ22 P3
U24 DQ21 P3
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 8 of 51
U25 DQ20 P3
U26 VDDQ P3
V1 VDD
V2 VDD
V3 VDDQ P2
V4 VDD
V5 DOFFB P2
V6 C– P2
V7 VSS
V8 VSS
V9 VSS
V10 VSS
V11 VSS
V12 VSS
V13 VSS
V14 VSS
V15 VSS
V16 VSS
V17 VSS
V18 VSS
V19 VSS
V20 VSS
V21 C- P3
V22 DOFFB P3
V23 VDD
V24 VDDQ P3
V25 VDD
V26 VDD
W1 VDD
W2 VDD
W3 VDDC
W4 ZQ P2
W5 OEB P2
W6 C+ P2
W7 VSS
W8 VSS
W9 VSS
W10 VREFA P2
W11 VREFA P2
W12 VREFA P2
W13 VREFA P2
W14 VREFA P3
W15 VREFA P3
W16 VREFA P3
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18 W17 VREFA P3
W18 VSS
W19 VSS
W20 VSS
W21 C+ P3
W22 OEB P3
W23 ZQ P3
W24 VDDC
W25 VDD
W26 VDD
Y1 VDDQ P2
Y2 DQ15 P2
Y3 DQ16 P2
Y4 DQ17 P2
Y5 DQ18 P2
Y6 DQ19 P2
Y7 VSS
Y8 MRSTB
Y9 VSS
Y10 VSS
Y11 VSS
Y12 VSS
Y13 VSS
Y14 VSS
Y15 VSS
Y16 VSS
Y17 VSS
Y18 VSS
Y19 VSS
Y20 VSS
Y21 DQ19 P3
Y22 DQ18 P3
Y23 DQ17 P3
Y24 DQ16 P3
Y25 DQ15 P3
Y26 VDDQ P3
AA1 VDDQ P2
AA2 DQ10 P2
AA3 DQ11 P2
AA4 DQ12 P2
AA5 DQ13 P2
AA6 DQ14 P2
AA7 VSS
AA8 NC
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 9 of 51
AA9 NC
AA10 A1 P2
AA11 A6 P2
AA12 A11 P2
AA13 NC
AA14 NC
AA15 A11 P3
AA16 A6 P3
AA17 A1 P3
AA18 VSS
AA19 VSS
AA20 VSS
AA21 DQ 14 P3
AA22 DQ13 P3
AA23 DQ12 P3
AA24 DQ11 P3
AA25 DQ10 P3
AA26 VDDQ P3
AB1 VDDQ P2
AB2 DQ5 P2
AB3 DQ6 P2
AB4 DQ7 P2
AB5 DQ8 P2
AB6 DQ9 P2
AB7 VSS
AB8 NC
AB9 NC
AB10 A0 P2
AB11 A5 P2
AB12 A10 P2
AB13 A15 P2
AB14 A15 P3
AB15 A10 P3
AB16 A5 P3
AB17 A0 P3
AB18 VSS
AB19 VSS
AB20 VSS
AB21 DQ9 P3
AB22 DQ8 P3
AB23 DQ7 P3
AB24 DQ6 P3
AB25 DQ5 P3
AB26 VDDQ P3
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18 AC1 VDDQ P2
AC2 DQ0 P2
AC3 DQ1 P2
AC4 DQ2 P2
AC5 DQ3 P2
AC6 DQ4 P2
AC7 VSS
AC8 NC
AC9 NC
AC10 READYB P2
AC11 A4 P2
AC12 A9 P2
AC13 A14 P2
AC14 A14 P3
AC15 A9 P3
AC16 A4 P3
AC17 READYB P3
AC18 NC
AC19 VSS
AC20 VSS
AC21 DQ4 P3
AC22 DQ3 P3
AC23 DQ2 P3
AC24 DQ1 P3
AC25 DQ0 P3
AC26 VDDQ P3
AD1 B0B P2
AD2 B1B P2
AD3 CE1 P2
AD4 CE0B P2
AD5 CNTRSTB P2
AD6 CNTLDB P2
AD7 CNTINCB P2
AD8 MKRDB P2
AD9 NC
AD10 INTB P2
AD11 A3 P2
AD12 A8 P2
AD13 A13 P2
AD14 A13 P3
AD15 A8 P3
AD16 A3 P3
AD17 INTB P3
AD18 NC
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 10 of 51
Functional Description
The CY7C0452V18/0451V18/0450V18/0431V18/0430V18 is
a family of synchronous true four-ported Datapath Switching
Element (D SE), u p to 27 Gb/s an d 5 Mb density. All fou r ports
may be cl ocked at indepe ndent frequenc ies from one another.
Writes and reads are permitted simultaneously from all four
ports to the switch array. Simultaneous reads are allowed for
accesses to the same address location; however, simulta-
neous re ading and writ ing to the same l ocation is not a llowed.
The QuadPort DSE family can be clocked with synchronous,
pipelined accesses up to 167 MHz. Clock to data valid as low
as tCD = 3.5 ns. Registers on control, address and data lines
allow for minimal set-up and hold time.
The QuadPort DSE family supports a burst counter for block
transfers of data. The QuadPort DSE also supports features
such as: impedance matching, memory block retransmit cap a-
bility, count er address readback, and mask ad dress readb ack.
Burst Counter Operation
Each po rt con tai ns a burst counte r on th e inp ut add ress regis-
ter . Af ter externally loading the counter with th e initial add ress,
the counter will self-increment the address internally (more de-
t ails to fo llow). Th e internal wri te pulse width is indep endent of
the duration o f the R /W input signa l. The internal write pulse is
self-timed to allow the shortest possible cycle times.
Counter enable inputs are provided to block the external ad-
dress input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with an external address when
the port’s Counter Load pi n (C NTLD ) is asserte d LOW. When
the port’s Counter Increment pin (CNTINC) is asserted, the
address counter will increment on each subsequent LOW-to-
HIGH transition of that port’s clock signal. This will read/write
one word from/into each successive address location until
CNTINC is deasserted. The counter can address the entire
memory array and will loop back to the start. Counter Reset
AD19 MKRDB P3
AD20 CNTINCB P3
AD21 CNTLDB P3
AD22 CNTRSTB P3
AD23 CE0B P3
AD24 CE1 P3
AD25 B1B P3
AD26 B0B P3
AE1 DIO P2
AE2 B2B P2
AE3 B3B P2
AE4 MKLDB P2
AE5 RETXB P2
AE6 CNTRDB P2
AE7 WRP0B P2
AE8 VDD
AE9 VDD
AE10 CNTINTB P2
AE11 A2 P2
AE12 A7 P2
AE13 A12 P2
AE14 A12 P3
AE15 A7 P3
AE16 A2 P3
AE17 CNTINTB P3
AE18 VDD
AE19 VDD
AE20 WRP0B P3
AE21 CNTRDB P3
AE22 RETXB P3
AE23 MKLDB P3
AE24 B3B P3
AE25 B2B P3
AE26 DIO P3
AF1 VSS
AF2 AIO P2
AF3 RWB P2
AF4 VDDC
AF5 VDDC
AF6 VDDA P2
AF7 VDDA P2
AF8 VDD
AF9 VDD
AF10 VDDA P2
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18 AF11 VDDA P2
AF12 VDDA P2
AF13 VDDA P2
AF14 VDDA P3
AF15 VDDA P3
AF16 VDDA P3
AF17 VDDA P3
AF18 VDD
AF19 VDD
AF20 VDDA P3
AF21 VDDA P3
AF22 VDDC
AF23 VDDC
AF24 R WB P3
AF25 AIO P3
AF26 VSS
Table 1. 676 BGA Pin Table (CY7C0451V18) (continued)
VSSPIN CY7C0451V18
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 11 of 51
(CNTRST) is used to reset the unmasked portion of burst
counter . A counter-mask register is used to control the counter
wrap. The counter and mask register operations are described
in more detail in the following sections.
The counter or mask register values can be read back on the
bidirectional address lines by activating CNTRD or MKRD, re-
spectively.
Block Retransmit
Retransmit is a feature that allows the reread of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the cou nter unm asked portion reache s it s max imum value set
by the mask register, it will wrap back to the initial value stored
in this “mirror register”. If WRP = 0 the unmasked bit s will wrap
to zero. The mirror register value will be loaded into the
counter when RETX is asserted LOW. When WRP = 1 the
unmas ked bit can w rap to mir ror register. If th e counter i s con-
tinuously configured in increment mode, it will increment again
to its maximum value and wraps back to the value initially
stored into the “mirror re gister ,” thus a llowing the access of the
same d ata repeate dly with out the n eed for a ny ex ternal logi c.
Programmable I/Os
Each port will have two strapping pins that are used to select
the I/ O st andard used b y dat a and ad dress/ contro l. S0 will s et
the I/O standard for data and S1 will set the I/O standard for
address and control. Either LVTTL or SSTL2 Class 1 I/Os will
be selected as shown.
I/O Standard Strapping Codes
Variable Impedance Sense
Anoth er p robl em tha t is often enco unt ered in h igh -sp eed digi-
tal design is what is commonly known as transmission line
effects. Impedance mismatches between devices and the
traces on the PCB cause these effects. These mismatches
cause reflections on the board, which can dramatically impact
a system's ability to transmit data. One of the most common
ways used to solve this problem is to place terminating resis-
tors on each trace on the board. These resistor nets ensure
that the impedance of the device's I/O matches the traces on
the b oard. Th is app roach, t hou gh, can have a huge i mp act on
the amount of board space required in a system. The Quad-
Port D SE solves both problems by allowing the desig ner to set
the imp edance of the I/O driv er to match th e impeda nce of the
on board trac es.
Each port of the QuadPort DSE has a Variable Impedance
Sense (VIS) circuit. The circuit sets the output impedance for
the DQ bus . The cal ibra tio n ci rcuit has on e in put c al led ZQ. A
calibrating resistor (RQ) is connected between ZQ and
grou nd. The va lue of RQ m ust be 5X the value of the int ended
line impedance driven by the QuadPort DSE. The allowable
range of RQ to guarantee impedance matching with a toler-
ance of ±15% is between 175Ω and 500Ω. When MRST is
asserted LOW, the VIS control circuitry is reset and Ready is
deasserted. When MRST is released, the VIS circuit begins
the pr ocess of matchi ng the D Q outpu t impe dance to 0.2*RQ .
Ready will be asserted within 1024 cycles of each port's re-
spective clock. Each port's DQ output impedance is guaran-
teed to b e in the correct r ange when its Ready output is assert-
ed LOW. The output impedance is adjusted to account for
drift s i n supp ly vol tag e and te mp erature every 1 02 4 port cl ock
cycles thereafter. The user may also choose to disable vari-
able impedance matching by connecting ZQ directly to VDD.
When VIS is disabled, The DQ output impedance will be
less-than equal 75Ω.
Variable Impedance Parameters
Strapping Pin Value I/O Standard Selected
0 LVTTL
1 SSTL2
Parameter Minimum Maximum Units Tolerance
RQ Value 175 500 Ω±2%
Output
Impedance 35 100 Ω±15%
Reset Time NA 1024 cycles NA
Update
Time NA 1024 cycles NA
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 12 of 51
Notes:
2. CY7C0431/0430V18 (x 20) has 20 I/O pins instead of 40.
3. CY7C0452/0431V18 (128K) have 17 address bits instead of 16. CY7C0451/0430V18 (64K) have 16 address bits. CY7C0450V18 (32K) has 15 address bits
instead of 16.
4. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
Port-1
Control
Logic
Port 1
Counter/
Mask Reg/
Address
Decode
Port 1
I/O
40
QuadPort DSE
Array
5/2/1 Meg
128/64/32Kx40
128/64Kx20
Port 1 Operation-Control Logic Blocks[2, 3]
Port 4 Logic Blocks[4]
CNTLDP1
CNTINCP1
CNTRSTP1
CNTINTP1
MKRDP1
CNTRDP1
INTP1
I/O0P1-I/O39P1
A0P1–A15P1 16
MRST
C+P1
Port 1
Port 2 Port 3
Port 4
MKLDP1
B0P1
B1P1
B2P1
B3
P1
R/WP1
OEP1
CE
0P1
CE1P1
C-P1
Reset
Logic
TDI TDOTCK
TMS JTAG
Controller
TRST
Port 2 Logic Blocks[4] Port 3 Logic Blocks[4]
ZQP1
WRPP1
RETXP1
AIOP1
DIOP1
DOFF
READY
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 13 of 51
Pin Definitions
Port 1 Port 2 Port 3 Port 4 Description
VSS Ground sup ply for the core, addres s/control, dat a, or
clock.
VDD Power supply for the core.
The user must ensure that VDD ramps simultaneously or
ahead of all other device power supplies.
VDDA P1 VDDA P2 VDDA P3 VDDA P4 Power supply for address/control I/O on port x
VDDQ P1 VDDQ P2 VDDQ P3 VDDQ P4 Power supply for data I/O on port x
VDDC Power supply for clock I/O
VREFA P1 VREFA P2 VREF A P3 VREFA P4 Pins must be co nnected to I/O refere nce voltage if us-
ing SSTL I/O on address/control on port x
VREFQ P1 VREFQ P2 VREFQ P3 VREFQ P4 Pins must b e connec ted to I/O reference voltage if us-
ing SSTL I/O on data on port x
A0P1–A15P1[3]. A0P2–A15P2[3]. A0P3–A15P3[3]. A0P4–A15P4[3].Address Input/Output
DQ0P1–
DQ39P1[2] DQ0P2–
DQ39P2[2] DQ0P3–
DQ39P3[2] DQ0P4–
DQ39P4[2] Data Bus Input/Output
C+P1 C+P2 C+P3 C+P4 Positive Clock Input. C+ is used to capture synchronous
inputs to the device. This input can be free running or
strobed. Maximum clock input rate is fMAX.
C–P1 C–P2 C–P3 C–P4 Negative Clock Input. C– is used to capture synchronous
inputs to the device and must be equal to C frequency.
This in put can be free running or strobed. Maximum cloc k
input rate is fMAX.
DIOP1 DIOP2 DIOP3 DIOP4 Data Pin I/O Standard Select Input. This pin will select
the I/O st andard of the data pins. A HIGH signal will select
the pins to switch at SSTL2 levels. A LOW signal will select
the pins to switch at LVTTL levels. The pins must be
strapped to either VCC or VSS upon power-up.
AIOP1 AIOP2 AIOP3 AIOP4 Address/Control Pin I/O Standard Select Input. This
pin wil l select the I/O st andard of th e address and control
pins. A HIGH signal will select the pins to switch at SSTL2
levels. A LOW signal will select the pins to switch at LVTTL
levels. The pins must be strapped to either VCC or VSS
upon power-up.
B0P1 B0P2 B0P3 B0P4 Byte 0 Select Input. Asserting this signal LOW enables
read and write operations to byte 0. For read operations
both the B0 and OE signals must be asserted to drive
output data on the lower byte of the data pins.
B1P1 B1P2 B1P3 B1P4 Byte 1 Select Input. Same function as B0, but to byte 1.
B2P1[5] B2P[5]2B2P3[5] B2P4[5] Byte 2 Select Input. Same function as B0, but to byte 2.
B3P1[5] B3P2[5] B3P3[5] B3P4[5] Byte 3 Select Input. Same function as B0, but to byte 3.
CE0P1,CE1P1 CE0P2,CE1P2 CE0P3,CE1P3 CE0P4,CE1P4 Chip Enable Input. T o select any port, both CE0 AND CE1
must be asserted to their active states (CE0 ≤ VIL and CE1
≥ VIH).
OEP1 OEP2 OEP3 OEP4 Output Enable I nput. This signal must be asserted LOW
to en able the I/O da ta line s during rea d operat ions. OE is
asynchronous input.
R/WP1 R/WP2 R/WP3 R/WP4 Read/Write Enable Input. This signal is asserted LOW to
write to the QuadPort memory array. For read operations,
assert this pin HIGH.
Note:
5. Not available for CY7C0431/0430V18 (x 20)
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 14 of 51
MRST Master Reset Input. This is one signal for all Ports. MRST
is an asynchronous input. Asserting MRST LOW performs
all of t he reset fu nctions as des cribed in th e text. A MRST
operation must be performed at power-up.
CNTRSTP1[6] CNTRSTP2[6] CNTRSTP3[6] CNTRSTP4[6] Counter Reset Input. Asserting this signal LOW resets
the unmasked portion of the burst address counter of its
respective port to zero. CNTRST is second to MRST in
priority with respect to counter and mask register opera-
tions.
MKLDP1[6] MKLDP2[6] MKLDP3[6] MKLDP4[6] Mask Register Load Input. Asserting this signal LOW
loads the mask register with the external address avail-
able on the address lines. MKLD operation ha s higher pr i-
ority over CNTLD operation.
CNTLDP1[6] CNTLDP2[6] CNTLDP3[6] CNTLDP4[6] Counter Load Input. Asserting this signal LOW loads the
burst counter with the external address present on the
address pins.
CNTINCP1[6] CNTINCP2[6] CNTINCP3[6] CNTINCP4[6] Counter Increment Input. Asserting this signal LOW in-
cremen ts the burs t address c oun ter o f its respectiv e po rt
on each rising edge of C.
CNTRDP1[6] CNTRDP2[6] CNTRDP3[6] CNTRDP4[6] Counter Readback Input. When asserted LOW, the in-
ternal address value of the counter will be read back on
the address lines. During CNTRD operation, both CNTLD
and CNTINC must be HIGH . Counter re adback ope ration
has higher priority over mask register readback operation.
Counter readback operation is independent of port chip
enables. If address readback operation occurs with chip
enable s activ e (CE0 = LO W, CE1 = HIGH), the d at a line s
(I/Os) will be three-stated.
MKRDP1[6] MKRDP2[6] MKRDP3[6] MKRDP4[6] Mask Register Readback Input. When asserted LOW,
the value of the mask register will be readback on address
lines. During mask reg ister readback operation, all
counter and MKLD inputs must be HIGH (see Counter and
Mask Register Operations truth table). Mask register read-
back operation is independent of port chip enabl es. DQ is
three- stated regardless of th e c hip enables. W hen the i n-
ternal counter is driven to the address pins, the DQ pins
are three-stated.
CNTINTP1[6] CNTINTP2[6] CNTINTP3[6] CNTINTP4[6] Counter Interrupt Flag Output. Flag is asserted LOW for
one clock cycle when the counter reaches maximum
count.
INTP1 INTP2 INTP3 INTP4 Interrupt Flag Output. Interrupt permits communications
between all four ports. The upper four memory locations
can be use d for message p assing. Exampl e of operation:
INTP4 is asserted LOW when another port writes to the
mailbox location of Port 4. Flag is cleared when Port 4
reads the contents of its mailbox. The same operation is
applicable to Ports 1, 2, and 3.
WRPP1[6] WRPP2[6] WRPP3[6] WRPP4[6] When the burst coun ter reaches the maximum c ount,
the u nmasked bit s will wrap t o 0 if WRP is asserted LOW .
Otherw ise, the counter will be loa ded with the conten ts of
the mirror register.
RETXP1[6] RETXP2[6] RETXP3[6] RETXP4[6] When RETX is asserted LOW the burst counter is loaded
with the contents of the mirror register.
Note:
6. Not available on CY7C0452V18
Pin Definitions (continued)
Port 1 Port 2 Port 3 Port 4 Description
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 15 of 51
ZQP1 ZQP2 ZQP3 ZQP4 Output Impedance Matching Input. This input is used to
adjust the device data outputs impedance to match the
syste m da ta bus i mpe da nce . O utpu t impedance i s se t to
0.2 x RQ , where RQ is a re si sto r connected between ZQ
and ground. The acceptable resistor values for RQ is
175Ω to 500Ω. Alternately, this pin can be connected di-
rect ly to VDD, which disables impedance matching. This
pin cannot be connected directly to VSS or left floating.
READYP1 READYP2 READYP3 READYP4 Output pin indicates the port is ready for operation.
The DLL has been properly locked to the clock input sig-
nals.
The DLL requires 1024 cycles to lock following a master
reset operation.
DOFFP1 DOFFP2 DOFFP3 DOFFP4 DLL off input pin dis ables the int egra ted Delay Lock ed
Loop c ircuit for the port. DO FF can b e to ggled LOW then
HIGH to reset the DLL for the associated port. That port
will require 1024 cycles for the DLL to relock, but the other
3 ports are unaffe cte d.
TRST JTAG Port Reset
TCK JTAG Test Clock Input. This can be CLK of any port or
an external clock connected to the JTAG TAP.
TDI JTAG Test Data Input. This is the only data input. TDI
inputs will shift data serially in to the selected register.
TDO JTAG Test Data Output. This is the only data output. TDO
transitions occur on the falling edge of TCK. TDO normally
three-stated except when captured data is shifted out of
the JTAG TAP.
TMS JTAG T est Mode Select Input. It controls the advance of
JT AG T AP state machine. S tate machine transitions occur
on the rising edge of TCK.
Pin Definitions (continued)
Port 1 Port 2 Port 3 Port 4 Description
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 16 of 51
Maximum Ratings
(Abov e wh ic h th e us eful life may be i mpaired. F or us er gui de-
lines, not tested.)
Storage Temperature ................................ –40°C to + 125°C
Ambient Temperature with
Power Applied............................................–40°C to + 125°C
Supply Voltage to Ground Potential..............–0.5V to + 1.9V
DC Voltage Applied to
Outputs in High Z State for LVTTL................–0.3V to + 3.9V
DC Input Voltage........ ...... ..... ...... ..... .............–0.3V to + 3.9V
DC Voltage Applied to
Outputs in High Z State for SSTL2................–0.3V to + 2.7V
DC Input Voltage for SSTL2..........................–0.3V to + 2.7V
Output Current into Outpu t s (LO W)..................... ..... ...20 mA
Static Discharge Voltage (HBM)................................>2200V
Static Discharge Voltage (CDM)..................................>750V
Latch-Up Current.....................................................>200 mA
Operating Ranges
Range Ambient
Temperature VDD
Commercial 0°C to +70°C 1.8V ± 5%
Industrial –40°C to +85°C 1.8V ± 5%
Current Characteristics Over the Operating Range
Parameter Description
CY7C0452V18/0451V18/0450V18/0431V18/0430V18
Unit
-167 -133 -100
Typ. Max. Typ. Max. Typ. Max.
ICC Core Operating Current (VDD = Max., IOUT = 0 mA)
Outputs Disabled, CE = VIL, f = fmax 900 1300 700 1100 500 900 mA
ISB Cor e S tandby C urrent (4 Port s CMOS Le vel, 0 ac-
tive) CE1-4 ≥ VIH, f = 0 200 500 150 500 100 500 mA
ICCQ I/O Operating Current per port
(VDDQ = Max, no external load, f = fmax)32 40 29 36 26 32 mA
ISBQ I/O Standby Current per port
(VDDQ = Max, (no ex ternal l oad, f = 0)
OR Outputs Disabled
12 20 12 20 12 20 mA
ICCA Address/ Control Operating Current per port
(VDDA = Max, no external load, f = fmax)24 30 22 27 20 24 mA
ISBA Address/Control Standby Current per port
(VDDA = Max, no external load, f = 0) 12 15 12 15 12 15 mA
ICCC Clock / JTAG Operating Current Total
(VDDC = Max, f = fmax)810810810mA
ISBC Clock / JTAG Standby Current Total
(VDDC = Max, CE1-4 ≥ VIH)810810810mA
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 17 of 51
Electri cal Characteristics
Parameter I/O Type Description
CY7C0452V18/0451V18/0450V18/0431V18/
0430V18 UnitMin. Max.
VDDQ/A SSTL2-Class 1 Supply Voltage 2.3 2.7 V
VREF Reference Voltage 1.15 1.35 V
VTT Termination Voltage VREF – 0.04 VREF + 0.04 V
VIH Input High Voltage VREF + 0.18 VDDQ + 0.3 V
VIL Input Low Voltage (VDDQ = 2.3V–2.7V) –0.3 VREF – 0.18 V
IOZ Outp ut Lea kag e Curren t –100 100 µA
IOH Output Source Current (VDDQ = 2.3V) –7.6 mA
IOL Output Sink Current (VDDQ = 2.3V) 7.6 mA
VDDQ/A LVTTL Supply Voltage 3.0 3.6 V
VIH Input High Voltage 2.0 VDD + 0.3 V
VIL Input Low Voltage –0.3 0.8 V
VOH Output High Voltage (IOH = –8 mA) 2.4 V
VOL Output Low Voltage (IOL = 8 mA) 0.4 V
IOZ Outp ut Lea kag e Curren t –100 100 µA
VDDC LVPECL
(Clocks only) Supply Voltage 3.0 3.6 V
VIH Input High Voltage VDD – 1.2 VDD – 0.85 V
VIL Input Low Voltage VDD – 1.85 VDD – 1.45 V
VIDIF Inpu t Differential Voltag e 600 1000 mV
JTAG TAP Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VOH1 Output HIGH Voltage IOH = –8.0 mA 2.4 V
VOL1 Output LOW Voltage IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
Capacitance
Parameter Description Test Conditions Max. Unit
CIN (ALL PINS) Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V 10 pF
COUT (ALL PINS) Output Capacitance 10 pF
CIN (C PINS) Input Capacitance 15 pF
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 18 of 51
AC Test Load
Note:
7. Test Conditions: C = 10 pF.
VTH =1.5V
OUTPUT
C
(a) Normal Load (LVTTL)
R = 50Ω
Z0 = 50Ω
[7]
3.0V
GND 90% 90%
10%
tr= 1.6 ns tf= 1.6 ns
10%
LVTTL INPUTS
(b) Three-state Delay
VTH =1.5V
OUTPUT
5 pF
R = 50Ω
Z0 = 50Ω
(c) TAP Load
TDO
C= 20 pF
Z0= 50Ω
GND
1.5V
50Ω
VTH =3.3V
OUTPUT
5 pF
R = 50Ω
Z0 = 50Ω
OUTPUT
C
(a) Normal Load (SSTL2 Class 1)
R = 50Ω
Z0 = 50Ω
[7]
SSTL2 INPUTS
RS = 25Ω
MEASURE
POINT
VTT = 0.5 * VDDQ
VSWING ( M AX)
= 1.5V
VIHmin(AC) = VREF + 0.35V
VREF = 1.25V
VILmax(AC) = VREF – 0.35V
SLEW = (VIHMIN(AC) – VILMAX(AC))/deltaT = 1.0 V/ns
deltaTdeltaT
V
DD_CLK
V
SS_CLK
V
IH(MAX)
V
IH(MIN)
V
IL(MAX)
V
IL(MIN)
V
IDIF
t
r
/ t
f
90%
10%
90%
10%
t
r
= Rise Time <= 0.6 ns
t
f
= Fall Time <= 0.6 ns
All timing referenced to C+ and C- crossing
LVPECL Input Waveform
LVPECL INPUTS
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 19 of 51
Switching Characteristics Over the C omm er cia l/Industri al Op era ting Range
Parameter
Description
CY7C0452V18/0451V18/0450V18/0431V18/0430V18
Unit
-167 -133 -100
qualifier Min. Max. Min. Max. Min. Max.
fMAX Maximum Operating Frequency 167 133 100
tCYC Clock Cycle Time 6 7.5 10 ns
tCH Clock HIGH Time 2.7 3.4 4.0 ns
tCL Clock LOW Time 2.7 3.4 4.0 ns
tRClock Rise Time 0.6 0.6 0.6 ns
tFClock Fall Time 0.6 0.6 0.6 ns
tSD Input Data Set-up Time 1.9 2.3 3.0 ns
tHD Input Data Hold Time 0.7 0.7 0.7 ns
tSWRP WRP0 Set-up Time 1.9 2.3 3.0 ns
tHWRP WRP0 Hold Time 0.7 0.7 0.7 ns
tSRT RETX Set-u p Time 1.9 2.3 3.0 ns
tHRT RETX Hold T ime 0.7 0.7 0.7 ns
tSA Address Set-u p Time 1.9 2.3 3.0 ns
tHA Address Hold T ime 0.7 0.7 0.7 ns
tSB Byte Set-up Time 1.9 2.3 3.0 ns
tHB Byte Hold Time 0.7 0.7 0.7 ns
tSC Chip Enable Set-up Time 1.9 2.3 3.0 ns
tHC Chip Enable Hold Time 0.7 0.7 0.7 ns
tSW R/W Set-up Time 1.9 2.3 3.0 ns
tHW R/W Hold Time 0.7 0.7 0.7 ns
tSCLD CNTLD Set-up Time 1.9 2.3 3.0 ns
tHCLD CNTLD Hold Time 0.7 0.7 0. 7 ns
tSCINC CNTINC Set-up Time 1.9 2.3 3.0 ns
tHCINC CNTINC Hold Time 0.7 0.7 0.7 ns
tSCRD CNTRD Set-up Ti me 1.9 2.3 3.0 ns
tHCRD CNTRD Hold Ti me 0.7 0.7 0.7 ns
tSRST CNTRST Set-up T ime 1.9 2.3 3.0 ns
tHRST CNTRST Hold Time 0.7 0.7 0.7 ns
tSMLD MKLD Set-up Time 1.9 2.3 3.0 ns
tHMLD MKLD Hold Time 0.7 0.7 0.7 ns
tSMRD MKRD Set-up Time 1.9 2.3 3.0 ns
tHMRD MKRD Hold Time 0.7 0.7 0.7 ns
tOE Output Enab le to Dat a Valid 5.5 6.5 8.5 ns
tOLZ Output Enable to Low Z 1.0 1.0 1.0 ns
tOHZ Output Enable to High Z 1.0 5.5 1.0 5.5 1.0 8.5 ns
tCA Clock to Counter Addr . Readback V alid 6.0 7.5 10 ns
tAC Address Output Hold After Clock HIGH 1.0 1.0 1.0 ns
tCKHZA Clock High to Address Output High Z 1.0 6.0 1.0 7.5 1.0 10.0 ns
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 20 of 51
tCKLZA Clock High to Address Output Low Z 1.0 1.0 1.0 ns
tCM Clock to Master Register Readback
Valid 6.0 7.5 10 ns
tCD with DLL Clock to DQ Valid 3.5 4 .0 4.5 ns
tDC with DLL DQ/A Ou tpu t Hold After Clock HIGH 1.0 1.0 1.0 ns
tCKLZ with DLL Clock High to DQ/A Output Low Z 0.5 1.0 1.0 ns
tCKHZ with DLL Clock High to DQ/A Output High Z 0.5 3.5 1.0 4.0 1.0 4.5 ns
tCD2 no DLL Clock to DQ Valid (DOFF=0) 4.7 6.0 7.0 ns
tDC2 no DLL DQ/A Output Hold After Clock HIGH
(DOFF=0) 1.0 1.0 1.0 ns
tCKHZ2 no DLL Clock HIGH to DQ/A Output High Z
(DOFF=0) 1.04.71.06.01.07.0ns
tCKLZ2 no DLL Clock HIGH to DQ/A Output Low Z
(DOFF=0) 1.0 1.0 1.0 ns
tCCS Clock to Clock Set-up Time 5.0 6.5 9.0 ns
tSCINT Clock to CNTINT LOW 4.7 6 7 ns
tRCINT Clock to CNTINT HIGH 4.7 6 7 ns
tSINT Clock to INT LOW 7.5 9 10 ns
tRINT Clock to INT HIGH 7.5 9 10 ns
tRS Master Reset Pulse Width 24 30 40 ns
tRSR Master Reset Recovery Time 18 22.5 30 ns
tRSF Master Reset to Outputs
Inactive/High Z 18 22.5 30 ns
tRDY Master Reset Release to Port Ready 1024 1024 1024 Cycles
fJTAG JTAG TAP Controller Frequency 10 10 10 MHz
tTCYC TCK Cycle Time 100 100 100 ns
tTH TCK High Time 40 40 40 ns
tTL TCK Low T ime 40 40 40 ns
tTMSS TMS Set-Up to TCK Rise 10 10 10 ns
tTMSH TMS Hold to TCK Rise 10 10 10 ns
tTDIS TDI Set-Up to TCK Rise 10 10 10 ns
tTDIH TDI Hold to TCK Rise 10 10 10 ns
tTDOV TCK Low to TDO Valid 20.0 20 20.0 ns
tTDOX TCK Low to TDO Invalid 0 0 0 ns
tTRS TRST Pulse Width 24 30 40 ns
Switching Characteristics Over the C ommercial/I ndu strial Opera ting Ran ge (conti nue d)
Parameter
Description
CY7C0452V18/0451V18/0450V18/0431V18/0430V18
Unit
-167 -133 -100
qualifier Min. Max. Min. Max. Min. Max.
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 21 of 51
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
TDO
t
TCYC
t
TMSH
t
TL
t
TH
t
TMSS
t
TDIS
t
TDIH
t
TDOX
t
TDOV
JTAG Timing and Switching Waveforms
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 22 of 51
Switching Waveforms
Notes:
8. A master reset cycle is required after power-up
9. The parameter tS represents the set-up time required for each input
10. At po wer up, TRST must be asserted low for at least tTRS to ensure the TAP controller is in the Test-Logic-Reset state.
Master Re set[8, 9, 10]
C–
C+
MRST
DQ39:0[2]
CNTINT
INT
A16:0[3]
READY
All Control Inputs
tCYC
tCL tCH
tCHCH tCH
tCL
tRS tRSR
tRSF
tS[9]
tRDY
INACTIVE ACTIVE
TRST
tTRS
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 23 of 51
Notes:
11. An is the address for location n. Dn is data written to location n. Qn is the data read from location n.
12. There are 3 cycles of latency for data to reach the DQ bus in response to a read instruction
13. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, M R ST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X
14. CE0 = B3 = B2 = B1 = B0 = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, OE = CNTINC = RETX = WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
Read Cycle[6, 7, 13]
C–
C+
R/W
A16:0[3]
DQ39:0[2]
AnAn+1 An+2 An+3 An+4 An+5
QnQn+1
Qx
Qx-1
Qx-2
Qx-3
tCYC
tCH tCL
tCH tCL
tCHCH tCHC
tSW tHW
tSA tHA
tDC tCD
tSW tHW
tSA tHA
tSD tHD
Writ e Cycle[11, 14]
C–
C+
R/W
A16:0[3]
DQ39:0[2]
AnAn+1 An+2 An+3 An+4
Dn+2
Dn+1
Dn
tCYC
tCH tCL
tCH tCL
tCHCH tCHCH
Dn+3 Dn+4
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 24 of 51
Notes:
15. B1 represents Bank #1 and B2 represents Bank #2. Each bank consists of one QuadPort DSE device. A(B1) = A(B2)
16. CE0(B2) = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, M RS T = CE1(B1) = R/W = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
tCD
tHC
tSC
tHC
tSC
tHA
tSA
tHA
Bank Select Read During Depth Expansion[11, 15, 16]
C–
C+
A16:0(B1)[3]
A16:0(B2)[3]
DQ39:0(B1)[2]
CE0(B1)
CE1(B2)
DQ39:0(B2)[2]
tCYC
tCH tCL
tCH tCL tCHCH
tCHCH
AnAn+1 An+2 An+3 An+4 An+5 An+6
AnAn+1 An+2 An+3 An+4 An+5 An+6
Qn
Qn+1
Qn+2
Qx
Qx-1
Qx-2
Qx3
tSA
tDC
tCD tCKHZ tCKLZ
tCKHZ tCKLZ
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 25 of 51
Note:
17. CE0(B2) = OE = B3 = B2 = B1 = B0 = R/W = CNTLD = VIL, MRST = CE1(B1) = CNTRST = MKLD = VIH,CNTINC = RETX = WRP0 = CNTRD = MKRD= X
Switching Waveforms (continued)
tHC
tSC
tHC
tSC
tHA
tSA
tHA
Bank Select Write During Depth Expansion[11, 15, 17]
C–
C+
A16:0(B1)[3]
A16:0(B2)[3]
DQ39:0(B1)[2]
CE0(B1)
CE1(B2)
DQ39:0(B2)[2]
tCYC
tCH tCL
tCH tCL tCHCH
tCHCH
AnAn+1 An+2 An+3 An+4 An+5 An+6
AnAn+1 An+2 An+3 An+4 An+5 An+6
tSA
DnDn+1 Dn+2 Dn+3 Dn+4 Dn+5 Dn+6
DnDn+1 Dn+2 Dn+3 Dn+4 Dn+5 Dn+6
tHD
tSD
tHD
tSD
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 26 of 51
Notes:
18. When OE = VIL, the last read operation is allowed to complete before the DQ bus is three-stated and the user is allowed to drive write data.
19. Four dummy writes should be issued to accomplish bus turnaround. The fifth write instruction is the first valid write.
20. The address should be held constant during the four dummy writes and first valid write instruction to avoid data corruption.
21. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, M R ST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X
22. OE should be deasserted and tOHZ allowed to elapse before the first write operation is issued.
23. Any read scheduled to complete after OE is asserted will be preempted.
24. CE0 = B3 = B2 = B1 = B0 = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, C NTINC = RETX = WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
Qx-2 Qx-1 Qx
tCKHZ
tCD tSD tHD
tSW tHW
tSA tHA
tSW tHW
tSA tHA
tCL
tCH
tCHCH
tCHCH
tCL
tCH
Dn+2
Dn+1
Dn
AnAn+1 An+2
Ax
Read-to-Write (OE = VIL)[11, 12, 18, 19 , 20, 21]
C–
C+
A16:0[3]
R/W
DQ39:0[2] Qx-3
Qx-4
tCYC
tDC
Ax+2 Ax+3 Ax+4
Qx
tCD
tDC
Dn+4
Dn+3
Dn+2
Dn+1
Dn
Qx-1
Qx-2
An+2 An+3 An+4
An+1
An
tSD tHD
tSW tHW
tSA tHA
tSW tHW
tSA tHA
tCL
tCH
tCHCH
tCHCH
tCL
tCH
Read-to-Write (OE Controlled)[11, 12, 22, 23, 24 ]
C–
C+
A16:0[3]
R/W
DQ39:0[2]
tCYC
OE
tOH
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 27 of 51
Note:
25. CE0 = OE = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
tCD
tHW
tSW
tHB
tSB
tHD
tSD
Byte Enable Write[11, 25]
C–
C+
R/W
A16:0[3]
DQ39:30[2,5]
An
DQ29:20[2,5]
DQ19:10[2]
DQ9:0[2]
tCYC
tCL
tCHCH
tCHCH
B3[5]
B2[5]
B1
B0
0x000
0x000
0x000
0x000
0x3FF
0x3FF
0x3FF
0x3FF
0x155
0x155
0x2AA
0x2AA
0x155
0x3FF
0x2AA
0x000
tCH
tCH tCL
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 28 of 51
Note:
26. CE0 = OE = CNTLD = VIL, MRST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
0x2AA
0x155
0x3FF
0x000
0x2AA
0x155
0x3FF
0x000
tCD
tCKHZ
tSW tHW
tSD
tSB tHB
Byte Enable Read[11, 26]
C–
C+
R/W
A16:0[3]
DQ39:30[2,5]
DQ29:20[2,5]
DQ19:10[2]
DQ9:0[2]
tCYC
tCL
tCHCH
tCHCH
B3[5]
B2[5]
B1
B0
tCH
tCH tCL
tHD
tCKLZ
An
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 29 of 51
Note:
27. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = R/W = CNTRST = MKLD = RETX = VIH, WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
Read with Address Counter Advance[6, 11, 27]
C–
C+
A16:0[3]
DQ39:0[2]
tCYC
tCH tCL
tCH tCL tCHCH
tCHCH
An
Internal address AnAn+3
An+2
An+1
CNTLD
CNTINC
tSA tHA
tSCINC tHCINC
tSCLD tHCLD
Qx-1 Qx
Qx-2 QnQn+1 Qn+2
tCD tDC
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 30 of 51
Note:
28. CE0 = B3 = B2 = B1 = B0 = R/W = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, OE = WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
tHCLD
Write with Address Counter Advance[6, 11, 28]
C–
C+
A16:0[3]
tCYC
tCH tCL
tCH tCL tCHCH
tCHCH
An
Internal address AnAn+3
An+2
An+1
CNTLD
CNTINC
tSA tHA
tSCINC tHCINC
tSCL
DQ39:0[2] DnDn+1 Dn+2 Dn+2 Dn+3 Dn+4 Dn+5
tHD
tSD
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 31 of 51
Notes:
29. Only umasked bits of the burst counter are reset in response to a CNTRST operation. MASK = 0x00FFF.
30. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, R/W = WRP0 = CNTRD = MKRD = X
31. MASK = 0x00FFF.
Switching Waveforms (continued)
Counter Reset[6, 11, 29, 30, 31]
C–
C+
A16:0[3]
tCYC
tCH tCL
tCH tCL tCHCH
tCHCH
OX1755
Internal address 0X17550 0X170010X170000X17551
CNTLD
CNTINC
tHA
CNTRST
tHCINC
tSCINC
0X17002
tHCLD
tHRST
tSRST
R/W
DQ39:0[2] Q17550 Q17551 Q17000
tCD tDC
tSCLD
tSA
tHW
tSW
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 32 of 51
Notes:
32. The internal burst counter reaches its maximum count when each bit is either masked or equal to 1.
33. Each port has a mirror register that loads the external address value in response to a CNTLD ope ra tion.
34. All bits of the mirror register are reset to 0 in response to a MRST ope ra tion.
35. Unmasked bits of the mirror register are reset to 0 in response to a CNTRST operation.
36. The value in the mirror register is unaffected by all other burst counter operations including CNTINC.
37. When WR P0 = VIH, the internal burst counter is loaded with the contents of the mirror register on the cycle after COUNT = maximum count.
38. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, CNTRD = MKRD = X
Switching Waveforms (continued)
tDC
tRCINT
tSCINT
Counter Interrupt (WRP = VIH)[6, 11, 31, 32, 31, 33, 34 , 35, 36, 37, 38]
C–
C+
A16:0[3]
tCYC
tCH tCL
tCH tCL tCHCH
tCHCH
OX17FFC
Internal address 0X17FFC 0X17FFF0X17FFE0X17FFD
CNTLD
CNTNC
tHA
CNTINT
0X17FFC
tHCLD
R/W
DQ39:0[2] Q17FFC Q17FFD Q17FFE
tCD
tSCLD
tSA
tHCINC
tSCINC
tHW
tSW
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 33 of 51
Notes:
39. When WR P0 = VIL, the unmasked bits of the burst counter are reset to 0 on the cycle after COUNT = maximum count.
40. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, CNTRD = MKRD = X
Switching Waveforms (continued)
Counter Interrupt (WRP = VIL)[6, 11, 31, 32, 39, 40]
C–
C+
A16:0[3]
tCYC
tCH tCL
tCH tCL tCHCH
tCHCH
OX17FFC
Internal address 0X17FFC 0X17FFF0X17FFE0X17FFD
CNTLD
CNTNC
tHA
CNTINT
0X17000
tHCLD
tRCINT
tSCINT
R/W
DQ39:0[2] Q17FFC Q17FFD Q17FFE
tCD
tDC
tSCLD
tSA
tHCINC
tSCINC
tHW
tSW
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 34 of 51
Notes:
41. When RET X= VIL, the value in the mirror register is loaded to the burst counter regardless of the counter’s current value.
42. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = VIH, WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
tCHCH
tDC
Forced Retransmit[6, 11, 31, 32, 33, 34, 35, 36, 41, 42]
C–
C+
A16:0[3]
tCYC
tCH tCL
tCH tCL
tCHCH
An
Internal address AnAn
An+2
An+1
CNTLD
CNTINC
tHA
RETX
An+1
tHCLD
tHRT
tSRT
R/W
DQ39:0[2] QnQn+1 Qn+2
tCD
tSCLD
tSA
tHCINC
tSCINC
tHW
tSW
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Note:
43. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = MKLD = RETX = VIH, WRP0 = MKRD = X
Switching Waveforms (continued)
tCKHZ
tCKLZ
tCKHZ
Load and Read Address Counter[6, 11, 43]
C–
C+
A16:0[3]
tCY
tCH tCL
tCH tCL tCHCH
tCHC
An
CNTLD
CNTINC
tHA
CNTRD
tHCINC
tSCIN
tHCLD
tHCRD
tSCR
R/W
DQ39:0[2] QnQn+1 Qn+1
tCD tDC
tSCLD
tSA
An+1
tCKLZ
tCA2
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Note:
44. CE0 = OE = B3 = B2 = B1 = B0 = VIL, MRST = CE1 = CNTRST = CNTLD = CNTINC = RETX = CNTRD = VIH, WRP0 = X
Switching Waveforms (continued)
0x17FF
tCKLZ
tCKHZ
tCKLZ
tCKHZ
tHA
Load and Read Mask Register[6, 11, 44]
C–
C+
A16:0[3]
tCY
tCH tCL
tCH tCL
MKLD
MKRD
tHMLD
tHM-
tSM-
R/W
DQ39:0[2]
tSMLD
tSA tCKHZ
tCKLZ
tCA2
0x17FFC
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Notes:
45. Port 1 Mailbox Address = 0x1FFFF, Port 2 Mailbox Address = 0x1FFFE, Port 3 Mailbox Address = 0x1FFFD, Port Mailbox Address = 0x1FFFC
46. There is one cycle of latency between writing a mailbox location and the INT flag being asserted LOW.
47. There is one cycle of latency between reading a mailbox location and the INT flag being deasserted HIGH.
48. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, M R ST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
0x1FFFE
0x1FFF
Mailbox Interrupt[11, 45 , 46, 47, 48]
C–(P1)
C+(P1)
A16:0(P1)[3]
tCYC
tCH tCL
tCH tCL tCHCH
tCHC
tHA
R/W(P1)
DQ39:0(P1)[2] D1FFFE
tHD
C–(P2)
C+(P2)
tCH tCL
tCH tCL tCHCH
tCHC
A16:0(P2)[3]
R/W(P2)
DQ39:0(P2)[2] Q1FFFE
tCD tDC
INT(P2)
tRINT
tSINT
tHW
tSW
tHA
tSA
tSD
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Notes:
49. If tCCS is not allowed to elapse between the write on Port 1 and the Read on Port 2, the data resulting from the read operation is indeterminate.
50. This waveform applies to write to read operations on any two ports.
51. CE0 = OE = B3 = B2 = B1 = B0 = CNTLD = VIL, M R ST = CE1 = CNTRST = MKLD = VIH, CNTINC = RETX = WRP0 = CNTRD = MKRD = X
Switching Waveforms (continued)
tHA
tDC
tCD
Port 1 Write to Port 2 Read[11, 49, 50, 51]
C–(P1)
C+(P1)
A16:0(P1)[3]
tCYC
tCH tCL
tCH tCL tCHCH
tCHCH
An
tHA
R/W(P1)
DQ39:0(P1)[2] Dn
tHD
tSD
C–(P2)
C+(P2)
tCCS
tCH tCL
tCH tCL tCHCH
tCHCH
A16:0(P2)[3]
R/W(P2)
DQ39:0(P2)[2] Qn
An
tSA
tHW
tSW
tSA
tHW
tSW
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Notes:
52. “X” = “Don’t Care,” “H” = VIH, “L” = VIL.
53. OE is an asynchronous input signal.
54. When CE changes state, deselection and read happen after one cycle of latency.
55. CE0 = OE = VIL; CE1 = R/W = VIH.
56. Count er ope rat i on and mask regist er operati on are indepe nd ent of Ch ip En able s .
Table 2. Read/Write and Enable Operation (Any Port)[52, 53, 54]
Inputs Outputs
OE CCE0CE1R/W I/O0–I/O39 Operation
X H X X High-Z Deselected
X X L X High-Z Deselected
X L H L DIN Write
L L H H DOUT Read
H X L H X High-Z Outputs Disabled
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)[6, 52 , 55, 56 ]
CMRST CNTRST MKLD CNTLD RETX CNTINC CNTRD MKRD Mode Operation
X L X X X X X X X Master
Reset Counter/Address Register Reset and
Mask Register Set (resets entire chip as
per reset state table)
H L X X X X X X Reset Coun ter/ Address Regi ster Reset
H H L X X X X X Load Load of Addres s Lines i nto Ma sk R egi s-
ter
H H H L X X X X Load Load of Address Lines into Counter/Ad-
dress Register
H H H H L X X X Re-
Transmit Load address from Mask Register
H H H H H L X X Incre-
ment Counter Increment
H H H H H H L X Read-
back Readback Counter on Address Lines
H H H H H H H L Read-
back Readback Mask Register on Address
Lines
H H H H H H H H Hold Counter Hold
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Master Reset
The QuadPort DSE has a global asynchronous master reset
input, MRST. A complete device reset can be initiated at any
time by asserting MRST LOW . A master reset cycle is re quired
at power-u p. MRST m ust remain asserted for at least t RS. Ad-
ditionally, MRST should not be released until all power sup-
plies are fully r amp ed and al l po rt c loc k s a re s t ab le. Asserti ng
MRST will have the following effects:
1. Ready is deasserted (driven HIGH).
2. All DQ and address are three-stated. (No effect on
JTAG/TAP signals)
3. The internal burst counter for each port is reset to all 0s.
4. The internal mirror register for each port is reset to all 0s.
5. The internal mask register for each port is set to all 1s (fu lly
unmasked state).
6. All pipel ine c ontrol regis ters wi ll be set to an inac tive st ate.
7. All mailbox and burs t counte r interrup t s will be deasse rted
(driven HIGH).
8. The control circuitry for the internal delay-locked-loops
(DLLs ) and varia ble impedance se nse (VIS) circuitry f or all
ports will be res et.
The circuitry for each port includes a delay-lock-loop (DLL)
and variable impedance sense (VIS). The DLL and VIS circuits
require a fully ramped power supply and stable clock to oper-
ate correctly. Releasing MRST is a signal to QuadPort DSE
that all power supplies have fully ramped and all port clocks
are st able. At this time the DLL loc k sequence and VIS match-
ing procedure will commence. Each port’s READY signal will
be ass erted (LOW) whe n the DLL is l ocked and outp ut imped-
ance matched to 0.2 * RQ. READY will be asserted within
1024 clock cycles of MRST’s release. Releasing MRST has
the foll owin g effects:
1. DLL circuit starts lock procedure.
2. VIS circuit starts matching output impedance.
3. READY for each port is asserted within 1024 clock cycles
of the c lock for the respective port. If bo th the DLL and VIS
circuitry for a port are disabl ed (DOFF = 0 and VIS = V CC),
then the port’s READY is asserted within 2 cloc k cy cle s.
The following operation commences independent of the
READY output st a te.
4. Data and address outputs remain in three-state, but the
three-state control passes to the control pipeline.
5. The burst counter is released from reset.
6. The mirror register is released from reset.
7. The mask register is released from preset.
8. External c on trol in puts are a llo wed to la tch i nto th e control
pipeline.
9. All mailbox and burst counter interrupts are released from
preset.
READY Outputs
The QuadPort DSE output circuitry includes some advanced
features that enhance the user's interface to the DQ bus. Each
port inc ludes an on -board DLL that i s used to red uce all output
timing parameters. Each port also has a VIS circuit that match-
es the DQ output driver impedance to one fifth of an external
calibra tion resisto r (0.2 * RQ). Th e user can use t he VIS circu it
to match the output driver impedance to the board trace im-
pedanc e, wh ich elim inate s the require ment f or exte rnal serie s
matc h res ist ors . Bot h t he DL L a nd V IS c irc uits r equi re a cal i-
bration period. Cal ib rati on c ann ot s t art b efo re the supplies for
each port have ramped and the clock inputs are stable. Both
the DLL and VIS circuits are reset when MRST is asserted.
Calibration of both circuits starts when MRST is released.
When either the DLL or VIS circuits are enabled, the device
will not be fully functional until the calibration period has
elap sed. This is indic ated to the user b y the READY ou tput for
each po rt. When MRST is asserted (LOW), READY is deas-
serted (HIGH). READY will not be asserted until both the DLL
and VIS circuits have completed calibration. READY is guar-
anteed to be asserted within 1024 clock cycles after MRST is
released.
Any operation that results in data being driven to the DQ bus
is prohibited before READY is asserted. All other operations
are allowed during the period between the release of MRST
and the assertion of READY.
The DLL circuit can be disabled by asserting DOFF. The VIS
can be disabled by connection the ZQ input to VDD. If both
circuits are disabled when MRST is asserted, READY will be
asserted within two clock cycles after MRST is released.
Interrupts
The upper four memory locations may be used for message
passing and permit communications between ports. Table 4
shows the interrupt operation for all ports. For the 2-Meg
QuadPo rt DSE, the highest me mory locati on FFFF is the mail-
box for Port 1, FFFE is the mailbox for Port 2, FFFD is the
mailbox for Port 3, and FFFC is the mailbox for Port 4. Table
4 shows that in order to set Port 1 INTP1 flag, a write by any
other port to address FFFF will assert INTP1 LOW. A read of
FFFF loc ation by Port 1 will reset INT P1 HIGH. When one port
writes to the other port’s mailbo x, the Interrupt flag (INT ) of the
port that the mailbox belongs to is asserted LOW . The Interrupt
is reset when the owner (port) of the mailbox reads the con-
tents of the mailbox.
Each port can read the other port’s mailbox without resetting
the in terrupt. If an applicatio n does not requi re message pas s-
ing, INT pins should be treated as no-connect and should be
left floating. When two port s or more write to the same mailbo x
at the same time INT will be asserted but the contents of the
mailbo x are not gua rant eed to be valid.
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Note:
57. During Master Reset the control signals will be set to a de selected read st ate: CE0i = B1i = B2i = B3i = B4i = R/Wi = MKLDi = MKRDi = CNTRDi = CNTRSTi =
CNTLDi = CNTINCi = VIH; CE1i = VIL. The “i” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals.
Table 4. Interrupt Operation Example[57]
Port 1 Port 2 Port 3 Port 4
Function A0P1–15P1 INTP1 A0P2–15P2 INTP2 A0P3–15P3 INTP3 A0P4–15P4 INTP4
Set Port 1 INTP1 Flag X L FFFF XFFFF XFFFF X
Reset Po rt 1 INTP1 Flag FFFF H X X X X X X
Set Port 2 INTP2 Flag FFFE X X L FFFE XFFFE X
Reset Port 2 INTP2 Flag X X FFFE H X X X X
Set Port 3 INTP3 Flag FFFD XFFFD X X L FFFD X
Reset Po rt 3 INTP3 Flag X X X X FFFD H X X
Set Port 4 INTP4 Flag FFFC XFFFC XFFFC X X L
Reset Port 4 INTP4 Flag XXXXXXFFFC H
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Address Counter Control Operations[6]
Counter enable inputs are provided to s tall the operati on of the
address input and utilize the inte rnal address generated by the
internal counter for the fast interleaved memory applications.
A por t’s burst counter is loaded with the port’s Counter Load
pin (CNTLD). When the po rt’s Counte r Increment (CNTINC) is
asserted, the address counter will increment on each transi-
tion of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTINC is
deasserted. Depending on the mask register state, the counter
can address the entire memory array and will loop back to
start. Counter Reset (CNTRST) is used to reset the Burst
Counter (the Mask Register value is unaffected, the unmasked
bits are reset). Wh en using the counter in re adback mo de, the
internal address value of the counter will be read back on the
addr ess lines w hen the Cou nter Readbac k Signal (C NTRD) is
asserted. Figure 1 provides a block diagram of the readback
operation. Table 3 lists con trol signals re quired for cou nter op-
erations. The signals are listed based on their priority. For ex-
ample, Master Reset takes precedence over Counter Reset,
and Co unter Loa d has lo wer pri ority th an Mask R egist er Load
(described below). All counter operations are independent of
Chip Enables (CE0 and CE1).The read back address can be
either of the burst counter or the mask register based on the
levels of Counter Read signal (CNTRD) and Mask Register
Read signal (MKRD). Both signals are synchronized to the
port's clock as shown in Ta b le 3 . Counter read has a higher
priority than mask read.
Addr.
Read
Back
Counter/
Address
Register
CLK
CNTLD = 1
CNTINC = 1
CNTRST = 1
MKLD = 1
MKRD
CNTRD
QuadPort
Array
Mask
Register
Read back
Register
Bidirectional
Address Lines
Figure 1. C ounter and Mask Register Read Back on Address Lines
DSE
RETX = 1
WRP = 1
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Counter-Mask Regist er
The burst counter ha s a m ask register tha t c ont rols w he n a nd
where the counter wraps . An interrupt fla g (CNTINT) is assert-
ed for one clock cycle when the unmasked portion of the
count er a dd res s r e ac hes ma xi mu m cou nt ( all 1s) . The ex am -
ple in Figure 2 sh ow s the co unter mask re gi ste r lo ade d w it h a
mask value of 003F unmasking the first 6 bits with bit “0” as
the LSB and bit “15” as the MSB. The maximum value the
mask register can be loaded with is FFFF. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of XXX8. The “blocked” addresses (in this case,
the 6th address through the 15 th add res s) are lo ade d with an
address but do not increment once loaded. The counter ad-
dress will start at address XXX8. With CNTINC asserted LOW ,
the counter will increment its internal address value till it reach-
es the mask register value of 3F and wraps around the mem-
ory block to location XXX0. Therefore, the counter uses the
mask-register to define wrap-around point. The mask register
of a port is loaded when MKLD (mask register load) for that
port is LO W. When MKRD is L OW, the value of the m as k reg-
ister can be read out on the address lines in a manner similar
to the counter read back operation (see Ta ble 3 for required
conditions).
When the bu rst counter is loa ded wi th an addr ess hig her than
the mask register value, the higher addresses will form the
mask ed portion of th e counter add ress and are called block ed
addresses. The blocked addresses will not be changed or af-
fected by the counter incre ment operation. The only ex ception
is mask register bit 0. It can be masked to allow the address
counter to increment by two. If the mask register bit 0 is loaded
with a lo gi c va lue of “0,” then ad dre ss cou nte r bit 0 is ma sk ed
and can not be changed during counter increment operation.
If the load ed valu e for addre ss cou nter bit 0 is “0,” t he c oun ter
will increment by two and the address values are even. If the
loaded value for address counter bit 0 is “1,” the counter will
increment by two and the address values are odd. This oper-
ation allows the user to achieve an 80-bit interface using any
two ports, where the counter of one port counts even address-
es and the counter of the other port counts odd addresses.
This even-odd address scheme stores one half of an 80-bit
word in even memory locations, and the other half in odd mem-
ory locations. CNTINT will be asserted when the unmasked
portion of the counter reaches its maximum count. Loading
mask regis ter bit 0 with “1” allows th e counter to incre ment the
address value sequentially.
Table 3 groups the operations of the mask register with the
oper ations of the ad dress coun ter . Add ress count er and mask
register signals are all synchronized to the port's clock C+.
Master reset (MRST) is the only asynchrono us signal l isted on
Table 3. Signals are listed based on their priority going from
left column to right column with MRST being the highest. A
LOW o n MR ST will reset the counter register to all zeros and
the mask register to all ones. On the other hand, a LOW on
CNTRST will only clear the address counter register to zeros
and the mask register will remain unaffected.
There are four operations for the counter and mask register:
1. Load operation: When CNTLD or M KLD is LOW, the ad-
dress counter or the mask register is loaded with the ad-
dress value presented at the address lines. This value rang-
es from 0 to FFF F (64K). The mask regi ster load operatio n
has a higher priority over the address counter load opera-
tion.
Note:
58. The “X” in this diagram represents the counter upper-bits.
215 214 2621
2522
242320
215 214 2621
2522
242320
215 214 2621
2522
242320
215 214 2621
2522
242320
H
H
H
L
11
0s 1
01
0101
00
Xs 1
X0
X0X0
11
Xs 1
X1
X1X1
00
Xs 0
X0
X0X0
Blocked Address Counter Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Regis ter = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Figure 2. Programmable Counter-Mask Register Operation[58]
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2. Increment: Once th e addre ss counte r is loaded w ith an ex-
ternal a ddress, the coun ter can intern ally increment the ad-
dress value by asserting CNTINC LOW. The counter c an
address the entire memory array (depend on the value of
the mask register) and loop back to location 0. The incre-
ment operation is second in priority to the load operation.
3. Readback: The intern al value of eithe r the b urst counter or
the mask register can be read out on the address lines when
CNTRD or MKRD is LOW. Counter readback has higher
priority over mask register readback. Counter and mask
register readback have the same latency as memory READ
operations, i.e., three (3) cycles. The address will be valid
after tCA2 (for counter readback) or tCM2 (for mask read-
back) from the port’s third following clock rising edge. Ad-
dress re ad back oper atio n is i ndepen dent of the port’s chip
enables (CE0 and CE1). If address readback occu rs w hil e
the port is enabled (chip enables active), the data lines
(I/Os) will be three-stated, during the cycle the address is
driven from the part.
4. Hold operation: In order to hold the value of the address
counte r at certain a ddress, all signa ls in Table 3 have to be
HIGH. This operation has the least priority. This operation
is useful in many applications where wait states are needed
or whe n th e a ddress is av ai lab le few c ycle s a hea d of dat a.
The count er and mask regi ster op erat ions are to tall y in depen-
dent of port chip enables.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C0452/451/450/431/430V18 incorporates a serial
boundary scan test access port (TAP). This port operates in
accordance with IEEE Standard 1149.1-2001. Note that the
T AP controller functions in a manner that does not conflict with
the operation of other devices using 1149.1 fully compliant
T APs. Th e T AP operates using JEDEC standard 3.3V I/O logic
levels. It is composed of four input connections and one output
connection required by the test logic defined by the standard.
Disabling the JTAG Feature
It is possible to operate the QuadPort DSE without using the
JTAG feature, by setting TRST* to ground (VSS).
Test Access Por t (TAP) – Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are cap t ure d on the ris ing edg e o f TC K. Al l ou tpu t s are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pi n i s u se d to se rial ly in put informa tio n i nto the regis-
ters and can be conn ec ted to the in pu t of a ny of t he re gi ste r s.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Con-
troller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data Out (TDO)
The TDO outp ut pi n is used to serially clock dat a ou t from the
registers. The output is active depending upon the current
sta te of the TAP state mach ine (see TAP Controller Sta te Dia-
gram (FSM )). T he output ch ang es on the fal li ng e dg e o f TC K.
TDO is co nne cte d to th e least sig nif ic ant b it (LSB) o f any reg-
ister.
Test Reset (TRSTB)
This input provides for asynchronous initialization of the TAP
controller. According to IEEE 1149.1-2001 the TAP controller
shall be asynchronously reset to the TEST-Logic_reset con-
troll er st ate when a 0 logic is appl ied to TRST B. TAP initializ a-
tion is independent of system initialization (MRSTB).
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the QuadPort DSE
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded into
the TDI pin on the rising edge of TCK. Data is output on the
TDO pin on the falling edge of TCK.
Instruction Re gis ter
Four-bit instructio ns can be s eri al ly loaded into the ins truc ti on
register. This register is loaded when it is placed between the
TDI an d TDO pi ns as sh ow n i n th e fo llo wing JTAG/BIST Con-
troller diagram. Upon power-up, the instruction register is load-
ed with the IDCODE instruction. It is also loaded with the ID-
CODE instruction if the controller is placed in a reset state as
described in the Test Reset section. When the TAP controller
is in the Capture IR state, th e two leas t significant bits are load-
ed with a binary “01” pattern to allow for fault isolation of the
board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
someti mes a dva nta geous to skip cert ain devic es. The byp ass
registe r is a si ngle-bit register that can be plac ed between TDI
and TDO pins. This allows data to be shifted through the
QuadPort DSE with minimal delay. The bypass register is set
LOW ( VSS) when the BYPASS instruction is executed .
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the QuadPort DSE. The boundary scan register
is loaded with the contents of the QP Input and Output ring
when the T AP co ntroller is in the Captu re-DR state an d is then
placed between the TDI and TDO pins when the controller is
moved to the Shift-DR state. The EXTEST, and SAM-
PLE/PRELOAD instructions can be used to capture the con-
tents of the Input and Output ring.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the QuadPort DSE and can be shifted out when the TAP
control ler is in the Shift-DR st ate. The ID registe r has a vendor
code and other information described in the Identification Reg-
ister Definitions table.
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TAP Instruction Set
Sixteen different instructions are possible with the 4-bit instruc-
tion register. All combinations are listed in Table 6, Instru cti on
Codes. Seven of these instructions (codes) are listed as RE-
SER VED and sho uld not b e us ed. Th e oth er ni ne i nst ruc tion s
are described in detail below. The TAP controller used in this
QuadPort DSE is fully compliant to the 1 149.1 convention. The
TAP controller can be used to load address, data or control
signals into the QuadPort DSE and can preload the Input or
output buffers. The QuadPort DSE implements all of the
1149.1 instructions except INTEST. Table 6 lists all instruc-
tions. I nstructions are loaded into the TAP controller dur ing the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction reg ister through the TDI and TDO pin s.
To exec ute the instruct ion once it is shifted in, the T AP cont rol-
ler needs to be move d into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction that is to be exe-
cuted whenever the instruction register is loaded with all 0s.
EXTEST allows circuitry external to the QuadPort DSE pack-
age to be tested. Boundary-scan register cells at output pins
are used to apply test stimuli , while those at input pi ns capture
test resu lts.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the identification register. It also places the
identification register between the TDI and TDO pins and al-
lows the IDCODE to be shifted out o f the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
when- eve r t he TAP controller is giv en a tes t log ic reset s tate.
High-Z
The High-Z instruction causes the bypass register to be con-
nected bet w een the TDI and TDO p ins w he n th e TAP control-
ler is in a Shift-DR state. It also places all QuadPort DSE out-
puts into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PR ELOAD i s a 1149.1 mandato ry instru ction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
sta te, a snap shot of dat a on the inpu ts an d output pin s is cap-
tured in the boundary scan register. The user must be aware
that the TAP controller clock can only operate at a frequency
up to 10 MHz, while the QuadPort DSE clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Captu re-D R s t ate , an inpu t or out put w ill un derg o a tra nsi tio n.
The TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but there is
no guaran tee as to the value th at will be captu red. Repeat able
results may not be possible. To guarantee that the boundary
scan register will capture the correct value of a signal, the
QuadPo rt D SE signal must be stabilized long eno ugh to me et
the TAP controller’s capture set-up plus hold times. Once the
data is captured, it is possible to shift out the data by putting
the TAP into the Shift-DR state. This places the boundary scan
register between the TDI and TDO pins. If the TAP controller
goes into the Update-DR state, the sampled data will be up-
dated.
BYPASS
When the BYPASS instructio n is l oad ed in the i nstruc tion reg-
ister and the TAP is placed in a Shift-DR state, the bypass
registe r is plac ed between the TDI an d TDO pins . The adv an-
tage of the BYP ASS instruction is that it shortens the boundary
scan path when mul tip le d ev ic es are co nnected toge the r on a
board.
CLAMP
The opti onal CLA MP instruct ion allows the st ate of the s ignals
driven from QuadPort DSE pins to be determined from the
bounda ry-scan regist er while the BYPASS register is selected
as the serial path between TDI and TDO. CLAMP controls
boundary cells to 1 or 0.
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 46 of 51
Tap Controller State Diagram (FSM)[59]
Note:
59. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
TEST-LOGIC
RESET
RUN_TEST/
IDLE SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
01
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 47 of 51
0
3 2 1 0
31 30 29 0
0557
Bypass Register (BYR )
Instruction Register (IR)
Identific ati on R egi ste r (IDR)
Boundary Scan Register (BSR)
TDI
Selection
Circuitry
TCK
TMS
TAP
CONTROLLER
TRST
(MUX)
39 38 37
0
EID Register
63 62 61
0
VIS Register
TDO
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 48 of 51
Note:
60. Instruction that requires a master reset after completion before using the chip in normal mode
Table 5. Scan Regist ers S ize s
Register Name Bit Size
Bypass (BYR) 1
Instruction (IR) 4
Identification (IDR) 32
Electrical Identification Register (EID) 40
Variable Impedance Register (VIS) 64
Boundary Scan (BSR) 558
Table 6. I nstr uc tion Iden tifica tion Codes
Instruction Code Description
Bypass 1111 Places the bypass register (BYR) between TDI and TDO.
Sample/Preload 1000 Captures the Input/Output ring contents. Places the boundary scan register (BSR)
between TDI and TDO.
Extest[60] 0000 Captures the Input/Output ring contents. Places the boundary scan register (BSR)
between the TDI and TDO.
Idcode 1011 Loads the ID register (IDR) with the vendor ID code and places the register be-
tween TDI and TDO.
Clamp[60] 0100 Controls boundary to 1/0. Uses BYR.
Highz[60] 0111 Places t he BYR b etw e en T DI and TDO. Fo rce s all Q ua dPo rt DSE ou tpu t dri ve rs
to a High-Z state.
Intest[60] 0001 Allows testing of the on-chip system logic while the component is assembled on
the board. The test stimuli are shifted in one at a time and applied to the on-chip
system logic.
Eidcode 1001 Loads the Electrical Identification Register (EID) with the vendor Electrical ID code
and places the register between TDI and TDO.
VIS 1010 Loads the Variable Impedance Register (VIS) with the vendor VIS ID code and
places the register between TDI and TDO.
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 49 of 51
Ordering Information
128K x 40 1.8V Synchronous QuadPort DSE
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
167 CY7C0452V18-167BBI BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Industrial
CY7C0452V18-167BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
133 CY7C0452V18-133BBI BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Industrial
CY7C0452V18-133BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
100 CY7C0452V18-100BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
64K x 40 1.8V Synchronous QuadPort DSE
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
167 CY7C0451V18-167BBI BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Industrial
CY7C0451V18-167BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
133 CY7C0451V18-133BBI BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Industrial
CY7C0451V18-133BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
100 CY7C0451V18-100BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
32K x 40 1.8V Synchronous QuadPort DSE
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
167 CY7C0450V18-167BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
133 CY7C0450V18-133BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
100 CY7C0450V18-100BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
128K x 20 1.8V Synchronous QuadPort DSE
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
167 CY7C0431V18-167BBI BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Industrial
CY7C0431V18-167BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
133 CY7C0431V18-133BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
100 CY7C0431V18-100BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
64K x 20 1.8V Synchronous QuadPort DSE
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
167 CY7C0430V18-167BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
133 CY7C0430V18-133BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
100 CY7C0430V18-100BBC BB676
Ball Grid Array (BGA) 27 x 27 mm, 1.0-mm pitch
Commercial
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 50 of 51
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
QuadPort is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
may be the trademarks of their respective holders.
676-Ball FBGA (27 x 27 x 1.6 mm) BB676
51-85125-*B
CY7C0452V18/0451V18/0450V18
CY7C0431V18/0430V18
PRELIMINARY
Document #: 38-06065 Rev. ** Page 51 of 51
Document Title: CY7C0452V18/0451V18/0450V18/0431V18/0430V18 QuadPort™ Datapath Switching Element (DSE)
Family
Document Number: 38-06065
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 117356 08/02/02 OOR New Data Sheet
