IDT72261LA20PFI8 - Integrated Device Technology

DSC-4671/4

JANUARY 2009

IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT72261LA

IDT72271LA

CMOS SuperSync FIFO™

16,384 x 9

32,768 x 9

FEATURES:

••

•Choose among the following memory organizations:

IDT72261LA 16,384 x 9

IDT72271LA 32,768 x 9

••

•Pin-compatible with the IDT72281/72291 SuperSync FIFOs

••

•10ns read/write cycle time (8ns access time)

••

•Fixed, low first word data latency time

••

•Auto power down minimizes standby power consumption

••

•Master Reset clears entire FIFO

••

•Partial Reset clears data, but retains programmable settings

••

•Retransmit operation with fixed, low first word data latency time

••

•Empty, Full and Half-Full flags signal FIFO status

••

•Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

••

•Program partial flags by either serial or parallel means

••

•Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

••

•Output enable puts data outputs into high impedance state

••

•Easily expandable in depth and width

••

•Independent Read and Write clocks (permit reading and writing

simultaneously)

FUNCTIONAL BLOCK DIAGRAM

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

16,384 x 9

32,768 x 9

FLAG

LOGIC

FF/IR

PAF

EF/OR

PAE

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET

LOGIC

WEN WCLK D

-D

MRS

REN

RCLK

OE Q

-Q

OFFSET REGISTER

PRS

FWFT/SI

SEN

4671 drw 01

••

•Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

••

•High-performance submicron CMOS technology

••

•Industrial temperature range (–40°C to +85°C) is available

••

•Green parts available, see ordering information

DESCRIPTION:

The IDT72261LA/72271LA are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.

These FIFOs offer numerous improvements over previous SuperSync

FIFOs, including the following:

••

•The limitation of the frequency of one clock input with respect to the other

has been removed. The Frequency Select pin (FS) has been removed,

thus it is no longer necessary to select which of the two clock inputs,

RCLK or WCLK, is running at the higher frequency.

••

•The period required by the retransmit operation is now fixed and short.

••

•The first word data latency period, from the time the first word is written

to an empty FIFO to the time it can be read, is now fixed and short. (The

variable clock cycle counting delay associated with the latency period found

on previous SuperSync devices has been eliminated on this SuperSync

family.)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

PIN CONFIGURATIONS

TQFP (PN64-1, ORDER CODE: PF)

STQFP (PP64-1, ORDER CODE: TF)

TOP VIEW

DESCRIPTION (CONTINUED)

PIN 1

WEN

SEN

DC(1)

VCC

GND(2)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DNC(3)

GND

DNC(3)

VCC

DNC(3)

GND

DNC(3)

GND

WCLK

PRS

MRS

FWFT/SI

GND

FF/IR

PAF

VCC

PAE

EF/OR

RCLK

REN

VCC

GND

4671 drw 02

NOTES:

1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.

2. This pin may either be tied to ground or left open.

3. DNC = Do Not Connect.

SuperSync FIFOs are particularly appropriate for network, video, telecom-

munications, data communications and other applications that need to buffer

large amounts of data.

The input port is controlled by a Write Clock (WCLK) input and a Write Enable

(WEN) input. Data is written into the FIFO on every rising edge of WCLK when

WEN is asserted. The output port is controlled by a Read Clock (RCLK) input

and Read Enable (REN) input. Data is read from the FIFO on every rising

edge of RCLK when REN is asserted. An Output Enable (OE) input is provided

for three-state control of the outputs.

The frequencies of both the RCLK and the WCLK signals may vary from 0

to fMAX with complete independence. There are no restrictions on the

frequency of one clock input with respect to the other.

There are two possible timing modes of operation with these devices:

IDT Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not

appear on the data output lines unless a specific read operation is

performed. A read operation, which consists of activating REN and enabling

a rising RCLK edge, will shift the word from internal memory to the data output

lines.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

DESCRIPTION (CONTINUED)

Figure 1. Block Diagram of Single 16,384 x 9 and 32,768 x 9 Synchronous FIFO

DATA OUT (Q

- Q

)

DATA IN (D

- D

)

MASTER RESET (MRS)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

IDT

72261LA

72271LA

PARTIAL RESET (PRS)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

RETRANSMIT (RT)

4671 drw 03

HALF FULL FLAG (HF)

SERIAL ENABLE(SEN)

In FWFT mode, the first word written to an empty FIFO is clocked directly

to the data output lines after three transitions of the RCLK signal. A REN

does not have to be asserted for accessing the first word. However,

subsequent words written to the FIFO do require a LOW on REN for

access. The state of the FWFT/SI input during Master Reset determines

the timing mode in use.

For applications requiring more data storage capacity than a single

FIFO can provide, the FWFT timing mode permits depth expansion by

chaining FIFOs in series (i.e. the data outputs of one FIFO are connected

to the corresponding data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),

FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable

Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF

and FF functions are selected in IDT Standard mode. The IR and OR

functions are selected in FWFT mode. HF, PAE and PAF are always

available for use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point

in memory. (See Table I and Table II.) Programmable offsets determine

the flag switching threshold and can be loaded by two methods: parallel or

serial. Two default offset settings are also provided, so that PAE can be

set to switch at 127 or 1,023 locations from the empty boundary and the

PAF threshold can be set at 127 or 1,023 locations from the full boundary.

These choices are made with the LD pin during Master Reset.

For serial programming, SEN together with LD on each rising edge of

WCLK, are used to load the offset registers via the Serial Input (SI). For

parallel programming, WEN together with LD on each rising edge of WCLK,

are used to load the offset registers via Dn. REN together with LD on each rising

edge of RCLK can be used to read the offsets in parallel from Qn regardless

of whether serial or parallel offset loading has been selected.

During Master Reset (MRS) the following events occur: The read and write

pointers are set to the first location of the FIFO. The FWFT pin selects IDT

Standard mode or FWFT mode. The LD pin selects either a partial flag default

setting of 127 with parallel programming or a partial flag default setting of 1,023

with serial programming. The flags are updated according to the timing mode

and default offsets selected.

The Partial Reset (PRS) also sets the read and write pointers to the first

location of the memory. However, the timing mode, partial flag program-

ming method, and default or programmed offset settings existing before

Partial Reset remain unchanged. The flags are updated according to the

timing mode and offsets in effect. PRS is useful for resetting a device in

mid-operation, when reprogramming partial flags would be undesirable.

The Retransmit function allows data to be reread from the FIFO more

than once. A LOW on the RT input during a rising RCLK edge initiates a

retransmit operation by setting the read pointer to the first location of the

memory array.

If, at any time, the FIFO is not actively performing an operation, the chip

will automatically power down. Once in the power down state, the standby

supply current consumption is minimized. Initiating any operation (by

activating control inputs) will immediately take the device out of the power

down state.

The IDT72261LA/72271LA are fabricated using IDT’s high speed sub-

micron CMOS technology.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

Symbol Name I/O Description

D0–D8Data Inputs I Data inputs for a 9-bit bus.

MRS Master Reset I MRS initializes the read and write pointers to zero and sets the output register to all zeroes.

During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of

two programmable flag default settings, and serial or parallel programming of the offset settings.

PRS Partial Reset I PRS initializes the read and write pointers to zero and sets the output method (serial or parallel),

and programmable flag settings are all retained.

RT Retransmit I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets

the EF flag to

LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming

method, existing timing mode or programmable flag settings. RT is useful to reread data from the

first physical location of the FIFO.

FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode. Through/Serial

In After Master Reset, this pin functions as a serial input for loading offset registers

WCLK Write Clock I When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into

the programmable registers for parallel programming, and when enabled by SEN, the rising

edge of WCLK writes one bit of data into the programmable register for serial programming.

WEN Write Enable I WEN enables WCLK for writing data into the FIFO memory and offset registers.

RCLK Read Clock I When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets

from the programmable registers.

REN Read Enable I REN enables RCLK for reading data from the FIFO memory and offset registers.

OE Output Enable I OE controls the output impedance of Qn.

SEN Serial Enable I SEN enables serial loading of programmable flag offsets.

LD Load I During Master Reset, LD selects one of two partial flag default offsets (127 or

1,023) and determines

the flag offset programming method, serial or parallel. After

Master Reset, this pin enables writing to

and reading from the offset registers.

DC Don't Care I This pin must be tied to either VCC or GND and must not toggle after Master Reset.

FF/IR Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory

Input Ready is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space

available for writing to the FIFO memory.

EF/OR Empty Flag/ O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory

Output Ready is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data

available at the outputs.

PAF Programmable O PAF goes LOW if the number of words in the FIFO memory is more than word capacity of the FIFO

Almost-Full Flag minus the full offset value m, which is stored in the Full Offset register. There are two possible default

values for m: 127 or 1,023.

PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the

Almost-Empty Flag Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values for n

can be programmed into the device.

HF Half-Full Flag O HF indicates whether the FIFO memory is more or less than half-full.

Q0–Q8Data Outputs O Data outputs for a 9-bus

VCC Power +5 Volt power supply pins.

GND Ground Ground pins.

PIN DESCRIPTION

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V

Commercial/Industrial

GND Supply Voltage 0 0 0 V

VIH Input High Voltage 2.0 — — V

Commercial/Industrial

VIL(1) Input Low Voltage — — 0.8 V

Commercial/Industrial

TA Operating Temperature 0 — +70 °C

Commercial

TA Operating Temperature –40 — +85 °C

Industrial

Symbol Rating Com’l & Ind’l Unit

VTERM Terminal Voltage –0.5 to +7 V

with respect to GND

TSTG Storage –55 to +125 °C

Temperature

IOUT DC Output Current –50 to +50 mA

NOTES:

1. With output deselected, (OE ≥ VIH).

2. Characterized values, not currently tested.

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; In dustr ial: VCC = 5V ± 10%, T A = – 40°C to +85°C)

Symbol Parameter(1) Conditions Max. Unit

CIN(2) Input VIN = 0V 10 pF

Capacitance

COUT(1,2) Output VOUT = 0V 10 pF

Capacitance

NOTE:

1.5V undershoots are allowed for 10ns once per cycle.

IDT72261LA

IDT72271LA

Commercial and Industrial(1)

tCLK = 10, 15, 20 ns

Symbol Parameter Min. Max. Unit

ILI(2) Input Leakage Current –1 1 µA

ILO(3) Output Leakage Current –10 10 µA

VOH Output Logic “1” Voltage, IOH = –2 mA 2 .4 — V

VOL Output Logic “0” Voltage, IOL = 8 mA — 0 .4 V

ICC1(4,5,6) Active Power Supply Current — 75 mA

ICC2(4,7) Standby Current — 20 mA

NOTES:

1. Industrial temperature range product for the 15ns and 20ns speed grade are available as a standard device.

2. Measurements with 0.4 ≤ VIN ≤ VCC.

3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

4. Tested with outputs disabled (IOUT = 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. Typical ICC1 = 15 + 1.85*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,

CL = capacitive load (in pF).

7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

ABSOLUTE MAXIMUM RATINGS

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING

CONDITIONS

CAPACITANCE

(TA = +25°C, f = 1.0MHz)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

4671 drw 04

1.1K

30pF*

680Ω

D.U.T.

Commercial Commercial & Industrial(2)

IDT72261LA10 IDT72261LA15 IDT72261LA20

IDT72271LA10 IDT72271LA15 IDT72271LA20

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

fSClock Cycle Frequency — 100 — 66.7 — 50 MHz

tAData Access Time 2 8 2 1 0 2 1 2 ns

tCLK Clock Cycle Time 10 — 15 — 20 — ns

tCLKH Clock High Time 4 .5 — 6 — 8 — n s

tCLKL Clock Low Time 4 .5 — 6 — 8 — ns

tDS Data Setup Time 3 — 4 — 5 — ns

tDH Data Hold Time 0 — 1 — 1 — ns

tENS Enable Setup Time 3 — 4 — 5 — ns

tENH Enable Hold Time 0 — 1 — 1 — ns

tLDS Load Setup Time 3 — 4 — 5 — ns

tLDH Load Hold Time 0 — 1 — 1 — ns

tRS Reset Pulse Width(3) 10 — 15 — 20 — ns

tRSS Reset Setup Time 10 — 15 — 20 — ns

tRSR Reset Recovery Time 10 — 1 5 — 2 0 — ns

tRSF Reset to Flag and Output Time — 10 — 15 — 2 0 ns

tFWFT Mode Select Time 0 — 0 — 0 — ns

tRTS Retransmit Setup Time 3 — 4 — 5 — ns

tOLZ Output Enable to Output in Low Z(4) 0 —0— 0—ns

tOE Output Enable to Output Valid 2 6 3 8 3 10 ns

tOHZ Output Enable to Output in High Z(4) 2 638 310ns

tWFF Write Clock to FF or IR —8—10—12ns

tREF Read Clock to EF or OR —8—10—12ns

tPAF Write Clock to PAF —8—10—12ns

tPAE Read Clock to PAE —8—10—12ns

tHF Clock to HF —16—20—22ns

tSKEW1 Skew time between RCLK and WCLK for FF/IR 5—6—10—ns

tSKEW2 Skew time between RCLK and WCLK for PAE and PAF 12 — 15 — 20 — ns

tSKEW3 Skew time between RCLK and WCLK for EF/OR 60 — 60 — 60 — ns

tSKEW4 Skew time between RCLK and WCLK for PAE and PAF 15 — 17 — 25 — ns

for Re-transmit operation

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; In dustr ial: VCC = 5V ± 10%, T A = – 40°C to +85°C)

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

Input Pulse Levels GND to 3.0V

Input Rise/Fall Times 3ns

Input Timing Reference Levels 1.5V

Output Reference Levels 1.5V

Output Load See Figure 1

AC TEST CONDITIONS

Figure 2. Output Load

* Includes jig and scope capacitances.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

If the FIFO is full, the first read operation will cause FF to go HIGH.

Subsequent read operations will cause PAF and HF to go HIGH at the

conditions described in Table 1. If further read operations occur, without

write operations, PAE will go LOW when there are n words in the FIFO,

where n is the empty offset value. Continuing read operations will cause

the FIFO to become empty. When the last word has been read from the

FIFO, the EF will go LOW inhibiting further read operations. REN is ignored

when the FIFO is empty.

When configured in IDT Standard mode, the EF and FF outputs are

double register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be found in Figure

7, 8 and 11.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the

manner outlined in Table 2. To write data into to the FIFO, WEN must be

LOW. Data presented to the DATA IN lines will be clocked into the FIFO

on subsequent transitions of WCLK. After the first write is performed, the

Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill

up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the

FIFO, where n is the empty offset value. The default setting for this value

is stated in the footnote of Table 2. This parameter is also user program-

mable. See section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read

operations were taking place, the HF would toggle to LOW once the

8,194th word for the IDT72261LA and 16,386th word for the IDT72271LA,

respectively was written into the FIFO. Continuing to write data into the

FIFO will cause the PAF to go LOW. Again, if no reads are performed, the

PAF will go LOW after (16,385-m) writes for the IDT72261LA and (32,769-

m) writes for the IDT72271LA, where m is the full offset value. The default

setting for this value is stated in the footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting

further write operations. If no reads are performed after a reset, IR will go

HIGH after D writes to the FIFO. D = 16,385 writes for the 72261LA and

32,769 writes for the IDT72271LA, respectively. Note that the additional

word in FWFT mode is due to the capacity of the memory plus output

If the FIFO is full, the first read operation will cause the IR flag to go LOW.

Subsequent read operations will cause the PAF and HF to go HIGH at the

conditions described in Table 2. If further read operations occur, without

write operations, the PAE will go LOW when there are n + 1 words in the

FIFO, where n is the empty offset value. Continuing read operations will

cause the FIFO to become empty. When the last word has been read from

the FIFO, OR will go HIGH inhibiting further read operations. REN is

ignored when the FIFO is empty.

When configured in FWFT mode, the OR flag output is triple register-

buffered, and the IR flag output is double register-buffered.

Relevant timing diagrams for FWFT mode can be found in Figure 9, 10

and 12.

FUNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH

(FWFT) MODE

The IDT72261LA/72271LA support two different timing modes of opera-

tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The

selection of which mode will operate is determined during Master Reset,

by the state of the FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard

mode will be selected. This mode uses the Empty Flag (EF) to indicate

whether or not there are any words present in the FIFO. It also uses the Full

Flag function (FF) to indicate whether or not the FIFO has any free space

for writing. In IDT Standard mode, every word read from the FIFO,

including the first, must be requested using the Read Enable (REN) and

RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will

be selected. This mode uses Output Ready (OR) to indicate whether or not

there is valid data at the data outputs (Qn). It also uses Input Ready (IR)

to indicate whether or not the FIFO has any free space for writing. In the

FWFT mode, the first word written to an empty FIFO goes directly to Qn

after three RCLK rising edges, REN = LOW is not necessary. Subsequent

words must be accessed using the Read Enable (REN) and RCLK.

Various signals, both input and output signals operate differently de-

pending on which timing mode is in effect.

IDT STANDARD MODE

In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the

manner outlined in Table 1. To write data into to the FIFO, Write Enable

(WEN) must be LOW. Data presented to the DATA IN lines will be clocked

into the FIFO on subsequent transitions of the Write Clock (WCLK). After

the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent

writes will continue to fill up the FIFO. The Programmable Almost-Empty

flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO,

where n is the empty offset value. The default setting for this value is stated

in the footnote of Table 1. This parameter is also user programmable. See

section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read

operations were taking place, the Half-Full flag (HF) would toggle to LOW

once the 8,193th word for IDT72261LA and 16,385th word for IDT72271LA

respectively was written into the FIFO. Continuing to write data into the

FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.

Again, if no reads are performed, the PAF will go LOW after (16,384-m)

writes for the IDT72261LA and (32,768-m) writes for the IDT72271LA. The

offset “m” is the full offset value. The default setting for this value is stated

in the footnote of Table 1. This parameter is also user programmable. See

section on Programmable Flag Offset Loading.

When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further

write operations. If no reads are performed after a reset, FF will go LOW

after D writes to the FIFO. D = 16,384 writes for the IDT72261LA and

32,768 for the IDT72271LA, respectively.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable. The

IDT72261LA/72271LA has internal registers for these offsets. Default

settings are stated in the footnotes of Table 1 and Table 2. Offset values

can be programmed into the FIFO in one of two ways; serial or parallel

loading method. The selection of the loading method is done using the LD

(Load) pin. During Master Reset, the state of the LD input determines

whether serial or parallel flag offset programming is enabled. A HIGH on

LD during Master Reset selects serial loading of offset values and in

addition, sets a default PAE offset value of 3FFH (a threshold 1,023 words

from the empty boundary), and a default PAF offset value of 3FFH (a

threshold 1,023 words from the full boundary). A LOW on LD during Master

Reset selects parallel loading of offset values, and in addition, sets a

default PAE offset value of 07FH (a threshold 127 words from the empty

boundary), and a default PAF offset value of 07FH (a threshold 127 words

from the full boundary). See Figure 3, Offset Register Location and Default

Values.

In addition to loading offset values into the FIFO, it also possible to read

the current offset values. It is only possible to read offset values via parallel

read.

Figure 4, Programmable Flag Offset Programming Sequence, summa-

rizes the control pins and sequence for both serial and parallel program-

ming modes. For a more detailed description, see discussion that follows.

The offset registers may be programmed (and reprogrammed) any time

after Master Reset, regardless of whether serial or parallel programming

has been selected.

Number of

Words in

FIFO

1 to n

(1)

1 to n

(1)

(n+1) to 8,192

8,193 to (16,384-(m+1))

(16,384-m)

(2)

to 16,383

16,384

IDT72261LA IDT72271LA FF PAF HF PAE EF

HHHL L

HHHL H

HHHH H

HHLH H

HLLHH

LLLHH

4671 drw 05

1 to n+1

(1)

1 to n+1

(1)

(n+2) to 16,385

16,386 to (32,769-(m+1))

(32,769-m)

(2)

to 32,768

32,769

IR PAF HF PAE OR

LHHLH

LHHLL

LHHHL

LHL HL

LLL HL

HL L H L

IDT72261LA IDT72271LA

Number of

Words in

FIFO (

(n+1) to 16,384

16,385 to (32,768-(m+1))

(32,768-m)

(2)

to 32,767

32,768

(n+2) to 8,193

8,194 to (16,385-(m+1))

(16,385-m)

(2)

to 16,384

16,385

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE

TABLE 2 — STATUS FLAGS FOR IDT STANDARD MODE

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IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

Figure 4. Programmable Flag Offset Programming Sequence

Figure 3. Offset Register Location and Default Values

EMPTY OFFSET (LSB) REG.

870

EMPTY OFFSET (MSB) REG.

00H

85 0

IDT72261LA ⎯ 16,384 x 9 ⎯ BIT

FULL OFFSET (LSB) REG.

870

FULL OFFSET (MSB) REG.

00H

85 0

DEFAULT VALUE

07FH if LD is LOW at Master Reset

3FFH if LD is HIGH at Master Reset

DEFAULT VALUE

07FH if LD is LOW at Master Reset

3FFH if LD is HIGH at Master Reset

4671 drw 06

IDT72271LA ⎯ 32,768 x 9 ⎯ BIT

EMPTY OFFSET (LSB) REG.

870

EMPTY OFFSET (MSB) REG.

00H

86 0

FULL OFFSET (LSB) REG.

870

FULL OFFSET (MSB) REG.

00H

86 0

DEFAULT VALUE

07FH if LD is LOW at Master Reset

3FFH if LD is HIGH at Master Reset

DEFAULT VALUE

07FH if LD is LOW at Master Reset

3FFH if LD is HIGH at Master Reset

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

WCLK RCLK Selection

X Parallel write to registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

X Parallel read from registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

X X No Operation

X Write Memory

X Read Memory

X X No Operation

4671 drw 07

WEN

REN

1XSerial shift into registers:

28 bits for the 72261LA

SEN

30 bits for the 72271LA

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

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JANUARY 7, 2009

SERIAL PROGRAMMING MODE

If Serial Programming mode has been selected, as described above,

then programming of PAE and PAF values can be achieved by using a

combination of the LD, SEN, WCLK and SI input pins. Programming PAE

and PAF proceeds as follows: when LD and SEN are set LOW, data on

the SI input are written, one bit for each WCLK rising edge, starting with

the Empty Offset LSB and ending with the Full Offset MSB. A total of 28

bits for the IDT72261LA and 30 bits for the IDT72271LA. See Figure 13,

Serial Loading of Programmable Flag Registers, for the timing diagram for

this mode.

Using the serial method, individual registers cannot be programmed

selectively. PAE and PAF can show a valid status only after the complete

set of bits (for all offset registers) has been entered. The registers can be

reprogrammed as long as the complete set of new offset bits is entered.

When LD is LOW and SEN is HIGH, no serial write to the registers can

occur.

Write operations to the FIFO are allowed before and during the serial

programming sequence. In this case, the programming of all offset bits

does not have to occur at once. A select number of bits can be written to

the SI input and then, by bringing LD and SEN HIGH, data can be written

to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH

with LD and SEN restored to a LOW, the next offset bit in sequence is

written to the registers via SI. If an interruption of serial programming is

desired, it is sufficient either to set LD LOW and deactivate SEN or to set

SEN LOW and deactivate LD. Once LD and SEN are both restored to a

LOW level, serial offset programming continues.

From the time serial programming has begun, neither partial flag will be

valid until the full set of bits required to fill all the offset registers has been

written. Measuring from the rising WCLK edge that achieves the above

criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE

will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2.

It is not possible to read the flag offset values in a serial mode.

PARALLEL MODE

If Parallel Programming mode has been selected, as described above,

then programming of PAE and PAF values can be achieved by using a

combination of the LD, WCLK, WEN and Dn input pins. For the

IDT72261LA and the IDT72271LA, programming PAE and PAF proceeds

as follows: when LD and WEN are set LOW, data on the inputs Dn are

written into the Empty Offset LSB Register on the first LOW-to-HIGH

transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK,

data are written into the Empty Offset MSB Register. Upon the third LOW-

to-HIGH transition of WCLK, data are written into the Full Offset LSB

written into the Full Offset MSB Register. The fifth transition of WCLK

writes, once again, to the Empty Offset LSB Register. See Figure 14,

Parallel Loading of Programmable Flag Registers for the IDT72261LA, for

the timing diagram for this mode.

The act of writing offsets in parallel employs a dedicated write offset

and a write should not be performed simultaneously to the offset registers.

A Master Reset initializes both pointers to the Empty Offset (LSB) register.

A Partial Reset has no effect on the position of these pointers.

Write operations to the FIFO are allowed before and during the parallel

programming sequence. In this case, the programming of all offset

registers does not have to occur at one time. One, two or more offset

registers can be written and then by bringing LD HIGH, write operations

can be redirected to the FIFO memory. When LD is set LOW again, and

WEN is LOW, the next offset register in sequence is written to. As an

alternative to holding WEN LOW and toggling LD, parallel programming

can also be interrupted by setting LD LOW and toggling WEN.

Note that the status of a partial flag (PAE or PAF) output is invalid during

the programming process. From the time parallel programming has

begun, a partial flag output will not be valid until the appropriate offset word

has been written to the register(s) pertaining to that flag. Measuring from

the rising WCLK edge that achieves the above criteria; PAF will be valid

after two more rising WCLK edges plus tPAF, PAE will be valid after the next

two rising RCLK edges plus tPAE plus tSKEW2.

The act of reading the offset registers employs a dedicated read offset

Qn pins when LD is set LOW and REN is set LOW. For the IDT72261LA

and the IDT72271LA, data are read via Qn from the Empty Offset LSB

LOW-to-HIGH transition of RCLK, data are read from the Empty Offset

MSB Register. Upon the third LOW-to-HIGH transition of RCLK, data are

read from the Full Offset LSB Register. Upon the fourth LOW-to-HIGH

transition of RCLK, data are read from the Full Offset MSB Register. The

fifth transition of RCLK reads, once again, from the Empty Offset LSB

for the IDT72261LA, for the timing diagram for this mode.

It is permissible to interrupt the offset register read sequence with reads

or writes to the FIFO. The interruption is accomplished by deasserting

REN, LD, or both together. When REN and LD are restored to a LOW level,

reading of the offset registers continues where it left off. It should be noted,

and care should be taken from the fact that when a parallel read of the flag

offsets is performed, the data word that was present on the output lines

Qn will be overwritten.

Parallel reading of the offset registers is always permitted regardless of

which timing mode (IDT Standard or FWFT modes) has been selected.

RETRANSMIT OPERATION

The Retransmit operation allows data that has already been read to be

accessed again. There are two stages: first, a setup procedure that resets

the read pointer to the first location of memory, then the actual retransmit,

which consists of reading out the memory contents, starting at the

beginning of memory.

Retransmit setup is initiated by holding RT LOW during a rising RCLK

edge. REN and WEN must be HIGH before bringing RT LOW. At least one

word, but no more than D - 2 words should have been written into the FIFO

between Reset (Master or Partial) and the time of Retransmit setup.

D = 16,384 for the IDT72261LA and D = 32,768 for the IDT72271LA in IDT

Standard mode. In FWFT mode, D = 16,385 for the IDT72261LA and D

= 32,769 for the IDT72271LA.

If IDT Standard mode is selected, the FIFO will mark the beginning of the

Retransmit setup by setting EF LOW. The change in level will only be

noticeable if EF was HIGH before setup. During this period, the internal

read pointer is initialized to the first location of the RAM array.

When EF goes HIGH, Retransmit setup is complete and read operations

may begin starting with the first location in memory. Since IDT Standard

mode is selected, every word read including the first word following

Retransmit setup requires a LOW on REN to enable the rising edge of

RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the

relevant timing diagram.

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IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

If FWFT mode is selected, the FIFO will mark the beginning of the

Retransmit setup by setting OR HIGH. During this period, the internal read

pointer is set to the first location of the RAM array.

When OR goes LOW, Retransmit setup is complete; at the same time,

the contents of the first location appear on the outputs. Since FWFT mode

is selected, the first word appears on the outputs, no LOW on REN is

necessary. Reading all subsequent words requires a LOW on REN to

enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT

Mode), for the relevant timing diagram.

For either IDT Standard mode or FWFT mode, updating of the PAE, HF

and PAF flags begin with the rising edge of RCLK that RT is setup. PAE

is synchronized to RCLK, thus on the second rising edge of RCLK after RT

is setup, the PAE flag will be updated. HF is asynchronous, thus the rising

edge of RCLK that RT is setup will update HF. PAF is synchronized to

WCLK, thus the second rising edge of WCLK that occurs tSKEW after the

rising edge of RCLK that RT is setup will update PAF. RT is synchronized

to RCLK.

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TEMPERATURE RANGES

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

JANUARY 7, 2009

SIGNAL DESCRIPTION

INPUTS:

DATA IN (D0 - D8)

Data inputs for 9-bit wide data.

CONTROLS:

MASTER RESET (MRS)

A Master Reset is accomplished whenever the MRS input is taken to a

LOW state. This operation sets the internal read and write pointers to the

first location of the RAM array. PAE will go LOW, PAF will go HIGH, and

HF will go HIGH.

If FWFT is LOW during Master Reset then the IDT Standard mode,

along with EF and FF are selected. EF will go LOW and FF will go HIGH.

If FWFT is HIGH, then the First Word Fall Through mode (FWFT), along

with IR and OR, are selected. OR will go HIGH and IR will go LOW.

If LD is LOW during Master Reset, then PAE is assigned a threshold 127

words from the empty boundary and PAF is assigned a threshold 127

words from the full boundary; 127 words corresponds to an offset value of

07FH. Following Master Reset, parallel loading of the offsets is permitted,

but not serial loading.

If LD is HIGH during Master Reset, then PAE is assigned a threshold

1,023 words from the empty boundary and PAF is assigned a threshold

1,023 words from the full boundary; 1,023 words corresponds to an offset

value of 3FFH. Following Master Reset, serial loading of the offsets is

permitted, but not parallel loading.

Parallel reading of the registers is always permitted. (See section

describing the LD pin for further details.)

During a Master Reset, the output register is initialized to all zeroes. A

Master Reset is required after power up, before a write operation can take

place. MRS is asynchronous.

See Figure 5, Master Reset Timing, for the relevant timing diagram.

PARTIAL RESET (PRS)

A Partial Reset is accomplished whenever the PRS input is taken to a

LOW state. As in the case of the Master Reset, the internal read and write

pointers are set to the first location of the RAM array, PAE goes LOW, PAF

goes HIGH, and HF goes HIGH.

Whichever mode is active at the time of Partial Reset, IDT Standard mode

or First Word Fall Through, that mode will remain selected. If the IDT Standard

mode is active, then FF will go HIGH and EF will go LOW. If the First Word

Fall Through mode is active, then OR will go HIGH, and IR will go LOW.

Following Partial Reset, all values held in the offset registers remain

unchanged. The programming method (parallel or serial) currently active

at the time of Partial Reset is also retained. The output register is initialized

to all zeroes. PRS is asynchronous.

A Partial Reset is useful for resetting the device during the course of

operation, when reprogramming partial flag offset settings may not be

convenient.

See Figure 6, Partial Reset Timing, for the relevant timing diagram.

RETRANSMIT (RT)

The Retransmit operation allows data that has already been read to be

accessed again. There are two stages: first, a setup procedure that resets

the read pointer to the first location of memory, then the actual retransmit,

which consists of reading out the memory contents, starting at the

beginning of the memory.

Retransmit setup is initiated by holding RT LOW during a rising RCLK

edge. REN and WEN must be HIGH before bringing RT LOW.