IDT70P5258ML IDT70P525ML IDT70V525ML HIGH-SPEED 8K x 16 TriPort STATIC RAM Features High-speed access - Industrial: 55ns (max.) Low-power operation - IDT70P5258ML and IDT70P525ML Active: 54mW (typ.) Standby: 7.2W (typ.) - IDT70V525ML Active: 450mW (typ.) Standby: 250W (typ.) TriPort architecture allows simultaneous access to the memory from all three ports Fully asynchronous operation from each of the three ports: P1, P2, and P3 IDT70P5258 supports 3.0V and 1.8V I/O's Available in 144-ball 0.5mm-pitch fpBGA Industrial temperature range (-40C to +85C) Functional Block Diagram PORT 2 Address Decode A0P2 - A11P2 BE0P1, BE1P1 R/WP1 OEP1 I/O0P1-I/O15P1 CEP2 PORT 2 I/O Control PORT 1 I/O Control BE0P1, BE1P1 OEP2 I/O0P2-I/O15P2 CEP3 Memory Array A0P1 - A11P1 R/WP2 R/WP3 PORT 3 I/O Control OEP3 PORT 1 Address Decode I/O0P3-I/O15P3 PORT 3 Address Decode BE0P1, BE1P1 R/WP1 Interrupt Control OEP1 INTP1 - P2 INTP1 - P3 CEP2, CEP3 R/WP2, R/WP3 A0P3 - A11P3 OEP2, OEP3 INTP3 - P1 INTP2 - P1 , 5681 drw 01 MARCH 2004 1 (c)2004 Integrated Device Technology, Inc. DSC 5681/2 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range Description The IDT70X525X is a high-speed 8K x 16 TriPort Static RAM designed to be used in systems where multiple access into a common RAM is required. This TriPort Static RAM offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. The IDT70X525X is also designed to be used in systems where onchip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrated or withstand contention when more than one port simultaneously accesses the same TriPort RAM location. The IDT70X525X provides three independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user's responsibility to ensure data integrity when simultaneously accessing the same memory location from mutiple ports. An automatic power down feature, controlled by BE0 and BE1 on Port 1 and CE on Port 2 and on Port 3, permits the on-chip circuitry of each port to enter a very low power standby power mode. The IDT70X525X is packaged in a 144-ball 0.5mm-pitch fpBGA. Pin Configurations(1,2,3) 70(P/V)525XBZ BZ-144 Top View 12/19/03 A1 A2 A3 A4 A5 A6 A7 I/O7P3 I/O6P2 I/O4P3 I/O3P2 I/O1P2 OEP3 R/WP2 B1 B2 B3 B4 B5 B6 B7 I/O7P2 I/O6P3 VDD(1) I/O2P3 I/O0P3 OEP2 CEP3 C1 I/O9P2 D1 C2 Vss D2 C3 C4 C5 D3 D4 D5 I/O10P3 I/O8P2 I/O5P3 I/O3P3 I/O1P3 E1 E2 E3 E4 I/O11P3 I/O11P2 I/O8P3 I/O4P2 F1 F2 F3 F4 E5 V DD F5 I/O12P3 I/O12P2 I/O9P3 VDD(1) VDD(1) G1 G2 G3 G4 I/O15P2 I/O13P3 I/O10P2 I/O13P2 H1 H2 H3 I/O15P3 I/O14P3 I/O14P2 J1 J2 I/O2P1 I/O1P1 K1 K2 J3 VDD K3 I/O3P1 I/O0P1 I/O4P1 L1 L2 C6 C7 I/O5P2 I/O2P2 I/O0P2 R/WP3 CE P2 L3 H4 VDD J4 Vss K4 Vss L4 G5 Vss H5 Vss J5 Vss K5 V DD L5 D7 D6 VDD(1) V DD E6 E7 Vss Vss F6 F7 Vss Vss G6 G7 Vss Vss H6 H7 Vss J6 J7 Vss Vss K6 K7 Vss L6 Vss V DD L7 A8 NC B8 NC C8 D8 Vss E8 Vss F8 Vss G8 Vss H8 Vss J8 VDD K8 VDD L8 M1 M2 VDD M3 M4 M5 M6 M7 M8 I/O9P1 I/O11P1 I/O13P1 I/O15P1 R/WP1 BE1P1 A10 A11 A12 A11P2 A9P2 A 7P2 A6P2 B9 B10 B11 B12 A10P3 A8P3 C9 A 11P3 A10P2 I/O6P1 I/O5P1 I/O8P1 I/O10P1 I/O12P1 I/O14P1 OEP1 BE0P1 I/O7P1 A9 D9 C10 A8P2 D10 A 5P3 A6P3 C11 C12 A5P2 A4P3 D11 D12 A 9P3 A7P3 E9 E10 E11 E12 A3P3 A2P3 A2P2 F11 F12 A0P3 F9 Vss G9 Vss H9 V DD J9 F10 V DD G10 K9 A1P3 G12 A1P2 VDD(1) H10 H11 H12 , VDD INTP3P1 INTP2P1 J11 K10 K11 A2P1 L9 L10 L11 A11P1 J12 A0P1 INTP1P3 INTP1P2 A3P1 M9 A 0P2 G11 A10P1 NC A 3P2 V DD J10 V DD A4P2 A9P1 M10 A 8P1 K12 A 1P1 L12 A7P1 A4P1 M11 M12 A 6P1 A5P1 5681 drw 02 NOTES: 1. VDDQ for 70P5258. 6.42 2 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range Pin Configurations(1,2) Symbol Pin Name A 0P1 - A11P1 Address Lines - Port 1 (Input) A 0P2 - A11P2 Address Lines - Port 2 (Input) A 0P3 - A11P3 Address Lines - Port 3 (Input) I/O0P1 - I/O15P1 Data I/O - Port 1 I/O0P2 - I/O15P2 Data I/O - Port 2 I/O0P3 - I/O15P3 Data I/O - Port 3 R/WP1 Read/Write - Port 1 (Input) R/WP2 Read/Write - Port 2 (Input) R/WP3 Read/Write - Port 3 (Input) CEP2 Chip Enable - Port 2 (Input) CEP3 Chip Enable - Port 3 (Input) OEP1 Output Enable - Port 1 (Input) OEP2 Output Enable - Port 2 (Input) OEP3 Output Enable - Port 3 (Input) BE0P1 Bank Enable 0 - Port 1 (Input) BE1P1 Bank Enable 1 - Port 1 (Input) INTP1 - P2 Interrupt P1 - P2 - Port 1 (Output) INTP1 - P3 Interrupt P1 - P3 - Port 1 (Output) INTP2 - P1 Interrupt P2 - P1 - Port 2 (Output) INTP3 - P1 Interrupt P3 - P1 - Port 3 (Output) V DD Power (Input) V DDQ Port Power Supply (Input)(3,4) V SS Ground (Input) NOTES: 1. All VDD pins must be connected to the power supply. 2. All V SS pins must be connected to the ground supply. 3. IDT70P5258 only. 4. For Port 2 and Port 3. 5681 tbl 01 6.42 3 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range Recommended DC Operating Conditions Symbol Device Port Parameter Min. Typ. Max. 1.7 1.8 1.9 1.7 1.8 1.9 2.7 3 3.3 2.7 3 3.3 ____ ____ ____ ____ ____ ____ 0 0 0 Port 1 1.2 ____ VDD+0.2 Port 2 & 3 2 ____ VDDQ+0.2 70P5258 70P525 VDD All Supply Voltage 70V525 70P5258 Port 2 & 3 70P525 VDDQ VSS N/A 70V525 N/A All All I/O Supply Voltage (1) Ground Unit V V V 70P5258 Input High Voltage VIH V 70P525 All 1.2 ____ VDD+0.2 70V525 All 2 ____ VDD+0.2 Port 1 -0.2 ____ 0.4 Port 2 & 3 -0.2 ____ 0.6 70P5258 Input Low Voltage VIL V 70P525 All -0.2 ____ 0.4 70V525 All -0.2 ____ 0.6 5681 tbl 02 NOTES: 1. The supply voltage for all ports on the IDT70P525 and IDT70V525 is supplied by VDD so there are no VDDQ pins on these devices. 2. VIL > -1.5V for pulse width less than 10ns. 3. VTERM must not exceed VDD + 10% for Port 1 or VDDQ + 10% for Port 2 and Port 3. Capacitance(1) Absolute Maximum Ratings(1) (TA = +25C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) Max Unit Port 1 V IN = 3dV 18 pF Port 2 & 3 V IN = 3dV 9 pF Port 1 VOUT = 3dV 20 pF Port 2 & 3 VOUT = 3dV 11 pF Port 5681 tbl 03 Symbol NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and the output signals switch from 0V to 3V or from 3V to 0V. Rating VTERM(2) Terminal Voltage with Respect to GND TBIAS Temperature Under Bias Industrial Unit -0.5 to VDDMAX + 0.3V V -55 to +125 o C C C TSTG Storage Temperature -65 to +150 o TJN Junction Temperatue +150 o IOUT (for 70V525) DC Output Current 50 mA IOUT (for 70P525 DC Output Current and 70P5258) 20 mA 5681 tbl 05 Maximum Operating Temperature and Supply Voltage(1) Grade Industrial Ambient Temperature -40C to +85C Device VSS VDD 70P525 70P5258 0V 1.8V + 100mV 70V525 0V 3.0V + 300mV NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 10% for Port 1 or VDDQ + 10% for Port 2 and Port 3 for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 10% (Port 1) or VDDQ + 10% (Port 2 and Port 3). 5681 tbl 04 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 6.42 4 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,4) 70P5258 70P525 Ind'l Only Symbol Parameter Test Condition Version CE = VIL, Outputs Open f = fMAX(2) IDD Dynamic Operating Current (Both Ports Active - CMOS Level Inputs) ISB1 Standby Current (Both Ports - CER and CEL = VIH CMOS Level Inputs) f = fMAX(2) ISB2 Standby Current (One Port CMOS Level Inputs) ISB3 ISB4 70V525 Ind'l Only Typ.(1) Max. Typ.(1) Max. Unit 30 50 150 180 mA IND'L L IND'L L .004 .016 5 10 mA CE"A" = VIL and CE"B" = VIH(3), Active Port Outputs Open f = fMAX(2) IND'L L 17 28 90 110 mA Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V f = fMAX(2) IND'L L 4 16 84 150 A Standby Current (One Port CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VDD - 0.2V(3) VIN > VDD - 0.2V or VIN < 0.2V, Active Port Outputs Open f = fMAX(2) IND'L L 17 28 90 110 mA 5681 tbl 06 NOTES: 1. VDD = 1.8V for 70P5258 and 70P525. V DD = 3.0V for 70V525, TA = +25C, and are not production tested. IDD DC = 15mA (typ.) 2. At f = fMAX, address and control lines are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions". 3. For the 70P5258, if Port "A" is Port 1 then Port "B" may be either Port 2 or Port 3. If Port "A" is either Port 2 or Port 3, Port "B" must be Port 1. 4. VDD = 1.8V + 100mV for 70P525 and 70P5258. VDD = 3.0V + 300mV for 70V525. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(2) Symbol ILI ILO Device Port 70P5258 All 70P525 All Parameter Input Leakage Current Min. Max. VDD = 1.8V, VIN = 0V to VDD Test Conditions ____ 1 VDD = 1.8V, VIN = 0V to VDD ____ 1 1 70V525 All VDD = 3.0V, VIN = 0V to VDD ____ 70P5258 All CEx = BEx = VIH, VOUT = 0V to VDD ____ 1 All CEx = BEx = VIH, VOUT = 0V to VDD ____ 1 CEx = BEx = VIH, VOUT = 0V to VDD ____ 1 IOL = +0.1mA ____ 0.2 IOL = +2mA ____ 0.4 70P525 70V525 Output Leakage Current All Port 1 Unit A A 70P5258 Port 2 & 3 VOL Output Low Voltage V 70P525 All IOL = +0.1mA ____ 0.2 70V525 All IOL = +2mA ____ 0.4 IOH = -0.1mA 1.4 ____ IOH = -2mA 2.1 ____ Port 1 70P5258 Port 2 & 3 VOH Output High Voltage V 70P525 All IOH = -0.1mA 1.4 ____ 70V525 All IOH = -2mA 2.1 ____ 5681 tbl 07 NOTE: 1. At VDD < 2.0V input leakages are undefined. 2. VDD = 1.8V + 100mV for 70P525 and 70P5258. V DD = 3.0V + 300mV for 70V525. 6.42 5 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range AC Test Conditions Input Pulse Levels GND to 3.0V/GND to 1.8V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V/0.9V Output Reference Levels 3.3V 1.5V/0.9V Output Load Figures 1, 2 and 3 590 5681 tbl 08 DATAOUT 435 30pF 5681 drw 05 3.0V 1.8V R1 1022 13500 R2 729 10800 Figure 2. AC Output Test Load for the 70V525 5681 tbl 09 3.0V/1.8V 3.3V R1 590 DATAOUT R2 30pF(1) 5pF 435 5681 drw 06 5681 drw 04 Figure3. AC Output Test Load for the 70V525 (for tHZ, tLX, tWZ, t OW) Figure 1. AC Output Test Load for the 70P525 and 70P5258 Timing Waveform of Read Cycle No. 1, Any Port(1) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATA VALID DATA VALID , 5681 drw 07 NOTE: 1. R/W = VIH and CE (or BEX) = VIL. 6.42 6 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage 70X525X Ind'l Only Symbol Parameter Min. Max. Unit Read Cycle Time 55 ____ ns Address Access Time ____ 55 ns Chip Enable Access Time ____ 55 ns tAOE Output Enable Access Time ____ 30 ns tOH Output Hold from Address Change 5 ____ ns tLZ Output Low-Z Time (1,2) 5 tHZ (1,2) READ CYCLE tRC tAA tACE tPU tPD Output High-Z Time Chip Enable to Power Up Time (2) Chip Disable to Power Down Time (2) ____ ns ____ 25 ns 0 ____ ns ____ 55 ns 5681 tb10 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. Timing Waveform of Read Cycle No. 2, Any Port(1, 2) tACE CEx or BEx(3) tAOE OE tLZ tHZ (4) DATAOUT (5) VALID DATA tPU tPD ICC 50% CURRENT 50% ISB , 5681 drw 08 NOTES: 1. R/W = VIH for Read Cycles. 2. Addresses valid prior to or coincident with CE (or BEx) transition LOW. 3. CE for Port 2 or Port 3, BEx for Port 1. 4. Timing depends on which signal is asserted last, CE (or BEx) or OE. 5. Timing depends on which signal is deasserted first, CE (or BEx) or OE. 6.42 7 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage 70X525X Ind'l Only Symbol Parameter Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 55 ____ ns tEW Chip Enable to End-of-Write 45 ____ ns 45 ____ ns ns tAW Address Valid to End-of-Write tAS Address Set-up Time 0 ____ tWP Write Pulse Width(3) 40 ____ ns tWR Write Recovery Time 0 ____ ns 30 ____ ns ____ 25 ns 0 ____ ns ____ 25 ns 0 ____ tDW Data Valid to End-of-Write tHZ Output High-Z Time tDH Data Hold Time tWZ tOW (1,2) (1,2) Write Enable to Output in High-Z Output Active from End-of-Write (1,2) ns 5681 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 6.42 8 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5) tWC ADDRESS tAS(6) tWR(3) tAW CE or BEx tHZ tWP(2) (7) R/W tWZ (7) tLZ tHZ (7) tOW DATAOUT (4) (4) tDW tDH DATAIN 5681 drw 09 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE or BEx (6) tAS (3) (2) tWR tEW R/W tDW tDH DATAIN , 5681 drw 10 NOTES: 1. R/W or CE (or BEx) = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE (or BEx) = V IL and a R/W = VIL. 3. tWR is measured from the earlier of CE (or BEx) or R/W = VIH to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE (or BEx) LOW transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE (or BEx) or R/W. 7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 3). This parameter is guaranteed but is not production tested. 6.42 9 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70X525X Ind'l Only Symbol Parameter Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ ns tWR Write Recovery Time 0 ____ ns tINS Interrupt Set Time ____ 45 ns tINR Interrupt Reset Time ____ 45 ns 5681 tbl 12 Waveform of Interrupt Timing(1) tWC (2) ADDR"A" CE"A" or BEx"A" INTERRUPT SET ADDRESS tAS (3) tWR(4) R/W"A" tINS (3) INT"B" , 5681 drw 12 tRC INTERRUPT CLEAR ADDRESS ADDR"B" CE"B" or BEx"B" (2) tAS (3) OE"B" tINR(3) INT"B" , 5681 drw 13 NOTES: 1. If Port A is Port 1, Port B may be either Port 2 or Port 3. If Port A is either Port 2 or Port 3, Port B must be Port 1. 2. See Interrupt Truth Table II. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 6.42 10 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range Functional Description The IDT70X525X provides three ports with separate control, address, and I/O pins that permit independent access for reads or writes to the two banks of memory. These devices have an automatic power down feature controlled by BE0 and BE1 on Port 1 and CE on Port 2 and Port 3. The CE (or BEX) controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE or BEX = VIH). When Port 1 is enabled, it has access to the full memory. When Port 2 is active it has access to Bank 1 of the memory. When Port 3 is active it has access to Bank 2 of the memory. See Truth Table I for a description of the Read/Write operation. Truth Table I - Read/Write Control PORT 1 PORT 2 or PORT 3 BE0 BE1 R/W CE OE D0-D15 H H X X X Z L H L X X DATA IN L H H X L DATAOUT H L L X X DATA IN Function Port Deselected Data on port written into Memory Bank 0 Data in Memory Bank 0 output on port Data on port written into Memory Bank 1 Data in Memory Bank 1 output on port H L H X L DATAOUT X X X X H Z Outputs Disabled L L X X X X Not Allowed X X X H X Z Port Deselected X X L L X DATA IN X X H L L DATAOUT X X X X H Z Outputs Disabled H H X H X Z BE0 = BE 1 = CEP3 = V IH, Sleep mode Data on port written into Memory Bank (2) Data in Memory Bank (2) output on port 5681 tbl 13 NOTE: 1. Both BE0, and BE1 cannot be active (BEx = VIL) simultaneously. 2. Memory Bank 0 for Port 2. Memory Bank 1 for Port 3. 6.42 11 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range Interrupts when BE1 = VIL, R/W is a "don't care". Port 2's interrupt flag (INTP2 - P1) is asserted when Port 1 writes to memory location FFF (HEX), where a write is defined as BE0 = R/W = VIL. Port 2 clears the interrupt by accessing address location FFF when CE = VIL, R/W is a "don't care". Likewise, Port 3's interrupt flag (INTP3 - P1) is asserted when Port 1 writes to memory location FFF (HEX), where a write is defined as BE1= R/W = VIL. Port 3 clears the interrupt by accessing address location FFF when CE= VIL, R/ W is a "don't care". If the user chooses the interrupt function, a memory location (mailbox or message center) is assigned to each port. Interrupt P1 - P2 of Port 1 (INTP1 - P2) is asserted when Port 2 writes to memory location FFE(HEX), where a write is defined as CE = R/W = VIL per Truth Table II. Port 1 clears the interrupt by accessing address location FFE when BE0 = VIL, R/W is a "don't care". Interrupt P1 - P3 of Port 1 (INTP1 - P3) is asserted when Port 3 writes to memory location FFE (HEX), where a write is defined as CE= R/W = VIL. Port 1 clears the interrupt by accessing address location FFE Truth Table II - Interrupt Flag Port 1 Port 2 or 3 R/W BE0 BE1 OE A11 - A0 INTP1 - P 2 INTP1 - P3 R/W CE OE A11 - A0 INTPx - P 1 L L H X FFF X X X X X X L Set P2 INT Flag X X X X X X X X L L FFF H Reset P2 INT Flag L H L X FFF X X X X X X L Set P3 INT Flag X X X X X X X X L L FFF H Reset P3 INT Flag X X X X X L X L L X FFE X Set P1 INTP1-P2 Flag (1) X L H L FFE H X X X X X X Reset P1 INTP1-P2 Flag X X X X X X L L L X FFE X Set P1 INTP1-P3 Flag (2) X H L L FFE X H X X X X X Reset P1 INTP1-P3 Flag Function 5681 tbl 14 NOTE: 1. Port 2 sets the INTP1 - P2 flag on Port 1 so all signals refer to Port 2. 2. Port 3 sets the INTP1 - P3 flag on Port 1 so all signals refer to Port 3. 6.42 12 IDT70X525XML Low Power 4K x 8 TriPort Static RAM Preliminary Industrial Temperature Range Ordering Information IDT XXXX A 999 A A Device Type Power Speed Package Process/ Temperature Range BZ 144-Ball Ball Grid Array (BZ144-1) 55 Industrial Only L Low Power 70P5258 70P525 70V525 128K (8K x 16) TriPort RAM Speed in nanoseconds 5681 drw 14 Datasheet Document History 10/14/03: 03/23/04: Initial datasheet Page 7 Corrected tOH spec min to 5ns in AC Electrical CharacteristicsTable 10 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 13 for Tech Support: 831-754-4613 DualPortHelp@idt.com