LM4991 www.ti.com SNAS217A - MAY 2004 - REVISED APRIL 2013 LM4991 3W Audio Power Amplifier with Shutdown Mode Check for Samples: LM4991 FEATURES DESCRIPTION * The LM4991 is a mono bridged audio power amplifier capable of delivering 3W of continuous average power into a 3 load with less than 10% THD when powered by a 5V power supply (see Note below). To conserve power in portable applications, the LM4991's micropower shutdown mode (ISD = 0.1A, typ) is activated when VDD is applied to the SHUTDOWN pin. 1 2 * * * * * * Available in Space-Saving WSON and SOIC Packages Ultra Low Current Shutdown Mode Can Drive Capacitive Loads up to 500pF Improved Click and Pop Circuitry Reduces Noises During Turn-On and Turn-Off Transitions 2.2 - 5.5V Operation No Output Coupling Capacitors, Snubber Networks, Bootstrap Capacitors or GainSetting Resistors Required Unity-Gain Stable APPLICATIONS * * * * Wireless and Cellular Handsets PDAs Portable Computers Desktop Computers KEY SPECIFICATIONS * * * Improved PSRR at 217kHz and 1kHz: 64 dB (typ) PO at VDD = 5.0V, 10% THD, 1kHz - LM4991LD (only), 3, 4: 3W (typ), 2.5 W (typ) - All packages, 8 load: 1.5 W (typ) Shutdown current: 0.1A (typ) Boomer audio power amplifiers are designed specifically to provide high power, high fidelity audio output. They require few external components and operate on low supply voltages from 2.2V to 5.5V. Since the LM4991 does not require output coupling capacitors, bootstrap capacitors, or snubber networks, it is ideally suited for low-power portable systems that require minimum volume and weight. Additional LM4991 features include thermal shutdown protection, unity-gain stability, and external gain set. Note: An LM4991LD that has been properly mounted to a circuit board will deliver 3W into 3 (at 10% THD). The other package options for the LM4991 will deliver 1.5W into 8 (at 10% THD). See the Application Information sections for further information concerning the LM4991LD and LM4991M. Connection Diagrams Top View Figure 1. SOIC Package See Package Number D0008A Top View Figure 2. WSON Package See Package Number NGN0008A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2013, Texas Instruments Incorporated LM4991 SNAS217A - MAY 2004 - REVISED APRIL 2013 www.ti.com Typical Application Figure 3. Typical Audio Amplifier Application Circuit These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage 6.0V -65C to +150C Supply Temperature -0.3V to VDD to +0.3V Input Voltage Power Dissipation (3) Internally Limited (4) 2000V ESD Susceptibility ESD Susceptibility (5) 200V Junction Temperature 150C Thermal Resistance (1) (2) (3) (4) (5) (6) JC (LD) (6) 4.3C/W JA (LD) 56C/W JC (MA) 35C/W JA (MA) 140C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics VDD= 5V state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensure for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX-TA)/JA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4991, TJMAX = 150C. For the JA's for different packages, please see theApplication Information section or the Absolute Maximum Ratings section. Human body model, 100pF discharged through a 1.5k resistor. Machine Model, 220pF-240pF discharged through all pins. The given JA is for an LM4991 packaged in an LDC08A with the Exposed-DAP soldered to an exposed 1in2 area of 1oz printed circuit board copper. Operating Ratings Temperature Range TMIN TA TMAX -40C TA +85C 2.2V VDD 5.5V Supply Voltage 2 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 LM4991 www.ti.com SNAS217A - MAY 2004 - REVISED APRIL 2013 Electrical Characteristics VDD = 5V (1) (2) The following specifications apply for VDD = 5V and RL = 8 unless otherwise specified. Limits apply for TA = 25C. LM4991 Parameter IDD Test Conditions Typ (3) Quiescent Power Supply Current VIN = 0V, no Load 3 7 VIN = 0V, RL = 8 4 10 VSHUTDOWN = VDD 0.1 2.0 ISD Shutdown Current VSDIH Shutdown Voltage VSDIL VOS THD = 1% (max), f = 1kHz Output Power Total Harmonic Distortion+Noise PO = 0.5W, f = 1kHz PSRR Power Supply Rejection Ratio (1) (2) (3) (4) (5) A (max) V 1.3 V 5 35 mV (max) (5) 2.38 0.9 W (min) LM4991LD, RL = 4 (5) 2.1 1.3 LM4991LD, RL = 3 (5) LM4991LD, RL = 4 (5) 3 2.5 LM4991, RL = 8 THD+N mA (max) LM4991LD, RL = 3 LM4991, RL = 8 THD+N = 10%, f = 1kHz Units (Limits) 1.5 Output Offset Voltage Po Limit (4) W 1.5 0.2 VRIPPLE = 200mV sine p-p, Input terminated with 10, f = 1kHz 64 % 55 dB (min) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics VDD= 5V state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensure for parameters where no limit is given, however, the typical value is a good indication of device performance. All voltages are measured with respect to the ground pin, unless otherwise specified. Typicals are specified at 25C and represent the parametric norm. Limits are ensured to AOQL (Average Outgoing Quality Level). When driving 3 or 4 loads from a 5V supply, the LM4991LD must be mounted to a circuit board. Electrical Characteristics VDD = 3V (1) (2) The following specifications apply for VDD = 3V and RL = 8 unless otherwise specified. Limits apply for TA = 25C. LM4991 Parameter IDD Test Conditions Typ (3) Limit (4) Units (Limits) Quiescent Power Supply Current VIN = 0V, no Load 3 7 VIN = 0V, RL = 8 4 7 mA (max) ISD Shutdown Current VSHUTDOWN = VDD 0.1 2.0 A (max) VSDIH Shutdown Voltage Input High 1.1 V VSDIL Shutdown Voltage Input Low 0.9 V VOS Output Offset Voltage Po Output Power 5 THD = 1% (max), f = 1kHz RL = 4 RL = 8 THD+N (1) (2) (3) (4) Total Harmonic Distortion+Noise PO = 0.25W, f = 1kHz 35 600 425 0.1 mV (max) mW % Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics VDD= 5V state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensure for parameters where no limit is given, however, the typical value is a good indication of device performance. All voltages are measured with respect to the ground pin, unless otherwise specified. Typicals are specified at 25C and represent the parametric norm. Limits are ensured to AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 3 LM4991 SNAS217A - MAY 2004 - REVISED APRIL 2013 www.ti.com Electrical Characteristics VDD = 3V (1) (2) (continued) The following specifications apply for VDD = 3V and RL = 8 unless otherwise specified. Limits apply for TA = 25C. LM4991 Parameter PSRR Test Conditions Typ (3) Power Supply Rejection Ratio VRIPPLE = 200mV sine p-p, Input terminated with 10, f = 1kHz Electrical Characteristics VDD = 2.6V Units (Limits) Limit (4) 68 dB (1) (2) The following specifications apply for VDD = 2.6V and RL = 8 unless otherwise specified. Limits apply for TA = 25C. LM4991 Parameter IDD Test Conditions Typ (3) Quiescent Power Supply Current VIN = 0V, no Load 2 VIN = 0V, RL = 8 3 VSHUTDOWN = VDD Limits (4) Units (Limits) mA (max) ISD Shutdown Current 0.1 A(max) VSDIH Shutdown Voltage Input High 1 V VSDIL Shutdown Voltage Input Low 0.9 V VOS Output Offset Voltage 5 THD = 1% (max), f = 1kHz Po Output Power THD+N Total Harmonic Distortion+Noise PO = 0.15W, f = 1kHz PSRR Power Supply Rejection Ratio (1) (2) (3) (4) 35 mV (max) RL = 4 400 mW RL = 8 300 % 0.1 VRIPPLE = 200mV sine p-p, Input terminated with 10, f = 1kHz 51 dB Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics VDD= 5V state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensure for parameters where no limit is given, however, the typical value is a good indication of device performance. All voltages are measured with respect to the ground pin, unless otherwise specified. Typicals are specified at 25C and represent the parametric norm. Limits are ensured to AOQL (Average Outgoing Quality Level). External Components Description (Figure 3) Components 4 Functional Description 1. Ri Inverting input resistance that sets the closed-loop gain in conjunction with Rf. This resistor also forms a high pass filter with Ci at fC= 1/(2 RiCi). 2. Ci Input coupling capacitor that blocks the DC voltage at the amplifiers input terminals. Also creates a highpass filter with Ri at fc = 1/(2 RiCi). Refer to the section, PROPER SELECTION OF EXTERNAL COMPONENTS, for an explanation of how to determine the value of Ci. 3. Rf Feedback resistance that sets the closed-loop gain in conjunction with Ri. 4. CS Supply bypass capacitor that provides power supply filtering. Refer to the POWER SUPPLY BYPASSING section for information concerning proper placement and selection of the supply bypass capacitor. 5. CB Bypass pin capacitor that provides half-supply filtering. Refer to the section, PROPER SELECTION OF EXTERNAL COMPONENTS, for information concerning proper placement and selection of CB. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 LM4991 www.ti.com SNAS217A - MAY 2004 - REVISED APRIL 2013 Typical Performance Characteristics LD and MA Specific Characteristics THD+N vs Frequency VDD = 5V, RL = 4, and PO = 1W THD+N vs Output Power VDD = 5V, RL = 4, and f = 1 kHz 1 1 THD+N (%) 10 THD+N (%) 10 0.1 0.01 20 0.1 100 1k 10k 20k 0.01 10m 100m FREQUENCY (Hz) OUTPUT POWER (W) Figure 4. Figure 5. 1 3 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 5 LM4991 SNAS217A - MAY 2004 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics THD+N vs Frequency VDD = 5V, RL = 8, and PO = 500mW THD+N vs Frequency VDD = 3V, RL = 4, and PO = 500mW 1 1 THD+N (%) 10 THD+N (%) 10 0.1 0.1 0.01 20 100 1k 0.01 20 10k 20k 1k 10k 20k FREQUENCY (Hz) Figure 6. Figure 7. THD+N vs Frequency VDD = 3V, RL = 8, and PO = 250mW THD+N vs Frequency VDD = 2.6V, RL = 4, and PO = 150mW 1 1 THD+N (%) 10 THD+N (%) 10 0.1 0.1 0.01 20 100 1k 0.01 20 10k 20k 100 1k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Figure 9. THD+N vs Frequency VDD = 2.6V, RL = 8, and PO = 150mW THD+N vs Output Power VDD = 5V, RL = 8, and f = 1kHz 1 1 THD+N (%) 10 THD+N (%) 10 0.1 0.01 20 6 100 FREQUENCY (Hz) 0.1 100 1k 10k 20k 0.01 10m 100m FREQUENCY (Hz) OUTPUT POWER (W) Figure 10. Figure 11. Submit Documentation Feedback 1 3 Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 LM4991 www.ti.com SNAS217A - MAY 2004 - REVISED APRIL 2013 Typical Performance Characteristics (continued) THD+N vs Output Power VDD = 3V, RL = 4, and f = 1kHz THD+N vs Output Power VDD = 3V, RL = 8, and f = 1kHz 1 1 THD+N (%) 10 THD+N (%) 10 0.1 0.1 0.01 10m 100m 0.01 10m 1 100m 1 OUTPUT POWER (W) OUTPUT POWER (W) Figure 12. Figure 13. THD+N vs Output Power VDD = 2.6V, RL = 4, and f = 1kHz THD+N vs Output Power VDD = 2.6V, RL = 8, and f = 1kHz 1 1 THD+N (%) 10 THD+N (%) 10 0.1 0.1 0.01 10m 100m 0.01 10m 1 100m 500m OUTPUT POWER (W) Figure 14. Figure 15. Power Supply Rejection Ratio (PSRR) vs Frequency VDD = 5V, RL = 8, input 10 terminated Power Supply Rejection Ratio (PSRR) vs Frequency VDD = 5V, RL = 8, input floating 0 0 -10 -10 -20 -20 -30 -30 PSRR LEVEL (dB) PSRR LEVEL (dB) OUTPUT POWER (W) -40 -50 -60 -70 -40 -50 -60 -70 -80 -80 -90 -90 -100 20 100 1k 10k 20k -100 20 FREQUENCY (Hz) 100 1k 10k 20k FREQUENCY (Hz) Figure 16. Figure 17. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 7 LM4991 SNAS217A - MAY 2004 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Power Supply Rejection Ratio (PSRR) vs Frequency VDD = 3V, RL = 8, input floating 0 0 -10 -10 -20 -20 -30 -30 PSRR LEVEL (dB) PSRR LEVEL (dB) Power Supply Rejection Ratio (PSRR) vs Frequency VDD = 3V, RL = 8, input 10 terminated -40 -50 -60 -70 -40 -50 -60 -70 -80 -80 -90 -90 -100 20 100 1k -100 20 10k 20k 100 FREQUENCY (Hz) 10k 20k FREQUENCY (Hz) Figure 19. Power Supply Rejection Ratio (PSRR) vs Frequency VDD = 2.6V, RL = 8, input 10 terminated Power Supply Rejection Ratio (PSRR) vs Frequency VDD = 2.6V, RL = 8, Input Floating 0 0 -10 -10 -20 -20 -30 -30 PSRR LEVEL (dB) PSRR LEVEL (dB) Figure 18. -40 -50 -60 -70 -40 -50 -60 -70 -80 -80 -90 -90 -100 20 -100 20 100 1k 10k 20k FREQUENCY (Hz) 8 1k 100 1k 10k 20k FREQUENCY (Hz) Figure 20. Figure 21. Open Loop Frequency Response, 5V Noise Floor, 5V, 8 80kHz Bandwidth, Input to GND Figure 22. Figure 23. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 LM4991 www.ti.com SNAS217A - MAY 2004 - REVISED APRIL 2013 Typical Performance Characteristics (continued) Power Dissipation vs Output Power, VDD = 5V Power Dissipation vs Output Power, VDD = 3V 0.5 1.4 0.45 : POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 : 1 0.8 0.6 : 0.4 0.2 0.4 0.35 : 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0 0.5 1 1.5 2 2.5 OUTPUT POWER (W) 0 0.2 0.4 0.6 0.8 1 OUTPUT POWER (W) Figure 24. Figure 25. Power Dissipation vs Output Power, VDD = 2.6V Shutdown Hysteresis Voltage VDD = 5V, SD Mode = VDD 0.4 POWER DISSIPATION (W) 0.35 : 0.3 0.25 0.2 : 0.15 0.1 0.05 0 0 0.1 0.2 0.4 0.5 0.3 OUTPUT POWER (W) 0.6 Figure 26. Figure 27. Shutdown Hysteresis Voltage VDD = 3V, SD Mode = VDD Shutdown Hysteresis Voltage VDD = 2.6V, SD Mode = VDD Figure 28. Figure 29. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 9 LM4991 SNAS217A - MAY 2004 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Output Power vs Supply Voltage, RL = 4 Output Power vs Supply Voltage, RL = 8 3 3.5 f = 1kHz f = 1kHz 2.5 OUTPUT POWER (W) OUTPUT POWER (W) 3 2.5 10% THD+N 2 1.5 1% THD+N 1 2 10% THD+N 1.5 1 1% THD+N 500m 500m 0 2.2 3 4 5 0 2.2 5.5 3 5 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 30. Figure 31. Output Power vs Supply Voltage, RL = 16 Output Power vs Supply Voltage, RL = 32 1000 900 1000 900 f=1kHz 800 OUTPUT POWER (mW) OUTPUT POWER (mW) 4 700 10% THD+N 600 500 1% THD+N 400 300 200 100 0 2.2 f=1kHz 800 700 600 500 10% THD+N 400 300 1% THD+N 200 100 3 4 5 0 2.2 5.5 SUPPLY VOLTAGE (V) 3 4 5 5.5 SUPPLY VOLTAGE (V) Figure 32. Figure 33. Frequency Response vs Input Capacitor Size Figure 34. 10 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 LM4991 www.ti.com SNAS217A - MAY 2004 - REVISED APRIL 2013 APPLICATION INFORMATION EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATION The LM4991's exposed-DAP (die attach paddle) package (LD) provides a low thermal resistance between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper traces, ground plane, and surrounding air. The result is a low voltage audio power amplifier that produces 2W at 1% THD with a 4 load. This high power is achieved through careful consideration of necessary thermal design. Failing to optimize thermal design may compromise the LM4991's high power performance and activate unwanted, though necessary, thermal shutdown protection. The LD package must have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad is connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink, and radiation area. Place the heat sink area on either outside plane in the case of a two-sided PCB, or on an inner layer of a board with more than two layers. Connect the DAP copper pad to the inner layer or backside copper heat sink area with 4(2x2) vias. The via diameter should be 0.012in-0.013in with a 1.27mm pitch. Ensure efficient thermal conductivity by plating through the vias. Best thermal performance is achieved with the largest practical heat sink area. If the heatsink and amplifier share the same PCB layer, a nominal 2.5in2 area is necessary for 5V operation with a 4 load. Heatsink areas not placed on the same PCB layer as the LM4991 should be 5in2 (min) for the same supply voltage and load resistance. The last two area recommendations apply for 25C ambient temperature. Increase the area to compensate for ambient temperatures above 25C. The LM4991's power de-rating curve in the Typical Performance Characteristics shows the maximum power dissipation versus temperature. An example PCB layout for the LD package is shown in the Demonstration Board Layout section. Further detailed and specific information concerning PCB layout, fabrication, and mounting an LD (WSON) package is available from Texas Instruments Package Engineering Group under application note AN-1187 (Literature Number SNOA401). PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3 AND 4 LOADS Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependant on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1 trace resistance reduces the output power dissipated by a 4 load from 2.0W to 1.95W. This problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. BRIDGE CONFIGURATION EXPLANATION As shown in Figure 3, the LM4991 has two operational amplifiers internally, allowing for a few different amplifier configurations. The first amplifier's gain is externally configurable; the second amplifier is internally fixed in a unity-gain, inverting configuration. The closed-loop gain of the first amplifier is set by selecting the ratio of Rf to Ri while the second amplifier's gain is fixed. Figure 3 shows that the output of amplifier one serves as the input to amplifier two, which results in both amplifiers producing signals identical in magnitude, but 180 out of phase. Consequently, the differential gain for the IC is AVD= 2 *(Rf/Ri) (1) By driving the load differentially through outputs Vo1 and Vo2, an amplifier configuration commonly referred to as "bridged mode" is established. Bridged mode operation is different from the classical single-ended amplifier configuration where one side of its load is connected to ground. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 11 LM4991 SNAS217A - MAY 2004 - REVISED APRIL 2013 www.ti.com A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closedloop gain without causing excessive clipping, please refer to the AUDIO POWER AMPLIFIER DESIGN section. Another advantage of the differential bridge output is no net DC voltage across load. This results from biasing VO1 and VO2 at the same DC voltage, in this case VDD/2 . This eliminates the coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration forces a single supply amplifier's half-supply bias voltage across the load. The current flow created by the halfsupply bias voltage increases internal IC power dissipation and my permanently damage loads such as speakers. POWER DISSIPATION Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. Equation (2) states the maximum power dissipation point for a bridge amplifier operating at a given supply voltage and driving a specified output load. PDMAX = 4*(VDD)2/(22RL) (2) Since the LM4991 has two operational amplifiers in one package, the maximum internal power dissipation is 4 times that of a single-ended ampifier. Even with this substantial increase in power dissipation, the LM4991 does not require heatsinking under most operating conditions and output loading. From Equation (2), assuming a 5V power supply and an 8 load, the maximum power dissipation point is 625 mW. The maximum power dissipation point obtained from Equation (2) must not be greater than the power dissipation that results from Equation (3): PDMAX = (TJMAX-TA)/JA (3) For the SO package, JA = 140C/W. For the LD package soldered to a DAP pad that expands to a copper area of 1.0in2 on a PCB, the LM4991's JA is 56C/W. TJMAX = 150C for the LM4991. The JA can be decreased by using some form of heat sinking. The resultant JA will be the summation of the JC, CS, and SA. JC is the junction to case of the package (or to the exposed DAP, as is the case with the LD package), CS is the case to heat sink thermal resistance and SA is the heat sink to ambient thermal resistance. By adding additional copper area around the LM4991, the JA can be reduced from its free air value for the SO package. Increasing the copper area around the LD package from 1.0in2 to 2.0in2 area results in a JA decrease to 46C/W. Depending on the ambient temperature, TA, and the JA, Equation (3) can be used to find the maximum internal power dissipation supported by the IC packaging. If the result of Equation (2) is greater than that of Equation (3), then either the supply voltage must be decreased, the load impedance increased, the JA decreased, or the ambient temperature reduced. For the typical application of a 5V power supply, with an 8 load, and no additional heatsinking, the maximum ambient temperature possible without violating the maximum junction temperature is approximately 61C provided that device operation is around the maximum power dissipation point and assuming surface mount packaging. For the LD package in a typical application of a 5V power supply, with a 4 load, and 1.0in2 copper area soldered to the exposed DAP pad, the maximum ambient temperature is approximately 77C providing device operation is around the maximum power dissipation point. Internal power dissipation is a function of output power. If typical operation is not around the maximum power dissipation point, the ambient temperature can be increased. Refer to the Typical Performance Characteristics curves for power dissipation information for different output powers and output loading. POWER SUPPLY BYPASSING As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the LM4991 as possible. The capacitor connected between the bypass pin and ground improves the internal bias voltage's stability, producing improved PSRR. The improvements to PSRR increase as the bypass pin capacitor increases. Typical applications employ a 5V regulator with 10F and a 0.1F bypass capacitors which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of the LM4991 with a 1F tantalum capacitor. The selection of bypass capacitors, especially CB, is dependent upon PSRR requirements, click and pop performance as explained in the section, PROPER SELECTION OF EXTERNAL COMPONENTS, system cost, and size constraints. 12 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 LM4991 www.ti.com SNAS217A - MAY 2004 - REVISED APRIL 2013 SHUTDOWN FUNCTION In order to reduce power consumption while not in use, the LM4991 contains a shutdown pin to externally turn off the amplifier's bias circuitry. This shutdown feature turns the amplifier off when a logic high is placed on the shutdown pin. The trigger point between a logic low and logic high level is typically half- supply. It is best to switch between ground and supply to provide maximum device performance. By switching the shutdown pin to VDD, the LM4991 supply current draw will be minimized in idle mode. While the device will be disabled with shutdown pin voltages less then VDD, the idle current may be greater than the typical value of 0.1A. In either case, the shutdown pin should be tied to a definite voltage to avoid unwanted state changes. In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry which provides a quick, smooth transition into shutdown. Another solution is to use a single-pole, single-throw switch in conjunction with an external pull-up resistor. When the switch is closed, the shutdown pin is connected to ground and enables the amplifier. If the switch is open, then the external pull-up resistor will disable the LM4991. This scheme ensures that the shutdown pin will not float thus preventing unwanted state changes. PROPER SELECTION OF EXTERNAL COMPONENTS Proper selection of external components in applications using integrated power amplifiers is critical to optimize device and system performance. While the LM4991 is tolerant of external component combinations, consideration to component values must be used to maximize overall system quality. The LM4991 is unity-gain stable which gives a designer maximum system flexibility. The LM4991 should be used in low gain configurations to minimize THD+N values, and maximize the signal to noise ratio. Low gain configurations require large input signals to obtain a given output power. Input signals equal to or greater than 1 Vrms are available from sources such as audio codecs. Please refer to the section, AUDIO POWER AMPLIFIER DESIGN, for a more complete explanation of proper gain selection. Besides gain, one of the major considerations is the closed-loop bandwidth of the amplifier. To a large extent, the bandwidth is dictated by the choice of external components shown in Figure 3. The input coupling capacitor, Ci, forms a first order high pass filter which limits low frequency response. This value should be chosen based on needed frequency response for a few distinct reasons. Selection Of Input Capacitor Size Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 100Hz to 150Hz. Thus, using a large input capacitor may not increase actual system performance. In addition to system cost and size, click and pop performance is effected by the size of the input coupling capacitor, Ci. A larger input coupling capacitor requires more charge to reach its quiescent DC voltage (nominally 1/2 VDD). This charge comes from the output via the feedback and is apt to create pops upon device enable. Thus, by minimizing the capacitor size based on necessary low frequency response, turn-on pops can be minimized. Besides minimizing the input capacitor size, careful consideration should be paid to the bypass capacitor value. Bypass capacitor, CB, is the most critical component to minimize turn-on pops since it determines how fast the LM4991 turns on. The slower the LM4991's outputs ramp to their quiescent DC voltage (nominally 1/2 VDD), the smaller the turn-on pop. Choosing CB equal to 1.0F along with a small value of Ci (in the range of 0.1F to 0.39F), should produce a virtually clickless and popless shutdown function. While the device will function properly, (no oscillations or motorboating), with CB equal to 0.1F, the device will be much more susceptible to turn-on clicks and pops. Thus, a value of CB equal to 1.0F is recommended in all but the most cost sensitive designs. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 13 LM4991 SNAS217A - MAY 2004 - REVISED APRIL 2013 www.ti.com AUDIO POWER AMPLIFIER DESIGN Design a 1W/8 Audio Amplifier Given: Power Output 1 Wrms Load Impedance 8 Input Level 1 Vrms Input Impedance 20 k Bandwidth 100 Hz-20 kHz 0.25 dB A designer must first determine the minimum supply rail to obtain the specified output power. By extrapolating from the Output Power vs Supply Voltage graphs in theTypical Performance Characteristics section, the supply rail can be easily found. A second way to determine the minimum supply rail is to calculate the required Vopeak using Equation (3) and add the output voltage. Using this method, the minimum supply voltage would be (Vopeak + (VODTOP + VODBOT)), where VODBOT and VODTOP are extrapolated from the Dropout Voltage vs Supply Voltage curve in the Typical Performance Characteristics section. (4) Using the Output Power vs Supply Voltage graph for an 8 load, the minimum supply rail is 4.6V. But since 5V is a standard voltage in most applications, it is chosen for the supply rail. Extra supply voltage creates headroom that allows the LM4991 to reproduce peaks in excess of 1W without producing audible distortion. At this time, the designer must make sure that the power supply choice along with the output impedance does not violate the conditions explained in the POWER DISSIPATION section. Once the power dissipation equations have been addressed, the required differential gain can be determined from Equation (4). (5) (6) Rf/Ri = AVD/2 From Equation (4), the minimum AVD is 2.83; use AVD = 3. Since the desired input impedance was 20k, and with a AVD impedance of 2, a ratio of 1.5:1 of Rf to Ri results in an allocation of Ri = 20k and Rf = 30k. The final design step is to address the bandwidth requirements which must be stated as a pair of -3dB frequency points. Five times away from a -3dB point is 0.17dB down from passband response which is better than the required 0.25dB specified. fL = 100Hz/5 = 20Hz fH = 20kHz * 5 = 100kHz As stated in the External Components Description section, Ri in conjunction with Ci create a highpass filter. Ci 1/(2*20k*20Hz) = 0.397F; use 0.39F The high frequency pole is determined by the product of the desired frequency pole, fH, and the differential gain, AVD. With a AVD = 3 and fH = 100kHz, the resulting GBWP = 150kHz which is much smaller than the LM4991 GBWP of 4MHz. This figure displays that if a designer has a need to design an amplifier with a higher differential gain, the LM4991 can still be used without running into bandwidth limitations. 14 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 LM4991 www.ti.com SNAS217A - MAY 2004 - REVISED APRIL 2013 REVISION HISTORY Changes from Original (April 2013) to Revision A * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LM4991 15 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM4991LD/NOPB ACTIVE WSON NGN 8 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 L4991 LM4991LDX/NOPB ACTIVE WSON NGN 8 4500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 L4991 LM4991MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LM49 91MA LM4991MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LM49 91MA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM4991LD/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM4991LDX/NOPB WSON NGN 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM4991MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4991LD/NOPB WSON NGN 8 1000 210.0 185.0 35.0 LM4991LDX/NOPB WSON NGN 8 4500 367.0 367.0 35.0 LM4991MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE NGN0008A WSON - 0.8 mm max height SCALE 3.000 PLASTIC SMALL OUTLINE - NO LEAD 4.1 3.9 A B PIN 1 INDEX AREA 4.1 3.9 PIN 1 ID DETAIL A PIN 1 ID C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C 2.2 0.05 EXPOSED THERMAL PAD SYMM (0.2) TYP 6X 0.8 4 5 2X 2.4 SYMM 9 3 0.05 SEE DETAIL A 8 1 8X (0.25) (0.25) PIN 1 ID (0.2) 8X 0.6 0.4 0.35 0.25 0.1 0.05 (0.15) C A B C 4214794/A 11/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT NGN0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (2.2) SYMM 8X (0.5) 1 8 8X (0.3) SYMM 9 (3) (1.25) 6X (0.8) 4 (R0.05) TYP 5 ( 0.2) VIA TYP (0.85) (3.3) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND EXPOSED METAL SOLDER MASK OPENING METAL EXPOSED METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4214794/A 11/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN NGN0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 0.59 SYMM 8X (0.5) METAL TYP 1 8 8X (0.3) 4X (1.31) SYMM 9 (0.755) 6X (0.8) 5 4 (R0.05) TYP 4X (0.98) (3.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4214794/A 11/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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