CAT24S128C4ATR - ON SEMICONDUCTOR

September, 2018 − Rev. 7 1Publication Order Number:

CAT24S128/D

CAT24S128

128 Kb I2C CMOS Serial

EEPROM with Software

Write Protect

Description

The CAT24S128 is a 128 Kb Serial CMOS EEPROM, internally

organized as 16,384 words of 8 bits each.

It features a 64−byte page write buffer and supports both the

Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C

protocol.

The device features programmable software write protection which

provides partial as well as full memory array protection.

Features

•Supports Standard, Fast and Fast−Plus I2C Protocol

•1.7 V to 5.5 V Supply Voltage Range

•64−Byte Page Write Buffer

•User Programmable Block Write Protection − Protect 1/4, 1/2, 3/4 or

Entire EEPROM Array

•Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs

(SCL and SDA)

•Low Power CMOS Technology

•1,000,000 Program/Erase Cycles

•40 Year Data Retention

•Industrial Temperature Range: −40°C to +85°C

•Ultra−thin 4−ball WLCSP Package

•This Device is Pb−Free, Halogen Free/BFR Free and RoHS

Compliant**

Figure 1. Functional Symbol

SDA

SCL CAT24S128

VCC

VSS

** For additional information on our Pb−Free strategy and soldering details,

please download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

www.onsemi.com

PIN CONFIGURATION

VCC

VSS

SCL

See detailed ordering and shipping information in the package

dimensions section on page 12 of this data sheet.

ORDERING INFORMATION

SDA

WLCSP−4 (C4A, C4U)

(Top View)

Serial Data Input/OutputSDA

Serial Clock InputSCL

Power SupplyVCC

GroundVSS

FunctionPin Name

PIN FUNCTION

WLCSP−4

C4A SUFFIX

CASE 567KV

X = Specific Device Code

= (see ordering information)

Y = Production Year (Last Digit)

M = Production Month (1−9, O, N, D)

W = Production Week Code

MARKING DIAGRAMS

Pin 1

WLCSP−4

C4U SUFFIX

CASE 567PC

Pin 1

(C4A) (C4U)

CAT24S128

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Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Storage Temperature −65 to +150 °C

Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 1.0 V. During transitions, the voltage on any pin may

undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol Parameter Min Units

NEND (Note 3) Endurance 1,000,000 Program / Erase Cycles

TDR (Note 4) Data Retention 40 Years

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

3. Page Mode, VCC = 5 V, 25°C

4. TA = 55°C

Table 3. DC AND AC OPERATING CONDITIONS

Supply Voltage / Temperature Range Operation

VCC = 1.7 V to 5.5 V / TA = −40°C to +85°CREAD / WRITE

VCC = 1.6 V to 5.5 V / TA = −40°C to +85°C READ

VCC = 1.6 V to 5.5 V / TA = 0°C to +85°C WRITE

Table 4. D.C. OPERATING CHARACTERISTICS

Symbol Parameter Test Conditions Min Max Units

ICCR Read Current Read, fSCL = 400 kHz/1 MHz 1 mA

ICCW Write Current 2 mA

ISB Standby Current All I/O Pins at GND or VCC VCC ≤ 2.5 V 1mA

VCC > 2.5 V 2

ILI/O Pin Leakage Pin at GND or VCC 2mA

VIL1 Input Low Voltage VCC ≥ 2.5 V −0.5 0.3 VCC V

VIL2 Input Low Voltage VCC < 2.5 V −0.5 0.25 VCC V

VIH1 Input High Voltage VCC ≥ 2.5 V 0.7 VCC VCC + 1 V

VIH2 Input High Voltage VCC < 2.5 V 0.75 VCC VCC + 1 V

VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V

VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 5. PIN IMPEDANCE CHARACTERISTICS

Symbol Parameter Conditions Max Units

CIN (Note 5) SDA I/O Pin Capacitance VIN = 0 V 8 pF

CIN (Note 5) Input Capacitance (other pins) VIN = 0 V 6 pF

5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

CAT24S128

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Table 6. A.C. CHARACTERISTICS (Note 6)

Symbol Parameter

Standard

VCC = 1.7 V − 5.5 V Fast

VCC = 1.7 V − 5.5 V Fast−Plus

VCC = 1.7 V − 5.5 V

Units

Min Max Min Max Min Max

FSCL Clock Frequency 100 400 1,000 kHz

tHD:STA START Condition Hold Time 4 0.6 0.25 ms

tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms

tHIGH High Period of SCL Clock 4 0.6 0.40 ms

tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms

tHD:DAT Data In Hold Time 000ms

tSU:DAT Data In Setup Time 250 100 50 ns

tR (Note 7) SDA and SCL Rise Time 1,000 20 300 100 ns

tF (Note 7) SDA and SCL Fall Time 300 20 300 100 ns

tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms

tBUF Bus Free Time Between

STOP and START 4.7 1.3 0.5 ms

tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms

tDH Data Out Hold Time 100 100 50 ns

Ti (Note 7) Noise Pulse Filtered at SCL

and SDA Inputs 100 50 50 ns

tWR Write Cycle Time 5 5 5 ms

tPU

(Notes 7, 8) Power-up to Ready Mode 0.35 0.35 0.35 ms

6. Test conditions according to “A.C. Test Conditions” table.

7. Tested initially and after a design or process change that af fects this parameter.

8. tPU is the delay between the time VCC is stable and the device is ready to accept commands.

Table 7. A.C. TEST CONDITIONS

Input Levels 0.2 x VCC to 0.8 x VCC

Input Rise and Fall Times v 50 ns

Input Reference Levels 0.3 x VCC, 0.7 x VCC

Output Reference Levels 0.5 x VCC

Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF

Figure 2. Maximum Pull−up Resistance vs. Load Capacitance

LOAD CAPACITANCE (pF)

10010

0.1

PULL−UP RESISTANCE (kW)

300 ns Rise Time

120 ns Rise Time SDA

VCC

VSS

CAT24S128

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Power−On Reset (POR)

The CAT24S128 incorporates Power−On Reset (POR)

circuitry which protects the device against powering up in

the wrong state.

The CAT24S128 will power up into Standby mode after

VCC exceeds the POR trigger level and will power down into

Reset mode when VCC drops below the POR trigger level.

This bi−directional POR feature protects the device against

‘brown−out’ failure following a temporary loss of power.

Pin Description

SCL: The Serial Clock input pin accepts the Serial Clock

generated by the Master.

SDA: The Serial Data I/O pin receives input data and

transmits data stored in EEPROM. In transmit mode, this pin

is open drain. Data is acquired on the positive edge, and is

delivered on the negative edge of SCL.

Functional Description

The CAT24S128 supports the Inter−Integrated Circuit

(I2C) Bus data transmission protocol, which defines a device

that sends data to the bus as a transmitter and a device

receiving data as a receiver. Data flow is controlled by a

Master device, which generates the serial clock and all

START and STOP conditions. The CAT24S128 acts as a

Slave device. Master and Slave alternate as either

transmitter or receiver. Up to 8 devices may be connected to

the bus as determined by the device address inputs A0, A1,

and A2.

I2C Bus Protocol

The I2C bus consists of two ‘wires’, SCL and SDA. The

two wires are connected to the VCC supply via pull−up

resistors. Master and Slave devices connect to the 2−wire

bus via their respective SCL and SDA pins. The transmitting

device pulls down the SDA line to ‘transmit’ a ‘0’ and

releases it to ‘transmit’ a ‘1’.

Data transfer may be initiated only when the bus is not

busy (see A.C. Characteristics).

During data transfer, the SDA line must remain stable

while the SCL line is HIGH. An SDA transition while SCL

is HIGH will be interpreted as a START or STOP condition

(Figure 3). The START condition precedes all commands. It

consists of a HIGH to LOW transition on SDA while SCL

is HIGH. The START acts as a ‘wake−up’ call to all

receivers. Absent a START, a Slave will not respond to

commands. The STOP condition completes all commands.

It consists of a LOW to HIGH transition on SDA while SCL

is HIGH.

Device Addressing

The Master initiates data transfer by creating a START

condition on the bus. The Master then broadcasts an 8−bit

serial Slave address. The first 4 bits of the Slave address are

set to 1010, for normal Read/Write operations (Figure 4).

The next 3 bits are set to 0 0 1. The last bit, R/W, specifies

whether a Read (1) or W rite (0) operation is to be performed.

Acknowledge

After processing the Slave address, the Slave responds

with an acknowledge (ACK) by pulling down the SDA line

during the 9th clock cycle (Figure 5). The Slave will also

acknowledge all address bytes and every data byte presented

in Write mode if the addressed location is not write

protected. In Read mode the Slave shifts out a data byte, and

then releases the SDA line during the 9th clock cycle. As

long as the Master acknowledges the data, the Slave will

continue transmitting. The Master terminates the session by

not acknowledging the last data byte (NoACK) and by

issuing a STOP condition. Bus timing is illustrated in

Figure 6.

CAT24S128

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START

CONDITION STOP

CONDITION

SDA

SCL

Figure 3. START/STOP Conditions

1010

DEVICE ADDRESS

Figure 4. Slave Address Bits

0 0 1 R/W

189

START

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER)

ACK SETUP (≥ tSU:DAT)

BUS RELEASE DELAY (RECEIVER)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 5. Acknowledge Timing

ACK DELAY (≤ tAA)

SCL

SDA IN

SDA OUT

Figure 6. Bus Timing

tSU:STA tHD:STA

tHD:DAT

tLOW

tAA

tHIGH

tLOW

tDH tBUF

tSU:DAT tSU:STO

CAT24S128

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Write Operations

Byte Write

In Byte W rite mode the Master sends a START, followed

by Slave address, two byte address (Table 8) and data to be

written (Figure 7). The Slave, CAT24S128 acknowledges

all 4 bytes, and the Master then follows up with a STOP,

which in turn starts the internal Write operation (Figure 8).

During the internal Write cycle (tWR), the CAT24S128 will

not acknowledge any Read or Write request from the Master.

Page Write

The CAT24S128 contains 16,384 bytes of data, arranged

in 256 pages of 64 bytes each. A two byte address word

(Table 8), following the Slave address, points to the first

byte to be written into the memory array. The most

significant 8 bits from the address active bits (a13 to a6)

identify the page and the last 6 bits (a5 to a0) identify the byte

within the page. Up to 64 bytes can be written in one Write

cycle (Figure 9). The internal byte address counter is

automatically incremented after each data byte is loaded. If

the Master transmits more than 64 data bytes, then earlier

bytes will be overwritten by later bytes in a ‘wrap−around’

fashion (within the selected page). The internal Write cycle

starts immediately following the STOP.

Acknowledge Polling

The ready/busy status of the CAT24S128 can be

ascertained by sending Read or Write requests immediately

following the STOP condition that initiated the internal

Write cycle. As long as internal Write is in progress, the

CAT24S128 will not acknowledge the Slave address.

Software Write Protection

The user can select to write-protect partial or full memory

array by writing a specific data into the Write Protect

bytes memory addressing space, at address 1xxx xxx x xxxx

xxxx.

The software write protect control bits from the Write

Protect Register are shown in Table 9. The write protect

control bits, b0 to b3 are non-volatile.

The WPEN (Write Protect Enable) bit enables the write

protection when it is set to “1”. When the WPEN bit is “0”,

the whole memory array can be written.

The BP0 and BP1 (Block Protect) bits determine which

area is write protected. The user can select to protect a

quarter, one half, three quarters or the entire memory by

setting these bits according to Table 10. The protected

blocks then become read-only.

The least significant bit from the Write Protect Register,

WPL allows the user to lock the write protection status.

When the WPL bit is set to “1” the control bits, b0 to b3 from

WPR cannot be modified. Therefore the protected blocks

can be permanently protected. If WPL bit is “0” the status of

control bits from the WPR can be changed.

The CAT24S128 will not acknowledge the data byte and

the write request will be rejected for the addresses located in

the protected area.

NOTE: Once the WPL bit is set to “1”, the user can no

longer modify the WPR bits, therefore the write

protection status is permanently locked.

Table 8. BYTE ADDRESS

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Memory

Array 0 x a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0

Write

Protect

1 x x x x x x x x x x x x x x x

Table 9. WRITE PROTECT REGISTER

b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 0 WPEN BP1 BP0 WPL

Table 10. BLOCK PROTECTION

BP1 BP0 Array Address Protected Protection

0 0 3000 - 3FFF Upper Quarter Protection

0 1 2000 - 3FFF Upper Half Protection

1 0 1000 - 3FFF Upper 3/4 Array Protection

1 1 0000 - 3FFF Full Array Protection

CAT24S128

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Writing the Write Protect Register

The write operation to the Write Protect Register is

performed using a Byte Write instruction (Figure 7) at

address 1xxx xxxx xxxx xxxx. The data byte contains the 4

least significant bits as significant bits. The b7 to b4 bits are

don’t care during the write operation. Sending more than one

data byte will cancel the write cycle (Write Protect Register

content will not be changed).

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

BYTE DATA

BYTE

Figure 7. Byte Write Sequence

a13−a8a7−a0

* A15 = 0 for Memory Array access; A15 = 1 for Write Protect Register access

A14 = Don’t Care bit

STOP

CONDITION START

CONDITION ADDRESS

ACK

8th Bit

Byte n

SCL

SDA

Figure 8. Write Cycle Timing

tWR

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

BYTE DATA

BYTE

DATA

BYTE

n+1

DATA

BYTE

n+P

P v 63 Figure 9. Page Write Sequence

a13−a8a7−a0

* A15 = 0 for Memory Array access; A15 = 1 for Write Protect Register access

A14 = Don’t Care bit

CAT24S128

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Read Operations

Immediate Read

Upon receiving a Slave address with the R/W bit set to ‘1’,

the CAT24S128 will interpret this as a request for data

residing at the current byte address in memory. The

CAT24S128 will acknowledge the Slave address, will

immediately shift out the data residing at the current address,

and will then wait for the Master to respond. If the Master

does not acknowledge the data (NoACK) and then follows

up with a STOP condition (Figure 10), the CAT24S128

returns to Standby mode.

Selective Read

To read data residing at a specific location, the internal

address counter must first be initialized as described under

Byte Write. If rather than following up the two address bytes

with data, the Master instead follows up with an Immediate

Read sequence, then the CAT24S128 will use the 14 active

address bits to initialize the internal address counter and will

shift out data residing at the corresponding location. If the

Master does not acknowledge the data (NoACK) and then

follows up with a STOP condition (Figure 11), the

CAT24S128 returns to Standby mode.

Sequential Read

If during a Read session the Master acknowledges the 1st

data byte, then the CAT24S128 will continue transmitting

data residing at subsequent locations until the Master

responds with a NoACK, followed by a ST OP (Figure 12).

In contrast to Page Write, during Sequential Read the

address count will automatically increment to and then

wrap−around at end of memory (rather than end of page).

Write Protect Register Read

To read the Write Protect Register, the master simply

sends a Selective Read instruction (Figure 12) at address

1xxx xxxx xxxx xxxx. The data byte shifted out by the

device shows the content of the WPR according to Table 9.

If the master acknowledges the data byte and send more

clocks, the WPR content will continue to be read out.

Delivery State

The CAT24S128 is shipped erased, i.e., all memory array

bytes are FFh and the Write Protect Register bits set to 0

(00h).

SCL

SDA 8th Bit

STOP

NO ACKDATA OUT

SLAVE

ADDRESS

KDATA

BYTE

BUS ACTIVITY:

MASTER

SLAVE

Figure 10. Immediate Read Sequence and Timing

CAT24S128

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SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

BYTE

DATA

BYTE

SLAVE

ADDRESS

Figure 11. Selective Read Sequence

a13−a8a7−a0

* A15 = 0 for Memory Array access; A15 = 1 for Write Protect Register access

A14 = Don’t Care bit

BUS ACTIVITY:

MASTER

SLAVE DATA

BYTE

DATA

BYTE

n+1

DATA

BYTE

n+2

DATA

BYTE

n+x

SLAVE

ADDRESS

Figure 12. Sequential Read Sequence

CAT24S128

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PACKAGE DIMENSIONS

WLCSP4, 0.84x0.84

CASE 567KV

ISSUE B

ÈÈ

SEATING

PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE

SPHERICAL CROWNS OF THE CONTACT BALLS.

4. COPLANARITY APPLIES TO SPHERICAL CROWNS OF

THE SOLDER BALLS.

5. DIMENSION b IS MEASURED AT THE MAXIMUM CON-

TACT BALL DIAMETER PARALLEL TO DATUM C.

PIN A1

REFERENCE

0.05 C

TOP VIEW

SIDE VIEW

NOTE 4

NOTE 3

DIM

AMIN NOM

−−−

MILLIMETERS

b0.16 0.18

e0.40 BSC

−−−

0.08 0.10

A2 0.23 REF

0.81 0.84

MAX

0.20

0.35

0.12

0.87

e1 0.50 BSC

4X b

BOTTOM VIEW

NOTE 5

A0.05 BC

0.03 C

e1/2

e/2

PITCH

0.18

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.40

0.50

RECOMMENDED

PITCH

CAT24S128

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PACKAGE DIMENSIONS

WLCSP4, 0.84x0.84

CASE 567PC

ISSUE A

ÈÈ

SEATING

PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE

SPHERICAL CROWNS OF THE SOLDER BALLS.

4. COPLANARITY APPLIES TO THE SPHERICAL

CROWNS OF THE SOLDER BALLS.

5. DIMENSION b IS MEASURED AT THE MAXIMUM

CONTACT BALL DIAMETER PARALLEL TO DATUM C.

6. BACKSIDE COATING IS OPTIONAL.

PIN A1

REFERENCE

0.05 C

4X b

0.05 C

TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 4

PITCH

0.18

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.40

0.50

RECOMMENDED

PITCH

NOTE 3

NOTE 5

DETAIL A

NOTE 6

DIE COAT

(OPTIONAL) A3

DIM

AMIN NOM

−−−

MILLIMETERS

b0.16 0.18

e0.40 BSC

−−−

0.08 0.10

A2 0.15 REF

A3 0.025 REF

0.81 0.84

MAX

0.20

0.30

0.12

0.87

DET AIL A

A0.05 BC

0.03 C

e1 0.50 BSC

e1/2

e/2

CAT24S128

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ORDERING INFORMATION (Notes 9 thru 12)

Device Order Number

Specific

Device

Marking Package

Type Temperature Range Lead Finish Shipping

CAT24S128C4ATR E WLCSP 4−ball Industrial

(−40°C to +85°C) N/A Tape & Reel,

5,000 Units / Reel

CAT24S128C4UTR E WLCSP 4−ball Industrial

(−40°C to +85°C) N/A Tape & Reel,

5,000 Units / Reel

9. All packages are RoHS−compliant (Lead−free, Halogen−free).

10.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

11.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device

Nomenclature document, TND310/D, available at www.onsemi.com

12.Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultraviolet light. When exposed to ultraviolet light

the EEPROM cells lose their stored data.

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CAT24S128/D

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