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CY7C1041G
CY7C1041GE
4-Mbit (256K words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-91368 Rev. *N Revised July 13, 2018
4-Mbit (256K w ords × 16-bit) Static RAM with Er ror-Correcti ng Code (ECC)
Features
■High speed
❐tAA = 10 ns/15 ns
■Embedded ECC for single-bit error correction[1, 2]
■Low active and standby currents
❐Active current: ICC = 38 mA typical
❐Standby current: ISB2 = 6 mA typical
■Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■1.0-V data retention
■TTL-compatible inputs and outputs
■Error indication (ERR) pin to indicate 1-bit error detection and
correction
■Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA
packages
Functional Description
CY7C1041G and CY7C1041GE are high-performance CMOS
fast static RAM devices with embedded ECC. Both devices are
offered in single chip-enable option and in multiple pin
configurations. The CY7C1041GE device includes an ERR pin
that signals an error-detection and correction event during a read
cycle.
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O0
through I/O15 and address on A0 through A17 pins. The Byte High
Enable (BHE) and Byte Low Enable (BLE) inputs control write
operations to the upper and lower bytes of the specified memory
location. BHE controls I/O8 through I/O15 and BLE controls I/O0
through I/O7.
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O15). Byte accesses can be performed by
asserting the required byte enable signal (BHE or BLE) to read
either the upper byte or the lower byte of data from the specified
address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
during the following events:
■The device is deselected (CE HIGH)
■The control signals (OE, BLE, BHE) are de-asserted
On the CY7C1041GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)[1]. See the Truth
Table on page 14 for a complete description of read and write
modes.
The logic block diagram is on page 2.
Product Portfolio
Product [3] Features and Options (see Pin
Configurations on page 4)Range VCC Range
(V)
Speed
(ns)
10/15
Power Dissipation
Operating ICC, (mA) Standby, ISB2
(mA)
f = fmax
Typ [4] Max Typ [4] Max
CY7C1041G(E)18 Single Chip Enable
Optional ERR pins
Industrial 1.65 V–2.2 V 15 – 40 6 8
CY7C1041G(E)30 2.2 V–3.6 V 10 38 45
CY7C1041G(E) 4.5 V–5.5 V 10 38 45
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details.
3. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 15 for details.
4. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC =3V (for a V
CC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 2 of 21
Logic Block Diagram – CY7C1041G
MEMORY
ARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMNDECODER
A10
SENSE
AMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
ECCENCODER INPUTBUFFER
I/O0‐I/O7
I/O8‐I/O15
BHE
WE
OE
BLE
CE
Logic Block Diagram – CY7C1041GE
MEMORY
ARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMNDECODER
A10
SENSE
AMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
ECCENCODER INPUTBUFFER
I/O0‐I/O7
I/O8‐I/O15
BHE
WE
OE
BLE
ERR
CE
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 3 of 21
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
AC Switching Characteristics ......................................... 9
Switching Waveforms .................................................... 10
Truth Table ...................................................................... 14
ERR Output – CY7C1041GE .......................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC® Solutions ...................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 4 of 21
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable
without ERR, CY7C1041G [5], Package/Grade ID: BVXI [7] Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable
with ERR, CY7C1041GE [5, 6], Package/Grade ID: BVXI [7]
Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm)
Single Chip Enable without ERR, CY7C1041G [5],
Package/Grade ID: BVJXI [7]
Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm)
Single Chip Enable with ERR, CY7C1041GE [5, 6],
Package/Grade ID: BVJXI [7]
OEBLE A0A2
A1NC
BHEI/O0A3CEA4I/O8
I/O2
I/O1A5I/O10
A6I/O9
I/O3
VSS A17 I/O11
A7VCC
I/O4
VCC NC I/O12
A16 VSS
I/O5
I/O6A14 I/O13
A15 I/O14
NCI/O7A12 WEA13 I/O15
A8
NC A9A11
A10 NC
12 3456
A
B
C
D
E
F
G
H
OEBLE A0A2
A1NC
BHEI/O0A3CEA4I/O8
I/O2
I/O1A5I/O10
A6I/O9
I/O3
VSS A17 I/O11
A7VCC
I/O4
VCC ERR I/O12
A16 VSS
I/O5
I/O6A14 I/O13
A15 I/O14
NCI/O7A12 WEA13 I/O15
A8
NC A9A11
A10 NC
12 3456
A
B
C
D
E
F
G
H
OEBLE A0A2
A1NC
BHEI/O8A3CEA4I/O0
I/O10
I/O9A5I/O1
A6I/O2
I/O11
VSS A17 I/O3
A7VCC
I/O12
VCC NC I/O4
A16 VSS
I/O13
I/O14 A14 I/O5
A15 I/O6
NCI/O15 A12 WEA13 I/O7
A8
NC A9A11
A10 NC
12 3456
A
B
C
D
E
F
G
H
OEBLE A0A2
A1NC
BHEI/O8A3CEA4I/O0
I/O10
I/O9A5I/O1
A6I/O2
I/O11
VSS A17 I/O3
A7VCC
I/O12
VCC ERR I/O4
A16 VSS
I/O13
I/O14 A14 I/O5
A15 I/O6
NCI/O15 A12 WEA13 I/O7
A8
NC A9A11
A10 NC
12 3456
A
B
C
D
E
F
G
H
Notes
5. NC pins are not connected internally to the die.
6. ERR is an output pin.
7. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8]
balls are swapped.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 5 of 21
Figure 5. 44-pin TSOP II/44-pin SOJ Single Chip Enable with ERR, CY7C1041GE [8, 9]
Figure 6. 44-pin TSOP II/44-pin SOJ Single Chip Enable without ERR, CY7C1041G [8]
Pin Configurations (continued)
A1 243
A2 342
A3 441
A15
738
A16
639
/CE
I/O7
I/O0
936
I/O6
I/O1
10 35
VSSVCC 11 34
VCC
VSS 12 33
I/O4
I/O2
13 32
I/O5
I/O3
14 31
A14
/WE
15 30
A13
A5
16 29
A12
A6
17 28
A11
A7
18 27
A10
A8
19 26
A9
20 25
ERR
21 24
22 23
A0 144
/OE
837
A17
A4 540
44- pin TSOP II
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/BHE
/BLE
A1 243
A2 342
A3 441
A15
738
A16
639
/CE
I/O7
I/O0
936
I/O6
I/O1
10 35
VSSVCC 11 34
VCC
VSS 12 33
I/O4
I/O2
13 32
I/O5
I/O3
14 31
A14
/WE
15 30
A13
A5
16 29
A12
A6
17 28
A11
A7
18 27
A10
A8
19 26
A9
20 25
NC
21 24
22 23
A0 144
/OE
837
A17
A4 540
44-pin TSOP II
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/BHE
/BLE
Notes
8. NC pins are not connected internally to the die.
9. ERR is an output pin.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 6 of 21
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND [10] ................. –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z State [10] .................................. –0.5 V to VCC + 0.5 V
DC input voltage [10] ........................... –0.5 V to VCC + 0.5 V
Current into outputs (in LOW state) ............................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Grade Ambient Temperature VCC
Industrial –40 C to +85 C 1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Test Conditions 10 ns/15 ns Unit
Min Typ [11] Max
VOH Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – –
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA 2.2 – –
3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.5 [12] ––
VOL Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 V
2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4
2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4
4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4
VIH Input HIGH
voltage
1.65 V to 2.2 V – 1.4 – VCC + 0.2 [10] V
2.2 V to 2.7 V – 2 – VCC + 0.3 [10]
2.7 V to 3.6 V – 2 – VCC + 0.3 [10]
4.5 V to 5.5 V – 2 – VCC + 0.5 [10]
VIL Input LOW
voltage
1.65 V to 2.2 V – –0.2 [10] –0.4V
2.2 V to 2.7 V – –0.3 [10] –0.6
2.7 V to 3.6 V – –0.3 [10] –0.8
4.5 V to 5.5 V – –0.5 [10] –0.8
IIX Input leakage current GND < VIN < VCC –1 – +1 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A
ICC Operating supply current Max VCC, IOUT = 0 mA,
CMOS levels
f = 100 MHz – 38 45 mA
f = 66.7 MHz – – 40
ISB1 Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
––15mA
ISB2 Automatic CE power-down
current – CMOS inputs
Max VCC, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–68mA
Notes
10. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V),
VCC =3V (for V
CC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C.
12. This parameter is guaranteed by design and not tested.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 7 of 21
Capacitance
Parameter [13] Description Test Conditions 48-ball VFBGA 44-pin SOJ 44-pin TSOP II Unit
CIN Input capacitance TA = 25 C, f = 1 MHz,
VCC = VCC(typ)
10 10 10 pF
COUT I/O capacitance 10 10 10 pF
Thermal Resistance
Parameter [13] Description Test Conditions 48-ball VFBGA 44-pin SOJ 44-pin TSOP II Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a
3 × 4.5 inch, four-layer
printed circuit board
31.35 55.37 68.85 C/W
JC Thermal resistance
(junction to case)
14.74 30.41 15.97 C/W
AC Test Loads and Waveforms
Figure 7. AC Test Loads and Waveforms [14]
90%
10%
VHIGH
GND
90%
10%
All Input Pulses
VCC
Output
5 pF*
* Including
jig and
scope (b)
R1
R2
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
30 pF*
* Capacitive load consists
of all components of the
test environment
High-Z Characteristics:
(a)
> 1 V/ns
Parameters 1.8 V 3.0 V 5.0 V Unit
R1 1667 317 317
R2 1538 351 351
VTH 0.9 1.5 1.5 V
VHIGH 1.8 3 3 V
Notes
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 8 of 21
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Conditions Min Max Unit
VDR VCC for data retention 1 – V
ICCDR Data retention current VCC = 1.2 V, CE > VCC – 0.2 V[15],
VIN > VCC – 0.2 V, or VIN < 0.2 V
–8mA
tCDR[16] Chip deselect to data retention
time
0–ns
tR[15, 16] Operation recovery time VCC > 2.2 V 10 – ns
VCC < 2.2 V 15 – ns
Data Retention Waveform
Figure 8. Data Retention Waveform [15]
tCDR tR
VDR = 1.0 V
DATA RETENTION MODE
VCC(min) VCC(min)
VCC
CE
Notes
15. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s.
16. These parameters are guaranteed by design.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 9 of 21
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter [17] Description 10 ns 15 ns Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 10 – 15 – ns
tAA Address to data / ERR valid – 10 – 15 ns
tOHA Data / ERR hold from address change 3 – 3 – ns
tACE CE LOW to data / ERR valid – 10 – 15 ns
tDOE OE LOW to data / ERR valid – 4.5 – 8 ns
tLZOE OE LOW to low impedance [18] 0–0–ns
tHZOE OE HIGH to HI-Z [18, 19] –5–8ns
tLZCE CE LOW to low impedance [18] 3–3–ns
tHZCE CE HIGH to HI-Z [18, 19] –5–8ns
tPU CE LOW to power-up [19, 18] 0–0–ns
tPD CE HIGH to power-down [19, 18] –10–15ns
tDBE Byte enable to data valid – 4.5 – 8 ns
tLZBE Byte enable to low impedance [18] 0–0–ns
tHZBE Byte disable to HI-Z [19] –6–8ns
Write Cycle [20, 21]
tWC Write cycle time 10 – 15 – ns
tSCE CE LOW to write end 7 – 12 – ns
tAW Address setup to write end 7 – 12 – ns
tHA Address hold from write end 0–0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 7 – 12 – ns
tSD Data setup to write end 5 – 8 – ns
tHD Data hold from write end 0 – 0 – ns
tLZWE WE HIGH to low impedance [18] 3–3–ns
tHZWE WE LOW to HI-Z [19] –5–8ns
tBW Byte Enable to write end 7–12 –ns
Notes
17. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
le ve l s o f 0 t o 3 V (f or VCC > 3 V) and 0 to VCC (fo r V CC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 7 on page 7, unless specified otherwise
18. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 7 on page 7. Transition is measured 200 mV from
steady state voltage.
19. These parameters are guaranteed by design and are not tested.
20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
21. The minimum write cycle pulse width in Write Cycle No 2 (WE Controlled, OE LOW) should be equal to sum of tsdand tHZWE.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 10 of 21
Switching Waveforms
Figure 9. Read Cycle No. 1 of CY7C1041G (Address Transition Controlled) [22, 23]
Figure 10. Read Cycle No. 1 of CY7C1041GE (Address Transition Controlled) [22, 23]
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ERR PREVIOUS ERR VALID ERR VALID
tOHA
tAA
Notes
22. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL.
23. WE is HIGH for the read cycle.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 11 of 21
Figure 11. Read Cycle No. 2 (OE Controlled) [24, 25]
Switching Waveforms (continued)
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tDBE
tLZBE
tLZCE
tPU
HIGH IMPEDANCE DATAOUT
VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
BHE/
BLE
DATA I /O
tHZOE
tHZBE
SUPPLY
CURRENT
VCC
ISB
Notes
24. WE is HIGH for the read cycle.
25. Address valid prior to or coincident with CE LOW transition.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 12 of 21
Figure 12. Write Cycle No. 1 (CE Controlled) [26, 27]
Figure 13. Write Cycle No. 2 (WE Controlled, OE LOW) [26, 27, 28]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/
BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPW E
tHA
tBW
tHD
tHZOE tSD
DATA
IN VALID
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tBW
BHE /
BLE
tAW tHA
tSA tPWE
tLZW E
tHZWE
WE
DATA IN VALID
Notes
26. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
27. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
28. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 13 of 21
Figure 14. Write Cycle No. 3 (BLE or BHE Controlled) [29, 30]
Figure 15. Write Cycle No. 4 (WE Controlled) [29, 30, 31]
Switching Waveforms (continued)
DATA IN VALID
ADDRESS
CE
WE
DATA I /O
tWC
tSCE
tAW
tSA
tBW
tHA
tHD
tHZWE tSD
BHE/
BLE
tPWE
tLZWE
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATA IN VALID
tBW
NOTE 32
CE1
ADDRESS
CE2
WE
DATA I/O
OE
BHE/BLE
Notes
29. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
30. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
31. Data I/O is high impedance if OE = VIH.
32. During this period the I/Os are in output state. Do not apply input signals.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 14 of 21
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
HX
[33] X[33] X[33] X[33] HI-Z HI-Z Power down Standby (ISB)
L L H L L Data out Data out Read all bits Active (ICC)
L L H L H Data out HI-Z Read lower bits only Active (ICC)
L L H H L HI-Z Data out Read upper bits only Active (ICC)
L X L L L Data in Data in Write all bits Active (ICC)
L X L L H Data in HI-Z Write lower bits only Active (ICC)
L X L H L HI-Z Data in Write upper bits only Active (ICC)
L H H X X HI-Z HI-Z Selected, outputs disabled Active (ICC)
L X X H H HI-Z HI-Z Selected, outputs disabled Active (ICC)
ERR Output – CY7C1041GE
Output [34] Mode
0 Read operation, no single-bit error in the stored data.
1 Read operation, single-bit error detected and corrected.
HI-Z Device deselected or outputs disabled or Write operation
Notes
33. The input voltage levels on these pins should be either at VIH or VIL.
34. ERR is an Output pin.If not used, this pin should be left floating.
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 15 of 21
Ordering Information
Speed
(ns)
Voltage
Range Ordering Code Package
Diagram
Package Type
(all Pb-free)
Operating
Range
10 2.2 V–3.6 V CY7C1041GE30-10ZSXI 51-85087 44-pin TSOP II, ERR output Industrial
CY7C1041GE30-10ZSXIT 51-85087 44-pin TSOP II, ERR output, Tape and Reel
CY7C1041G30-10ZSXI 51-85087 44-pin TSOP II
CY7C1041G30-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
CY7C1041GE30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output
CY7C1041GE30-10BVXIT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output,
Tape and Reel
CY7C1041G30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm)
CY7C1041G30-10BVXIT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), Tape and Reel
CY7C1041G30-10BVJXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC
CY7C1041G30-10BVJXIT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC,
Tape and Reel
CY7C1041G30-10VXI 51-85082 44-pin SOJ (400 Mils)
CY7C1041G30-10VXIT 51-85082 44-pin SOJ (400 Mils), Tape and Reel
CY7C1041GE30-10VXI 51-85082 44-pin SOJ (400 Mils), ERR output
CY7C1041GE30-10VXIT 51-85082 44-pin SOJ (400 Mils), ERR output,
Tape and Reel
4.5 V–5.5 V CY7C1041G-10ZSXI 51-85087 44-pin TSOP II
CY7C1041G-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
CY7C1041GE-10ZSXI 51-85087 44-pin TSOP II, ERR output
CY7C1041GE-10ZSXIT 51-85087 44-pin TSOP II, ERR output, Tape and Reel
CY7C1041GE-10VXI 51-85082 44-pin SOJ (400 Mils), ERR output
CY7C1041GE-10VXIT 51-85082 44-pin SOJ (400 Mils), ERR output,
Tape and Reel
CY7C1041G-10VXI 51-85082 44-pin SOJ (400 Mils)
CY7C1041G-10VXIT 51-85082 44-pin SOJ (400 Mils), Tape and Reel
15 1.65 V–2.2 V CY7C1041G18-15ZSXI 51-85087 44-pin TSOP II
CY7C1041G18-15ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
CY7C1041G18-15VXI 51-85082 44-pin SOJ (400 Mils)
CY7C1041G18-15VXIT 51-85082 44-pin SOJ (400 Mils), Tape and Reel
CY7C1041G18-15BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm)
CY7C1041G18-15BVXT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), Tape and Reel
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 16 of 21
Ordering Code Definitions
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = ZS or BV or BVJ or V
ZS = 44-pin TSOP II; BV = 48-ball VFBGA;
BVJ = 48-ball VFBGA-JEDEC Compliant; V = 44-pin Molded SOJ
Speed: XX = 10 ns or 15 ns
Voltage Range: XX = 30 or blank or 18
30 = 2.2 V–3.6 V; blank = 4.5 V–5.5 V; 18 = 1.65 V–2.2 V
E = ERR output Single bit error indication
Revision Code “G”: Process Technology = 65 nm
Data Width: 1 = × 16-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 -XX I704 G1 XX XE XX X
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 17 of 21
Package Diagrams
Figure 16. 44-pin TSOP II (Z44) Package Outline, 51-85087
Figure 17. 44-pin SOJ (400 Mils) Package Outline, 51-85082
51-85087 *E
51-85082 *E
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 18 of 21
Figure 18. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
Package Diagrams (continued)
51-85150 *H
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 19 of 21
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE byte high enable
BLE byte low enable
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
VFBGA very fine-pitch ball grid array
WE write enable
Symbol Unit of Measure
°C Degrees Celsius
MHz megahertz
Amicroamperes
smicroseconds
mA milliamperes
mm millimeters
ns nanoseconds
ohms
%percent
pF picofarads
Vvolts
Wwatts
CY7C1041G
CY7C1041GE
Document Number: 001-91368 Rev. *N Page 20 of 21
Document History Page
Document Title: CY7C1041G/CY7C1041GE, 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-91368
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
*F 4867081 NILE 07/31/2015 Changed status from Preliminary to Final.
*G 4876251 NILE 08/07/2015 Updated Ordering Information:
Updated part numbers.
*H 4968879 NILE 10/16/2015 Fixed typo in bookmarks.
*I 5019226 VINI 11/18/2015 Updated Ordering Information:
Updated part numbers.
*J 5122043 NILE 02/02/2016 Updated Truth Table.
*K 5223335 NILE 08/30/2016 Updated DC Electrical Characteristics:
Removed values of VOH parameter corresponding to “2.7 V to 3.6 V” range.
Added values of VOH parameter corresponding to “2.7 V to 3.0 V” and “3.0 V
to 3.6 V” ranges.
Updated Note 10 (Replaced “2 ns” with “20 ns”).
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*L 5655218 NILE 03/09/2017 Updated Logic Block Diagram – CY7C1041G (Updated diagram to change the
devices from Dual Chip enabled to Single Chip enabled).
Updated Logic Block Diagram – CY7C1041GE (Updated diagram to change
the devices from Dual Chip enabled to Single Chip enabled).
Updated to new template.
*M 5731242 GNKK 05/09/2017 Updated logo and copyright.
Completing Sunset Review.
*N 6245720 NILE 07/13/2018 Updated Features:
Added Note 2 and referred the same note in “Embedded ECC for single-bit
error correction”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-91368 Rev. *N Revised July 13, 2018 Page 21 of 21
CY7C1041G
CY7C1041GE
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