CY62146GN MoBL®
4-Mbit (256K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-95417 Rev. *E Revised December 15, 2017
4-Mbit (256K × 16) Static RAM
Features
■Very high speed: 45 ns
■Temperature ranges
❐Industrial: –40 °C to +85 °C
■Wide voltage range: 2.20 V to 3.60 V and 4.5 V to 5.5 V
■Ultra low standby power
❐Typical standby current: 3.5 A
❐Maximum standby current: 8.7 A
■Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
■Automatic power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in a 44-pin TSOP II and 48-ball VFBGA Packages
Functional Description
The CY62146GN is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
advanced circuit design designed to provide an ultra low active
current. Ultra low active current is ideal for providing More
Battery Life (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
Logic Block Diagram
256K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BHE
A16
A0
A1
A9
A10
BLE
A17
Document Number: 001-95417 Rev. *E Page 2 of 16
CY62146GN MoBL®
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Document Number: 001-95417 Rev. *E Page 3 of 16
CY62146GN MoBL®
Pin Configurations
Figure 1. 44-pin TSOP II Pinout [1] Figure 2. 48-ball VFBGA Pinout [1]
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
WE
A
11
A
10
A
6
A
0
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
Vss
A
7
I/O
0
BHE
NC
A
17
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
CC
A
1
A
2
A
3
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (A)
f = 1 MHz f = fmax
Min Typ[2] Max Typ[2] Max Typ[2] Max Typ[2] Max
CY62146GN30 Industrial 2.2 3.0 3.6 45 3.5 6 15 20 3.5 8.7
CY62146GN 4.5 5.0 5.5 45
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-95417 Rev. *E Page 4 of 16
CY62146GN MoBL®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential ........................... –0.3 V to + VCC + 0.5 V
DC voltage applied to outputs
in High-Z state[3, 4] ........................... –0.3 V to + VCC + 0.5 V
DC input voltage[3, 4] ........................ –0.3 V to + VCC + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... >2001 V
Latch-up Current .................................................... >200 mA
Operating Range
Device Range Ambient
Temperature VCC[5]
CY62146GN30 Industrial –40 °C to +85 °C 2.2 V to 3.6 V,
4.5 V to 5.5 V
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns.
4. VIH(max) = VCC + 2.0 V for pulse durations less than 20 ns.
5. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
7. This parameter is guaranteed by design and not tested.
8. Chip enable (CE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns Unit
Min Typ[6] Max
VOH Output high
voltage
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA 2 – –
V
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.5[7] ––
VOL Output low
voltage
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA – – 0.4
V2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA – – 0.4
4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA – – 0.4
VIH[4] Input high
voltage
2.2 V to 2.7 V – 1.8 – VCC + 0.3
V2.7 V to 3.6 V – 2.0 – VCC + 0.3
4.5 V to 5.5 V – 2.2 – VCC + 0.5
VIL[3] Input LOW
Voltage
2.2 V to 2.7 V VCC = 2.2 V to 2.7 V –0.3 – 0.6
V2.7 V to 3.6 V VCC = 2.7 V to 3.6 V –0.3 – 0.8
4.5 V to 5.5 V – –0.5 – 0.8
IIX Input leakage current GND < VI < VCC –1 – +1 mA
IOZ Output leakage current GND < VO < VCC, Output disabled –1 – +1 mA
ICC VCC operating supply current
f = fmax = 1/tRC VCC = VCC(max),
IOUT = 0 mA
CMOS levels
–1520
mA
f = 1 MHz – 3.5 6
ISB1 Automatic CE power down current –
CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and data only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
–3.58.7A
ISB2[8] Automatic CE power down current –
CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–3.58.7A
Document Number: 001-95417 Rev. *E Page 5 of 16
CY62146GN MoBL®
Capacitance
Parameter[9] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = VCC(typ)
10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter[9] Description Test Conditions 48-ball VFBGA TSOP II Unit
JA
Thermal resistance
(junction to ambient) Still air, soldered on a
3 × 4.5 inch,
four-layer printed
circuit board
31.35 68.85 C/W
JC
Thermal resistance
(junction to case) 14.74 15.97 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms[10]
VCC
VCC
Output
R2
30 pF
Including
JIG and
Scope
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
Output V
All Input Pulses
RTH
R1
Equivalent to: Thevenin Equivalent
Parameters 2.50 V 3.0 V Unit
R1 16667 1103
R2 15385 1554
RTH 8000 645
VTH 1.20 1.75 V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
10. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95417 Rev. *E Page 6 of 16
CY62146GN MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ Max Unit
VDR VCC for data retention 1.0 – – V
ICCDR[11, 12] Data retention current
VCC = 1.2 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
––13A
tCDR[13] Chip deselect to data retention
time – 0––ns
tR[14] Operation recovery time – 45 – – ns
Data Retention Waveform
Figure 4. Data Retention Waveform
VCC(min)
VCC(min)
tCDR
VDR >1.0 V
DATA RETENTION MODE
tR
VCC
CE
Notes
11. Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating.
12. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-95417 Rev. *E Page 7 of 16
CY62146GN MoBL®
Switching Characteristics
Over the Operating Range
Parameter[15, 16] Description 45 ns Unit
Min Max
Read Cycle
tRC Read cycle time 45 –ns
tAA Address to data valid –45 ns
tOHA Data hold from address change 10 –ns
tACE CE LOW to data valid –45 ns
tDOE OE LOW to data valid –22 ns
tLZOE OE LOW to Low-Z[17] 5 – ns
tHZOE OE HIGH to High-Z[17, 18] –18 ns
tLZCE CE LOW to Low-Z[17] 10 –ns
tHZCE CE HIGH to High-Z[17, 18] –18 ns
tPU CE LOW to power up 0 – ns
tPD CE HIGH to power down –45 ns
tDBE BLE / BHE LOW to data valid –22 ns
tLZBE BLE / BHE LOW to Low-Z[17] 5 – ns
tHZBE BLE / BHE HIGH to High-Z[17, 18] –18 ns
Write Cycle[19, 20]
tWC Write cycle time 45 –ns
tSCE CE LOW to write end 35 –ns
tAW Address setup to write end 35 –ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 35 –ns
tBW BLE / BHE LOW to write end 35 –ns
tSD Data setup to write end 25 –ns
tHD Data hold from write end 0 – ns
tHZWE WE LOW to High-Z[17, 18] –18 ns
tLZWE WE HIGH to Low-Z[17] 10 –ns
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 3 on page 5.
16. These parameters are guaranteed by design.
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write
20. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-95417 Rev. *E Page 8 of 16
CY62146GN MoBL®
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled)[21, 22]
Figure 6. Read Cycle No. 2 (OE Controlled)[22, 23]
PREVIOUS DATA VALID DATAOUT
VALID
tRC
tAA
tOHA
ADDRESS
DATA I/O
50%
50%
DATAOUT
VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA I/O
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
21. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE.
Document Number: 001-95417 Rev. *E Page 9 of 16
CY62146GN MoBL®
Figure 7. Write Cycle No. 1 (WE Controlled)[24, 25, 26]
Figure 8. Write Cycle No. 2 (CE Controlled)[24, 25, 26]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 27
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
NOTE 27
Notes
24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
25. Data I/O is high impedance if OE = VIH.
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 001-95417 Rev. *E Page 10 of 16
CY62146GN MoBL®
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)[28, 29]
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[28]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 30
CE
ADDRESS
WE
DATA I/O
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 30
DATA I/O
ADDRESS
CE
WE
BHE/BLE
Notes
28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
29. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
30. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 001-95417 Rev. *E Page 11 of 16
CY62146GN MoBL®
Truth Table
CE [31] WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High-Z Deselect/power-down Standby (ISB)
L X X H H High-Z Output disabled Active (ICC)
L H L L L Data out (I/O0–I/O15) Read Active (ICC)
LHLHL
Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z Read Active (ICC)
LHLLH
Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z Read Active (ICC)
L H H X X High-Z Output disabled Active (ICC)
L L X L L Data in (I/O0–I/O15) Write Active (ICC)
LLXHL
Data in (I/O0–I/O7);
I/O8–I/O15 in High-Z Write Active (ICC)
LLXLH
Data in (I/O8–I/O15);
I/O0–I/O7 in High-Z Write Active (ICC)
Note
31. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 001-95417 Rev. *E Page 12 of 16
CY62146GN MoBL®
Ordering Code Definitions
Ordering Information
Speed
(ns)
Voltage
Range (V) Ordering Code
Package
Diagram Package Type (Pb-free) Operating
Range
45
2.2 V–3.6 V
CY62146GN30-45ZSXI 51-85087 44-pin TSOP II
Industrial
CY62146GN30-45ZSXIT 51-85087 44-pin TSOP II, Tape & Reel
CY62146GN30-45BVXI 51-85150 48-ball VFBGA (6 × 8 × 1 mm)
CY62146GN30-45BVXIT 51-85150 48-ball VFBGA (6 × 8 × 1 mm), Tape & Reel
4.5 V–5.5 V CY62146GN-45ZSXI 51-85087 44-pin TSOP II
CY62146GN-45ZSXIT 51-85087 44-pin TSOP II, Tape & Reel
X: T = Tape and Reel; Blank = Bulk
Temperature Grade: X = I; I = Industrial
Pb-free
Package Type: XX = ZS or BV
ZS = TSOP II; BV = 48-Ball VFBGA
Speed Grade: 45 ns
Voltage Range: 30 = 3 V typical, No Character = 5 V typical
Process Technology: GN = 65 nm Technology
Bus Width: 6 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
CY 45 XX
621 46GN 30 X X
-X
Document Number: 001-95417 Rev. *E Page 13 of 16
CY62146GN MoBL®
Package Diagrams
Figure 11. 44-pin TSOP Z44-II Package Outline, 51-85087
Figure 12. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85087 *E
51-85150 *H
Document Number: 001-95417 Rev. *E Page 14 of 16
CY62146GN MoBL®
Acronyms Document Conventions
Units of Measure
Table 1. Acronyms Used in this Document
Acronym Description
BHE byte high enable
BLE byte low enable
CMOS complementary metal oxide semiconductor
CE chip enable
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
VFBGA very fine-pitch ball grid array
WE write enable
Table 2. Units of Measure
Symbol Unit of Measure
°C Degrees Celsius
MHz megahertz
Amicroamperes
mA milliamperes
ns nanoseconds
ohms
pF picofarads
Vvolts
Wwatts
Document Number: 001-95417 Rev. *E Page 15 of 16
CY62146GN MoBL®
Document History Page
Document Title: CY62146GN MoBL®, 4-Mbit (256K × 16) Static RAM
Document Number: 001-95417
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 5048897 NILE 12/14/2015 New data sheet.
*A 5072822 NILE 01/05/2016
Added “4.5 V to 5.5 V” voltage range related information in all instances across
the document.
Updated Ordering Information:
Updated part numbers.
*B 5092237 NILE 01/21/2016
Added 48-ball VFBGA package related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
Added spec 51-85150 *H (Figure 12).
*C 5142534 NILE 02/18/2016
Updated Ordering Code Definitions under Ordering Information (Replaced
“GN = 90 nm” with “GN = 65 nm Technology”).
Updated to new template.
*D 5555156 NILE 12/15/2016
Updated Ordering Information: Updated part numbers.
Updated Electrical Characteristics:
Enhance VIH for 2.2V - 2.7V operating range from 2.0V to 1.8V.
Enhance VOH for 2.7V - 3.6V operating range from 2.2V to 2.4V.
Updated Notes 3 and 4.
Updated Thermal Resistance.
Updated Sales Support, Copyright and Disclaimer.
*E 5995870 AESATMP9 12/15/2017 Updated logo and copyright.
Document Number: 001-95417 Rev. *E Revised December 15, 2017 Page 16 of 16
© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
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damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
CY62146GN MoBL®
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Arm® Cortex® Microcontrollers cypress.com/arm
Automotive cypress.com/automotive
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Interface cypress.com/interface
Internet of Things cypress.com/iot
Memory cypress.com/memory
Microcontrollers cypress.com/mcu
PSoC cypress.com/psoc
Power Management ICs cypress.com/pmic
Touch Sensing cypress.com/touch
USB Controllers cypress.com/usb
Wireless Connectivity cypress.com/wireless
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
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