LM555CNNOPB - NATIONAL SEMICONDUCTOR

LM5115

Secondary Side Post Regulator / Synchronous Buck

Controller

General Description

The LM5115 is a versatile switching regulator controller. It

has two main application configurations. The first is utilizing

the Secondary Side Post Regulation (SSPR) technique to

implement multiple output power converters. In the second

configuration, it can be used as a standalone synchronous

buck controller (Please see page 14 for more details). The

SSPR technique develops a highly efficient and well regu-

lated auxiliary output from the secondary side switching

waveform of an isolated power converter. Regulation of the

auxiliary output voltage is achieved by leading edge pulse

width modulation (PWM) of the main channel duty cycle.

Leading edge modulation is compatible with either current

mode or voltage mode control of the main output. The

LM5115 drives external high side and low side NMOS power

switches configured as a synchronous buck regulator. A

current sense amplifier provides overload protection and

operates over a wide common mode input range. Additional

features include a low dropout (LDO) bias regulator, error

amplifier, precision reference, adaptive dead time control of

the gate signals and thermal shutdown.

Features

nSelf-synchronization to main channel output

nStandalone DC/DC Synchronous buck mode

nLeading edge pulse width modulation

nVoltage-mode control with current injection and input line

feed-forward

nOperates from AC or DC input up to 75V

nWide 4.5V to 30V bias supply range

nWide 0.75V to 13.5V output range.

nTop and bottom gate drivers sink 2.5A peak

nAdaptive gate driver dead-time control

nWide bandwidth error amplifier (4MHz)

nProgrammable soft-start

nThermal shutdown protection

nTSSOP-16 or thermally enhanced LLP-16 packages

Typical Application Circuit

20134901

FIGURE 1. Simplified Multiple Output Power Converter Utilizing SSPR Technique

July 2006

LM5115 Secondary Side Post Regulator / Synchronous Buck Controller

Connection Diagram

20134902

16-Lead TSSOP

See NS Package Numbers MTC16

20134921

16-Lead LLP

See NS Package Numbers SDA16A

Ordering Information

Ordering Number Package Type NSC Package Drawing Supplied As

LM5115MTC TSSOP-16 MTC16 92 Units Per Anti-Static Tube

LM5115MTCX TSSOP-16 MTC16 2500 units shipped as Tape & Reel

LM5115SD LLP-16 SDA16A 1000 units shipped as Tape & Reel

LM5115SDX LLP-16 SDA16A 4500 units shipped as Tape & Reel

Pin Descriptions

Pin Name Description Application Information

1 CS Current Sense amplifier positive input A low inductance current sense resistor is connected between

CS and VOUT. Current limiting occurs when the differential

voltage between CS and VOUT exceeds 45mV (typical).

2 VOUT Current sense amplifier negative input Connected directly to the output voltage. The current sense

amplifier operates over a voltage range from 0V to 13.5V at the

VOUT pin.

3 AGND Analog ground Connect directly to the power ground pin (PGND).

4 CO Current limit output For normal current limit operation, connect the CO pin to the

COMP pin. Leave this pin open to disable the current limit

function.

5 COMP Compensation. Error amplifier output COMP pin pull-up is provided by an internal 300uA current

source.

6 FB Feedback. Error amplifier inverting input Connected to the regulated output through the feedback resistor

divider and compensation components. The non-inverting input

of the error amplifier is internally connected to the SS pin.

7 SS Soft-start control An external capacitor and the equivalent impedance of an

internal resistor divider connected to the bandgap voltage

reference set the soft-start time. The steady state operating

voltage of the SS pin equal to 0.75V (typical).

8 RAMP PWM Ramp signal An external capacitor connected to this pin sets the ramp slope

for the voltage mode PWM. The RAMP capacitor is charged

with a current that is proportional to current into the SYNC pin.

The capacitor is discharged at the end of every cycle by an

internal MOSFET.

9 SYNC Synchronization input A low impedance current input pin. The current into this pin sets

the RAMP capacitor charge current and the frequency of an

internal oscillator that provides a clock for the free-run (DC

input) mode .

LM5115

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Pin Descriptions (Continued)

Pin Name Description Application Information

10 PGND Power Ground Connect directly to the analog ground pin (AGND).

11 LO Low side gate driver output Connect to the gate of the low side synchronous MOSFET

through a short low inductance path.

12 VCC Output of bias regulator Nominal 7V output from the internal LDO bias regulator. Locally

decouple to PGND using a low ESR/ESL capacitor located as

close to controller as possible.

13 HS High side MOSFET source connection Connect to negative terminal of the bootstrap capacitor and the

source terminal of the high side MOSFET.

14 HO High side gate driver output Connect to the gate of high side MOSFET through a short low

inductance path.

15 HB High side gate driver bootstrap rail Connect to the cathode of the bootstrap diode and the positive

terminal of the bootstrap capacitor. The bootstrap capacitor

supplies current to charge the high side MOSFET gate and

should be placed as close to controller as possible.

16 VBIAS Supply Bias Input Input to the LDO bias regulator and current sense amplifier that

powers internal blocks. Input range of VBIAS is 4.5V to 30V.

- Exposed Pad

(LLP

Package

Only)

Exposed Pad, underside of LLP package Internally bonded to the die substrate. Connect to system

ground for low thermal impedance.

LM5115

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Block Diagram

20134903

LM5115

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VBIAS to GND –0.3V to 32V

VCC to GND –0.3V to 9V

HS to GND –1V to 76V

VOUT, CS to GND – 0.3V to 15V

All other inputs to GND −0.3V to 7.0V

Storage Temperature Range –55˚C to +150˚C

Junction Temperature +150˚C

ESD Rating

HBM (Note 2) 2 kV

Operating Ratings

VBIAS supply voltage 5V to 30V

VCC supply voltage 5V to 7.5V

HS voltage 0V to 75V

HB voltage VCC + HS

Operating Junction Temperature –40˚C to +125˚C

Typical Operating Conditions

PARAMETER MIN TYP MAX UNITS

Supply Voltage, VBIAS 4.5 30 V

Supply Voltage, VCC 4.5 7 V

Supply voltage bypass, CVBIAS 0.1 1 µF

Reference bypass capacitor, CVCC 0.1 1 10 µF

HB-HS bootstrap capacitor 0.047 µF

SYNC Current Range (VCC = 4.5V) 50 150 µA

RAMP Saw Tooth Amplitude 1 1.75 V

VOUT regulation voltage (VBIAS min = 3V + VOUT) 0.75 13.5 V

Electrical Characteristics Unless otherwise specified, T

= –40˚C to +125˚C, VBIAS = 12V, No Load on

LO or HO.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VBIAS SUPPLY

Ibias VBIAS Supply Current F

SYNC

= 200kHz 4 mA

VCC LOW DROPOUT BIAS REGULATOR

VccReg VCC Regulation VCC open circuit. Outputs not

switching

6.65 77.15 V

VCC Current Limit (Note 4) 40 mA

VCC Under-voltage Lockout Voltage Positive going VCC 4 4.5 V

VCC Under-voltage Hysteresis 0.2 0.25 0.3 V

SOFT-START

SS Source Impedance 43 60 77 kΩ

SS Discharge Impedance 100 Ω

ERROR AMPLIFIER and FEEDBACK REFERENCE

VREF FB Reference Voltage Measured at FB pin 0.737 0.75 0.763 V

FB Input Bias Current FB = 2V 0.2 0.5 µA

COMP Source Current 300 µA

Open Loop Voltage Gain 60 dB

GBW Gain Bandwidth Product 4 MHz

Vio Input Offset Voltage -7 07mV

COMP Offset Threshold for V

= high RAMP = CS

=VOUT=0V

RAMP Offset Threshold for V

= high COMP =

1.5V, CS = VOUT = 0V

1.1 V

CURRENT SENSE AMPLIFIER

Current Sense Amplifier Gain 16 V/V

Output DC Offset 1.27 V

Amplifier Bandwidth 500 kHz

LM5115

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Electrical Characteristics Unless otherwise specified, T

= –40˚C to +125˚C, VBIAS = 12V, No Load on LO

or HO. (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CURRENT LIMIT

ILIMIT Amp Transconductance 16 mA / V

Overall Transconductance 237 mA / V

Positive Current Limit V

-V

VOUT

VOUT = 6V and CO/COMP = 1.5V

37 45 53 mV

Positive Current Limit Foldback V

-V

VOUT

VOUT = 0V and CO/COMP = 1.5V

31 38 45 mV

VCLneg Negative Current Limit VOUT = 6V

-V

VOUT

to cause LO to

shutoff

-17 mV

RAMP GENERATOR

SYNC Input Impedance 2.5 kΩ

SYNC Threshold End of cycle detection threshold 15 µA

Free Run Mode Peak Threshold RAMP peak voltage with dc current

applied to SYNC.

2.3 V

Current Mirror Gain Ratio of RAMP charge current to

SYNC input current.

2.7 3.3 A/A

Discharge Impedance 100 Ω

LOW SIDE GATE DRIVER

OLL

LO Low-state Output Voltage I

= 100mA 0.2 0.5 V

OHL

LO High-state Output Voltage I

= -100mA, V

OHL

-V

0.4 0.8 V

LO Rise Time C

LOAD

= 1000pF 15 ns

LO Fall Time C

LOAD

= 1000pF 12 ns

OHL

Peak LO Source Current V

=0V 2 A

OLL

Peak LO Sink Current V

= 12V 2.5 A

HIGH SIDE GATE DRIVER

OLH

HO Low-state Output Voltage I

= 100mA 0.2 0.5 V

OHH

HO High-state Output Voltage I

= -100mA, V

OHH

–V

0.4 0.8 V

HO Rise Time C

LOAD

= 1000pF 15 ns

HO High Side Fall Time C

LOAD

= 1000pF 12 ns

OHH

Peak HO Source Current V

=0V 2 A

OLH

Peak HO Sink Current V

= 12V 2.5 A

SWITCHING CHARACTERISITCS

LO Fall to HO Rise Delay C

LOAD

= 0 70 ns

HO Fall to LO Rise Delay C

LOAD

= 0 50 ns

SYNC Fall to HO Fall Delay C

LOAD

= 0 120 ns

SYNC Rise to LO Fall Delay C

LOAD

= 0 50 ns

THERMAL SHUTDOWN

Thermal Shutdown Temp. 150 165 ˚C

Thermal Shutdown Hysteresis 25 ˚C

THERMAL RESISTANCE

Junction to Ambient MTC Package 125 ˚C/W

Junction to Ambient SDA Package 32 ˚C/W

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of

the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the

Electrical Characteristics tables.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩresistor into each pin.

Note 3: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical

Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 4: Device thermal limitations may limit usable range.

LM5115

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Typical Performance Characteristics

Efficiency vs. Load Current and Vphase V

Regulator Start-up Characteristics, V

vs. V

BIAS

20134922

20134904

Current Value (CV) vs. Current Limit (V

) Current Sense Amplifier Gain and Phase vs. Frequency

20134906 20134907

Current Error Amplifier Transconductance Overall Current Amplifier Transconductance

20134908 20134909

LM5115

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Typical Performance Characteristics (Continued)

Common Mode Output Voltage vs. Positive Current Limit

Common Mode Output Voltage vs. Negative Current

Limit (Room Temp)

20134910 20134911

Load Regulation to Current Limit

20134905

LM5115

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Detailed Operating Description

The LM5115 controller contains all of the features necessary

to implement multiple output power converters utilizing the

Secondary Side Post Regulation (SSPR) technique. The

SSPR technique develops a highly efficient and well regu-

lated auxiliary output from the secondary side switching

waveform of an isolated power converter. Regulation of the

auxiliary output voltage is achieved by leading edge pulse

width modulation (PWM) of the main channel duty cycle.

Leading edge modulation is compatible with either current

mode or voltage mode control of the main output. The

LM5115 drives external high side and low side NMOS power

switches configured as a synchronous buck regulator. A

current sense amplifier provides overload protection and

operates over a wide common mode input range from 0V to

13.5V. Additional features include a low dropout (LDO) bias

regulator, error amplifier, precision reference, adaptive dead

time control of the gate driver signals and thermal shutdown.

A programmable oscillator provides a PWM clock signal

when the LM5115 is powered by a dc input (free-run mode)

instead of the phase signal of the main channel converter

(SSPR mode).

Low Drop-Out Bias Regulator

(VCC)

The LM5115 contains an internal LDO regulator that oper-

ates over an input supply range from 4.5V to 30V. The output

of the regulator at the VCC pin is nominally regulated at 7V

and is internally current limited to 40mA. VCC is the main

supply to the internal logic, PWM controller, and gate driver

circuits. When power is applied to the VBIAS pin, the regu-

lator is enabled and sources current into an external capaci-

tor connected to the VCC pin. The recommended output

capacitor range for the VCC regulator is 0.1uF to 100uF.

When the voltage at the VCC pin reaches the VCC under-

voltage lockout threshold of 4.25V, the controller is enabled.

The controller is disabled if VCC falls below 4.0V (250mV

hysteresis). In applications where an appropriate regulated

dc bias supply is available, the LM5115 controller can be

powered directly through the VCC pin instead of the VBIAS

pin. In this configuration, it is recommended that the VCC

and the VBIAS pins be connected together such that the

external bias voltage is applied to both pins. The allowable

VCC range when biased from an external supply is 4.5V to

7V.

Synchronization (SYNC) and

Feed-Forward (RAMP)

The pulsing “phase signal” from the main converter synchro-

nizes the PWM ramp and gate drive outputs of the LM5115.

The phase signal is the square wave output from the trans-

former secondary winding before rectification (Figure 1). A

resistor connected from the phase signal to the low imped-

ance SYNC pin produces a square wave current (I

SYNC

)as

shown in Figure 2. A current comparator at the SYNC input

monitors I

SYNC

relative to an internal 15µA reference. When

SYNC

exceeds 15µA, the internal clock signal (CLK) is reset

and the capacitor connected to the RAMP begins to charge.

The current source that charges the RAMP capacitor is

equal to 3 times the I

SYNC

current. The falling edge of the

phase signal sets the CLK signal and discharges the RAMP

capacitor until the next rising edge of the phase signal. The

RAMP capacitor is discharged to ground by a low imped-

ance (100Ω) n-channel MOSFET. The input impedance at

SYNC pin is 2.5kΩwhich is normally much less than the

external SYNC pin resistance.

The RAMP and SYNC functions illustrated in Figure 2 pro-

vide line voltage feed-forward to improve the regulation of

the auxiliary output when the input voltage of the main

converter changes. Varying the input voltage to the main

converter produces proportional variations in amplitude of

the phase signal. The main channel PWM controller adjusts

the pulse width of the phase signal to maintain constant

volt*seconds and a regulated main output as shown in Fig-

ure 3. The variation of the phase signal amplitude and dura-

tion are reflected in the slope and duty cycle of the RAMP

signal of the LM5115 (I

SYNC

αphase signal amplitude). As a

result, the duty cycle of the LM5115 is automatically adjusted

to regulate the auxiliary output voltage with virtually no

change in the PWM threshold voltage. Transient line regu-

20134912

FIGURE 2. Line Feed-Forward Diagram

LM5115

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Synchronization (SYNC) and

Feed-Forward (RAMP) (Continued)

lation is improved because the PWM duty cycle of the aux-

iliary converter is immediately corrected, independent of the

delays of the voltage regulation loop.

The recommended SYNC input current range is 50µA to

150µA. The SYNC pin resistor (R

SYNC

) should be selected to

set the SYNC current (I

SYNC

) to 150µA with the maximum

phase signal amplitude, V

PHASE(max)

. This will guarantee

that I

SYNC

stays within the recommended range over a 3:1

change in phase signal amplitude. The SYNC pin resistor is

therefore:

SYNC

=(V

PHASE(max)

/ 150µA) - 2.5kΩ

Once I

SYNC

has been established by selecting R

SYNC

, the

RAMP signal amplitude may be programmed by selecting

the proper RAMP pin capacitor value. The recommended

peak amplitude of the RAMP waveform is 1V to 1.75V. The

RAMP

capacitor is chosen to provide the desired RAMP

amplitude with the nominal phase signal voltage and pulse

width.

RAMP

=(3xI

SYNC

)/V

RAMP

Where

RAMP

= RAMP pin capacitance

SYNC

= SYNC pin current current

= corresponding phase signal pulse width

RAMP

= desired RAMP amplitude (1V to 1.75V)

For example,

Main channel output = 3.3V. Phase signal maximum ampli-

tude = 12V. Phase signal frequency = 250kHz

•Set I

SYNC

= 150µA with phase signal at maximum ampli-

tude (12V):

SYNC

= 150µA = V

PHASE(max)

/(R

SYNC

+ 2.5 kΩ) = 12V /

SYNC

+ 2.5 kΩ)

SYNC

= 12V/150µA - 2.5kΩ= 77.5kΩ

•T

= Main channel duty cycle / Phase frequency =

(3.3V/12V) / 250kHz = 1.1µs

•Assume desired V

RAMP

= 1.5V

•C

RAMP

=(3xI

SYNC

)/V

RAMP

= (3 x 150µA x 1.1µs)

/ 1.5V

•C

RAMP

= 330pF

Error Amplifier and Soft-Start (FB,

CO, & COMP, SS)

An internal wide bandwidth error amplifier is provided within

the LM5115 for voltage feedback to the PWM controller. The

amplifier’s inverting input is connected to the FB pin. The

output of the auxiliary converter is regulated by connecting a

voltage setting resistor divider between the output and the

FB pin. Loop compensation networks are connected be-

tween the FB pin and the error amplifier output (COMP). The

amplifier’s non-inverting input is internally connected to the

SS pin. The SS pin is biased at 0.75V by a resistor divider

connected to the internal 1.27V bandgap reference. When

the VCC voltage is below the UVLO threshold, the SS pin is

discharged to ground. When VCC rises and exceeds the

positive going UVLO threshold (4.25V), the SS pin is re-

leased and allowed to rise. If an external capacitor is con-

nected to the SS pin, it will be charged by the internal resistor

divider to gradually increase the non-inverting input of the

error amplifier to 0.75V. The equivalent impedance of the SS

resistor divider is nominally 60kΩwhich determines the

charging time constant of the SS capacitor. During start-up,

the output of the LM5115 converter will follow the exponen-

tial equation:

VOUT(t) = VOUT(final) x (1 - exp(-t/R

))

Where

Rss = internal resistance of SS pin (60kΩ)

Css = external Soft-Start capacitor

VOUT(final) = regulator output set point

The initial ∆v/∆t of the output voltage is VOUT(final) / Rss x

Css and VOUT will be within 1% of the final regulation level

after 4.6 time constants or when t = 4.6 x Rss x Css.

Pull-up current for the error amplifier output is provided by an

internal 300µA current source. The PWM threshold signal at

the COMP pin can be controlled by either the open drain

error amplifier or the open drain current amplifier connected

through the CO pin to COMP. Since the internal error ampli-

20134913

FIGURE 3. Line Feed-forward Waveforms

LM5115

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Error Amplifier and Soft-Start (FB,

CO, & COMP, SS) (Continued)

fier is configured as an open drain output it can be disabled

by connecting FB to ground. The current sense amplifier and

current limiting function will be described in a later section.

Leading Edge Pulse Width

Modulation

Unlike conventional voltage mode controllers, the LM5115

implements leading edge pulse width modulation. A current

source equal to 3 times the I

SYNC

current is used to charge

the capacitor connected to the RAMP pin as shown in Figure

4. The ramp signal and the output of the error amplifier

(COMP) are combined through a resistor network to produce

a voltage ramp with variable dc offset (CRMIX in Figure 4).

The high side MOSFET which drives the HS pin is held in the

off state at the beginning of the phase signal. When the

voltage of CRMIX exceeds the internal threshold voltage CV,

the PWM comparator turns on the high side MOSFET. The

HS pin rises and the MOSFET delivers current from the main

converter phase signal to the output of the auxiliary regula-

tor. The PWM cycle ends when the phase signal falls and

power is no longer supplied to the drain of the high side

MOSFET.

Leading edge modulation of the auxiliary PWM controller is

required if the main converter is implemented with peak

current mode control. If trailing edge modulation were used,

the additional load on the transformer secondary from the

auxiliary channel would be drawn only during the first portion

of the phase signal pulse. Referring to Figure 5, the turn off

the high side MOSFET of the auxiliary regulator would cre-

ate a non-monotonic negative step in the transformer cur-

rent. This negative current step would produce instability in a

peak current mode controller. With leading edge modulation,

the additional load presented by the auxiliary regulator on

the transformer secondary will be present during the latter

portion of the phase signal. This positive step in the phase

signal current can be accommodated by a peak current

mode controller without instability.

20134914

FIGURE 4. Synchronization and Leading Edge Modulation

20134920

FIGURE 5. Leading versus Trailing Edge Modulation

LM5115

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Voltage Mode Control with Current

Injection

The LM5115 controller uniquely combines elements and

benefits of current mode control in a voltage mode PWM

controller. The current sense amplifier shown in Figure 6

monitors the inductor current as it flows through a sense

resistor connected between CS and VOUT. The voltage gain

of the sense amplifier is nominally equal to 16. The current

sense output signal is shifted by 1.27V to produce the inter-

nal CV reference signal. The CV signal is applied to the

negative input of the PWM comparator and compared to

CRMIX as illustrated in Figure 4. Thus the PWM threshold of

the voltage mode controller (CV) varies with the instanta-

neous inductor current. Insure that the Vbias voltage is at

least 3V above the regulated output voltage (VOUT).

Injecting a signal proportional to the instantaneous inductor

current into a voltage mode controller improves the control

loop stability and bandwidth. This current injection eliminates

the lead R-C lead network in the feedback path that is

normally required with voltage mode control (see Figure 7).

Eliminating the lead network not only simplifies the compen-

sation, but also reduces sensitivity to output noise that could

pass through the lead network to the error amplifier.

The design of the voltage feedback path through the error

amp begins with the selection of R1 and R2 in Figure 7 to set

the regulated output voltage. The steady state output voltage

after soft-start is determined by the following equation:

VOUT(final) = 0.75V x (1+R1/R2)

The parallel impedance of the R1, R2 resistor divider should

be approximately 2kΩ(between 0.5kΩand 5kΩ). Lower

resistance values may not be properly driven by the error

amplifier output and higher feedback resistances can intro-

duce noise sensitivity. The next step in the design process is

selection of R3, which sets the ac gain of the error amplifier.

The ac gain is given by the following equation and should be

set to a value less than 30.

GAIN(ac) = R3/(R1|| R2) <30

The capacitor C1 is connected in series with R3 to increase

the dc gain of the voltage regulation loop and improve output

voltage accuracy. The corner frequency set by R3 x C1

should be less than 1/10th of the cross-over frequency of the

overall converter such that capacitor C1 does not add phase

lag at the crossover frequency. Capacitor C2 is added to

reduce the noise in the voltage control loop. The value of C2

should be less than 500pF and C2 may not be necessary

with very careful PC board layout.

20134915

FIGURE 6. Current Sensing and Limiting

LM5115

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Voltage Mode Control with Current Injection (Continued)

Current Limiting (CS, CO and

VOUT)

Current limiting is implemented through the current sense

amplifier as illustrated in Figure 6. The current sense ampli-

fier monitors the inductor current that flows through a sense

resistor connected between CS and VOUT. The voltage gain

of the current sense amplifier is nominally equal to 16. The

output of current sense signal is shifted by 1.27V to produce

the internal CV reference signal. The CV signal drives a

current limit amplifier with nominal transconductance of

16mA/V. The current limit amplifier has an open drain (sink

only) output stage and its output pin CO is typically con-

nected to the COMP pin. During normal operation, the volt-

age error amplifier controls the COMP pin voltage which

adjusts the PWM duty cycle by varying the internal CRMIX

level (Figure 4). However, when the current sense input

voltage V

exceeds 45mV, the current limit amplifier pulls

down on COMP through the CO pin. Pulling COMP low

reduces the CRMIX signal below the CV signal level. When

CRMIX does not exceed the CV signal, the PWM compara-

tor inhibits output pulses until the CRMIX signal increases to

a normal operating level.

A current limit fold-back feature is provided by the LM5115 to

reduce the peak output current delivered to a shorted load.

When the common mode input voltage to the current sense

amplifier (CS and VOUT pins) falls below 2V, the current limit

threshold is reduced from the normal level. At common mode

voltages >2V, the current limit threshold is nominally 45mV.

When VOUT is reduced to 0V the current limit threshold

drops to 36mV to reduce stress on the inductor and power

MOSFETs.

Negative Current Limit

When inductor current flows from the regulator output

through the low side MOSFET, the input to the current sense

comparator becomes negative. The intent of the negative

current comparator is to protect the low side MOSFET from

excessive currents. Negative current can lead to large nega-

tive voltage spikes on the output at turn off which can dam-

age circuitry powered by the output. The negative current

comparator threshold is sufficiently negative to allow induc-

tor current to reverse at no load or light load conditions. It is

not intended to support discontinuous conduction mode with

diode emulation by the low side MOSFET. The negative

current comparator shown illustrated in Figure 6 monitors

the CV signal and compares this signal to a fixed 1V thresh-

old. This corresponds to a negative V

voltage between CS

and VOUT of -17mV. The negative current limit comparator

turns off the low side MOSFET for the remainder of the cycle

when the V

input falls below this threshold.

Gate Drivers Outputs (HO & LO)

The LM5115 provides two gate driver outputs, the floating

high side gate driver HO and the synchronous rectifier low

side driver LO. The low side driver is powered directly by the

VCC regulator. The high side gate driver is powered from a

bootstrap capacitor connected between HB and HS. An

external diode connected between VCC and HB charges the

bootstrap capacitor when the HS is low. When the high side

MOSFET is turned on, HB rises with HS to a peak voltage

equal to VCC + V

-V

where V

is the forward drop of the

external bootstrap diode. Both output drivers have adaptive

dead-time control to avoid shoot through currents. The adap-

tive dead-time control circuit monitors the state of each

driver to ensure that the opposing MOSFET is turned off

before the other is turned on. The HB and VCC capacitors

should be placed close to the pins of the LM5115 to minimize

voltage transients due to parasitic inductances and the high

peak output currents of the drivers. The recommended range

of the HB capacitor is 0.047µF to 0.22µF.

Both drivers are controlled by the PWM logic signal from the

PWM latch. When the phase signal is low, the outputs are

held in the reset state with the low side MOSFET on and the

high side MOSFET off. When the phase signal switches to

the high state, the PWM latch reset signal is de-asserted.

The high side MOSFET remains off until the PWM latch is

set by the PWM comparator (CRMIX >CV as shown in

Figure 4). When the PWM latch is set, the LO driver turns off

the low side MOSFET and the HO driver turns on the high

20134916

FIGURE 7. Voltage Sensing and Feedback

LM5115

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Gate Drivers Outputs (HO & LO)

(Continued)

side MOSFET. The high side pulse is terminated when the

phase signal falls and SYNC input comparator resets the

PWM latch.

Thermal Protection

Internal thermal shutdown circuitry is provided to protect the

integrated circuit in the event the maximum junction tem-

perature limit is exceeded. When activated, typically at 165

degrees Celsius, the controller is forced into a low power

standby state with the output drivers and the bias regulator

disabled. The device will restart when the junction tempera-

ture falls below the thermal shutdown hysteresis, which is

typically 25 degrees. The thermal protection feature is pro-

vided to prevent catastrophic failures from accidental device

overheating.

Standalone DC/DC Synchronous

Buck Mode

The LM5115 can be configured as a standalone DC/DC

synchronous buck controller. In this mode the LM5115 uses

leading edge modulation in conjunction with valley current

mode control to control the synchronous buck power stage.

The internal oscillator within the LM5115 sets the clock

frequency for the high and low side drivers of the external

synchronous buck power MOSFETs . The clock frequency in

the synchronous buck mode is programmed by the SYNC

pin resistor and RAMP pin capacitor. Connecting a resistor

between a dc bias supply and the SYNC pin produces a

current, I

SYNC

, which sets the charging current of the RAMP

pin capacitor . The RAMP capacitor is charged until its

voltage reaches the peak ramp threshold of 2.25V. The

RAMP capacitor is then discharged for 300ns before begin-

ning a new PWM cycle. The 300ns reset time of the RAMP

pin sets the minimum off time of the PWM controller in this

mode. The internal clock frequency in the synchronous buck

mode is set by I

SYNC

, the ramp capacitor, the peak ramp

threshold, and the 300ns deadtime.

CLK

)1 / ((C

RAMP

x 2.25V) / (I

SYNC

x 3) + 300ns)

See the LM5115 dc evaluation board application note (AN-

1367) for more details on the synchronous buck mode.

20134923

FIGURE 8. Simplified Typical Application Circuit (Synchronous Buck Mode)

20134924

FIGURE 9. Efficiency vs. Load Current and V

(Synchronous Buck Mode)

LM5115

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Application Circuit

20134917

LM5115 Secondary Side Post Regulator

(Inputs from LM5025 Forward Active Clamp Converter, 36V to 78V)

LM5115

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Physical Dimensions inches (millimeters) unless otherwise noted

TSSOP-16 Outline Drawing

NS Package Number MTC16

LLP-16 Outline Drawing

NS Package Number SDA16A

LM5115

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Notes

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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LM5115 Secondary Side Post Regulator / Synchronous Buck Controller