iMC010FLSA-15 - Intel - Product.Network

December 1996 Order Number: 290434-006

SERIES 2 FLASH MEMORY CARDS

iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA

Extended Temperature Specifications Included

Y2, 4, 10 and 20 Megabyte Capacities

YPCMCIA 2.1/JEIDA 4.1 68-Pin Standard

Ð Hardwired Card Information

Structure

Ð Byte- or Word-Wide Selectable

YComponent Management Registers for

Card Status/Control and Flexible

System Interface

YAutomatic Erase/Write

Ð Monitored with Ready/Busy Output

YCard Power-Down Modes

Ð Deep-Sleep for Low Power

Applications

YMechanical Write Protect Switch

YSolid-State Reliability

YIntel FlashFileTM Architecture

YHigh-Performance Read Access

Ð 150 ns Maximum

YHigh-Performance Random Writes

Ð6 ms Typical Word Write

YErase Suspend to Read Command

Ð Keeps Erase as Background Task

YNonvolatility (Zero Retention Power)

Ð No Batteries Required for Back-up

YETOXTM V 0.4mFlash Memory

Technology

Ð 5V Read, 12V Erase/Write

Ð High-Volume Manufacturing

Experience

YExtended Temperature Version

Ðb40§Ctoa

85§C

Intel’s Series 2 Flash Memory Card facilitates high-performance disk emulation in mobile PCs and dedicated

equipment. Manufactured with Intel’s ETOXTM III 0.8m, FlashFile Memory devices, the Series 2 Card allows

code and data retention while erasing and/or writing other blocks. Additionally, the Series 2 Flash Memory

Card features low power modes, flexible system interfacing and a 150 ns read access time. When coupled with

Intel’s low-power microprocessors, these cards enable high-performance implementations of mobile comput-

ers and systems.

Series 2 Cards conform to the Personal Computer Memory Card International Association (PCMCIA 2.1)/Jap-

anese Electronics Industry Development Association (JEIDA 4.1) 68-pin standard, providing electrical and

physical compatibility.

Data file management software, Flash Translation Layer (FTL), provides data file storage and memory man-

agement, much like a disk operating system. Intel’s Series 2 Flash Memory Cards, coupled with flash file

management software, effectively provide a removable, all-silicon mass storage solution with higher perform-

ance and reliability than disk-based memory architectures.

Designing with Intel’s FlashFile Architecture enables OEM system manufacturers to design and manufacture a

new generation of mobile PCs and dedicated equipment where high performance, ruggedness, long battery

life and lighter weight are a requirement. For large user groups in workstation environments, the Series 2

Cards provide a means to securely store user data and backup system configuration/status information.

SERIES 2 FLASH MEMORY CARDS

Table 1. Series 2 Flash Memory Card Pinout

Pin Signal I/O Function Active

1 GND Ground

2DQ

3I/O Data Bit 3

3DQ

4I/O Data Bit 4

4DQ

5I/O Data Bit 5

5DQ

6I/O Data Bit 6

6DQ

7I/O Data Bit 7

7CE

ÝI Card Enable 1 LO

10 I Address Bit 10

9OE

ÝI Output Enable LO

10 A11 I Address Bit 11

11 A9I Address Bit 9

12 A8I Address Bit 8

13 A13 I Address Bit 13

14 A14 I Address Bit 14

15 WEÝI Write Enable LO

16 RDY/BSYÝReady-Busy HI/LO

17 VCC Supply Voltage

18 VPP1 Supply Voltage

19 A16 I Address Bit 16

20 A15 I Address Bit 15

21 A12 I Address Bit 12

22 A7I Address Bit 7

23 A6I Address Bit 6

24 A5I Address Bit 5

25 A4I Address Bit 4

26 A3I Address Bit 3

27 A2I Address Bit 2

28 A1I Address Bit 1

29 A0I Address Bit 0

30 DQ0I/O Data Bit 0

31 DQ1I/O Data Bit 1

32 DQ2I/O Data Bit 2

33 WP O Write Protect HI

34 GND Ground

Pin Signal I/O Function Active

35 GND Ground

36 CD1ÝO Card Detect 1 LO

37 DQ11 I/O Data Bit 11

38 DQ12 I/O Data Bit 12

39 DQ13 I/O Data Bit 13

40 DQ14 I/O Data Bit 14

41 DQ15 I/O Data Bit 15

42 CE2ÝI Card Enable 2 LO

43 VS1O Voltage Sense 1 N.C.

44 RFU Reserved

45 RFU Reserved

46 A17 I Address Bit 17

47 A18 I Address Bit 18

48 A19 I Address Bit 19

49 A20 I Address Bit 20

50 A21 I Address Bit 21

51 VCC Supply Voltage

52 VPP2 Supply Voltage

53 A22 I Address Bit 22

54 A23 I Address Bit 23

55 A24 I Address Bit 24

56 A25 No Connect

57 VS2O Voltage Sense 2 N.C.

58 RST I Reset HI

59 WAITÝO Extend Bus Cycle LO

60 RFU Reserved

61 REGÝI Register Select LO

62 BVD2O Batt. Volt Det 2

63 BVD1O Batt. Volt Det 1

64 DQ8I/O Data Bit 8

65 DQ9I/O Data Bit 9

66 DQ10 I/O Data Bit 10

67 CD2ÝO Card Detect 2 LO

68 GND Ground

SERIES 2 FLASH MEMORY CARDS

Table 2. Series 2 Flash Memory Card Pin Descriptions

Symbol Type Name and Function

A0–A25 IADDRESS INPUTS: A0through A25 are address bus lines which enable direct

addressing of 64 megabytes of memory on a card. A0is not used in word

access mode. A24 is the most significant address bit. Note: A25 is a no-connect

but should be provided on host side.

DQ0–DQ15 I/O DATA INPUT/OUTPUT: DQ0through DQ15 constitute the bidirectional data

bus. DQ15 is the most significant bit.

CE1Ý,CE

ÝICARD ENABLE 1, 2: CE1Ýenables even bytes, CE2Ýenables odd bytes.

Multiplexing A0,CE

Ýand CE2Ýallows 8-bit hosts to access all data on DQ0

through DQ7. (See Table 3 for a more detailed description.)

OEÝIOUTPUT ENABLE: Active low signal gating read data from the memory card.

WEÝIWRITE ENABLE: Active low signal gating write data to the memory card.

RDY/BSYÝOREADY/BUSY OUTPUT: Indicates status of internally timed erase or write

activities. A high output indicates the memory card is ready to accept

accesses. A low output indicates that a device(s) in the memory card is(are)

busy with internally timed activities. See text for an alternate function (READY-

BUSY MODE REGISTER).

CD1Ý&CD

ÝOCARD DETECT 1, 2: These signals provide for correct card insertion detection.

They are positioned at opposite ends of the card to detect proper alignment.

The signals are connected to ground internally on the memory card and will be

forced low whenever a card is placed in the socket. The host socket interface

circuitry shall supply 10K or larger pull-up resistors on these signal pins.

WP O WRITE PROTECT: Write Protect reflects the status of the Write-Protect switch

on the memory card. WP set high ewrite protected, providing internal

hardware write lockout to the flash array.

VPP1,V

PP2 WRITE/ERASE POWER SUPPLY: (12V nominal) for erasing memory array

blocks or writing data in the array. They must be 12V to perform an erase/write

operation.

VCC CARD POWER SUPPLY (5V nominal) for all internal circuitry.

GND I GROUND for all internal circuitry.

REGÝIREGISTER SELECT provides access to Series 2 Flash Memory Card registers

and Card Information Structure in the Attribute Memory Plane.

RST I RESET from system, active high. Places card in Power-On Default State.

RESET pulse width must be t200 ns.

WAITÝOWAIT (Extend Bus Cycle) is used by Intel’s I/O cards and is driven high.

BVD1, BVD2OBATTERY VOLTAGE DETECT: Upon completion of the power on reset cycle,

these signals are driven high to maintain SRAM-card compatibility.

RFU RESERVED FOR FUTURE USE

NC NO INTERNAL CONNECTION. Pin may be driven or left floating.

VS1,VS

2VOLTAGE SENSE: Notifies the host Socket of the card’s VCC requirements.

VS1and VS2are both open, indicating a 5V VCC card.

SERIES 2 FLASH MEMORY CARDS

290434–3

Figure 1. Detailed Block Diagram. The Card Control Logic Provides

Decoding Buffering and Control Signals.

SERIES 2 FLASH MEMORY CARDS

APPLICATIONS

Intel’s second generation Series 2 Flash Memory

Cards facilitate high performance disk emulation for

the storage of data files and application programs on

a purely solid-state removable medium. File man-

agement software, Flash Translation Layer (FTL), in

conjunction with the Series 2 Flash Memory Cards,

enable the design of high-performance light-weight

notebook, palmtop, and pen-based PCs that have

the processing power of today’s desktop computers.

Application software stored on the flash memory

card substantially reduces the slow disk-to-DRAM

download process. Replacing the mechanical disk

results in a dramatic enhancement of read perform-

ance and substantial reduction of power consump-

tion, size and weightÐconsiderations particularly

important in portable PCs and equipment. The Se-

ries 2 Card’s high performance read access time al-

lows the use of Series 2 Cards in an ‘‘execute-in-

place’’ (XIP) architecture. XIP eliminates redundancy

associated with DRAM/Disk memory system archi-

tectures. Operating systems stored in Flash Memory

decreases system boot or program load times, en-

abling the design of PCs that boot, operate, store

data files and execute application programs from/to

nonvolatile memory without losing the ability to per-

form an update.

File management systems modify and store data

files by allocating flash memory space intelligently.

Wear leveling algorithms, employed to equally dis-

tribute the number of rewrite cycles, ensure that no

particular block is cycled excessively relative to oth-

er blocks. This provides hundreds of thousands of

hours of power on usage.

This file management software enables the user to

interact with the flash memory card in precisely the

same way as a magnetic disk.

Series 2 Flash Memory Cards provide durable non-

volatile memory storage for mobile PCs on the road,

facilitating simple transfer back into the desktop en-

vironment.

For systems currently using a static RAM/battery

configuration for data acquisition, the Series 2 Flash

Memory Card’s nonvolatility eliminates the need for

battery backup. The concern for battery failure no

longer exists, an important consideration for porta-

ble computers and medical instruments, both requir-

ing continuous operation. Series 2 Cards consume

no power when the system is off, and only 60 mAin

Deep-Sleep mode (2 Megabyte card). Furthermore,

Flash Memory Cards offer a considerable cost and

density advantage over memory cards based on

static RAM with battery backup.

Besides disk emulation, the Series 2 Card’s electri-

cal block-erasure, data writability, and inherent non-

volatility fit well with data accumulation and record-

ing needs. Electrical block-erasure provides design

flexibility to selectively rewrite blocks of data, while

saving other blocks for infrequently updated param-

eters and lookup tables. For example, networks and

systems that utilize large banks of battery-backed

DRAM to store configuration and status benefit from

the Series 2 Flash Card’s nonvolatility and reliability.

SERIES 2 ARCHITECTURE

OVERVIEW

The Series 2 Flash Memory Card contains a 2 to 20

Megabyte Flash Memory array consisting of 2 to 20

28F008SA FlashFile Memory devices. Each

28F008SA contains sixteen individually-erasable, 64

Kbyte blocks; therefore, the Flash Memory Card

contains from 32 to 320 device blocks. It also con-

tains two Card Control Logic devices that manage

the external interface, address decoding, and com-

ponent management logic. (Refer to Figure 1 for a

block diagram.)

To support PCMCIA-compatible word-wide access,

devices are paired so that each accessible memory

block is 64 KWords (see Figure 2). Card logic allows

the system to write or read one word at a time, or

one byte at a time by referencing the high or low

byte. Erasure can be performed on the entire block

pair (high and low device blocks simultaneously), or

on the high or low byte portion separately.

Also in accordance with PCMCIA specifications this

product supports byte-wide operation, in which the

flash array is divided into 128K x 8 bit device blocks.

In this configuration, odd bytes are multiplexed onto

the low byte data bus.

SERIES 2 FLASH MEMORY CARDS

290434–1

Figure 2. Memory Architecture. Each Device Pair Consists of Sixteen 64 KWord Blocks.

Series 2 Flash Memory Cards offer additional fea-

tures over the Bulk Erase Flash Card product family

(refer to iMC001FLKA, iMC002FLKA and

iMC004FLKA data sheets). Some of the more nota-

ble enhancements include: high density capability,

erase blocking, internal write/erase automation,

erase suspension to read, Component Management

Registers that provide software control of device-

level functions and a deep-sleep mode.

Erase blocking facilitates solid-state storage applica-

tions by allowing selective memory reclamation. Mul-

tiple 64 Kbyte blocks may be simultaneously erased

within the memory card as long as not more than

one block per device is erasing. This shortens the

total time required for erasure, but requires addition-

al supply current. A block typically requires 1.6 sec-

onds to erase. Each memory block can be erased

and completely written 100,000 times.

Erase suspend allows the system to temporarily in-

terrupt a block erase operation. This mode permits

reads from alternate device blocks while that same

device contains an erasing block. Upon completion

of the read operation, erasure of the suspended

block must be resumed.

Write/erase automation simplifies the system soft-

ware interface to the card. A two-step command se-

quence initiates write or erase operations and pro-

vides additional data security. Internal device circuits

automatically execute the algorithms and timings

necessary for data-write or block-erase operations,

including verifications for long-term data integrity.

While performing either data-write or block-erase,

the memory card interface reflects this by bringing

its RDY/BSYÝ(Ready/Busy) pin low. This output

goes high when the operation completes. This fea-

ture reduces CPU overhead and allows software

polling or hardware interrupt mechanisms. Writing

memory data is achieved in single byte or word in-

crements, typically in 6 ms.

Read access time is 150 ns or less over the entire

operating temperature range.

The Reset-PowerDown mode reduces power con-

sumption to less than 60 mA to help extend battery

life of portable host systems. Activated through soft-

ware control, this mode optionally affects the entire

flash array (Global Reset-PowerDown Register) or

specific device pairs (Sleep Control Register).

SERIES 2 FLASH MEMORY CARDS

PCMCIA/JEIDA INTERFACE

The Series 2 Flash Memory Card interface supports

the PCMCIA 2.1 and JEIDA 4.1 68-pin card format

(see Tables 1 and 2). Detailed specifications are de-

scribed in the PC Card Standard, Release 2.1, July,

1993, published by PCMCIA. The Series 2 Card con-

forms to the requirements of both Release 1 and

Release 2 of the PC Card Standard.

Series 2 Card pin definitions are equivalent to the

Bulk-Erase Flash Card except that certain No Con-

nects are now used. A22 through A24, RST (Reset),

and RDY/BSYÝ(Ready/Busy) have pin assign-

ments as set by the PCMCIA standard.

NOTE: The READY/BUSY signal is abbreviated as

RDY/BSY

by PCMCIA (card level) and as

RY/BY

by JEDEC (component level).

The outer shell of the Series 2 card meets all

PCMCIA/JEIDA Type 1 mechanical specifications.

See Figure 19 for mechanical dimensions.

WRITE PROTECT SWITCH

A mechanical write protect switch provides the

card’s memory array with internal write lockout. The

Write-Protect (WP) output pin reflects the status of

this mechanical switch. It outputs a high signal (VOH)

when writes are disabled. This switch does not lock

out writes to the Component Management Regis-

ters.

BATTERY VOLTAGE DETECT

PCMCIA requires two signals, BVD1and BVD2,be

supplied at the interface to reflect card battery con-

dition. Flash Memory Cards do not require batteries.

When the power on reset cycle is complete, BVD1

and BVD2are driven high to maintain compatibility.

CARD DETECT

Two signals, CD1Ýand CD2Ý, allow the host to de-

termine proper socket seating. They reside at oppo-

site ends of the connector and are tied to ground

within the memory card.

DESIGN CONSIDERATIONS

The Series 2 Card consists of two separate memory

planes: the Common Memory Plane (or Main Memo-

ry) and the Attribute Memory Plane. The Common

Memory Plane resides in the banks of device pairs

and represents the user-alterable memory space.

The Component Management Registers (CMR) and

the hardwired Card Information Structure (CIS) re-

side in the Attribute Memory Plane within the Card

Control Logic, as shown in Figure 3. The Card Con-

trol Logic interfaces the PCMCIA connector and the

internal flash memory array and performs address

decoding and data control.

Attribute Memory Plane

accessible with

REG (pin 61) eVIL

290434–2

INTEL ePerformance Enhancement Register

PCMCIA eDefined in PCMCIA Release 2.0

Figure 3. Component Management Registers Allow S/W Control of Components within Card

SERIES 2 FLASH MEMORY CARDS

ADDRESS DECODE

Address decoding provides the decoding logic for

the 2 to 20 Device Chip Enables and the elements of

the Attribute Memory Plane. REGÝselects between

the Common Memory Plane (REGÝeVIH) and the

Attribute Memory Plane (REGÝeVIL).

NOTE:

The Series 2 Card has

active

address inputs A0to

A24 implying that reading and writing to addresses

beyond 32 Megabytes causes wraparound. Further-

more, reads to illegal addresses (for example, be-

tween 20 and 32 Meg on a 20 Megabyte card) re-

turns Default data (00FFH or FFFFH).

The 28F008SA devices, storing data, applications or

firmware, form the Common Memory Plane ac-

cessed individually or as device pairs. Memory is lin-

early mapped in the Common Memory Plane. Three

memory access modes are available when access-

ing the Common Memory Plane: Byte-Wide, Word

Wide, and Odd-Byte modes.

Additional decoding selects the hardwired PCMCIA

CIS and Component Management Registers

mapped in the Attribute Memory Plane beginning at

address 000000H.

The 512 memory-mapped even-byte CMRs are lin-

early mapped beginning at address 4000H in the At-

tribute Memory Plane.

DATA CONTROL

Data Control Logic selects the path and direction for

accessing the Common or Attribute Memory Plane.

It controls any of the PCMCIA-defined Word-Wide,

Byte-Wide or Odd-Byte modes for either reads or

writes to these areas. As shown in Table 3, input

pins which determine these selections are REGÝ,

A0through A24,WE

,OE

,CE

, and CE2Ý.

PCMCIA specifications allow only even-byte access

to the Attribute Memory Plane.

In Byte-Wide mode, bytes contiguous in software ac-

tually alternate between two device blocks of a de-

vice pair. Therefore, erasure of one device block

erases every other contiguous byte. In accordance

with the PCMCIA standard for memory configuration,

the Series 2 Card does not support confining contig-

uous bytes within one flash device when in by-8

mode.

SERIES 2 FLASH MEMORY CARDS

Table 3. Data Access Mode Truth Table

Function Mode REGÝCEÝ2CEÝ1A0OEÝWEÝVPP2 VPP1 D15–D8D7–D0

COMMON MEMORY PLANE

STANDBY(1) XHHXXXV

PPL(2) VPPL(2) HIGH-Z HIGH-Z

BYTE READ H H L L L H VPPL(2) VPPL(2) HIGH-Z EVEN-BYTE

HHLHLHV

PPL(2) VPPL(2) HIGH-Z ODD-BYTE

WORD READ H L L X L H VPPL(2) VPPL(2) ODD-BYTE EVEN-BYTE

ODD-BYTE READ H L H X L H VPPL(2) VPPL(2) ODD-BYTE HIGH-Z

BYTE WRITE H H L L H L VPPH VPPH X EVEN-BYTE

HHLHHLV

PPH VPPH X ODD-BYTE

WORD WRITE H L L X H L VPPH VPPH ODD-BYTE EVEN-BYTE

ODD-BYTE WRITE H L H X H L VPPH VPPL(2) ODD-BYTE X

ATTRIBUTE MEMORY PLANE

BYTE READ L H L L L H X(2) X(2) HIGH-Z EVEN-BYTE

LHLHLHX

(2) X(2) HIGH-Z INVALID

WORD READ L L L X L H X(2) X(2) INVALID EVEN-BYTE

DATA(3)

ODD-BYTE READ L L H X L H X(2) X(2) INVALID HIGH-Z

DATA(3)

BYTE WRITE L H L L H L X(2) X(2) X EVEN-BYTE

LHLHHLX

(2) X(2) X INVALID

OPERATION(3)

WORD WRITE L L L X H L X(2) X(2) INVALID EVEN-BYTE

OPERATION(3)

ODD-BYTE WRITE L L H X H L X(2) X(2) INVALID X

OPERATION(3)

NOTES:

1. Standby mode is valid in Common Memory or Attribute Memory access.

2. To meet the low power specifications, VPP eVPPL; however VPPH presents no reliability problems.

3. Odd-Byte data are not valid during access to the Attribute Memory Plane.

4. H eVIH,LeV

IL,XeDon’t Care.

SERIES 2 FLASH MEMORY CARDS

PRINCIPLES OF OPERATION

Intel’s Series 2 Flash Memory Card provides electri-

cally-alterable, non-volatile, random-access storage.

Individual 28F008SA devices utilize a Command

User Interface (CUI) and Write State Machine

(WSM) to simplify block-erasure and data write oper-

ations.

COMMON MEMORY ARRAY

Figure 4 shows the Common Memory Plane’s orga-

nization. The first block pair (64 KWords) of Com-

mon Memory, referred to as the Common Memory

Card Information Structure Block,

optionally

extends

the hardwired CIS in the Attribute Memory Plane for

additional card information. This may be written dur-

ing initial card formatting for OEM customization.

Since this CIS Block is part of Common Memory, its

data can be altered. Write access to the Common

Memory CIS Block is controlled by the Write Protect

Control Register which may be activated by system

software after power-up. Additionally, the entire

Common Memory plane (minus the Common Memo-

ry CIS Block) may be software write protected.

Note

that the Common Memory CIS Block is not part of

the Attribute Memory Plane. Do not assert REG

access the Common Memory CIS Block

13FFFFFH Device Pair 9

1200000H

1000000H Device Pair 8

0E00000H Device Pair 7

0C00000H Device Pair 6

0A00000H Device Pair 5

0800000H Device Pair 4

0600000H Device Pair 3

0400000H Device Pair 2

0200000H Device Pair 1

0020000H Device Pair 0

0000000H Optional CIS

Figure 4. Common Memory Plane. Use

the Optional Common Memory Plane

CIS for Custom Card Format Information.

HARDWIRED CIS

The card’s structure description resides in the even-

byte locations starting at 0000H and going to the

CIS ending tuple (FNULL) within the Attribute Memo-

ry Plane. Data included in the hardwired CIS con-

sists of tuples. Tuples are a variable-length list of

data blocks describing details such as manufactur-

er’s name, the size of each memory device and the

number of flash devices within the card.

COMPONENT MANAGEMENT

REGISTERS (CMRs)

The CMRs in the Attribute Memory Plane provide

special, software-controlled functionality. Card Con-

trol Logic includes circuitry to access the CMRs.

REG (PCMCIA, pin 61) selects the Attribute Memory

Plane (and therefore the CMRs) when equal to VIL.

CMRs are classified into two categories: those de-

fined by PCMCIA R2.1 and those included by Intel

(referred to as Performance Enhancement Regis-

ters) to enhance the interface between the host sys-

tem and the card’s flash memory array. CMRs (See

Figure 3) provide seven control functionsÐReady-

Busy Interrupt Mode, Device Ready-Busy Status,

Device Ready-Busy Mask, Reset-PowerDown Con-

trol, Software-controlled Write Protection, Card

Status and Soft Reset.

SOFT RESET REGISTER (PCMCIA)

(CONFIGURATION OPTION)

The SOFT RESET REGISTER (Attribute Memory

Plane Address 4000H, Figure 5) is defined in the

PCMCIA Release 2.0 specification as the Configura-

tion Option Register.

Bit 7 is the soft reset bit (SRESET). Writing a 1 to

this bit initiates card reset to the power-on default

state (see Side Bar page 11). This bit must be

cleared to use the CMRs or to access the devices.

SRESET implements in software what the reset pin

implements in hardware. On power-up, the card au-

tomatically assumes default conditions. Similar to

the reset pin (pin 58), this bit clears at the end of a

power-on reset cycle or a system reset cycle.

Bits 0 through 6 are not used by this memory card,

but power up as zeroes for PCMCIA compatibility.

SERIES 2 FLASH MEMORY CARDS

SOFT RESET REGISTER

(CONFIGURATION OPTION REGISTER)

(Read/Write Register)

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 4 BIT 2 BIT 1 BIT 0

PCMCIA CONFIGURATION INDEX

4000H SRESET RESETS TO ZERO ON POWER UP

1eRESET, CLEAR TO ACCESS CARD

Figure 5. SOFT RESET REGISTER (PCMCIA). Sets the Memory Card in the Power-On Default State.

POWER-ON DEFAULT CONDITIONS

#All Devices Powered Up In Standby Mode

#Common Memory Available For Writes

#All Device Ready/Busy Outputs Unmasked

#PCMCIA Ready/Busy Mode Enabled

#Ready/Busy Output Goes To Ready

Global PowerDown Register (PCMCIA)

(Configuration and Status)

The Global Reset-PowerDown Register (Attribute

Memory Plane Address 4002H, Figure 6) is referred

to as the Configuration and Status Register in the

PCMCIA Release 2.0 specification.

Bit 2 (RP) controls global card power-down. Writing

a 1 to this bit places each device within the card into

‘‘Deep-Sleep’’ mode.

Devices in Deep-Sleep are not

accessible.

Recovery from power-down requires

500 ns for reads and 1 ms for writes.

The RP bit defaults to 0 on card power-up or reset.

Setting or clearing this bit has no affect on the bit

settings of the Sleep Control Register.

The remaining Global Reset-PwrDwn Register bits

are defined for Intel’s family of I/O cards and are

driven low for compatibility.

GLOBAL RESET-POWER-DOWN REGISTER

(CONFIGURATION AND STATUS REGISTER)

(Read/Write Register)

1ePOWER DOWN

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

4002H ZEROES RP ZEROES

Figure 6. GLOBAL RESET-PWRDWN REGISTER (PCMCIA). The RP

Bit Enables Reset PowerDown of All Flash Memory Devices.

SERIES 2 FLASH MEMORY CARDS

CARD STATUS REGISTER

(Read Only Register)

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

4100H ADM ADS SRESET CMWP RP CISWP WP RDY/BSYÝ

Figure 7. CARD STATUS REGISTER (Intel) Provides a Quick Review of the Card’s Status

CARD STATUS REGISTER (INTEL)

The Read-Only, CARD STATUS REGISTER (Attri-

bute Memory Plane Address 4100H, Figure 7) re-

turns generalized status of the Series 2 Card and its

CMRs.

Bit 0 (RDY/BSYÝ) reflects the card’s RDY/BSYÝ

(Ready-Busy) output. Software polling of this bit pro-

vides data-write or block-erase operation status. A

zero indicates a busy device(s) in the card.

Bit 1 (WP) reports the position of the card’s Write

Protection switch with 1 indicating write protected. It

reports the status of the WP pin.

Bit 2 (CISWP) reflects whether the Common Memo-

ry CIS is write protected using the WRITE PROTECT

Bit 3 (RP) reports whether the entire flash memory

array is in ‘‘Deep-Sleep’’ (Reset-PwrDwn) mode,

with 1 indicating ‘‘Deep-Sleep’’. This bit reflects the

RP bit of the GLOBAL RESET-POWERDOWN REG-

ISTER. Powering down

all

device pairs individually

(using the Sleep Control Register), also sets this bit.

Bit 4 (CMWP) reports whether the Common Memory

Plane (minus Common Memory CIS) is write protect-

ed via the WRITE PROTECT REGISTER with 1 indi-

cating write protected.

Bit 5 (SRESET) reflects the SRESET bit of the SOFT

RESET REGISTER. It reports that the card is in Soft

Reset with 1 indicating reset. When this bit is zero,

the flash memory array and CMRs may be ac-

cessed, otherwise clear it via the SRESET REGIS-

TER.

Bit 6 (ADS, ANY DEVICE SLEEP) is the ‘‘ORed’’

value of the SLEEP CONTROL REGISTER. Power-

ing down any device pair sets this bit.

Bit 7 (ADM, ANY DEVICE MASKED) is the ‘‘ORed’’

value of the READY/BUSY MASK REGISTER.

Masking any device sets this bit.

WRITE PROTECTION REGISTER

(INTEL)

The WRITE PROTECTION REGISTER (Attribute

Memory Plane Address 4104H, Figure 8) selects

whether the optional Common Memory CIS and the

remaining Common Memory blocks are write pro-

tected (see Figure 4).

Enable Common Memory CIS write protection by

writing a 1 to the CISWP Bit (bit 0).

Enable write protection of the remaining Common

Memory blocks by writinga1totheCMWP Bit (bit

1).

In the power-on default state, both bits are 0, and

therefore not write protected.

Reserved bits (2– 7) have undefined values and

should be written as zeroes for future compatibility.

SERIES 2 FLASH MEMORY CARDS

WRITE PROTECTION REGISTER

(Read/Write Register)

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

4104H RESERVED FOR FUTURE USE CMWP CISWP

1eWRITE PROTECT

Figure 8. WRITE PROTECTION REGISTER (Intel) Eliminates Accidental Data Corruption

SLEEP CONTROL REGISTER (INTEL)

Unlike the GLOBAL RESET-POWERDOWN REGIS-

TER, which simultaneously resets and places all

flash memory devices into a Deep-Sleep mode, the

SLEEP CONTROL REGISTER (Attribute Memory

Plane Address 4118H– 411AH, Figure 9) allows se-

lective power-down control of individual device pairs.

Writinga1toaspecific bit of the SLEEP CONTROL

into the ‘‘Deep-Sleep’’ mode.

Devices in Deep-Sleep

are not accessible

. On cards with fewer than

20 Megabytes (10 device pairs), writing a one to an

absent device pair has no affect and reads back as

zero.

This register contains all zeroes (i.e., not in Deep-

Sleep mode) when the card powers up or after a

hard or soft reset. Furthermore, the Global Reset-

PowerDown Register has no affect on the contents

of this register. Therefore, any bit settings of the

Sleep Control Register will remain unchanged after

returning from a global reset and power down (writ-

ing a zero to the RP bit of the Global Reset-Power-

Down Register).

READY-BUSY STATUS

The bits in the Read-only, READY-BUSY Status

4134H, Figure 10) reflect the status (READYe1,

BUSYe0) of each device’s RY/BYÝoutput. A busy

condition indicates that a device is currently pro-

cessing a data-write or block-erase operation.

These bits are logically ‘‘AND-ed’’ to form the

Ready/Busy output (RDY/BSYÝ, pin 16) of the

PCMCIA interface. On memory cards with fewer

than 20 devices, unused Device RY/BYÝStatus

SLEEP CONTROL REGISTER

(Read/Write Register)

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

411AH RESERVED DEVICES DEVICES

18/19 16/17

4118H DEVICES DEVICES DEVICES DEVICES DEVICES DEVICES DEVICES DEVICES

14/15 12/13 10/11 8/9 6/7 4/5 2/3 0/1

1eSELECTED DEVICE PAIR IN POWER-DOWN MODE AND RESET

Figure 9. SLEEP CONTROL REGISTER (Intel) Allows Specific

Devices to be Reset and Put into Power-Down Mode

SERIES 2 FLASH MEMORY CARDS

READY-BUSY STATUS REGISTER

(Read/Write Register)

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

4134H RESERVED DEVICE DEVICE DEVICE DEVICE

19 18 17 16

4132H DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE

15 14 13 12 11 10 9 8

4130H DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE

76543210

DEVICE READY, 0 eDEVICE BUSY

Figure 10. READY-BUSY STATUS REGISTER (Intel) Provides

Operation Status of All Flash Memory Devices

READY-BUSY MASK REGISTER

(INTEL)

The bits of the Read/Write READY-BUSY MASK

4120H– 4124H, Figure 11) mask out the correspond-

ing ‘‘AND-ed’’ READY-BUSY STATUS REGISTER

bits from the PCMCIA data bus (RDY/BSYÝ, pin 16)

and the CARD STATUS REGISTER RDY/BSYÝBit

(bit 0).

In an unmasked condition (MASK REGISTER bits e

0), any device RY/BYÝoutput going low pulls the

card’s RDY/BSYÝoutput to VIL (BUSY). In this

case, all devices must be READY to allow the card’s

RDY/BSYÝoutput to be ready (VIH).

This is referred

to as the PCMCIA READY-BUSY MODE. An alter-

nate type of READY-BUSY function is described in

the next section, READY-BUSY MODE REGISTER.

READY-BUSY MASK

(Read/Write Register)

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

4124H RESERVED DEVICE DEVICE DEVICE DEVICE

19 18 17 16

4122H DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE

15 14 13 12 11 10 9 8

4120H DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE

76543210

MASK ENABLED

Figure 11. READY-BUSY MASK REGISTER (Intel) Essential for Write Optimization

SERIES 2 FLASH MEMORY CARDS

If the READY-BUSY MASK REGISTER bits are set

to ones (masked condition), the RDY/BSYÝoutput

and the CARD STATUS REGISTER RDY/BSYÝbit

will reflect a READY condition regardless of the

state of the corresponding devices. The READY-

BUSY MASK REGISTER does not affect the

READY-BUSY STATUS REGISTER allowing soft-

ware polling to determine operation status.

Unmasked is the default condition for the bits in this

es, unused device mask bits appear as masked.

READY-BUSY MODE REGISTER

(INTEL)

The READY-BUSY MODE REGISTER (Attribute

Memory Plane Address 4140H, Figure 12) provides

the selection of two types of system interfacing for

the busy-to-ready transition of the card’s

RDY/BSYÝpin:

1. The standard PCMCIA READY-BUSY MODE, in

which the card’s RDY/BSYÝsignal generates a

low-to-high transition (from busy to ready) only

after

all

busy devices (not including masked

devices) have completed their data-write or block-

erase operations. This may result in a long inter-

rupt latency.

2. A High-Performance mode that generates a low-

to-high (from busy-to-ready) transition after each

device becomes ready. This provides the host

system with immediate notification that a specific

device’s operation has completed and that de-

vice may now be used. This is particularly useful

in a file management application where a block

pair, containing only deleted files, is being erased

to free up space so new file data may be written.

Enabling the HIGH-PERFORMANCE READY-BUSY

MODE requires a three step sequence:

1. Set all bits in the READY/BUSY MASK REGIS-

TER. This prevents ready devices from triggering

an unwanted interrupt when step 3 is performed.

2. Write 01H to the READY-BUSY MODE REGIS-

TER. This sets the MODE bit.

3. Write 01H to the READY-BUSY MODE REGIS-

TER. This clears the RACK bit.

The MODE and RACK bits

must

be written in the

prescribed sequence,

not

simultaneously. The

card’s circuitry is designed purposely in this manner

to prevent an initial, unwanted busy-to-ready tran-

sition. Note that in Step 2, writing to the RACK bit is

a Don’t Care.

When the High-Performance Mode is enabled, spe-

cific READY-BUSY MASK bits must be cleared after

an operation is initiated on the respective devices.

After each device becomes ready, the RDY/BSYÝ

pin makes a low-to-high transition. To catch the next

device’s completion of an operation, the RACK bit

must be cleared by writing ‘‘01H’’ to the Ready/Busy

Mode Register.

READY-BUSY MODE REGISTER

(Read/Write Register)

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

4140H RESERVED FOR FUTURE USE RACK MODE

MODE eREADY-BUSY MODE

0ePCMCIA MODE

1eHIGH PERFORMANCE

RACK eREADY ACKNOWLEDGE CLEAR TO

SET UP RDY/BSYÝPIN, THEN CLEAR AFTER

EACH DEVICE BECOMES READY TO ACKNOWL-

EDGE TRANSITION.

Figure 12. High Performance Ready-Busy Mode REGISTER (Intel)

Used to Trigger a Ready Interrupt for Each Device

SERIES 2 FLASH MEMORY CARDS

PRINCIPLES OF DEVICE OPERATION

Individual 28F008SA devices include a Command

User Interface (CUI) and a Write State Machine

(WSM) to manage write and erase functions in each

device block.

The CUI serves as the device’s interface to the Card

Control Logic by directing commands to the appro-

priate device circuitry (Table 4). It allows for fixed

power supplies during block erasure and data writes.

The CUI handles the WEÝinterface into the device

data and address latches, as well as system soft-

ware requests for status while the WSM is operating.

The CUI itself does not occupy an addressable

memory location. The CUI provides a latch used to

store the command and address and data informa-

tion needed to execute the command. Erase Setup

and Erase Confirm commands require both appropri-

ate command data and an address within the block

to be erased. The Data Write Setup command re-

quires both appropriate command data and the ad-

dress of the location to be written, while the Data

Write command consists of the data to be written

and the address of the location to be written.

The CUI initiates flash memory writing and erasing

operations only when VPP is at 12V. Depending on

the application, the system designer may choose to

make the VPP power supply switchable (available

when writes and erases are required) or hardwired to

VPPH. When VPP eVPPL, power savings are in-

curred and memory contents cannot be altered. The

CUI architecture provides protection from unwanted

write and erase operations even when high voltage

is applied to VPP. Additionally, all functions are dis-

abled whenever VCC is below the write lockout volt-

age VLKO, or when the card’s Deep-Sleep modes

are enabled. The WSM automates the writing and

erasure of blocks within a device. This on-chip state

machine controls block erase and data-write, freeing

the host processor for other tasks. After receiving

the Erase Setup and Erase Confirm commands from

the CUI, the WSM controls block-erase. Progress is

monitored via the device’s status register, the card’s

control logic, and the RDY/BSYÝpin of the

PCMCIA interface. Data-write is similarly controlled,

after destination address and expected data are

supplied.

Table 4. Device Command Set

28F008SA Command(1) Cycles

Req’d

Bus First Bus Ccyle Second Bus Cycle

Operation Addr(2) Data Operation Addr(2) Data

x8 Mode x16 Mode x8 Mode x16 Mode

Read Array/Reset 1 Write DA FFH FFFFH

Intelligent Identifer 3 Write DA 90H 9090H Read IA IID(3) IID(3)

Read Device Status Register 2 Write DA 70H 7070H Read DA SRD(4) SRD(4)

Clear Device Status Register 1 Write DA 50H 5050H

Erase Setup/Erase Confirm 2 Write BA 20H 2020H Write BA D0H D0D0H

Erase Suspend/ 2 Write DA B0H B0B0H Write DA D0H D0D0H

Erase Resume

Write Setup/Write 2 Write WA 40H 4040H Write WA WD(5) WD(5)

Alternate Write Setup/Write(6) 2 Write WA 10H 1010H Write WA WD(5) WD(5)

NOTES:

1. Commands other than those shown above are reserved by Intel for future device implementations and should not be

used.

2. DA eA device-level (or device pair) address within the card.

BA eAddress within the block of a specific device (device pair) being erased.

WA eAddress of memory location to be written.

IA eA device-level address; 00H for manufacturer code, 01 for device code.

3. Following the intelligent identifier command, two read operations access manufacturer (89H) and device codes (A2H).

4. SRD eData read from Device Status Register.

5. WD eData to be written at location WA. Data is latched on the rising edge of WEÝ.

6. Either 40H or 10H are recognized by the WSM as the Write Setup command.

SERIES 2 FLASH MEMORY CARDS

COMMAND DEFINITIONS

Read Array (FFH) Ð

Upon initial card power-up, after exit from the Deep-

Sleep modes, and whenever illegal commands are

given, individual devices default to the Read Array

mode. This mode is also entered by writing FFH into

the CUI. In this mode, microprocessor read cycles

retrieve array data. Devices remain enabled for

reads until the CUI receives an alternate command.

Once the internal WSM has started a block-erase or

data-write operation within a device, that device will

not recognize the Read Array command until the

WSM has completed its operation (or the Erase Sus-

pend command is issued during erase).

Intelligent Identifier (90H) Ð

After executing this command, the intelligent identifi-

er values can be read. Only address A0of each de-

vice is used in this mode, all other address inputs

are reserved and should be cleared to 0. [(Manufac-

turer code e89H for A0e0), (Device code eA2H

for A0e1)]. The device will remain in this mode

until the CUI receives another command.

This information is useful by system software in de-

termining what type of flash memory device is con-

tained within the card and allows the correct match-

ing of device to write and erase algorithms. System

software that fully utilizes the PCMCIA specification

will not use the intelligent identifier mode, as this

data is available within the Card Information Struc-

ture (refer to section on PCMCIA Card Information

Structure).

Read Status Register (70H)

After writing this command, a device read outputs

the contents of its Status Register, regardless of the

address presented to that device. The contents of

this register are latched on the falling edge of OEÝ,

CE1Ý(and/or CE2Ý), whichever occurs last in the

read cycle. This prevents possible bus errors which

might occur if the contents of the Status Register

changed while reading its contents. CE1Ý(and

CE2Ýfor odd-byte or word access) or OEÝmust be

toggled with each subsequent status read, or the

completion of a write or erase operation will not be

evident. This command is executable while the

WSM is operating, however, during a block-erase or

data-write operation, reads from the device will auto-

matically return status register data. Upon comple-

tion of that operation, the device remains in the

Status Register read mode until the CUI receives

another command.

The read Status Register command functions when

VPP eVPPL or VPPH.

Clear Status Register (50H)

The Erase Status and Write Status bits may be set

to ‘‘1’’s by the WSM and can only be reset by the

Clear Status Register Command. These bits indicate

various failure conditions. By allowing system soft-

ware to control the resetting of these bits, several

operations may be performed (such as cumulatively

writing several bytes or erasing multiple blocks in

sequence). The device’s Status Register may then

be polled to determine if an error occurred during

that sequence. This adds flexibility to the way the

device may be used.

Additionally, the VPP Status bit (SR.3) MUST be re-

set by system software (Clear Status Register com-

mand) before further block-erases are attempted

(after an error).

The Clear Status Register command functions when

VPP eVPPL or VPPH. This command puts the device

in the Read Array mode.

Write Setup/Write

A two-command sequence executes a data-write

operation. After the system switches VPP to VPPH,

the write setup command (40H) is written to the CUI

of the appropriate device, followed by a second

write specifying the address and write data (latched

on the rising edge of WEÝ). The device’s WSM con-

trols the data-write and write verify algorithms inter-

nally. After receiving the two-command write se-

quence, the device automatically outputs Status

detects the completion of the write operation by an-

alyzing card-level or device-level indicators. Card-

level indicators include the RDY/BSYÝpin and the

READY-BUSY STATUS REGISTER; while device-

level indicators include the specific device’s Status

is valid while the write operation is active. Upon

completion of the data-write sequence (see section

on Status Register) the device’s Status Register re-

flects the result of the write operation. The device

remains in the Read Status Register mode until the

CUI receives an alternate command.

SERIES 2 FLASH MEMORY CARDS

Erase Setup/Erase Confirm

Commands (20H)

Within a device, a two-command sequence initiates

an erase operation on one device block at a time.

After the system switches VPP to VPPH, an Erase

Setup command (20H) prepares the CUI for the

Erase Confirm command (D0H). The device’s WSM

controls the erase algorithms internally. After receiv-

ing the two-command erase sequence, the device

automatically outputs Status Register data when

read (see Figure 14). If the command after erase

setup is not an Erase Confirm command, the CR

sets the Write Failure and Erase Failure bits of the

Status Register, places the device into the Read

Status Register mode, and waits for another com-

mand. The Erase Confirm command enables the

WSM for erase (simultaneously closing the address

latches for that device’s block (A16–A19). The CPU

detects the completion of the erase operation by an-

alyzing card-level or device-level indicators. Card-

level indicators include the RDY/BSY pin and the

READY-BUSY STATUS REGISTER; while device-

level indicators include the specific device’s Status

Suspend command is valid during an active erase

operation. Upon completion of the erase sequence

(see section on Status Register) the device’s Status

The device remains in the Read Status Register

mode until the CUI receives an alternate command.

The two-step block-erase sequence ensures that

memory contents are not accidentally erased. Erase

attempts while VPPL kVPPkVPPH produce spuri-

ous results and are not recommended. Reliable

block erasure only occurs when VPP eVPPH.Inthe

absence of this voltage, memory contents are pro-

tected against erasure. If block erase is attempted

while VPP eVPPL, the VPP Status bit will be set to

‘‘1’’.

When erase completes, the Erase Status bit should

be checked. If an erase error is detected, the de-

vice’s Status Register should be cleared. The CUI

remains in Read Status Register mode until receiv-

ing an alternate command.

Erase Suspend (B0H)/Erase Resume

(D0H)

Erase Suspend allows block erase interruption to

read data from another block of the device or to

temporarily conserve power for another system op-

eration. Once the erase process starts, writing the

Erase Suspend command to the CUI (see Figure 15)

requests the WSM to suspend the erase sequence

at a predetermined point in the erase algorithm. In

the erase suspend state, the device continues to

output Status Register data when read.

Polling the device’s RY/BYÝand Erase Suspend

Status bits (Status Register) will determine when the

erase suspend mode is valid. It is important to note

that the card’s RDY/BSYÝpin will also transition to

VOH and will generate an interrupt if this pin is con-

nected to a system-level interrupt. At this point, a

Read Array command can be written to the device’s

CUI to read data from blocks other than those

which are suspended. The only other valid com-

mands at this time are Read Status Register (70H)

and Erase Resume (D0H). If VPP goes low during

Erase Suspend, the VPP Status bit is set in the

Status Register and the erase operation is aborted.

The Erase Resume command clears the Erase Sus-

pend state and allows the WSM to continue with the

erase operation. The device’s RY/BYÝStatus and

Erase Suspend Status bits and the card’s READY-

BUSY Status Register are automatically updated to

reflect the erase resume condition. The card’s RDY/

BSYÝpin also returns to VOL.

Invalid/Reserved

These are unassigned commands having the same

effect as the Read Array command. Do not issue

any command other than the valid commands speci-

fied above. Intel reserves the right to redefine these

codes for future functions.

SERIES 2 FLASH MEMORY CARDS

DEVICE STATUS REGISTER

Each 28F008SA device in the Series 2 Card con-

tains a Status Register which displays the condition

of its Write State Machine. The Status Register is

read at any time by writing the Read Status com-

mand to the CUI. After writing this command, all sub-

sequent Read operations output data from the

Status Register, until another command is written to

the CUI.

Bit 7ÐWSM Status

This bit reflects the Ready/Busy condition of the

WSM. A ‘‘1’’ indicates that read, block-erase or

data- write operations are available. A ‘‘0’’ indicates

that write or erase operations are in progress.

Bit 6ÐErase Suspend Status

If an Erase Suspend command is issued during the

erase operation, the WSM halts execution and sets

the WSM Status bit and the Erase Suspend Status

bit to a ‘‘1’’. This bit remains set until the device

receives an Erase Resume command, at which point

the CUI resets the WSM Status bit and the Erase

Suspend Status bit.

Bit 5ÐErase Status

This bit will be cleared to 0 to indicate a successful

block-erasure. When set to a ‘‘1’’, the WSM has

been unsuccessful at performing an erase verifica-

tion. The device’s CUI only resets this bit to a ‘‘0’’ in

response to a Clear Status Register command.

Bit 4ÐWrite Status

This bit will be cleared to a 0 to indicate a successful

data-write operation. When the WSM fails to write

data after receiving a write command, the bit is set

to a ‘‘1’’ and can only be reset by the CUI in re-

sponse to a Clear Status Register command.

Bit 3ÐVPP Status

During block-erase and data-write operations, the

WSM monitors the output of the device’s internal

VPP detector. In the event of low VPP, the WSM sets

(‘‘1’’) the VPP Status bit, the status bit for the opera-

tion in progress (either write or erase). The CUI re-

sets these bits in response to a Clear Status Regis-

ter command. Also, the WSM RY/BYÝbit will be set

to indicate a device ready condition. This bit MUST

be reset by system software (Clear Status Register

command) before further data writes or block erases

are attempted.

Device Status Register (Read Only Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WSM Erase Erase Write VPP

Reserved

Status Suspend Status Status Status

Status

SERIES 2 FLASH MEMORY CARDS

290434–17

Bus Command x8 Mode x16 Mode

Operation

Write Write Setup Data e40H Data e4040H

Address eByte Address eWord

Within Card to be Within Card to be

Written Written

Write Data Write Data to be Written Data to be Written

Address eByte Address eWord

Within Card to be Within Card to be

Written Written

Read Defaults to Status Register Status Register

Device Sta- Data. Toggle OEÝ, Data. Toggle OEÝor

tus Register CE1Ýor CE2Ýto (CE1Ýand CE2Ý)

Read Mode update Status to update Status

Standby Check SR Bit 7 Check SR Bits

1eReady, 7 and 15

0eBusy 1 eReady,

0eBusy

FULL STATUS CHECK

PROCEDURE

290434–18

Bus Command x8 Mode x16 Mode

Operation

Standby Check SR Bit 3 Check SR Bits

1eVPP Detected 3 and 11

Low 1 eVPP Detected

Low

Standby Check SR Bit 4 Check SR Bits

1eData Write Error 4 and 12

1eData Write Error

Figure 13. Device-Level Automated Write Algorithm

NOTES:

1. Repeat for subsequent data writes.

2. In addition, the card’s READY-BUSY STATUS REGISTER or the RDY/BSYÝpin may be used.

3. Full device-level status check can be done after each data write or after a sequence of data writes.

4. Write FFH (or FFFFH) after the last data write operation to reset the device(s) to Read Array Mode.

5. If a data write operation fails due to a low VPP (setting SR Bit 3), the Clear Status Register command MUST be issued

before further attempts are allowed by the Write State Machine.

6. If a data write operation fails during a multiple write sequence, SR Bit 4 (Write Status) will not be cleared until the

Command User Interface receives the Clear Status Register command.

SERIES 2 FLASH MEMORY CARDS

290434–19

Bus Command x8 Mode x16 Mode

Operation

Write Erase Data e20H Data e2020H

Setup Address eBlock Address eBlock Pair

Within Card to be Within Card to be

Erased Erased

Write Erase Data eD0H Data eD0D0H

Address eBlock Address eBlock

Within Card to be Pair Within Card to

Erased be Erased

Read Defaults to Status Register Status Register

Device Sta- Data. Toggle OEÝ, Data. Toggle OEÝor

tus Register CE1Ýor CE2Ýto (CE1Ýand CE2Ý)

Read Mode update Status to update Status

Standby Check SR Bit 7 Check SR Bits 7 and 15

1eReady, 1 eReady,

0eBusy 0 eBusy

FULL STATUS CHECK PROCEDURE

290434–20

Bus Command x8 Mode x16 Mode

Operation

Standby Check SR Bit 3 Check SR Bits

1eVPP Detected 3 and 11

Low Either Bit 1 eVPP

Detected Low

Standby Check SR Bits 4 and 5 Check SR Bits 4, 5,

Both 1 eCommand 12, 13

Sequence Error All 1 eCommand

Sequence Error

Standby Check SR Bit 5 Check SR Bits

1eBlock Erase 5 and 13

Error Both 1 eBlock

Erase Failure

Figure 14. Device-Level Automated Erase Algorithm

NOTES:

1. Repeat for subsequent data writes.

2. In addition, the card’s READY-BUSY STATUS REGISTER or the RDY/BSYÝpin may be used.

3. Full device-level status check can be done after each block erase or after a sequence of block erases.

4. Write FFH (or FFFFH) after the last block erase operation to reset the device(s) to Ready Array Mode.

5. If a block erase operation fails due to a low VPP (setting SR Bit 3), the Clear Status Register command MUST be issued

before further attempts are allowed by the Write State Machine.

6. If a block erase operation fails during a multiple block erase sequence, SR Bit 4 (Write Status) will not be cleared until the

Command User Interface receives the Clear Status Register command.

SERIES 2 FLASH MEMORY CARDS

290434–27

Bus Command x8 Mode x16 Mode

Operation

Write Suspend Data eB0H, Data eB0B0H,

Erase Address eDesired Address eDesired

Block to Erase Block Pair to Erase

Suspend Suspend

Read Status Register Status Register

Data. Toggle OEÝ, Data. Toggle OEÝor

CE1Ýor CE2Ýto (CE1Ýand CE2Ý)

update Status to update Status

Standby Check SR Bit 7 Check SR Bit 7 and 15

1eReady, 1 eReady,

0eBusy 0 eBusy

Standby Check SR Bit 6 Check SR Bit 6 and 14

1eSuspended, 1 eSuspended,

0eIn Progress 0 eIn Progress

Write Rd Array Data eFFH Data eFFFFH

Cmd

Read Read Data Read Data

until finished until finished

Write Erase Data eD0H, Data eD0D0H,

Resume Address eValid Address eValid

Block Address. Block Pair Address.

Figure 15. Erase Suspend/Resume Algorithm. Allows Reads to Interrupt Erases.

POWER CONSUMPTION

STANDBY MODE

In most applications, software will only be accessing

one device pair at a time. The Series 2 Card is de-

fined to be in the standby mode when one device

pair is in the Read Array Mode while the remaining

devices are in the Deep-Sleep Mode. The Series 2

Card’s CE1Ýand CE2Ýinput signals must also be

at VIH. In standby mode, much of the card’s circuitry

is shut off, substantially reducing power consump-

tion. Typical power consumption for a 20 Megabyte

Series 2 card in standby mode is 65 mA.

SLEEP MODE

Writing a ‘‘1’’ to the PWRDWN bit of the GLOBAL

POWERDOWN REGISTER places all FlashFile

Memory devices into a Deep-Sleep mode. This dis-

ables most of the 28F008SA’s circuitry and reduces

current consumption to 0.2 mA per device. Addition-

ally, when the host system pulls ASIC control logic

high and latches all address and data lines (i.e., not

toggling), the card’s total current draw is reduced to

approximately 5 mA (CMOS input levels) for a 20

Megabyte card. On writing a ‘‘0’’ to the PWRDWN bit

(Global PowerDown Register) or any individual de-

vice pair (Sleep Control Register), a Deep-Sleep

mode recovery period must be allowed for

28F008SA device circuitry to power back on.

SERIES 2 FLASH MEMORY CARDS

SYSTEM DESIGN CONSIDERATIONS

POWER SUPPLY DECOUPLING

Flash memory power-switching characteristics re-

quire careful device decoupling. System designers

are interested in three supply current issuesÐstand-

by, active and transient current peaks, produced by

rising and falling edges of CE1Ýand CE2Ý. The

capacitive and inductive loads on the card and inter-

nal flash memory device pairs determine the magni-

tudes of these peaks.

The Flash Memory Card features on-card ceramic

decoupling capacitors connected between VCC and

GND, and between VPP1/VPP2 and GND to help

transient voltage peaks.

On the host side, the card connector should also

have a 4.7 mF electrolytic capacitor between VCC

and GND, as well as between VPP1/VPP2 and GND.

The bulk capacitors will overcome voltage slumps

caused by printed-circuit-board trace inductance,

and will supply charge to the smaller capacitors as

needed.

POWER UP/DOWN PROTECTION

Each device in the Flash Memory Card is designed

to offer protection against accidental erasure or writ-

ing, caused by spurious system-level signals that

may exist during power transitions. The card will

power-up into the Read Array Mode.

A system designer must guard against active writes

for VCC voltages above VLKO when VPP is active.

Since both WEÝand CE1Ý(and/or CE2Ý) must be

low for a command write, driving either to VIH will

inhibit writes. With its Command User Interface, al-

teration of device contents only occurs after suc-

cessful completion of the two-step command se-

quences.

While these precautions are sufficient for most appli-

cations, an alternative approach would allow VCC to

reach its steady state value before raising VPP1/

VPP2 above VCC a2.0V. In addition, upon power-

ing-down, VPP1/VPP2 should be below VCC a2.0V,

before lowering VCC.

HOT INSERTION/REMOVAL

The capability to remove or insert PC cards while the

system is powered on (i.e., hot insertion/removal)

requires careful design approaches on the system

and card levels. To design for this capability consid-

er card overvoltage stress, system power droop and

control line stability.

A PCMCIA/JEIDA specified socket properly se-

quences the power supplies to the flash memory

card via shorter and longer pins. This assures that

hot insertion and removal will not result in card dam-

age or data loss.

PCMCIA CARD INFORMATION

STRUCTURE

The Card Information Structure (CIS) starts at ad-

dress zero of the card’s Attribute Memory Plane. It

contains a variable-length chain of data blocks (tu-

ples) that conform to a basic format as shown in

Table 5. This section describes each tuple contained

within the Series 2 Flash Memory Card.

The Device Information Tuple

This tuple (CISTPLÐDEV e01H) contains informa-

tion pertaining to the card’s speed and size. The Se-

ries 2 Card is offered with a 150 nanosecond access

time. Card sizes range between 2 and 20 Mega-

bytes.

Table 5. Tuple Format

Bytes Data

0 Tuple Code: CISTPLÐxxx. The tuple code 0FFH indicates no more tuples in the list.

1 Tuple Link: TPLÐLlNK. Link to the next tuple in the list. This can be viewed as the number of

additional bytes in tuple, excluding this byte. If the link field is zero, the tuple body is empty. If the

link field contains 0FFH, this tuple is the last tuple in the list.

2bn Bytes specific to this tuple.

SERIES 2 FLASH MEMORY CARDS

The Device Geometry Tuple

This tuple (CISTPLÐDEVlCEGEO e1EH) is con-

ceptually similar to a DOS disk geometry tuple

(CISTPLÐGEOMETRY), except it is not a format-

dependent property; this deals with the fixed archi-

tecture of the memory device(s).

Fields are defined as follows:

DGTPL BUSÐValue en, where system bus width

e2(nb1) bytes. N e2 for standard PCMClA Re-

lease 1.0/2.0 cards.

DGTPL EBSÐValue en, where the memory array’s

physical memory segments have a minimum erase

block size of 2(nb1) address increments of

DGTPLÐBUS-wide accesses.

DGTPL RBSÐValue en, where the memory ar-

ray’s physical memory segments have a minimum

read block size of 2(nb1) address increments of

DGTPLÐBUS-wide accesses.

DGTPL WBSÐValue en, where the memory ar-

ray’s physical memory segments have a minimum

write block size of 2(nb1) address increments of

DGTPLÐBUS-wide accesses.

DGTPL PARTÐValue en, where the memory ar-

ray’s physical memory segments can have partitions

subdividing the arrays in minimum granularity of

2(nb1) number of erase blocks.

FL DEVICE INTERLEAVEÐValue en, where card

architectures employ a multiple of 2(nb1) times inter-

leaving of the entire memory arrays with the above

characteristics. Non-interleaved cards have values

ne1.

Jedec Programming

Information Tuple

This tuple (CISTPLÐJEDEC e18H) contains the

Intel manufacturing identifier (89H) and the

28F008SA device ID (A2H).

Level 1 Version/Product

Information Tuple

This tuple (CISTPLÐVERI e15H) contains Level-1-

version compliance and card-manufacturer informa-

tion. Fields are described as follows:

TPLLV1 MAJORÐMajor version number e04H.

TPLLV1 MINORÐMinor version number e01H for

release 2.0.

TPLLV1 INFOÐ

Name of manufacturer eintel;

Name of product eSERIES2-‘‘Card size’’;

Card type e2;

Speed e150 ns or 200 ns

Test Codes eDBBDRELP

Legalities eCOPYRIGHT intel

Corporation 1991

The Configurable Card Tuple

This tuple (ClSTPLÐCONF e1AH) describes the

interface supported by the card and the locations of

the Card Configuration Registers and the Card Con-

figuration Table.

Fields are described as follows:

TPCC SZÐSize of fields byte e01H.

TPCC LASTÐIndex number of the last entry in the

Card Configuration Table e00H.

TPCC RADRÐConfiguration Registers Base Ad-

dress in Reg Space e4000H.

TPCC RMSKÐConfiguration Registers Present

Mask e03H.

The End-Of-List Tuple

The end-of-list tuple (CISTPLÐEND eFFH) marks

the end of a tuple chain. Upon encountering this tu-

ple, continue tuple processing as if a long-link to ad-

dress 0 of common memory space were encoun-

tered.

SERIES 2 FLASH MEMORY CARDS

Tuple Value Description

Address

00H 01H CISTPLÐDEV

02H 03H TPLÐLINK

04H 53H DEVICEÐINFO e

FLASH 150 ns

52H DEVICEÐINFO e

FLASH 200 ns

CARD SIZE

06H 06H 2M

0EH 4M

26H 10M

4EH 20M

08H FFH END OF

DEVICE

0AH 1EH CISTPLÐ

DEVICEGEO

0CH 06H TPLÐLINK

0EH 02H DGTPLÐBUS

10H 11H DGTPLÐEBS

12H 01H DGTPLÐRBS

14H 01H DGPLÐWBS

16H 03H DGTPLÐPART

18H 01H FLÐDEVICE

INTERLEAVE

1AH 18H CISTPLÐJEDEC

1CH 02H TPLÐLINK

1EH 89H INTEL J-ID

20H A2H 28F008 J-ID

22H 15H CISTPLÐVER1

24H 50H TPLÐLINK

26H 04H TPLLV1

MAJOR

28H 01H TPLLV1

MINOR

2AH 69H TPLLV1 INFO

2CH 6EH n

2EH 74H t

30H 65H e

Tuple Value Description

Address

32H 6CH l

34H 00H END TEXT

36H 53H S

38H 45H E

3AH 52H R

3CH 49H I

3EH 45H E

40H 53H S

42H 32H 2

44H 2DH Ð

46H 30H 2M e0

30H 4M e0

31H 10M e1

32H 20M e2

48H 32H 2M e2

34H 4M e4

30H 10M e0

30H 20M e0

4AH 20H SPACE

4CH 00H END TEXT

4EH 32H CARD TYPE 2

50H 41H A e2M, 150 ns

42H B e4M, 150 ns

45H E e10M, 150 ns

5AH Z e20M, 150 ns

48H H e2M, 200 ns

49H I e4M, 200 ns

4CH L e10M, 200 ns

4FH O e20M, 200 ns

SERIES 2 FLASH MEMORY CARDS

Tuple Value Description

Address

52H 20H SPACE

54H 52H REGBASE-R

56H 45H E

58H 47H G

5AH 42H B

5CH 41H A

5EH 53H S

60H 45H E

62H 20H SPACE

4000h

64H 34H 4

66H 30H 0

68H 30H 0

6AH 30H 0

6CH 68H h

6EH 20H SPACE

70H 44H D

72H 42H B

74H 42H B

76H 44H D

78H 52H R

7AH 45H E

7CH 4CH L

7EH 50H P

80H 00H END TEXT

82H 43H C

84H 4FH O

86H 50H P

88H 59H Y

8AH 52H R

8CH 49H I

8EH 47H G

90H 48H H

92H 54H T

94H 20H SPACE

Tuple Value Description

Address

96H 69H i

98H 6EH n

9AH 74H t

9CH 65H e

9EH 6CH l

A0H 20H SPACE

CORPORATION

A2H 43H C

A4H 4FH O

A6H 52H R

A8H 50H P

AAH 4FH O

ACH 52H R

AEH 41H A

B0H 54H T

B2H 49H I

B4H 4FH O

B6H 4EH N

B8H 20H SPACE

BAH 31H 1

BCH 39H 9

BEH 39H 9

C0H 31H 1

C2H 00H END TEXT

C4H FFH END OF LIST

C6H 1AH CISTPLÐCONF

C8H 06H TPLÐLINK

CAH 01H TPCCÐSZ

CCH 00H TPCCÐLAST

CEH 00H TPCCÐRADR

D0H 40H TPCCÐRADR

D2H 03H TPCCÐRMSK

D4H FFH END OF LIST

D6H FFH CISTPLÐEND

D8H 00H INVALID ECIS

ADDRESS

SERIES 2 FLASH MEMORY CARDS

OPERATING SPECIFICATlONS

ABSOLUTE MAXIMUM RATINGS*

Storage TemperatureÀÀÀÀÀÀÀÀÀÀÀÀb40§Ctoa

85§C

Voltage on Any Pin with

Respect to Ground ÀÀÀÀÀb2.0V to VCC a2.0V(1)

VPP1/VPP2 Supply Voltage with

Respect to Ground ÀÀÀÀÀÀÀb2.0V to a14.0V(1, 2)

VCC Supply Voltage with

Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to a7.0V

NOTICE: This data sheet contains preliminary infor-

mation on new products in production. The specifica-

tions are subject to change without notice. Verify with

your local Intel Sales office that you have the latest

data sheet before finalizing a design.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

NOTES:

1. Minimum DC input voltage is b0.5V. During transitions, inputs may undershoot to b2.0V tor periods of less than 20 ns.

Maximum DC voltage on output pins is VCC a0.5V. The voltage may overshoot to VCC a2.0V for periods of less than 20

ns.

2. Maximum DC input voltage on VPP1/VPP2 may overshoot to a14.0V for periods of less than 20 ns.

COMMERCIAL TEMPERATURE OPERATING CONDITIONS

These operating conditions apply to commercial temperature devices.

Symbol Parameter Min Max Unit

TAOperating Temperature 0 70 §C

VCC VCC Supply Voltage (5%) 4.75 5.25 V

EXTENDED TEMPERATURE OPERATING CONDITIONS

These operating conditions apply to extended temperature devices.

Symbol Parameter Min Max Unit

TAOperating Temperature b40 85 §C

VCC VCC Supply Voltage (5%) 4.75 5.25 V

CHARACTERISTICS

All AC and DC characteristics apply to both commercial and extended temperature devices.

COMMON DC CHARACTERISTICS, CMOS and TTL

Symbol Parameter Notes Min Typ Max Unit Test Condition

ILI Input Leakage Current 1, 3 g1g20 mAV

CC eVCC Max

VIN eVCC or GND

ILO Output Leakage Current 1 g1g20 mAV

CC eVCC Max

VOUT eVCC or GND

VIL Input Low Voltage 1 b0.5 0.8 V

VIH Input High Voltage (TTL) 12.4 VCC a0.3 V

Input High Voltage (CMOS) 0.7 VCC VCC a0.3

VOL Output Low Voltage 1 VSS 0.4 V VCC eVCC Min

IOL e3.2 mA

VOH Output High Voltage 1 4.0 VCC VV

CC eVCC Min

IOH eb

2.0 mA

VPPL VPP during Read Only Operations 1, 2 0.0 6.5 V

VPPH VPP during Read/Write Operations 1 11.4 12.6 V

VLKO VCC Erase/Write Lock Voltage 1 2.0 V

NOTES:

1. Values are the same for byte and word wide modes and for all card densities.

2. Block Erases/Data Writes are inhibited when VPP eVPPL and not guaranteed in the range between VPPH and VPPL.

3. Exceptions: With VIN eGND, the leakage on CE1Ý,CE

, REGÝ,OE

,WE

, will be s500 mA due to internal pullup

resistors and, with VIN eVCC, RST leakage will be s500 mA due to internal pulldown resistor.

SERIES 2 FLASH MEMORY CARDS

DC CHARACTERISTICS, CMOS

Symbol Parameter Notes Byte Wide Mode Word Wide Mode Unit Test Condition

Min Typ Max Min Typ Max

ICCR VCC Read Current 1, 3 45 85 65 120 mA VCC eVCC Max,

Control Signals

eGND

tCYCLE e200 ns,

IOUT e0mA

CCW VCC Write Current 1, 3 35 80 45 110 mA Data Write

in Progress

ICCE VCC Erase Current 1, 2, 3 35 80 45 110 mA Block (Pair) Erase

in Progress

ICCS VCC Standby Current 2 Meg

1, 4, 6

110 420 110 420

VCC eVCC Max,

Control Signals

4 Meg 160 620 160 620 eVIH

10 Meg 310 1220 310 1220

20 Meg 560 2200 560 2200

ICCSL VCC Sleep Current 2 Meg

1, 4, 5

60 60

4 Meg 100 100

10 Meg 260 260

20 Meg 460 460

IPPW VPP Write 1, 3 15 30 mA Data Write

Current (VPP eVPPH) in Progress

IPPE VPP Erase 1, 3 15 30 mA Block (Pair) Erase

Current (VPP eVPPH) in Progress

IPPSL VPP Sleep Current 2 Meg

1, 5

0.2 10 0.2 10

4 Meg 0.4 20 0.4 20

10 Meg 1 50 1 50

20 Meg 2 100 2 100

IPPS1 VPP Standby or 2 Meg

1, 6

2.0 20 2.0 20

Read Current 4 Meg 2.2 30 2.2 30

(VPP sVCC)

10 Meg 2.8 60 2.8 60

20 Meg 3.8 110 3.8 110

IPPS2 VPP Standby or 2 Meg

1, 6

20 400 20 400

Read Current 4 Meg 40 800 40 800

(VPP lVCC)

10 Meg 100 2000 100 2000

20 Meg 200 4000 200 4000

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC e5.0V, VPP e12.0V, T e25§C.

2. The Data Sheet specification for the 28F008SA in Erase Suspend (ICCES) is 5 mA typical and 10 mA max with the device

deselected. If the device(s) are read while in Erase Suspend Mode, current draw is the sum of ICCES and ICCR.

3. Standby or Sleep currents are not included for non-accessed devices.

4. Address and data inputs to card static. Control line voltages equal to VIH or VIL.

5. All 28F008SA devices in Deep-Sleep (Reset-PowerDown) mode.

6. In Byte and Word Mode, all but two devices in Deep-Sleep.

SERIES 2 FLASH MEMORY CARDS

DC CHARACTERISTICS, TTL

Symbol Parameter Notes Byte Wide Mode Word Wide Mode Unit Test Condition

Min Typ Max Min Typ Max

ICCR VCC Read Current 1, 3 70 135 90 170 mA VCC eVCC Max,

Control Signals eGND

tCYCLE e200 ns,

IOUT e0mA

CCW VCC Write Current 1, 3 60 130 70 160 mA Data Write

in Progress

ICCE VCC Erase Current 1, 2, 3 60 130 70 160 mA Block (Pair) Erase

in Progress

ICCS VCC Standby Current 2 Meg

1, 4, 6 20 100 20 100 mA

VCC eVCC Max,

Control Signals

4 Meg eVIH

10 Meg

20 Meg

ICCSL VCC Sleep Current 2 Meg

4 Meg 1, 4, 5 20 100 20 100 mA

10 Meg

20 Meg

IPPW VPP Write 1, 3 10 30 20 60 mA Data Write

Current (VPP eVPPH) in Progress

IPPE VPP Erase 1, 3 10 30 20 60 mA Block (Pair) Erase

Current (VPP eVPPH) in Progress

IPPSL VPP Sleep Current 2 Meg

1, 5

0.2 10 0.2 10

4 Meg 0.4 20 0.4 20

10 Meg 1.0 50 1.0 50

20 Meg 2.0 100 2.0 100

IPPS1 VPP Standby or 2 Meg

1, 6

2.0 20 2.0 20

Read Current 4 Meg 2.2 30 2.2 30

(VPP sVCC)

10 Meg 2.8 60 2.8 60

20 Meg 3.8 110 3.8 110

IPPS2 VPP Standby or 2 Meg

1, 6

20 400 20 400

Read Current 4 Meg 40 800 40 800

(VPP lVCC)

10 Meg 100 2000 100 2000

20 Meg 200 4000 200 4000

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC e5.0V, VPP e12.0V, T e25§C.

2. The Data Sheet specification for the 28F008SA in Erase Suspend (ICCES) is 5 mA typical and 10 mA max with the device

deselected. If the device(s) are read while in Erase Suspend Mode, current draw is the sum of ICCES and ICCR.

3. Standby or Sleep currents are not included for non-accessed devices.

4. Address and data inputs to card static. Control line voltages equal to VIH or VIL.

5. All 28F008SA devices in Deep-Sleep (Reset-PowerDown) mode.

6. In Byte and Word Mode, all but two devices in Deep-Sleep.

7. The current consumption from the 28F008SA is insignificant in relation to the ASIC’s.

SERIES 2 FLASH MEMORY CARDS

AC CHARACTERISTICS

AC Timing Diagrams and characteristics are guaran-

teed to meet or exceed PCMCIA Release 2.0 speci-

fications. PCMCIA allows a 300 ns access time for

Attribute Memory. Note that read and write access

timings to the Series 2 Flash Memory Card’s Com-

mon and Attribute Memory Planes are identical at

150 ns. Furthermore, there is no delay in switching

between the Common and Attribute Memory Planes.

COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Read-Only Operations

Symbol Parameter Notes Min Max Unit

JEDEC PCMCIA

tAVAV tRC Read Cycle Time 150 ns

tAVQV ta(A) Address Access Time 150 ns

tELQV ta(CE) Card Enable Access Time 150 ns

tGLQV ta(OE) Output Enable Access Time 75 ns

tEHQX tdis (CE) Output Disable Time from CEÝ75 ns

tGHQZ tdis (CE) Output Disable Time from OEÝ75 ns

tGLQX ten (CE) Output Enable Time from CEÝ5ns

ELQX ten (OE) Output Enable Time from OEÝ5ns

AXQX tv(A) Data Valid from Add Change 0 ns

tRHQV Reset-PwrDwn Recovery to Output Delay 500 ns

tsu (VCC) CE Setup Time on Power-Up 1 ms

First Access after Reset 500 ns

290434–28

Transient Input/Output Reference Waveform (VCC e5.0V) for Standard Test Configuration

290434–29

Transient Input/Output Reference Waveform (VCC e3.3V) for Standard Test Configuration

SERIES 2 FLASH MEMORY CARDS

Figure 16. AC Waveform for Read Operations

290434–21

NOTE:

1. The hatched area may be either high or low.

SERIES 2 FLASH MEMORY CARDS

COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: Write Operations(1)

Symbol Parameter Notes Min Max Unit

JEDEC PCMCIA

tAVAV tWC Write Cycle Time 150 ns

tWLWH tw(WE) Write Pulse Width 80 ns

tAVWL tsu (A) Address Setup Time 20 ns

tAVWH tsu (A-WEH) Address Setup Time for WEÝ100 ns

tVPWH tvps VPP Setup to WEÝGoing High 100 ns

tELWH tsu (CE-WEH) Card Enable Setup Time for WEÝ100 ns

tDVWH tsu (D-WEH) Data Setup Time for WEÝ50 ns

tWHDX th(D) Data Hold Time 20 ns

tWHAX trec (WE) Write Recover Time 20 ns

tWHRL WEÝHigh to RDY/BSYÝ120 ns

tWHQV1 Duration of Data Write Operation 6 ms

tWHQV2 Duration of Block Erase Operation 0.3 sec

tQVVL VPP Hold from Operation Complete 2 0 ns

tWHGL th(OE-WE) Write Recovery before Read 10 ns

tRHWL Reset-PwrDwn Recovery to WEÝGoing Low 1 ms

NOTES:

1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to

AC Characteristics for Read-Only operations.

2. Refer to text on Data-Write and Block-Erase Operations.

BLOCK ERASE AND DATA WRITE PERFORMANCE

Parameter Notes Min Typ(3) Max Unit

Block Pair Erase Time(1) 2, 4 1.1 10 sec

Block Pair Write Time 2, 4 0.5 2.1 sec

Byte/Word Write Time 4 4.8 ms6ms3ms

NOTES:

1. Individual blocks can be erased 100,000 times.

2. Excludes System-Level Overhead.

3. 25§C, 12.0 VPP.

4. Monitor Ready/Busy Registers for the completion of a write/erase command.

SERIES 2 FLASH MEMORY CARDS

Figure 17. AC Waveform for Write Operations

290434–22

NOTE:

By writing the appropriate register, or on power-up, the card control ASIC generates the RPÝsignal to the card’s devices.

SERIES 2 FLASH MEMORY CARDS

COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: CEÝ-Controlled Write Operations(1)

Symbol Parameter Notes Min Max Unit

JEDEC PCMCIA

tAVAV tWC Write Cycle Time 1 150 ns

tELEH tw(WE) Chip Enable Pulse Width 1 80 ns

tAVEL tsu (A) Address Setup Time 1 20 ns

tAVEH tsu (A-WEH) Address Setup Time for CEÝ1 100 ns

tVPEH tvps VPP Setup to CEÝGoing High 1 100 ns

tWLEH tsu (CE-WEH) Write Enable Setup Time for CEÝ1 100 ns

tDVEH tsu (D-WEH) Data Setup Time for CEÝ150 ns

EHDX th(D) Data Hold Time 1 20 ns

tEHAX trec (WE) Write Recover Time 1 20 ns

tEHRL CEÝHigh to RDY/BSYÝ1 120 ns

tEHQV1 Duration of Duration of Data Write Operation 1 6 ms

Data Write

tEHQV2 Duration of Duration of Block Erase Operation 1 0.3 sec

Erase

tQVVL VPP Hold from Operation Complete 1, 2 0 ns

tEHGL th(OE-WE) Write Recovery before Read 1 10 ns

tRHEL Reset-PwrDwn Recovery to CEÝGoing Low 1 ms

NOTES:

1. Read timing characteristics during erase and data write operations are the same as during read-only operations. Refer to

AC Characteristics for Read-Only operations.

2. Refer to text on Data-Write and Block-Erase Operations.

SERIES 2 FLASH MEMORY CARDS

Figure 18. Alternate AC Waveform for Write Operations

290434–23

NOTE:

By writing the appropriate register, or on power-up, the card control ASIC generates the RPÝsignal to the card’s devices.

SERIES 2 FLASH MEMORY CARDS

290434–24

Figure 19. Series 2 Flash Memory Card Package Dimensions

SERIES 2 FLASH MEMORY CARDS

290434–25

Figure 20. Card Connector Socket

290434–26

L1 MAX L2 L3 REF

0.020 Pin TypeÐSee Table 1 0.024

(0.5) Detect 0.059 (1.5) g0.039 (0.6)

General 0.084 (2.1) g0.064

Power 0.098 (2.5) g0.078

Figure 21. Pin/Socket Contact Length with Wipe

SERIES 2 FLASH MEMORY CARDS

Label Dimensions

290434–30

NOTES:

Total label dimensions are g0.003×

Total label thickness with adhesive is 0.002×

Card Dimensions with Label

290434–31

Figure 22. Label Information

SERIES 2 FLASH MEMORY CARDS

Table 5. Capacitance TAe25§C, f e1.0 MHz

Symbol Characteristics Commercial Unit

Min Max

CIN Address/Control Capacitance (A0–A8,CE

,CE

)30pF

Address/Control Capacitance (A9–A24, all others) 20 pF

VCC,V

PP 2mF

COUT Output Capacitance 20 pF

NOTE:

Sampled, not 100% tested.

ORDERING INFORMATION

iMC020FLSA-15

WHERE:

ieINTEL

MC eMEMORY CARD

020 eDENSITY IN MEGABYTES

(002,004,010,020 AVAILABLE)

FL eFLASH TECHNOLOGY

SeBLOCKED ARCHITECTURE

AeSERIES 2

-ET eEXTENDED TEMPERATURE

15 e150 ns

M9508014,SBXXXX

MeMANILA

95 e1995

08 eWEEK 08

014 eLOT Ý

SBXXXX eCUSTOMER IDENTIFIER

ADDITIONAL INFORMATION ORDER NUMBER

28F008SA FlashFileTM Memory Data Sheet 290429

AP-361 ‘‘Implementing the Integrated Registers of the Series 2 Flash Memory Card’’ 292096

AP-364 ‘‘28F008SA Automation and Algorithms’’ 292099

AP-359 ‘‘28F008SA Hardware Interfacing’’ 292094

AP-360 ‘‘28F008SA Software Drivers’’ 292095

AP-606 ‘‘Interchangeability of Series 1/2/2aFlash Memory Cards’’

REVISION HISTORY

Number Description

02 Added 150 ns TUPLE, Deleted 250 ns TUPLE

Corrected Global Power Register Address to 4002H

Corrected Write Protection Register Address to 4104H

Corrected Ready-Busy Mode Register Address to 4140H

ICC Standby Byte Wide Mode MAX/TYP Increased

Added Power-On Timing Spec

Added First Access after Reset Spec

Changed Advanced Information to Preliminary

03 Added 2 MByte card support

Changed write timing waveforms to match PCMCIA

Changed PowerDown (PWD) to Reset-PowerDown (RP)

04 Extended Operating Temperature Range

Added Maximum Byte Write Time

05 Added 150 ns Timings

Change Cover Drawing to Accommodate Label

06 Modified DC characteristics to reflect a conversion to new memory componentsÐthe 0.4m

version of the 28F008SA. The new devices also have improved program and erase

performance.