1
®X9420
Low Noise/Low Power/SPI Bus
Single Digitally Controlled (XDCP™)
Potentiometer
FEATURES
• Solid-State Potentiometer
• SPI Serial Interface
• Register Oriented Format
—Direct read/write/transfer wiper positions
—Store as many as four positions per
potentiometer
• Power Supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low Power CMOS
—Standby current < 1µA
• High Reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 8-bytes of Nonvolatile EEPROM Memory
•10kΩ or 2.5kΩ Resistor Arrays
• Resolution: 64 Taps Each Pot
• 14 Ld TSSOP and 16 Ld SOIC Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
DESCRIPTION
The X9420 integrates a single digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Interface
and
Control
Circuitry
HOLD
CS
SI
A0
VH/RH
VL/RL
Data
8
VW/RW
SCK
S0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Data Sheet FN8195.1April 26, 2006
NOT RECOMMENDED FOR NEW DESIGNS
POSSIBLE SUBSTITUTE PRODUCT
ISL22416, ISL22419, ISL95311, ISL95711
2FN8195.1
April 26, 2006
Ordering Information
PART NUMBER PART
MARKING VCC LIMITS (V)
POTENTIOMETER
ORGANIZATION
(k) TEMP. RANGE
(°C) PACKAGE PKG.
DWG. #
X9420WS16* X9420WS 5 ±10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420WS16Z* (Note) X9420WS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WS16I* X9420WS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420WS16IZ* (Note) X9420WS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WV14* X9420 W 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420WV14Z* (Note) X9420 WZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WV14I* X9420 WI -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420WV14IZ* (Note) X9420 WZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YS16* X9420YS 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420YS16Z* (Note) X9420YS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YS16I* X9420YS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420YS16IZ* (Note) X9420YS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YV14* X9420 Y 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420YV14Z* (Note) X9420 YZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YV14I* X9420 YI -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420YV14IZ* (Note) X9420 YZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WS16-2.7* X9420WS F 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420WS16Z-2.7* (Note) X9420WS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WS16I-2.7* X9420WS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420WS16IZ-2.7*
(Note) X9420WS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420WV14-2.7* X9420 WF 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420WV14Z-2.7* (Note) X9420 WZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WV14I-2.7* X9420 WG -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420WV14IZ-2.7*
(Note) X9420 WZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YS16-2.7* X9420YS F 2.7 to 5.5 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3
X9420YS16Z-2.7* (Note) X9420YS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YS16I-2.7* X9420YS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9420YS16IZ-2.7* (Note) X9420YS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-free) M16.3
X9420YV14-2.7* X9420 YF 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9420YV14Z-2.7* (Note) X9420 YZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420YV14I-2.7* X9420 YG -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9420YV14IZ-2.7* (Note) X9420 YZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9420
3FN8195.1
April 26, 2006
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched
by the rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9420.
Chip Select (CS)
When CS is HIGH, the X9420 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9420, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A0)
The address inputs is used to set the least significant
bit of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9420. A maximum of 2 devices may occupy the
SPI serial bus.
Potentiometer Pins
VH/RH, VL/RL
The VH/RH and VL/RL input are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
VW/RW
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
System/Digital Supply (VCC)
VCC is the supply voltage for the system/digital
section. VSS is the system ground.
PIN CONFIGURATION
VCC
CS
RL/VL
SI
WP
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V+
NC
A0
SO
HOLD
SCK
NC
V-
DIP/SOIC
X9420
RH/VH
RW/VW
TSSOP
VCC
CS
RL/VL
SI
WP
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
A0
SO
HOLD
SCK
V-
X9420
RH/VH
RW/VW
X9420
4FN8195.1
April 26, 2006
PIN NAMES
PRINCIPLES OF OPERATION
The X9420 is a highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing
direct communication between the host and the XDCP
potentiometer.
Serial Interface
The X9420 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9420 is comprised of one resistor array
containing 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within the individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches. The block
diagram of the potentiometer is shown in Figure 1.
Wiper Counter Register (WCR)
The X9420 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9420 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Data Registers
The potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of the Data Registers is
a nonvolatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Register Descriptions
Table 1. Data Registers, (6-bit), Nonvolatile
There are four 6-bit Data Registers associated with the
potentiometer.
– {D5~D0}: These bits are for general purpose Non-
volatile data storage or for storage of up to four dif-
ferent wiper values.
Table 2. Wiper Counter Register, (6-bit), Volatile
– {WP5~WP0}: These bits specify the wiper position
of the potentiometer.
Symbol Description
SCK Serial Clock
SI, SO Serial Data
A0 Device Address
VH/RH,
VL/RL
Potentiometer Pins (terminal equivalent)
VW/RWPotentiometer Pins (wiper equivalent)
WP Hardware Write Protection
HOLD Serial Communication Pause
V+,V- Analog Supplies
VCC System Supply Voltage
VSS System Ground
NC No Connection
0 0 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
0 0 WP5 WP4 WP3 WP2 WP1 WP0
(MSB) (LSB)
X9420
5FN8195.1
April 26, 2006
Figure 1. Detailed Potentiometer Block Diagram
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
INSTRUCTIONS
Address/Identification (ID) Byte
The first byte sent to the X9420 from the host,
following a CS going HIGH to LOW, is called the
Address or Identification byte. The most significant
four bits of the slave address are a device type
identifier, for the X9420 this is fixed as 0101[B] (refer
to Figure 2).
The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address
is defined by the state of the A0 input pin. The X9420
compares the serial data stream with the address
input state; a successful compare of the address bit is
required for the X9420 to successfully continue the
command sequence. The A0 input can be actively
driven by a CMOS input signal or tied to VCC or VSS.
The remaining three bits in the ID byte must be set to 110.
Figure 2. Address/Identification Byte Format
Instruction Byte
The next byte sent to the X9420 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four data registers. The format is
shown below in Figure 3.
Figure 3. Instruction Byte Format
Serial Data Path
From Interface
Circuitry
Register 0 Register 1
REGISTER 2 REGISTER 3
Serial
Bus
Input
Parallel
Bus
Input
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCK
UP/DN
VH
VL
VW
8 6
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN VW = VL
IF WCR = 3F[H] THEN VW = VH
Wiper
(WCR)
100
11 0A0
Device Type
Identifier
Device Address
1
I1I2I3 I0 R1 R0 0 0
Register
Select
Instructions
X9420
6FN8195.1
April 26, 2006
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits are defined as 0.
Two of the eight instructions are two bytes in length
and end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register —
This instruction transfers the contents of one speci-
fied Data Register to the Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by tWRL. A transfer from
the WCR (current wiper position), to a Data Register is
a write to nonvolatile memory and takes a minimum of
tWR to complete. The transfer can occur between the
potentiometer and one of its associated registers.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9420; either between the host and
one of the Data Registers or directly between the host
and the WCR. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the pot,
– Write Wiper Counter Register—change current
wiper position of the pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The sequence of these operations is shown in Figure
5 and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of
the sequence and timing for this operation are shown
in Figure 7 and Figure 8.
Figure 4. Two-Byte Instruction Sequence
0101110A0I3 I2 I1 I0 R1 R0 0 0
SCK
SI
CS
X9420
7FN8195.1
April 26, 2006
Figure 5. Three-Byte Instruction Sequence (Write)
Figure 6. Three-Byte Instruction Sequence (Read)
Figure 7. Increment/Decrement Instruction Sequence
Figure 8. Increment/Decrement Timing Limits
0 101 0A0 I3 I2 I1 I0 R1 R0 0 0
SCL
SI
0 0 D5 D4 D3 D2 D1 D0
CS
11
0 101 0A0 I3 I2 I1 I0 R1 R0 0 0
SCL
SI
CS
11
S0
0 0 D5 D4 D3 D2 D1 D0
Don’t Care
0101110A0 I3 I2 I1 I0 0 0 0
SCK
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
CS
SCK
SI
VW
INC/DEC CMD Issued
tWRID
Voltage Out
X9420
8FN8195.1
April 26, 2006
Table 3. Instruction Set
Instruction
Instruction Set
OperationI3I2I1I0R1R0
Read Wiper Counter
Register
1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register
Write Wiper Counter
Register
1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register
Read Data Register 1 0 1 1 R1R00 0 Read the contents of the Data Register pointed to by
R1 - R0
Write Data Register 1 1 0 0 R1R00 0 Write new value to the Data Register pointed to by
R1 - R0
XFR Data Register to
Wiper Counter
Register
1101R
1R00 0 Transfer the contents of the Data Register pointed to
by R1 - R0 to the Wiper Counter Register
XFR Wiper Counter
Register to Data
Register
1110R
1R00 0 Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by R1 - R0
Increment/Decrement
Wiper Counter
Register
0 0 1 0 0 0 0 0 Enable Increment/decrement of the Wiper Counter
Register
Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by check-
ing the WIP bit.
X9420
9FN8195.1
April 26, 2006
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Read the contents of the Register pointed to by R1 - R0.
Write Data Register (DR)
Write a new value to the Register pointed to by R1 - R0.
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1 - R0 to the WCR.
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
wiper position
(sent by X9420 on SO) CS
Rising
Edge
0101110A
01001000000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by Host on SI) CS
Rising
Edge
0101110A
01010000000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by X9420 on SO) CS
Rising
Edge
0101110A
01011R
1
R
00000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by host on SI) CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0101110A
01100R
1
R
00000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses CS
Rising
Edge
0101110A
01101R
1
R
000
X9420
10 FN8195.1
April 26, 2006
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Increment/Decrement Wiper Counter Register (WCR)
Read Status
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0101110A
01110R
1
R
000
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
increment/decrement
(sent by master on SDA) CS
Rising
Edge
0101110A
000100000I/DI/D. . . .I/DI/D
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by X9420 on SO) CS
Rising
Edge
0101110A
0010100010000000
W
I
P
X9420
11 FN8195.1
April 26, 2006
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .....................-65C to +135C
Storage temperature ..........................-65C to +150C
Voltage on SCK, SCL or any
address input with respect to VSS ........... -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH/RH, VL/RL, VW/RW ........................... V- to V+
Lead temperature (soldering, 10s) .....................300C
IW (10s) ..............................................................±6mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as
a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH - VL)/63, single pot.
(4) Typical = Individual array resolution.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
RTOTAL End to End Resistance ±20 %
Power Rating 50 mW 25C, each pot
IW Wiper Current ±3 mA
RWWiper Resistance 150 250 ΩWiper Current = ± 1mA,
V+/V- = ±3V
40 100 ΩWiper Current = ± 1mA,
V+/V- = ±5V
Vv+ Voltage on V+ Pin X9420 +4.5 +5.5 V
X9420-2.7 +2.7 +5.5
Vv- Voltage on V- Pin X9420 -5.5 -4.5 V
X9420-2.7 -5.5 -2.7
VTERM Voltage on any VH/RH, VL/RL, VW/RW V- V+ V
Noise -140 dBV Ref: 1kHz
Resolution(4) 1.6 % See Note 5
Absolute Linearity(1) ±1 MI(3) Vw(n)(actual) - Vw(n)(expected)
Relative Linearity(2) ±0.2 MI(3) Vw(n + 1) - [Vw(n) + MI]
Temperature Coefficient of RTOTAL ±300 ppm/C See Note 5
Ratiometric Temperature Coefficient ±20 ppm/C See Note 5
CH/CL/CWPotentiometer Capacitances 10/10/25 pF See Circuit #3
IAL Rh, RI, Rw leakage current 0.1 10 µA Vin = V- to V+. Device is in
stand-by mode.
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C+70°C
Industrial -40°C+85°C
Device Supply Voltage (VCC) Limits
X9420 5V ± 10%
X9420-2.7 2.7V to 5.5V
X9420
12 FN8195.1
April 26, 2006
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then V+ and V-, and then the potentiometer pins, RH, RL,
and RW. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The VCC ramp rate
specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible.
If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for
proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not
be complete until VCC, V+ and V- reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction
can be issued. These parameters are periodically sampled and not 100% tested.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
ICC1 VCC Supply Current (Active) 400 µA fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC2 VCC Supply Current
(Non-volatile Write)
1mAf
SCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB VCC Current (Standby) 1 μA SCK = SI = VSS, Addr. = VSS
ILI Input Leakage Current 10 μAV
IN = VSS to VCC
ILO Output Leakage Current 10 μAV
OUT = VSS to VCC
VIH Input HIGH Voltage VCC x 0.7 VCC + 0.5 V
VIL Input LOW Voltage -0.5 VCC x 0.1 V
VOL Output LOW Voltage 0.4 V IOL = 3mA
Parameter Min. Units
Minimum Endurance 100,000 Data Changes per Bit per Register
Data Retention 100 Years
Symbol Test Max. Units Test Conditions
COUT(5) Output Capacitance (SO) 8 pF VOUT = 0V
CIN(5) Input Capacitance (A0, SI, and SCK) 6 pF VIN = 0V
Symbol Parameter Max. Max. Units
tPUR(6) Power-up to Initiation of Read Operation 1 1 ms
tPUW(6) Power-up to Initiation of Write Operation 5 5 ms
tRVCC VCC Power-up Ramp 0.2 50 V/msec
X9420
13 FN8195.1
April 26, 2006
A.C. TEST CONDITIONS EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
5V
1533Ω
100pF
SDA Output
Symbol Parameter Min. Max. Units
fSCK SSI/SPI Clock Frequency 2.0 MHz
tCYC SSI/SPI Clock Cycle Time 500 ns
tWH SSI/SPI Clock High Time 200 ns
tWL SSI/SPI Clock Low Time 200 ns
tLEAD Lead Time 250 ns
tLAG Lag Time 250 ns
tSU SI, SCK, HOLD and CS Input Setup Time 50 ns
tHSI, SCK, HOLD and CS Input Hold Time 50 ns
tRI SI, SCK, HOLD and CS Input Rise Time 2 µs
tFI SI, SCK, HOLD and CS Input Fall Time 2 µs
tDIS SO Output Disable Time 0 500 ns
tVSO Output Valid Time 100 ns
tHO SO Output Hold Time 0 ns
tRO SO Output Rise Time 50 ns
tFO SO Output Fall Time 50 ns
tHOLD HOLD Time 400 ns
tHSU HOLD Setup Time 100 ns
tHH HOLD Hold Time 100 ns
tHZ HOLD Low to Output in High Z 100 ns
tLZ HOLD High to Output in Low Z 100 ns
TINoise Suppression Time Constant at SI, SCK, HOLD and CS inputs 20 ns
tCS CS Deselect Time 2 µs
tWPASU WP, A0 and A1 Setup Time 0 ns
tWPAH WP, A0 and A1 Hold Time 0 ns
X9420
14 FN8195.1
April 26, 2006
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
Symbol Parameter Typ. Max. Units
tWR High-voltage Write Cycle Time (Store Instructions) 5 10 ms
Symbol Parameter Min. Max. Units
tWRPO Wiper Response Time After The Third (Last) Power Supply Is Stable 10 µs
tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 10 µs
tWRID Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement
Instruction)
450 ns
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X9420
15 FN8195.1
April 26, 2006
TIMING DIAGRAMS
Input Timing
Output Timing
Hold Timing
...
CS
SCK
SI
SO
MSB LSB
High Impedance
tLEAD
tH
tSU tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
...
CS
SCK
SO
SI ADDR
MSB LSB
tDIS
tHO
tV
...
...
CS
SCK
SO
SI
HOLD
tHSU tHH
tLZ
tHZ
tHOLD
tRO tFO
X9420
16 FN8195.1
April 26, 2006
XDCP Timing (for All Load Instructions)
XDCP Timing (for Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
...
CS
SCK
SI MSB LSB
VW
tWRL
...
SO High Impedance
...
CS
SCK
SO
SI ADDR
tWRID
High Impedance
VW
...
Inc/Dec Inc/Dec
...
CS
WP
A0
A1
tWPASU tWPAH
(Any Instruction)
X9420
17 FN8195.1
April 26, 2006
APPLICATIONS INFORMATION
Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solid-
state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory
used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
Basic Circuits
VR
VW
VR
I
Three terminal Potentiometer;
Variable voltage divider Two terminal Variable Resistor;
Variable current
VH
VL
Noninverting Amplifier
Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/CR1+R2} VO(max)
VLL = {R1/CR1+R2} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
+5V
-5V
LM308A
Cascading TechniquesBuffered Reference Voltage
–
+
+5V
R1
+V
-5V
VW
VWVOUT = VW
OP-07
VW
VW
+V
+V +V
X
(a) (b)
X9420
18 FN8195.1
April 26, 2006
X9420
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
α0o8o0o8o-
Rev. 2 4/06
19
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8195.1
April 26, 2006
X9420
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05