GE28F128W30T90 - Intel - Product.Network

Order Number: 290702, Revi sion: 011

June 2005

Intel® Wireless Flash Memory (W30)

28F640W30, 28F320W30, 28F128W30

Datasheet

Product Featu res

The Intel® Wire less Flas h Me m o ry (W 3 0 ) de vice co m b in es state-of-the-ar t In te l® Flash technology to

p rovide a versatile memory solution f o r high performa nce, low pow er, board constraint mem ory

applications. The W30 flash memory de vice off ers a multi-partition, dual-operation flash architecture

that enables the flash dev ice to read from one partit ion whil e programming or erasing in another partition.

This Read-While-Write or Read-W hile-Erase capabil ity makes it possible to ac hieve higher data

throughput rates com pared to single partition devices. Tw o processors can interleave code execution,

b ecause program and erase operations can now occur as background pro cesses.

The W30 flash memory device inc orp or ates an Enh anc ed Fac tory Pr ogram min g (EFP) m ode to impr ove

12 V factor y pr ogram ming perfo rma nce . This f eatur e hel ps eli min at e manu factu ri ng bott le necks asso ci ated

with program ming high-density flash memory devices. The EFP program time is 3.5 µs per word,

compared to the standard fac tory program tim e of 8.0 µs per wo rd, so EFP mode saves significant factory

p rogramming time for improved factory efficiency.

The W30 flash memory device also includes block lock-down and programmabl e WAIT s ignal polarity,

and is supported by an ar ray of softw are tools.

■Hi gh Performance Read-Whil e-Write /Erase

— Burs t Frequency at 40 MHz

— 7 0 ns In itia l A cc e ss Sp ee d

— 25 ns Page-Mode Read Speed

— 20 ns Burst-Mode Read Spee d

— Burs t-Mode and Page-Mode in All Blocks

and across All Partition Boundari es

— Burs t Suspend Feature

— Enhanced Factory Programm ing:

3.5 µs per Word Program Time

— Pro grammable WAIT Signal Polarity

■Flash Power

—V

CC = 1.70 V – 1.90 V

—V

CCQ = 2.20 V – 3.30 V

— Standby Curre nt (130 nm) = 8 µA (typ.)

— Read Cu rrent = 7 mA

(4 wor d burst, typical)

■Flash Softwar e

— 5 µs/9 µs (t yp.) Program/E rase Suspen d

Latency Time

—Intel

® Flash Data Integrator (FDI) and

Comm on Flash Interface (CFI) Compatible

■Qu al it y a nd Rel iab ili ty

— Operating Temperature:

–40 °C to +85 °C

— 100K Minimum Erase Cycles

— 130 nm ETOX™ VIII Pr ocess

— 180 nm ETOX™ VII Process

■Flash A rchitecture

— Multi ple 4-Mb it P artitions

— Dual Operation: RWW or RWE

— Paramet er Blo ck S i z e = 4-K w o r d

— Main block size = 32-Kword

— Top or Bottom Parameter Bloc ks

■Flash Security

— 128-bit Protection Regi ster: 64 Unique

Device Identifier Bits; 64 User OTP

Protection Regis ter Bits

— A bsolute Write Protection with VPP at

Ground

— P rogram and Erase Lockout during Power

Transitions

— Individual and Instanta neous Block

Locking/Unlocking with Lock-Down

■Density and Packaging

— 130 nm: 32Mb, 64Mb, and 128M b in V F

BGA Package; 64Mb, 128Mb in QUAD+

Package

— 180 nm: 32Mb and 128Mb Densities in VF

BGA Package; 64Mb Densit y in µBGA*

Package

— 56 Active Ball Matrix, 0.75 mm Ball-Pitch

— 16-bi t D ata B us

Notice: This document contai ns informati on on new products in production. The specifications

are subject to cha nge wit hout notic e. Verif y with your local Intel sales office that you have the

latest datasheet before finalizing a desi gn.

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

2 Order Numbe r: 290702 , Revision: 011

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA T SOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT.

Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, b y

estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® Wireless Flash Memory (W30) may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

Intel, ETOX, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United S tates and other countries.

*Other names and brands may be claimed as the property of others.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 3

Contents

1.0 Introduction ...............................................................................................................................8

1.1 Docu men t Pu r p o se........ ....... ............ .............. ....... ............ .............. ....... ............ .............. ....8

1.2 Nomenclature .......................................................................................................................8

1.3 Conventions..........................................................................................................................9

2.0 Functional Overview............................................................................................................10

2.1 Overview.............................................................................................................................10

2.2 Memo r y Map and Par tition ing... ............ ............... ....... ........... ............... ....... ............ ...........11

3.0 P ack age Info rm at ion............................................................................................................14

3.1 W30 Flash Memory Device – 130 nm Lithography................ ..... ....... ....... ....... ............ ..... ..14

3.2 W30 Flash Memory Device – 180 nm Lithography................ ..... ....... ....... ....... ............ ..... ..16

4.0 Ballout and Signal Descriptions......................................................................................19

4.1 Signal Ballout......................................................................................................................19

4.2 Signal Descriptions............ ............ ............ ............ ....... ......... ............ ....... ....... ............ .......21

5.0 Maximum Ratings and O perating Conditions ...........................................................25

5.1 Absolute Maxi mu m Ratings.................. ............... .............. .............. .............. ....... ............ ..25

5.2 Ope r at i n g Condi tions................... ....... ............ .............. .............. ....... ............ .............. .......26

6.0 Electrical Specificat ions.....................................................................................................27

6.1 DC Curr ent Char a cte ristics.......... ............ ............ .............. .............. .............. ....... ............ ..27

6.2 DC Volt a ge Characteristi cs............ .............. ............... .............. .............. .............. ..............28

7.0 AC Characteristics................................................................................................................29

7.1 Read Ope rations - 130 nm Lithog raphy. . .......................... ................................. .................29

7.2 Read Ope rations - 180 nm Lithog raphy. . .......................... ................................. .................30

7.3 AC Writ e Chara cte r i stic s......... ............ .............. .............. ............... .............. .............. ........ .40

7.4 Er as e an d Prog ra m Ti mes.... ....... ............ .............. ....... ............ .............. ....... ............ .........44

8.0 Power and Reset Specifications .....................................................................................45

8.1 Active Power.......................................................................................................................45

8.2 Automatic Pow er Savings (APS)........................................................................................45

8.3 Sta n dby Po we r .... .............. ............... ....... ............ .............. ....... ............ .............. ................45

8.4 Power -U p /Down Characteristi cs.... ....... ............ .............. ....... ............ .............. ............... ....46

8.4.1 System Reset and RST# ....................... .............. ................... .............. .................46

8.4.2 VCC, VPP, and RST# Transition s .. ............... .............. .............. .............. ..............46

8.5 Power Su p ply De co upling..... ....... ............ .............. .............. ....... ............ .............. ..............46

8.6 Rese t Sp e cifications...... ....... ............ .............. ....... ............ .............. ....... ............ ................47

8.7 AC I/O Test Conditions...... ....... ..... ....... ..... .. .......... .. ....... ..... ....... ..... ....... .. ..... ....... ..... ....... ..48

8.8 Fl as h Device Capacit a nc e........ ............... .............. .............. .............. .............. ............... ....49

9.0 Flash Device Operations....................................................................................................50

9.1 Bus Opera tions.............. ........... ........ ........... ............... ....... ............ .............. ....... ................50

9.1.1 Read ......................................................................................................................50

9.1.2 Burst Suspend .......................................................................................................51

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

4 Order Numbe r: 290702 , Revision: 011

9.1.3 Standby..................................................................................................................51

9.1.4 Reset .....................................................................................................................52

9.1.5 Write ......................................................................................................................52

9.2 Flash Device Commands....................................................................................................52

9.3 Command Sequencing............................ ................... .............. ................... ................. ......56

10.0 Read Operations....................................................................................................................57

10.1 Read Array..........................................................................................................................57

10.2 Read Device ID...................................................................................................................57

10.3 R ead Query (CFI).......................... .......................................... ...........................................58

10.4 R ead Status Register........................................ .......................... ................... .....................58

10.5 Clear Status Register..........................................................................................................60

11.0 Program Operations.............................................................................................................61

11.1 Word Program ....................................................................................................................61

11.2 Factory Programmin g.........................................................................................................63

11.3 Enhanced Factory Program (EFP).....................................................................................63

11.3.1 EF P Requirem ents and Conside rations ... ..................... .......................... ..............64

11.3.2 Setup.....................................................................................................................64

11.3.3 Program.................................................................................................................64

11.3.4 Verify......................................................................................................................65

11.3.5 Exit.........................................................................................................................65

12.0 Program and Erase Operations.......................................................................................67

12.1 Program /Erase Sus pend and Resum e................................................... ............................67

12.2 Block Erase.........................................................................................................................70

12.3 Read-Whi le-Write and Read-Whi le-Eras e........ ................... ...................................... .........72

13.0 Security Modes.......................................................................................................................73

13.1 Block Lock Operations........................................................................................................73

13.1.1 Lock.......................................................................................................................74

13.1.2 Unlock....................................................................................................................74

13.1.3 Lock-Down.............................................................................................................75

13.1.4 Blo ck Lock Status..................................................................................................75

13.1.5 Lock During Erase Suspe nd..................................................................................76

13.1.6 Status Register Error Checking.............................................................................76

13.1 .7 WP# Lock-D o wn Con tro l............... .............. .............. ....... ............ .............. ...........76

13.2 Protection Register.............................................................................................................77

13.2.1 R eading the Protection Register.................................... ...................................... ..78

13.2.2 Programing the Pro tection Register.......................................................................78

13.2.3 Locking the Prote ction Register .............................................................................78

13.3 VPP Prote ction.............. ....... ............ ....... ............ .............. ....... ............ ....... ............ ...........80

14.0 Set Read Configuration Register....................................................................................81

14.1 Read Mod e (RCR[15])............................... ............ .......................... ...................................83

14.2 First Acce ss Latency Cou nt (RCR[13:11])..........................................................................83

14.2.1 Laten cy Count Settings........................ .......................... ................... .....................84

14.3 WAIT Signal Polarit y (RCR[10]). .........................................................................................85

14.4 WAIT Sign al Fun ction.. ............ .............. ....... ............ .............. ....... ............ ....... ............ ......85

14.5 Data Hold (RCR[9]).............................................................................................................86

14.6 WAIT Delay (RCR[8])........... ............ .............. ............ ............ ............ ............ ............ ........87

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 5

14.7 Burst Sequence (RCR[7])........... ............ ............ ................................................................87

14.8 Clock Edge (RCR[6])..... .....................................................................................................88

14.9 Burst Wrap (RCR[3])...........................................................................................................89

14.10 B urst Length (RCR[2:0]).................. .............. ............ .............. ...........................................89

Appendix A Write State Machine...........................................................................................90

Appen dix B Common Flash Interface..................................................................................93

Appendix C Ordering Information.......................................................................................103

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

6 Order Numbe r: 290702 , Revision: 011

Revision History

Date of

Revision Version Description

09/19/00 -001 Initial release

03/14/01 -002

28F3208W30 product references removed (product wa s discon tinued)

28F640W30 product added

Re vise d Ta bl e 2, Signal Descrip tions (DQ15–0, ADV#, WAIT, S-UB#, S-LB#, VCCQ)

Re vised S ec tion 3. 1, Bu s Op er at i on s

Re vise d Ta bl e 5, Command Bus Definitions, Notes 1 and 2

Revised Section 4.2.2, First Latency Count (LC2–0); revised Figure 6, Data Output

with LC Setting at Code 3; added Figure 7, First Access Latency Configuration

Re vised S ec ti o n 4.2.3, WAIT Sig na l Polari ty (WT)

Ad de d Section 4.2.4, WAIT Signal Function

Re vised S ec ti o n 4.2.5, Data Output Configuration (DOC)

Ad de d Figure 8 , Data Output Configuration with WAIT Signal Delay

Re vise d Ta bl e 13 , Status Re gi st er D WS and P WS D es cription

Re vi sed ent ire Se c tion 5.0, Program and Era s e Voltages

Re vi sed ent ire Se c tion 5.3, Enha nced Factory Programming ( EFP)

Re vi sed ent ire Se c tion 8.0, Flash Security Modes

Re vi sed ent ire Se c tion 9.0, Flash Pr otec tion Register; added Table 15,

Simultaneous Opera tions Allowed wi th the Protection Register

Re vised S ec t i on 10 .1 , P ower-Up/Down Cha racteristics

Revised Section 11.3, DC Characteristics. C hanged ICCS,ICCWS, ICCES S pecs from

18 µA to 21µA; change d ICCR Spec from 12 mA to 15 mA (burst length = 4)

Ad de d Figure 2 0, WAIT Signal in Synchronous Non-Read Array Operation

Waveform

Ad de d Figure 2 1, WAIT S ignal in Asy nchronous Page-Mode Read Operation

Waveform

Ad de d Figure 2 2, WAIT Si gnal in Asynchronous Single-Wor d Read Opera tion

Waveform

Re vised F ig ure 23, Write Waveform

Re vised S ec t i on 12 .4 , Reset Operations

Clarified Section 13.2, SRAM Wri te Operat ion, Note 2

Re vised S ec t i on 14 .0 , Ordering Information

Minor text edits

04/05/02 -003

Deleted SRAM Section

Added 128M DC and AC Specifications

Adde d Burst Susp end

Added Read While Write Transition Waveforms

Various text edits

04/24/02 -004 Revised D ev i c e ID

Revis ed Write Speed Bin

Various text edits

10/20/02 -005

Ad de d La t en c y C ou nt Tabl es

Updated Packing Ball-Out and Dimension

Various text edits

Minor tex t clar i fic ations

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 7

01/14/03 -006

Revised Table 20, DC Current Characteristics, I CCS

Revised Table 20, DC Current Characteristics, I CCAPS

Removed Intel Burst order

Minor text edits

Updated Package Drawing and Dimensions

03/22/03 -007 Revi sed Table 22, Read Operations, tAPA

Added note to table 15, Configuration Reg ister D escriptions

Added note to section 3.1.1, Read

11/17/03 -008

Updated Block Lock Op erations (Sect . 7.1 and Fig. 11)

Updated improved AC timings

Added QUAD+ package option, and Appendix D

Minor text edits including new product-naming conventions

05/06/04 -009 Corrected Absolute Maximum Rating for VCCQ (Sect. 10.1, Table 18)

Minor text edits

05/17/04 -010 Restructured the datasheet according to new layout.

06/2005 -011 Timing D iagram Nomenclature Sy nergy wi th other product families

Added Ordering information

Minor Text Edits

Date of

Revision Version Description

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

8 Order Numbe r: 290702 , Revision: 011

1.0 Introduction

1.1 Document Purpose

This datasheet contains informatio n about the Intel ® Wireless Flash Memory (W30) device family.

Throughout this document, this device fa mi ly is referred to as the W30 flash memory device.

•This chapt er provides a flash memory overview.

•Chapter 2 .0 through Chapter 8.0 describe the memor y functionality.

•Chapter 6 .0 desc ribes the electrical specificati ons for extended temperature product offerings.

•Appendix A des cr ibes the Writ e State M achine (WSM),

•Appendix B describes the Intel® Common Flash Interface (CFI) as it applies to the W30 flash

memo ry device .

•Appendix C provides ordering information for the Intel® Wireless Flash Memory (W30)

device family.

1.2 Nomenclature

Acronym s that describe product featu res or usage are de fined here:

•APS - Aut omatic Power Savings

•BBA - Block Base Address

•CFI - Com mon Flash Interface

•CUI - Com m a nd U ser Inter f a ce

•DU - Do not U s e

•EF P - Enhanced Fact ory P r ogramming

•FDI - Flash Data Integrator

•NC - No Connect

•OTP - One-Time Program mable

•PBA - Partition Base Addre ss

•RCR - Read Configuration Register

•RWE - Read-While-Erase

•RWW - Read-Whi le -Write

•SCSP - Stacked Chip Scale Package

•SRD - Status Register Data

•VF BG A - Very-thin, Fine-pitch, Ball Grid Array

•WSM - W r ite St ate Machine

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 9

1.3 Conventions

The fol lowing abbreviated terms an d phrases are used throughout this documen t:

•1.8 V refers to the VCC operating voltage range of 1.7 V – 1.9 V (except where noted).

•3.0 V refers to the VCCQ operating voltage range of 2.2 V - 3.3 V.

•VPP =12V refers to 12 V ± 5%.

•When referring to register s, the term set mean s the bit i s a logi cal 1 , and cleared means the bit

is a logical 0.

•The terms pin and signal are often used interchangeably to refer to the external signal

connections on the package. (Ball is the ter m u s ed for BG A ) .

•A word i s 2 b yt es, or 16 b i t s .

•Signal names are i n all CAPS (for exam p le, WAIT).

•Voltage appli ed to the signal is subscripted (for example, VPP).

Throughout this docume nt, refere nces are made to top, bottom, parameter, and partit ion. To clarif y

thes e re ferences, the fol lowing convent ions have been adopted:

•A block is a group of bits (or words) that era s e s im ultaneous ly with one block erase

instruction.

•A main block contains 32 Kwords.

•A para meter b l o ck contains 4 Kwords.

•The Block Base Address (BBA) is the firs t addr ess of a block.

•A partition is a group of block s that share eras e and pr ogram circuitry and a common st atus

•The Partition Base Address (PBA) is the first address of a partition. For example, on a

32- Mbit top-paramet er flash device, partition number 5 has a PBA of 0x140000.

•The top partition is located at the highest physica l flash devi ce address . This partition can be

a main part ition or a paramet er pa rtition.

•The bottom partition is locat ed at the lowest physical flash device address. This partition ca n

be a main pa rtition or a param eter partition.

•A main partition contains only main blocks.

•A parameter partitio n conta ins a mixture of main blocks and paramete r blocks.

•A top parameter device (TPD) has the paramete r partit ion at the t op of the memory m ap with

the pa ramete r blo cks at t he top of tha t parti tion. This flash dev ice t ype was former ly refer red to

as a top-boot flash device.

•A bot t om parameter devi ce (BPD) has the parameter partition at the bottom of the memory

map with the parameter bloc ks at the bottom of that partition. This flash device type was

forme rly referred to as a bottom - boot block flash device.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

10 Order Numbe r: 290702 , Revision: 011

2.0 Functional Overview

This section provides an overview of the W30 flash memory device features an d arc hitecture .

2.1 Overview

The W30 flash memory dev ice provides Read-While-W ri te (RWW) and Read-Whi te-Erase (RWE)

capabili ty. This ca pability provides high-performa nce sync hronous and async hronous rea ds in

package-c omp atible densities usi ng a 16-bit data bus. Individually-erasable memory blocks are

optim ally sized for code and data storage. Eight 4-Kword parameter blocks are located in the

parameter partition at e ither the top or bottom of the memory m ap. The rest of the memory array is

gr ouped into 32-Kword main blocks.

The memor y archi tectu r e fo r the W30 fl ash memory device con sists of multiple 4-Mbit partitions,

the exact number depending on the flash device density. By dividing the memory array into

part iti ons, pr ogram or erase ope ration s can take place sim ultan eousl y during rea d operati ons. Bur st

r eads can traverse partition boundaries, but user application code is r es ponsible for ens uring that

burst reads do not extend into a partition that is actively progra mming or erasin g. Although each

partition has burst-rea d, write, and erase capabili ties, simultaneous operation is limite d to wr ite or

erase in one parti tion while other partit ions are in a read mode.

Augme nted erase-s uspend func tionality further enhances the RWW capabilities of the W30 flas h

me mory devic e. An erase can be suspe nded to perform a program or read operation within any

block, except a block that is eras e-suspende d. A program operation nested within a suspen ded

erase can subse quently be suspended to read yet another memory locatio n.

After power-up or reset, the W30 flash memory device defaults to as ynchronous rea d

configuration. Writing to th e flash memory devic e Read Configuration Regist er (RCR) enable s

synchronous burst-mode read operation. In synchronous mode, the CLK input increments an

internal burst address gen era tor. CLK also synchroni ze s the flash memory device with the host

CPU and outputs data on every, or on every other, valid CLK cycle after an initial latenc y. A

pr ogrammable WAIT output signals to the CPU when data from the flash memory device is read y.

I n addition to its improved architecture and interfa ce, the W30 flash memory devi ce inco rporates

Enha nced Factory Programming (EFP), a feature that enables fas t programming and lo w-power

designs . The EFP feature provides fa st progra m performance, which can increase the

ma nufac turing throughput of a fa ctory.

The W30 flash memory devic e support s read operati ons at 1.8 V and er ase and program oper ations

at 1.8 V or 12 V. With th e 1.8-V option, VCC and VPP can be tied together for an ultra - low-power

des ign. In addition to voltage flexi bility, the dedicated VPP input provides extens ive data

protection when VPP < VPPLK.

A 128- bit protect ion register ca n imp lement new security techniques and data prot ection schemes:

•A combination of factory-programmed and user-OTP data cells provide unique flash device

identification, he lp implement fraud or cloning prevention schemes, or help protect content.

•Zero-late ncy locking/unlocking on any memory block provide s instant and comp lete

pr otection for critical syste m co de and data.

•An additional block lock-down capability provides hardwa re protecti on where soft ware

com mands alone cannot cha nge the block prot ection status.

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Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 11

The fl ash dev ic e Co mman d Us er Int er f a ce (C U I) li n k s th e s y ste m pro c es sor to the in t e rn al fl ash

memory ope ration. A vali d com ma nd sequence written to the CUI initiates the flash device W rite

S tate Machine (WSM) opera tion, which automatically execute s the algorithms, timings , and

verifications necessary to manage fla sh memory program and erase. An internal status register

provides ready/busy indic ation results of the oper ation (success , fail, and so on).

Three power-sa ving feature s– Autom atic Power Savings (AP S ) , standby, and RST# – can

significantly reduce powe r cons um ption.

•The flash device automatically enters APS mode following read cycle completion.

•S tandby mode begins when the system desele cts the flas h memory by de-ass erting CE#.

•Driving RS T# low produces power savings simil ar to standby mode. It als o res ets the part to

read- arra y mode (important for system-level reset), clears internal s tatus registers , and

provides an additiona l level of flash device write protection.

2 .2 Memor y Ma p an d Pa rt iti on i n g

The W30 flash memory de vice is divided into 4-Mbit physica l partitions. This partitioning allows

simultaneous RWW or RW E operations, and enables users to segment code and data areas on

4-Mbit bo unda ries. The fl ash memory arr ay is as ymmetric ally bl oc ked, whic h enabl es syste m code

and data integr ation within a sing le flas h device. Each block can be eras ed independe ntly in block

eras e mode. S im ultaneous program and erase operations are not allowed; only one pa rtition at a

time can be active ly programming or erasing. See Table 1, “Bot tom Paramete r Memory Map” on

page 12 and Table 2, “Top Parameter Memory Map” on page 13.

•The 32-Mbit flash device has eight partitions.

•The 64-Mb it flash device has 16 partitions .

•The 128-Mbit flash device has 32 partitions.

Each flash device de nsity contains one para me ter partition a nd several main partitions . The 4-Mbit

parameter partition contai ns eigh t 4-Kword parameter bl ocks and se ven 32-Kword main blo cks .

Each 4- Mbit main partition contains eight 32- Kwor d blocks.

The bul k of the flash memory array is divided into main blocks that c an s tore code or data , and

parameter block s that allow sto r age of f requently upda ted small pa rameters that are normally

stored in EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs

can be emulated.

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June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

12 Order Numbe r: 290702 , Revision: 011

Tab le 1. Botto m Par ameter Me m ory Map

Size

(KW) Bl k # 32 Mbit Bl k # 6 4 Mbit Blk # 128 Mbit

Main Partitions

Sixteen

Partitions

32 262 7F8000-7FFFFF

32 135 400000-407FFF

Eight

Partitions

32 134 3F8000-3FFFFF 134 3F8000-3FFFFF

32 71 200000-207FFF 71 200000-207FFF

Four

Partitions

32 70 1F8000-1FFFFF 70 1F8000-1FFFFF 70 1F8000-1FFFFF

32 39 100000-107FFF 39 100000-107FFF 39 100000-107FFF

One

Partition

32 38 0F8000-0FFFFF 38 0F8000-0FFFFF 38 0F8000-0FFFFF

32 31 0C0000-0C7FFF 31 0C0000-0C7FFF 31 0C0000-0C7FFF

One

Partition

32 30 0B8000-0BFFFF 30 0B8000-0BFFFF 30 0B8000-0BFFFF

32 23 080000-087FFF 23 080000-087FFF 23 080000-087FFF

One

Partition

32 22 078000-07FFFF 22 078000-07FFFF 22 078000-07FFFF

32 15 040000-047FFF 15 040000-047FFF 15 040000-047FFF

Parameter Partition

One Partition

32 14 038000-03FFFF 14 038000-03FFFF 14 038000-03FFFF

32 8 008000-00FFFF 8 008000-00FFFF 8 008000-00FFFF

4 7 007000-007FFF 7 007000-007FFF 7 007000-007FFF

4 0 000000-000FFF 0 000000-000FFF 0 000000-000FFF

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 13

Table 2. Top Parameter Memory Map

Size

(KW) Blk # 32 Mbit Blk # 64 Mbit Bl k # 128 Mbit

Parameter Partition

One Partition

4 70 1FF000-1FFFFF 134 3FF000-3FFFFF 262 7FF000-7FFFFF

4 63 1F8000-1F8FFF 127 3F8000-3F8FFF 255 7F8000-7F8FFF

32 62 1F0000-1F7FFF 126 3F0000-3F7FFF 254 7F0000-7F7FFF

32 56 1C0000-1C7FFF 120 3C0000-3C7FFF 248 7C0000-7C7FFF

Main Partitions

One

Partition

32 55 1B8000-1BFFFF 119 3B8000-3BFFFF 247 7B8000-7BFFFF

32 48 18000-187FFF 112 380000-387FFF 240 780000-787FFF

One

Partition

32 47 178000-17FFFF 111 378000-37FFFF 239 778000-77FFFF

32 40 140000-147FFF 104 340000-347FFF 232 740000-747FFF

One

Partition

32 39 138000-13FFFF 103 338000-33FFFF 231 738000-73FFFF

32 32 100000-107FFF 96 300000-307FFF 224 700000-707FFF

Four

Partitions

32 31 0F8000-0FFFFF 95 2F8000-2FFFFF 223 6F8000-6FFFFF

32 0 000000-007FFF 64 200000-207FFF 192 600000-607FFF

Eight

Partitions

32 63 1F8000-1FFFFF 191 5F8000-5FFFFF

32 0 000000-007FFF 128 400000-407FFF

Sixteen

Partitions

32 127 3F8000-3FFFFF

32 0 000000-007FFF

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

14 Order Numbe r: 290702 , Revision: 011

3.0 Package Information

3.1 W30 Flash Memory Device – 130 nm Lithography

Figure 1. 32 Mb, 64 Mb, an d 128 Mb VF BGA Packa ge Draw ing

Tab le 3. 2 Mb, 64 Mb, and 128 Mb VF BGA Packag e Specifications

Dimension Symbol Millimeters Inches

Min Nom Max Min Nom Max

Package Height A - - 1.000 - - 0.0394

Ball Height A10.150 - - 0.0059 - -

Package Body Thic kness A2- 0.665 - - 0.0262 -

Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Package Body Width (32 Mb, 64 Mb) D 7.600 7.700 7.800 0. 2992 0.3031 0.3071

Package Body Width (128 Mb) D 10.900 11.000 11.100 0.4291 0.4331 0.4370

Package Body Length (32 Mb, 64 Mb, 1 28 Mb) E 8.900 9.000 9.100 0.3 504 0.3543 0.3583

Pitch [e] - 0.750 - - 0.0295 -

Ball (Lead) Count N - 56 - - 56 -

S ea tin g P la ne Co pl an ar i ty Y - - 0. 10 0 - - 0. 0039

Corner to Ball A1 Distance Along D (32 Mb, 64 Mb) S11.125 1.225 1.325 0.0443 0.0482 0.0522

Corner to Ball A1 Distance Along D (128 Mb) S12.775 2.2875 2.975 0.1093 0.1132 0.1171

Corne r to B a ll A1 Di stance Al ong E (32 Mb, 6 4 M b,12 8

Mb) S22.150 2.250 2.350 0.0846 0.0886 0.0925

Seating

Plane

Top View - Bump Side Down Bottom Vie w - Ba ll Sid e Up

Bal l A1

Corner

87654321

Bal l A1

Corner

87654321

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 15

Figure 2. 32Mb, 64M b and 128Mb QUAD+ P ackag e Drawing

Millimeters Inches

Dimensions Symbol Min Nom Max Notes Min Nom Max

Package Height A 1.200 0.0472

Ball Height A1 0.200 0.0079

Pack age Body Thickness A2 0.8 60 0.0339

Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Package Body L ength D 9.900 10.000 10.100 0.3898 0.3937 0.3976

Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189

Pitch e 0 .800 0.0315

B all (L ead) Count N 8 8 8 8

Seating P l ane Coplanari ty Y 0.10 0 0.0 039

Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512

Corner to Ball A1 Distance Along D S2 0.500 0.600 0.700 0.0197 0.0236 0.0276

Top View - Ball Down Bottom View - Ball Up

D rawi ng not t o scale.

2345678

A1 Inde x

Mark

12345678

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

16 Order Numbe r: 290702 , Revision: 011

3.2 W30 Flash Memory Device – 180 nm Lithography

Figure 3. 64Mb µBGA* CSP Package Draw ing and Dimens ions

Bo ttom V ie w - Bu mp side Up

To p View - S ilic o n b a c k s ide

Comple te Ink Ma r k Not

Side

View

Seati

Plan

Pin # 1

Indicator

Pin # 1

Corne

1 2 3 4 5 6 7 8

8 7 6 5 4 3 2 1

Millimeters

Inches

Symbol Min Nom Max Notes Min Nom Max

Package Height A 0.850 1.000 0.0335 0.0394

Ball Heigh t A1 0.150 0.0059

Package Body Thickness A2 0.612 0.712 0.812 0.0241 0.0280 0.0320

Bal l (Le a d) Widt h b 0.300 0.350 0.400 0.0118 0.0138 0.0157

Package Body Width D 7.600 7.700 7.800 0.2992 0.3031 0.3071

Package Body Length E 8.900 9.000 9.100 0.3503 0.3543 0.3583

Pitch [e] 0.750 0.0295

Ball (Lead) Count N 56 56

Seati ng Plane Coplanarity Y 0.100 0.0039

Corner to Ball A1 Distance Along D S1 1.125 1.225 1.325 0.0443 0.0482 0.0522

Corner to Ball A1 Distance Along E S2 2.150 2.250 2.350 0.0846 0.0886 0.0925

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 17

Figure 4. 32Mb VF BGA Package Drawi ng

Figure 5. 128Mb VF BGA Packag e Drawing

Seating

Plane

T op View - Bump Side D own Bott om View - Ball Side Up

Ball A1

Corne

Ba l l A1

Corner

87654321 87654321

Note: Dr awing not to scale

Side View

Seating

Plane Y

Note: Draw ing not to sc ale

Side View

Top View - Bump Side

Down Bot tom View - Ball Side

DBall A

Corne

765432110 9 8

76543211098

Ball A1

Corner

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

18 Order Numbe r: 290702 , Revision: 011

Table 4. 32Mb and 128Mb VF BGA Package Dimensions

Dimension Symbol Millimeters Inches

Min Nom Max Min Nom Max

Package Height A 0.850 - 1.000 0.0335 - 0 .0394

Ball Height A10.150 - - 0.0059 - -

Package Body Thic kness A20.615 0.665 0.715 0.0242 0.0262 0.0281

Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Package Body Width 32Mb D 7.600 7 .700 7 .800 0.2992 0.3031 0.3071

Package Body Length32Mb E 8.900 9.000 9.100 0.3503 0. 3543 0.3583

Package Body Width 128Mb D 12.400 12.500 12.600 0.4882 0.4921 0.4961

Package Body Length 128Mb E 11.900 12.000 12.100 0.4685 0.4724 0.4764

Pitch [e] - 0.750 - - 0.0295 -

Ball (Lead) Count 32Mb N - 56 - - 56 -

Ball (Lead) Count 128Mb N - 60 - - 60 -

S ea tin g P la ne Co pl an ar i ty Y - - 0. 1 00 - - 0.0 03 9

Corner to Ball A1 Distance Along D 32Mb S11.125 1.225 1.325 0.0443 0.0482 0.0522

Corner to Ball A1 Distance Along E 32Mb S22.150 2.250 2.350 0.0846 0.0886 0.0925

Co r n er t o Bal l A 1 Di sta nc e A lo ng D 12 8M b S12.775 2.875 2.975 0.1093 0.1132 0.1171

Corner to Ball A1 Distance Along E 128Mb S22.900 3.000 3.1000 0.1142 0.1181 0.1220

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 19

4.0 Ballout and Signal Descriptions

4.1 Signal Ballout

The W30 flash memory device is available in the 56-ball VF BGA and µBGA Chip Scale Package

with 0.75 mm ball pitch, or the QUAD+ SCSP package. Figure 6 shows the VF BGA and µBGA

package ballout. F igure 7 shows the QUAD+ package ba llout.

Notes:

1. On lower density flash memory devices, the upper address balls can be treated as NC. (that is, on 32-Mbit density, A22

and A21 are NC).

2. See Appendix C, “Ordering Information” on page 103 for mechani c al speci fic ations for the package.

Figure 6. 56-Ball VF BGA/ µBGA Ballout

Top View - Ball Side Down

Complete Ink Mark Not Shown

8 7 6 5 4 3 2 11 2 3 4 5 6 7 8

Bottom View - Ball Side Up

A4 A6 A18 VPP VCC VSS A8 A11

A3 A5 A17 RST# CLK A20 A9 A12

A2 A7 WE# ADV#

A19 A10 A13

A1 A14WP# DQ12 A16 WAIT A15

A0 CE# DQ1 DQ2 DQ4 DQ6 DQ15 VCCQ

OE# DQ0 DQ9 DQ10 DQ11 DQ13 DQ14 VSS

VSSQ DQ8 VCCQ DQ3 VCC DQ5 VSSQ DQ7

A22

A21

A4A6A18VPPVCCVSSA8A11

A3A5A17

RST#

CLKA20A9A12

A2A7

WE#ADV# A19A10A13

A1A14 WP#DQ12A16WAITA15

A0CE#DQ1DQ2DQ4DQ6DQ15VCCQ

OE#DQ0DQ9DQ10DQ11DQ13DQ14VSS

VSSQDQ8VCCQDQ3VCCDQ5VSSQDQ7

A22

A21

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

20 Order Numbe r: 290702 , Revision: 011

Notes:

1. On lower density flash memory devices, the upper address balls can be treated as NC (that is, on 64-Mb

density, A[25:23]are NC)

2. See Appendix C, “Ordering Information” on page 103 for mechanical specifications for the package.

Figure 7. 88-Ball (80 A ctive Balls ) QUAD+ Ballou t

Flash specific

SRAM/ P SR AM speci fic

Global

Legend:

Top Vi ew - Ball Side Down

87654321

DU DU DU

DUDUDU DU

A2 A7

A1 A6

A18 A19 VSS

VSSA23

A24

A25

A17

F2-VCC

CLK

A21

A22 A12

A11

A13A9P1-CS#

F-VPP,

F-VPEN

A20 A10 A15

F-WE# A8

D8 D2 D10 D5 D13 WAIT

A14 A16

F1-CE# P-Mode,

P-CRE

VSS VSS VSS

P2-CS#

F1-VCC

F2-VCC VCCQF3-CE#

D0 D1

D4 D6

D15D11

D12 D14

F1-OE#

F2-OE#

P-VCC

S-CS2

R-WE#

R-UB#

R-LB#

R-OE#

S-VCC

S-CS1#

F1-VCC

F-WP# ADV#

F-RST#

F2-CE#

VCCQ

VSS VSSVCCQ VSS

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 21

4.2 Signal Descriptions

•Table 5 de sc ri b es th e sig n a l s fo r th e 56 - b al l VF BG A an d µB G A C hi p Sc al e P ac k ag e .

•Table 6 describes the signals for the QUAD+ package ballout.

Table 5. Signal Descriptions - µBGA Package & VF BGA Package (Sheet 1 of 2)

Symbol Type Name and Function

A[22:0] Input ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]

D[15:0] Input/

Output

DATA INPUTS/OUTPUTS:

• Inpu ts data and com mands during write cycles.

• Outputs data during reads.

Data pins are High-Z when the flas h device or its outputs are deselected. Data is internally latched

during writes.

ADV# Input ADDRESS VALID: AD V# indicates valid address presence on address inputs. During synchronous

read operations, all add resses are latc hed on the rising edge of ADV#, or the next valid CLK edge with

ADV# low, whichever occurs first.

CE# Input CHIP ENABLE:

• Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.

• De-asserting CE# des elects the flash device, places it in standby mode, and tri- states all ou tputs.

CLK Input CLOCK: CL K synchronizes the flash device to the s y stem bus frequency during sy nchronous reads

and increments an internal address generator. During sy nchronous read operations, address es are

latched on ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.

OE# Input OUT PUT ENAB LE:

• When asserted, OE# e nables the flash device output data buffers during a read cycle.

• When OE# is deasserted, data outputs are placed in a high-impedance state.

RST# Input RESET: When low, RST# resets internal automation and inhibits write operations. This reset provides

data protection during powe r transitions. De-asserting RST# enables no rmal operation and plac es th e

flash device in asynchronous read-array mode.

WAIT Output WAIT: Th e W A IT si gn al ind ica t es val i d d ata du rin g sy nc hr onou s r e ad mod es . It ca n b e c onfi gu red to be

asserted- high o r asserted-low, ba sed on bit 10 of the Read Configuration R egister. WAIT is tri-stat ed if

CE # is deasserted. WAIT is not gated by OE#.

WE# Input WRI TE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the

rising edge of WE#.

WP# Input WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down

mechanism is enabled and blocks ma rked lock-dow n cannot be unlocke d through software. See

Section 13.1, “Block Lock Oper ations” on page 73 for details on block locking.

VPP Power/

Input

ERASE AND PROGRAM POWER: A val id voltage on this pin allo ws erasing or progr amming. Flash

memory contents cannot be altered when VPP < VPPLK. Do not attempt block erase and program

operations at invalid VPP vo ltag es .

Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops

from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must rema in above VPPL

min to perfor m in-system flash device modification. VPP can be 0 V during read operations.

VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.

VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin

at 12 V migh t red uc e bl oc k cy c lin g ca pabilit y.

VCC Power FL ASH DEVICE POWER SUPPLY: Writes are inhibited at VCC < VLKO. Do not attempt flash device

operations at invalid VCC voltages.

VCCQ Power OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ.

VSS Power GROUND: Pins for all internal flas h device c ircuitry must be connected to system ground.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

22 Order Numbe r: 290702 , Revision: 011

VSSQ Power OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal can be tied

directly to VSS.

DU — DO NOT USE: Do not use this pin. Do not connect this pin to any power supplies, signals, or other

pins; this pin must be floated.

NC — NO CONNECT: No internal connection; can be driven or floated.

Tab le 6. Signal Descriptions - Q UAD+ Packag e (Sh eet 1 of 3)

Symbol Type Description

A[MAX:MIN] Input

ADDRESS INPUTS: In puts for all die addresses du ring read and write operations.

•128-Mbit Die : AMAX = A22

•64-Mbit Die : AMAX = A21

•32-Mbit Die : AMAX = A20

A0 is the lowest-order 16-bit wide address.

A[25:24] denote high-or der addresses reserved for future flash device densi ties.

DQ[15:0] Input/

Output

DATA INPUTS/OUTPUTS:

• Inputs data and commands during write cy cles.

• Outputs data during read cycles.

Data signals float when the flash device or its outputs are deselected. Data are internally latched

during wri tes on the flash device.

F[3:1]-CE# Input

FLASH CHIP ENABLE: Low-true input.

F[3:1]-CE# low selects the associated flash memory die.

• When asserted, flash memory internal control logic, input buffers, decoders, and sense amplifiers

ar e ac tiv e .

• When deasserted, the associated flash die i s deselected, powe r is reduced to standby leve ls, an d

data and WAIT outputs are placed in high-Z state.

• F1 - C E# sel e c ts or deselects fl as h di e #1.

• F2-CE# selects or deselects flash die #2 and is RFU on combinations with only one flash die.

• F 3-C E# se le ct s or d esel ects fla sh di e #3 an d i s RF U on st acke d c omb in ati on s wit h on ly one or tw o

fl as h di es .

S-CS1#

S-CS2 Input

SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 respectively).

• When either /both SR AM Chip Select signals are asserted, SRA M internal control logic, input

buffers, decoder s , and sense amplifiers are active.

• When either/both SRAM Ch ip Select signals are deass erted, the SR AM is deselected and its

power i s reduced to standby levels.

S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are RFU on stacked

c ombinations without SRAM die.

P[2:1]-CS# Input

PSRAM CHIP SELECT: Low-true input.

• When asserted, PSRAM inter nal control logic, input buffers, decoders, and sens e amplifiers are

active.

• W hen deas ser te d, th e P SR AM is des ele ct e d an d it s po we r is re du ce d to st a nd by levels.

• P 1-CS# selects PSR AM die #1 and is avai lable on ly on st acked combinations with PSRAM die.

This ball is an RFU on stacked combinations without PSRAM.

• P 2-CS# selects PSR AM die #2 and is avai lable on ly on st acked combinations with two PS RAM

dies. This ball is an RFU on st acked combinations wi thout PSRAM or with a single PSRAM.

Tab le 5. Signal Descriptions - µBGA Pac kage & VF BGA Package (Sheet 2 of 2)

Symbol Type Name and Function

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 23

F[2:1]-OE# Input

FLASH OUTPUT ENABLE: Low-true input.

• Fx-OE# low enables the output buffers on the selected flash memory device.

• F[2:1]-OE# high disables the output buffers on the selected flash memory device, placing them in

High-Z.

• F1-OE# controls the outputs of flash die #1.

• F2-OE# controls the outputs of flash die #2 and flash die #3. F2-OE# is available on stacked

com binations with two or three flash die, and is RFU on stacked combinations with only one flash

die.

R-OE# Input

RAM OUTPUT ENABLE: Low-true input.

• R-OE# low enables the output buffers on the selected RAM.

• R-OE# high disables the RAM output buffers, and places the selected RAM outputs in High-Z.

R- O E# is availa ble on stacked combinations with P SRAM or SRAM die, and is an RFU on flash-only

sta c ke d co mbinations .

F-WE# Input FLASH WRITE ENABLE: Low-true input.

F-WE# controls writes to the selected flash die. Address and data are latched on the rising edge of

F-WE#.

R-WE# Input

RAM WRITE ENABLE: Low-true input.

R-WE # co ntr ol s wr ite s to t h e se lec te d RA M die.

R-WE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only

sta c ke d co mbinations .

CLK Input

CLOCK: Synchr onizes the flash die with th e system bus clo ck in synch ronous read mode and

incr em en ts the int e rnal addr e s s ge ne r ato r.

• During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the

next valid CLK edge with ADV# low, whichever occurs first.

• During asynchronous mode read operations, addresses are latched on the rising edge ADV#, or

are continuously flow-thr ough when ADV# is kept asserted.

WAIT Output

WAIT: Outp ut signal.

Indicates invalid d ata during sync hronous array or non-a rr ay flash memory reads. R ead Conf iguration

deasserted; WAIT is not gated by F-OE#.

• In syn chronous array o r non-array flash memory read m odes, WAIT indicates invalid data wh en

ass erted and valid data when deasserted.

• In asynchronous flash memory page read, and all flash memory write modes, WAIT is asserted.

F-WP# Input

FLASH WRITE PROTECT: Low-true input.

F-WP# enables/disables the lock-down protection mechanism of the selected flash die.

• F-WP# low enables the lock-down mechanism wher e locked down blocks ca nnot be unlocke d

using software commands.

• F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked

using software commands.

ADV# Input

ADDRESS VALID: Low-true input.

• During synchronous flash memory read operations, addresses are latched on the rising edge of

ADV#, or on the next valid CLK edge with ADV# low , whichever occurs first.

• During asynchronous flash memory read operations , addresses are latched on the rising edge of

ADV#, or are continuously flow-through when ADV# is kept asserted.

Table 6. Signal Descriptions - QUAD+ Package (Sheet 2 of 3)

Symbol Type Description

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

24 Order Numbe r: 290702 , Revision: 011

R-UB#

R-LB# Input

RAM UPPER / L O WER BYTE ENABLES: Lo w-true inpu t.

During RAM read and write cycles:

• R-UB# low enables the RAM high order bytes on D[15:8].

• R-LB# low enables the RAM low-order bytes on D[7:0].

R- UB# a nd R-LB# are available on stac ked combinations with P SRAM or SRAM die, and are RFU on

flas h-only stacked combinations.

F-RST# Input

FLASH RESET: Low-true input .

• F-RST # low initializes flash devi ce internal circuitry and disables flas h device operations.

• F-RST # high enables flash device operation.

Exit fr om reset places the flash device in asynchronous read array mo de.

P-Mode,

P-CRE Input

P-Mode (PSRAM Mode): Low-true input.

P-Mode programs the Configuration Regi ster, and enters/exits the Low Powe r Mode of the PSRAM

die.

P-Mode is available on stacked combinations with asynchronous-only PSRAM die.

•P-CRE (PSRAM Configuration Register Enable): High-true input.

• P -CRE is high, wri te operations load the Refr esh Control Register or Bus Contr ol Register.

• P-CRE applies only on combinations with synchronous PSRAM die.

P- Mode, P- CRE is an RFU on stacked combinations witho ut PSRAM die.

F-VPP,

F-VPEN Power

FLASH PROGRAM AND ERASE POWER: Valid F-VPP voltage on this ball enables flash memory

device program/erase operations.

Flash memory arr ay contents c annot be altered when F-VPP(F-VPEN) < VPPLK (VPENLK). Do not

attempt erase / progr am operations at invalid F-VPP (F-VPEN) voltages.

F-VPEN (Er ase/Program/Block Lock Enables) is not available for L18/L30 SCSP products.

F[2:1]-VCC Power

FLASH LOGIC POWER:

• F1-VCC supplies po wer t o the core logic of flash die #1.

• F2-VCC supplies power to the core logic of flash die #2 and flash die #3.

Write operations are inhibited when F-VCC < VLKO. Do not attempt flash device ope rations at invalid

F-VCC voltages.

F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked

c ombinations with only one flash die.

S-VCC Power S RAM POWER SUPPLY: Supplies power for SRAM operations.

S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked combinations

without SRAM die.

P-VCC Power PSRAM POWER SUPPLY: Supplies power for PSRAM operations.

P- VCC is available on stack ed combinations with PSRAM di e, and is RFU on stacked comb inations

without PSRAM die.

VCCQ Power FLASH DEVICE I/O POWER: Supply power for the flash device input and output buffers.

VSS Power FLASH DEVICE GROUND: Connect to system ground. Do not float any VSS connection.

RFU — RESERVED for FUTURE USE: Reserved for future flash device functionality/ enhancements. Contact

Intel regarding the use of balls designated RFU.

DU — DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.

Tab le 6. Signal Descriptions - Q UAD+ Packag e (Sh eet 3 of 3)

Symbol Type Description

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 25

5.0 Maximum Rati ngs and Operating Conditions

5.1 Absolute Maximum Ratings

Warning: Stressing the f lash device be yond the Absolut e Maximum Ratings in Table 7 might cause

permanent damage. The s e are st res s ratings only.

Notice: T his datasheet contains information on products in the design phase of development. The information

here is subject to change without notice. Do not finalize a design with this information.

Table 7. Ab solute Maxi mum Rating s

Parameter Maximum Rating Note

Temperature under Bia s –40 °C to +85 °C

Storage Temperature –65 °C to +125 °C

Voltage on Any Pin (except VCC, VCCQ, VPP) –0.5 V to +3.8 V

VPP Voltage –0.2 V to +14 V 1,2,3

VCC Voltage –0.2 V to +2.45 V 1

VCCQ Voltage –0.2 V to +3.8 V 1

Output Short Circuit Current 100 mA 4

Notes:

1. All specified vol tages are relative to VSS. Mi nimum DC voltage is –0.5 V on input /output

pins and –0.2 V on VCC an d VPP pins. During transitions, this level might undershoot to

–2.0 V for periods < 20 ns. Maximum DC v oltage on input/output pins is VCC +0.5 V which,

during transitions, might overshoot to VCC +2.0 V for periods < 20 ns.

2. Maximum DC voltage on VPP might overshoot to +14.0 V for periods < 2 0 ns.

3. VPP program voltage is normally VPPL. VPP can b e 12 V ± 0.6 V fo r 10 00 cy cle s o n th e ma in

blocks and 2500 cycles on the parameter blocks during progr am/erase.

4. Output shorted for no more than one second. No more than one output shorted at a time.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

26 Order Numbe r: 290702 , Revision: 011

5.2 Operating Conditions

Do not operate the W30 flash memory device beyond the Operating Conditions in Table 8.

Extended exposure beyond thes e Operating Conditions mi ght af fec t flash device reliability.

Tab le 8. Extende d Tem p eratur e Oper ation

Symbol Parameter1Min Nom Max Unit Notes

TAOperating Temperature –40 25 85 °C -

VCC VCC Supply Voltage 1.7 1.8 1.90

VCCQ I/O Supply Vo ltage 2 .2 3.0 3.3 3

VPPL VPP Voltage Supply (Logic Level) 0.90 1.80 1.95 2

VPPH Factory Programming VPP 11.4 12.0 12.6 2

tPPH Maximum VPP Hours VPP = 12 V - - 80 Hours 2

Block

Erase

Cycles

Main and Par ameter

Blocks VPP < VCC 100,000 - -

Cycles

Main Blocks VPP = 12 V - - 10 00 2

Paramet er Blocks V PP = 12 V - - 2500 2

Notes:

1. See Section 6.1, “DC Current Character istic s” on page 27 and Section 6.2, “DC Voltage

Characteristics” on page 28 for specific voltage-range specifications.

2. VPP is normally VPPL. VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main

blocks for extended temperatures and 2500 cycles on parameter blocks at extended

temperature.

3. Contact your Intel field representative for VCC/VCCQ operations down to 1.65 V.

4. See the tables in Section 6.0, “Electrical Specifications ” on page 27 and in Section 7.0, “AC

Characteristics” on page 29 f or op er a tin g charact e ris t ic s

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 27

6.0 Electrical Specifications

6.1 DC Current Characteristics

Ta ble 9. DC Current Characteristics (Sheet 1 of 2)

Sym Parameter (1) Note

VCCQ= 3.0 V

Unit Test Conditions32/64 Mbit 128 Mbit

Typ Max Typ Max

ILI Input Lo ad 9 - ±2 - ±2 µA VCC = VCCMax

VCCQ = VCCQMax

VIN = VCCQ or GND

ILO Output

Leakage DQ[15:0] - ±10 - ±10 µA VCC = VCCMax

VCCQ = VCCQMax

VIN = VCCQ or GND

180 nm

ICCS VCC Standby 10 621630

µA

VCC = VCCMax

VCCQ = VCCQMax

CE# = VCCQ

RST# =VCCQ

130 nm

ICCS 850870

180 nm

ICCAPS APS 11

621630

µA

VCC = VCCMax

VCCQ = VCCQMax

CE# = VSSQ

RST# =VCCQ

All other inputs =VCCQ or VSSQ

130 nm

ICCAPS 850870

ICCR Average

VCC

Read

Asynchronous

Page Mode

f=13 MHz 2 4 7 4 10 mA 4 Word Read

VCC = VCCMax

CE# = VIL

OE# = VIH

Inputs = VIH or VIL

Synchronous

CLK = 40 MH z 2

715715mABurst length = 4

916916mABurst length = 8

11 19 11 19 mA Burst length =16

12 22 12 22 mA Burst length =

Continuous

ICCW VCC Program 3,4,5 18 40 18 40 mA VPP = VPPL, Program in Progress

815815mA

VPP = VPPH, Program in Progress

ICCE VCC Blo ck Erase 3,4,5 18 40 18 40 mA VPP = VPPL, Block Erase in Progress

815815mA

VPP = VPPH, Block Erase in Progress

ICCWS VCC Program Suspend 6 6 21 6 30 µA CE# = VCC, Program Susp end ed

ICCES VCC Erase Suspend 6 6 21 6 30 µA CE# = VCC, E r as e Sus pen ded

IPPS

(IPPWS,

IPPES)

VPP Standby

VPP Program Suspend

VPP E r as e S us pe n d 30.250.25µAV

PP < VCC

IPPR VPP Read - 215215µA

VPP < VCC

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

28 Order Numbe r: 290702 , Revision: 011

6.2 DC Voltage Characteristics

IPPW VPP Program 4 0.05 0.10 0.05 0.10 mA VPP = VPPL, Program in Progress

8 221637 V

PP = VPPH, Program in Progress

IPPE VPP Erase 4 0.05 0.10 0.05 0.10 mA VPP = VPPL, Erase in Progress

822822 V

PP = VPPH, Er as e in Pro gr e ss

Notes:

1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25°C.

2. Aut omatic Power Sa vings (APS) reduces ICCR to approximately standby levels i n static ope ration. See ICCRQ

specification for details.

3. Sampled, not 100% tested.

4. VCC read + pr ogram curre nt is the sum of VCC read and VCC program currents.

5. VCC read + erase current is the sum of VCC rea d and VCC erase curren ts.

6. ICCES is specified with the flash device deselected. If the flash device is read while in erase s uspend, the c urrent is

ICCES plus ICCR.

7. VPP < VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.

8. VIL can undershoot to –0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less.

9. If VIN>VCC the input load current increases to 10 µA max.

10. ICCS is the average current measured over any 5ms time interval 5 µs af ter a CE# de-assertion.

11. Refer to section Section 8.2, “Automatic Power Savings (APS) ” on page 45 for ICCAPS measurement details.

Tab le 10. DC Voltage Characteristi cs

Sym P arameter (1) Note

VCCQ= 3.0 V

Unit Te st Cond it io ns32/6 4 Mb it 128 Mbit

Min Max Min Max

VIL Input Low 8 0 0.4 0 0.4 V

VIH Input High - VCCQ

– 0.4 VCCQ VCCQ

– 0.4 VCCQ V

VOL Output Low --0.1-0.1V

VCC = VCCMin

VCCQ = VCCQMin

IOL = 10 0 µ A

VOH Output High -VCCQ

– 0.1 -VCCQ

– 0.1 -V

VCC = VCCMin

VCCQ = VCCQMin

IOH = –100 µA

VPPLK VPP Lock-Out 7 - 0.4 - 0. 4 V

VLKO VCC Lock - 1.0 - 1.0 - V

VILKOQ VCCQ Lock - 0.9 - 0.9 - V

Note: For all numbered note refer ences i n this table, refer to the notes in Table 9, “DC Current

Characteristics” on page 27.

Table 9. DC Current Characteristics (Sheet 2 of 2)

Sym Parameter (1) Note

VCCQ= 3.0 V

Unit Te st Cond itions32/64 Mbi t 128 Mbit

Typ Max Typ Max

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 29

7.0 AC Characteristics

7.1 Read Operations - 13 0 nm Lithography

Table 11. Read Operations - 130 nm Lithography (Sheet 1 of 2)

# Sym Parameter 1

32-Mbit

64-Mbit 128-Mbit

Units Notes

-70 -85 -70

MinMaxMinMaxMinMax

Asynchronous Specifi cation s

R1 tAVAV Read Cycle Time 70 - 85 - 70 - ns 6

R2 tAVQV Address to Output Valid - 70 - 85 -70ns 6

R3 tELQV CE# Low to Output Valid - 70 - 85 -70ns 6

R4 tGLQV OE# Low to Output Valid - 30 - 30 - 30 ns 3

R5 tPHQV RST# High to Output Valid - 150 - 150 - 150 ns -

R6 tELQX CE# Low to Output Low-Z 0 - 0 - 0 - ns 4

R7 tGLQX OE# Low to Output Low-Z 0 - 0 - 0 - ns 3,4

R8 tEHQZ CE# High to Output High-Z - 20 - 20 - 20 ns 4

R9 tGHQZ OE# High to Output High-Z - 14 - 14 - 14 ns 3,4

R10 tOH CE# (OE#) High to Output Low-Z 0 - 0 - 0 - ns 3,4

R11 tEHEL CE# Pulse Width High 20 - 20 - 20 - ns 5

R12 tELTV CE# Low to WAIT Valid - 20 - 22 - 22 ns 5

R13 tEHTZ CE# High to WAIT High-Z - 25 - 25 - 25 ns 4,5

Latching Specifications

R101 tAVVH Ad dress Setu p to ADV# High 10 - 10 - 12 - ns -

R102 tELVH CE# Low to ADV# High 10 - 10 - 12 - ns -

R103 tVLQV ADV# Low to Output Valid - 70 85 -70ns 6

R104 tVLVH AD V# Pu ls e Wid th Lo w 10 - 10 - 12 - n s -

R105 tVHVL ADV# Pulse Width High 1 0 - 10 - 12 - ns -

R106 tVHAX Address Hold from ADV# High 9 - 9 - 9 - ns 2

R108 tAPA Page A ddress Access Time - 25 - 25 - 25 ns -

Clock Sp ec if ic ati on s

R200 fCLK CLK Frequency - 40 - 33 - 40 MHz -

R201 tCLK CLK Period 25 - 30 - 25 - ns -

R202 tCH/L CLK High or Low Time 9.5 - 9.5 - 9.5 - ns -

R203 tCHCL CLK Fall or Rise Time -3-5-5ns -

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

30 Order Numbe r: 290702 , Revision: 011

7.2 Read Operations - 180 nm Lithography

S yn chro nou s Spec ific ati ons

R301 tAVCH Address Valid Set up to CLK 9 - 9 - 10 - ns -

R302 tVLCH ADV# Low Setup to CLK 10 - 10 - 10 - ns -

R303 tELCH CE# Low Setup to CLK 9 - 9 - 9 - ns -

R304 tCHQV CLK to Output Valid - 20 - 22 - 20 ns -

R305 tCHQX Output Hold from CLK 5 - 5 - 5 - ns -

R306 tCHAX A ddress Hold from CLK 10 - 10 - 10 - ns 2

R307 tCHTV CLK to WAIT Valid - 20 - 22 - 22 ns -

Notes:

1. See Figure 22, “AC Input/Output Reference Waveform” on page 48 for timing measurements and maximum

allowable input slew rate.

2. Addr ess hold in synchronous-bur st mode is defined as tCHAX or tVHAX, whichever timing specification is

satisfied first.

3. OE# can be delayed by up to tELQV – tGLQV after the falling edge of CE# without impact to tELQV.

4. Sampled, not 100% tested.

5. Applies only to subsequent synchronous reads.

6. During the initial access of a synchronous burst r ead, data from the first word might begin to be driven onto the

data bus as early as the first clock edge after tAVQV.

Tab le 12. Read Op eration s - 180 nm Lithogra phy (Shee t 1 of 2)

# Sym Parame ter 1

32-Mbit

64-Mbit 128-Mbit

Units Notes

-70 -85 -90

Min Max Min Max Min Max

Asynchronous Specifications

R1 tAVAV Read Cycle Time 70 - 85 - 90 - ns 6

R2 tAVQV Address to Output Valid - 70 - 85 -90ns 6

R3 tELQV CE# Low to Output Valid - 70 - 85 -90ns 6

R4 tGLQV OE# Low to Output Valid - 30 - 30 - 30 ns 3

R5 tPHQV RST# High to Output Valid - 150 - 150 - 150 ns -

R6 tELQX CE# Low to Output Low- Z 0 - 0 - 0 - ns 4

R7 tGLQX OE# Low to Output Low- Z 0 - 0 - 0 - ns 3,4

R8 tEHQZ CE# High to Output High-Z - 20 - 20 - 20 ns 4

R9 tGHQZ OE# High to Output High-Z - 14 - 14 14 ns 3,4

Tab le 11. Read Op eration s - 130 nm Lithography (Sheet 2 of 2)

# Sym Parame ter 1

32-Mbit

64-Mbit 128-Mbit

Units Notes

-70 -85 -70

Min Max Min Max Min Max

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 31

R10 tOH CE# (OE#) High to Output Low-Z 0 - 0 - 0 - ns 3,4

R11 tEHEL CE# Pulse Width High 20 - 20 - 20 - ns 5

R12 tELTV CE# Low to WAIT Valid - 20 - 22 - 22 ns 5

R13 tEHTZ CE# High to WAIT High-Z - 25 - 25 - 25 ns 4, 5

Latching Specifications

R101 tAVVH Ad dress Setu p to ADV# High 10 - 1 0 - 12 - ns -

R102 tELVH CE# Low to ADV# High 10 - 10 - 12 - ns -

R103 tVLQV ADV# Low to Output Valid - 70 - 85 - 90 ns 6

R104 tVLVH AD V# Pu ls e Wid th Lo w 10 - 1 0 - 1 2 - ns -

R105 tVHVL ADV# Pulse Width High 10 - 10 - 12 - ns -

R106 tVHAX Address Hold from ADV# High 9 - 9 - 9 - ns 2

R108 tAPA Page Address Access Time - 25 - 25 - 30 ns -

Clock Sp ec if ic ati on s

R200 fCLK CLK Frequency - 40 - 33 - 33 MHz -

R201 tCLK CLK Period 25 - 30 - 30 - ns -

R202 tCH/L CLK High or Low Time 9.5 - 9.5 - 9.5 - ns -

R203 tCHCL CLK Fall or Rise Time - 3 5 - 5 ns -

Synchronous Specifications

R301 tAVCH Address Valid Setup to CLK 9 - 9 - 10 - ns -

R302 tVLCH ADV# Low Setup to CLK 10 - 10 - 10 - ns -

R303 tELCH CE# Low Setup to CLK 9 - 9 - 9 - ns -

R304 tCHQV CLK to Output Valid - 20 - 22 - 22 ns -

R305 tCHQX Output Hold from CLK 5 - 5 5 - ns -

R306 tCHAX Address Hold from CLK 10 - 10 - 10 - ns 2

R307 tCHTV CLK to WAIT Va lid - 20 - 22 - 22 ns -

Notes:

1. See Figure 22, “AC Input/Output Reference Waveform” on page 48 for timing measurements and maximum

allowable input slew rate.

2. Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichev er timing s pecif icati on is

satisfied first.

3. OE# can be delay ed by up t o tELQV– t GLQV after the falling edge of CE# without impact to tELQV.

4. Sampled, not 100% tes ted.

5. Applies only to subsequent synchronous reads.

6. During the initial access of a synchronous burst read, data from the first word might begin to be driven onto the

data bus as early as the firs t clock edge after tAVQV.

Table 12. Read Operations - 180 nm Lithography (Sheet 2 of 2)

# Sym Parameter 1

32-Mbit

64-Mbit 128-Mbit

Units Notes

-70 -85 -90

Min Max Min Max Min Max

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

32 Order Numbe r: 290702 , Revision: 011

Notes: .

1. WAIT shown asserted (RCR[10]=0)

2. ADV# assumed to be driven to VIL in this waveform

Figure 8. Asynchro no us Read Opera tion Waveform

Valid

Address

High Z

Valid

Output

R10

Address [A]

CE# [E]

OE# [G]

WE# [W]

Data [D/Q ]

RST# [P]

High Z

WAIT [T]

High Z

Note 1

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 33

Figure 9. Latched Asynch ron ou s Read Operati on Waveform

Hi g h Z Valid

Output

Valid

Address

Data [Q]

WE# [W]

OE# [G]

CE# [E]

A[MAX:2] [A]

ADV# [V]

RST # [P]

R102

R104

R10

R103

R101

R105 R106

A[1:0] [A]

Valid

Address

Valid

Address

Valid

Address

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

34 Order Numbe r: 290702 , Revision: 011

Note:

1. WAIT shown asserted (RCR[10] = 0).

Figure 10. Page-Mod e Read Op eration Waveform

R105

High Z Valid

Output Valid

Output

Valid

Address

Valid

Address Valid

Address

R102

R104

ADV# [V]

CE# [E]

OE# [G]

WE# [W]

Data [D/Q]

RS T# [P]

A[MAX:2] [A ]

A[1:0] [A]

R101

R106

R103

R108

R10R5

High Z

WAIT [T]

High Z

Note 1

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 35

Notes:

1. Section 14.2, “First Access Latency Count (RCR[13:11])” on page 83 describes how to insert clock

cycles during the initial access.

2. WAIT (shown asserted; R CR[10]=0) can be co nfigured to assert either duri ng, or one data cycl e before,

valid da t a.

3. In t hi s wa ve fo rm, an x-w ord bu rst is in it iat ed to t he mai n arr ay and i t i s t erm in at ed by a C E# d e- asse r tio n

after the first word in the burst. If this access had been done to Status, ID, or Query reads, the asserted

(low) WAIT signal would have remained asserted (low) as long as CE# is asserted (low).

Fi gure 11. Singl e Sy nc hrono us Re ad-A rray Operation Waveform

R12

R13

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

36 Order Numbe r: 290702 , Revision: 011

Notes:

1. Section 14.2, “First Access Latency Count (RCR[13:11])” on page 83 describes how to insert clock

c ycles du ring the initial access.

2. WAIT (shown asserted; RCR[10] = 0) can be configured to assert either during, or one data cycle

befor e, va li d data .

Figure 12. Synchron ous 4-Word Burst Read Opera tion Wav eform

R12

R11

R13

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 37

Notes:

1. Section 14.2, “First Access Latency Count (RCR[13:11])” on page 83 describes how to insert clock

cycles during the initial access.

2. WAIT (shown asserted; R CR[10]=0) can be co nfigured to assert either duri ng, or one data cycl e before,

valid data. (This exam ple assu mes a wait delay of t wo clocks.)

Figure 13. WAI T Functionality for EOWL (End-of-Word Line) Con dition Waveform

R12

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

38 Order Numbe r: 290702 , Revision: 011

Notes:

1. Section 14.2, “First Access Latency Count (RCR[13:11])” on page 83 describes how to insert clock

c ycles du ring the initial access.

2. WAIT shown asserted (RCR[10]=0).

Figure 14. WAI T Signal in Synchronous Non-Read Array Operation Waveform

R12

R13

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 39

Note:

1. During Burst Suspend, the Cl ock signal can be held hi gh or low.

Figure 15. Burst Suspend

Q0 Q1 Q1 Q2

R304R304

R13

R12

R9R4R9R4

R8R3

R106

R101

R105R105

R1R1

R305R305R305R304

CLK

Address [A]

ADV#

CE# [E]

OE# [G]

WAIT [T]

WE# [W]

ATA [D/Q]

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

40 Order Numbe r: 290702 , Revision: 011

7.3 AC Write Characteristics

Table 13. AC Write Characteristics

# Sym Pa rameter 1,2 Notes

32-Mbit

64-Mbit

128-Mbit Unit

-70 -85 / -90

MinMaxMinMax

W1 tPHWL (tPHEL) RST# High Recovery to WE# (CE#) Low 3150 - 150 - ns

W2 tELW L (tWLEL) CE# (WE#) Setup to WE# (CE#) Low 0 - 0 - ns

W3 tWLWH (tELEH) WE# (CE#) Write Pulse Width Low 445 - 60 - ns

W4 tDVWH (tDVEH) Data Setup to WE# (CE#) High 45 - 60 - ns

W5 tAVWH (tAVEH) Address Setup to WE# (CE#) High 45 - 60 - ns

W6 tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High 0 - 0 - ns

W7 tWHDX (tEHDX) Data Hold from WE # (CE #) High 0 - 0 - ns

W8 tWHAX (tEHAX) Address Hold from WE# (CE#) High 0 - 0 - ns

W9 tWHWL (tEHEL) WE# (CE#) Pulse Width High 5,6,725 - 25 - ns

W10 tVPWH (tVPEH) VPP Setup to WE# (CE#) High 3200 - 200 - ns

W11 tQVVL VPP Hol d from Valid SR D 3,80-0-ns

W12 tQVBL WP# Hold from Vali d SRD 3,80-0-ns

W13 tBHWH (tBHEH) WP# Setup to WE# (CE#) High 3200 - 200 - ns

W14 tWHGL (tEHGL) Write Recovery before Read - 0 - 0 - ns

W16 tWHQV WE# High to Valid Data 3,6,10 tAVQV

+ 40 -tAVQV

+ 50 -ns

W18 tWHAV WE# High to Address Valid 3,9,10 0 - 0 - ns

W19 tWHCV WE# High to CLK Valid 3,10 20 - 20 - ns

W20 tWHVH WE# High to ADV# High 3,10 20 - 20 - ns

Notes:

1. Write timing characteristics during erase suspend are the same as during write-only operations.

2. A writ e op er a tio n can be ter m in ated w ith eit h er C E# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high

(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.

5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low

( w hi ch ev er is las t). Hence , tWHWL = tEHEL = tWHEL = tEHWL.

6. System designers must take this into account, and can insert a software No-Op instruction to delay the first read after

issuing a command.

7. For commands other t han resume comm ands.

8. VPP must be held at VPPL or VPPH until block erase or program success is determined.

9. Applicable durin g asynchr onous reads following a write.

10. tW HCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst r ead. tWHCH/L an d tWHVH

both refer to the address latching event (either t he rising/falling clock edge or the ri sing ADV# edge, whichever occurs

first).

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 41

Notes:

1. VCC pow er-up and standby.

2. Write Program or Erase Setup command.

3. Write valid address and data (for program) or Erase Confirm command.

4. Automated program/erase delay.

5. Read status register data (SRD) to determine program/erase operation completion.

6. OE# and CE# must be asserted and WE# must be deasserted for read operations.

7. CLK is ignored (but can be kept active/toggling).

Figure 16. Write Operation s Wave form

Not e 1 N o t e 2 Note 3 Not e 4 Note 5

Address [A]

Valid

Address Valid

Address

CE# (WE#) [E(W)]

Not e 6

OE# [G]

WE# (CE#) [W(E)]

RS T# [P]

W11

W12

R105

VPP [V]

PPH

PPLK

WP# [B]

Data [Q]

Data In Valid

SRD

ADV# [V]

W16W1

W10

W13

W14

R101

R106

Data In

Valid

Address

Not e 6

R104

W5 W18

W19

W20

CLK [C]

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

42 Order Numbe r: 290702 , Revision: 011

Figure 17. Asynchro no us Read to Write Op eration Waveform

Figure 18. Asynchro no us Write to Read Operation

Q D

W4R10

W3W3

R9R4

R8R3

W8W5

R2 R1

ddres s [A]

CE# [E}

OE# [G]

WE# [W]

Data [D/Q]

RST# [P]

D Q

R2W7

W14

W18W3W3

R10W6W2

R1R1W8W5

ddress [A]

CE # [ E}

WE# [W]

OE# [G]

Data [D/Q ]

RST# [P]

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 43

Figure 19. Synch ronou s Read to Write Operation

Figure 20. Synchro nou s Write To Read Oper ation

Lat ency Count

Q D D

R13

R305

R304

R307R12

W15

W19

W9W3W3

W6R11R11

R303

W20

R104R104R106

R102

R105R105

W18

R101 R2

R306

R302

R301

CLK [C]

ddress [ A]

ADV# [V]

CE# [E ]

OE # [ G]

WE#

WAIT [ T]

Data [D/Q]

Latenc y C ount

D Q Q

R304

R305

R304

R307R12

W18

W19W3W3

R11 R303

R11

W20 R104R106

R104

R306W8W5

R302

R301 R2

CLK

ddress [A ]

ADV#

CE # [ E }

WE# [W]

OE# [G ]

WAIT [T]

Data [D/Q]

RS T# [ P]

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

44 Order Numbe r: 290702 , Revision: 011

7.4 Era se and Program Times

Tab le 14. Er ase and Program Time s

Operation Symbol Parameter Description1Notes VPPL VPPH Unit

Typ Max Typ Max

Erasing and Suspending

E ras e Time W500 tERS/PB 4-Kword Parameter Block 2,30.3 2.5 0.25 2.5 s

W501 tERS/MB 32-Kword Main Block 2,30.740.44 s

Suspend

Latency W600 tSUSP/P Program Suspend 25 10 5 10 µs

W601 tSUSP/E E rase Suspend 25 20 5 20 µs

Programming

Program

Time

W200 tPROG/W Single Word 212 150 8 130 µs

W201 tPROG/PB 4-Kword Parameter Block 2,30.05 .23 0.03 0.07 s

W202 tPROG/MB 32-Kword Main Block 2,30.4 1.8 0.24 0.6 s

Enhanced Factory Programming5

Program

W400 tEFP/W Single Word 4N/A N/A 3.5 16 µs

W401 tEFP/PB 4-Kword Parameter Block 2,3N/A N/A 15 - ms

W402 tEFP/MB 32-Kword Main Block 2,3N/A N/A 120 - ms

Operation

Latency

W403 tEFP/SETUP EFP Setup - N/A N/A - 5 µs

W404 tEFP/TRAN Program to Verify Transition - N/A N/A 2.7 5.6 µs

W405 tEFP/VERIFY Verify - N/A N/A 1.7 130 µs

Notes:

1. Unless noted otherwise, all parameters are measured at TA = + 25 °C and nom inal voltages, and are s ampled, not 100%

tested.

2. Excludes external system-level overhead.

3. Exact result s might vary based on system overhead.

4. W 40 0-Typ is the calc ulated dela y f or a si ng le pr o gramm ing pulse . W 40 0-Ma x in cludes th e de la y w he n progr a m mi ng

within a new word-line.

5. Some EFP performance degradation might occur if block cycling exceeds 10.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 45

8.0 Power and Reset Specifications

Intel® Wi reless Flash Memory (W 30) devices have a layered approach to powe r savings that can

significantly reduce ove rall system power consumption.

•The APS feat ure re duces power consump tion when the flash device is selected but idle.

•If CE# is deasserted, the memory enters its standby mode, where c urrent consumpt ion is even

lower.

•Asserting RST# provides current sa vings similar to standby mode.

The combi nation of these feat ures can minimize m emory power consumption, and therefore,

overall syste m powe r cons um ption.

8.1 Active Power

With CE# at VIL a nd RST# at VIH, t he f l ash de vic e i s i n the activ e mo de. Ref er to Section 6.1, “DC

Cur r ent Character is tics” on page 27, for I CC value s. When the f lash device is in active state, it

cons umes the most power from the sy stem. Minimiz ing flash device act ive current therefore

reduces system power cons umpt ion, especially in battery-powered appli ca tions.

8.2 Automatic Power Savings (APS)

Automatic Power Saving (APS) provides low power operation during a re ad acti ve state . ICCAPS is

the ave rage curren t measured over any 5 ms time int erval, 5 µs af ter CE# is deasserted. During

APS, aver age current is measured over the same time interval 5 µs after t he foll o w ing events:

•There is no internal read, program or erase activity.

•CE# is asserted.

•The address lines are quiescent, and at VIL or VIH.

OE# can be driven during APS.

8.3 Standby Power

When CE# is dea sserted, the fl as h device is deselected and pla ced in standby, substantia lly

reducing power consumption. In standby, the da ta outputs are placed in High-Z, indepe ndent of the

level placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time

interval, 5 µs after CE# is de asserted. During standby, average current is mea su r ed ove r the same

time interval 5 µs afte r CE# is deasserted.

When the fla sh device is dese lecte d (whil e CE# is deasserte d) during a progra m or erase operati on,

it continue s to c onsume active power until the program or erase ope ration completes.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

46 Order Numbe r: 290702 , Revision: 011

8.4 Power-Up/Down Characteristics

The flash device is protected agai nst acciden tal block erasure or programming during power

tr ansitions. Power supp ly sequencing is not required if VCC and VPP are connected together; so it

does not matter whether VPP or VCC powers-up first. If VPP is not connected to the system supp ly,

then V CC must attain VCCMIN before applying VCCQ and VPP. Do not drive flas h device inputs

before supply voltage = VCCQMIN. Power supply transitions can occur only when RST# is low.

8.4.1 System Reset and RST#

The use of RST# during system reset is im portant with automated program/erase flash devices,

because the system expects to read from the flash memory when it comes out of reset. If a CPU

r eset occ ur s without a flash memory r eset, the CPU is not properly initia lized, because th e f lash

me mory migh t be providing status information instead of arra y data.

Note: To allow proper CPU/flas h device ini tializa tion at system reset, connect RST# to the s ystem CPU

RESET# signal.

System d esigners must guard agai n st spuriou s writes when VCC vo ltages are abo v e VLKO.

Bec ause both WE# and CE# must be lo w for a command write, dri ving eit her si gnal to VIH inhi bit s

writes to the flash device. The CUI archi tecture provides additional protection, because memory

contents can be altered only after successful completion of the two-step comm and sequences.

The flash devic e is also di sabl ed until RS T# is br ought to VIH, regardless of its control input state s.

By holding the flash device in res et (RST# connected to sy stem PowerGood) during power-up/

down, invalid bus conditions duri ng power-up can be masked, pr oviding yet another level of

memory protection.

8.4.2 VCC, VPP, and RST# Transitions

The C U I la t ch es comm a nd s issued by s ystem software, and is not altered by VPP or CE#

transitions or WSM actions. Read-array mode is the power-up default state after the flash device

exits from reset mode or after VCC transitions above VLKO (Lockout voltage).

After complet ing program or b lock erase operation s (even after VPP transitions below VPPLK), t he

Read Array co mmand must reset the CUI to read-array mode if flash memory array access is

desired.

8.5 Power Supply D ecoupling

When the flash device is accessed, many internal c onditions ch ange. Circuits are ena bled to charge

pum ps and swit ch voltages. This internal activity produces transient noise.

To minimize the effe ct of this transient noise, device decoupling capacitors are required. Transi ent

current magnitudes depend on the flash device output capa citive an d inductive loading. Two-line

control and proper dec oupling capacitor selectio n sup pres ses these transient voltage pe aks.

Note: Eac h flash device must ha ve a 0. 1 µF ceramic capacitor connected between each power (VCC,

VCCQ, VPP), and ground (VS S , VSS Q ) sig nal. High-fre quency, inher ently low-inductanc e

capacitors must be as close as possible to t h e p acka g e signals.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number: 290702, Revisio n: 011 47

8.6 Reset Specifications

Table 15. Reset Specifications

# Symbol Parameter1Notes Min Max Unit

P1 tPLPH RST# Low to Reset during Read 1, 2, 3, 4 100 - ns

P2 tPLRH RST# Low to Reset during Block Erase 1, 3, 4, 5 - 20 µs

RST# Low to Reset during Program 1, 3, 4, 5 - 10 µs

P3 tVCCPH VCC Power Valid to Reset 1,3,4,5,6 60 - µs

Notes:

1. These specifications are valid for all product versions (packages and speeds).

2. The flash device might r eset if tPLPH< tPLPHMin, but this is no t gua ranteed.

3. Not applicable if RST# is tied to VCC.

4. Sampled, but not 100% tested.

5. If RST# is tied to VCC, the flash device is not ready until tVCCPH occurs after when VCC > VCCMin.

6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input v oltage must not exceed VCC un til VCC >

VCCMin.

Figure 21. Reset Operati ons Wave forms

(

A ) R eset durin g

read mode

(

B) Reset durin g

program or block erase

≤

(

C) Reset durin g

program or block erase

≥

RST# [P]

Abort

Complete

Abort

Complete

VCC

(

D) VCC Power-up to

RST# high

P1 R5

P2 R5

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wireless Fl ash Memory (W30) Datasheet

48 Order Numbe r: 290702 , Revision: 011

8.7 AC I/O Test Conditions

Note: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns.

Worst case speed conditions are wh en VCC = VCCMin.

Note: See Table 16 for component values.

Figure 22. AC Input/Output Reference Waveform

CCQ

/2 V

CCQ

Test Points

Input Outpu

Figure 23. T r ansient Equivalent Testing Load Circuit

Device

Under Test

CCQ

Out

Tab le 16. Test Configuration Compo nent Values for Worst Case Speed Conditions

Test Configuration CL (pF) R1 (kΩ)R

1 (kΩ)

VCCQMi n Sta n d ard Tes t 30 25 25

Note: CL in cludes jig capacitance.

Figure 24. Clock Input AC Wa veform

CLK [C] VIH

VIL

R203R202

R201

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 49

8.8 Flash Device Capacitance

TA = +25 ° C , f = 1 MH z

Symbol Parameter§Typ Max Unit Condition

CIN Input Capacitan ce 6 8 pF VIN = 0.0 V

COUT Out p ut Capacitan ce 8 12 pF VOUT = 0. 0 V

CCE CE# Input Capacitance 10 12 pF VIN = 0.0 V

§Sampled, not 100% tested.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel e ss Fl ash Memor y (W 30) Datasheet

50 Or der Numbe r: 290702, Revision: 011

9.0 Flash Device Operations

This chapter provides an overv iew of flas h device operati ons. The W30 flash memory device

f amily include s a n on-chip Write State Machine (WSM) to manage bloc k erase and program

algorithms. The WSM Command User Interface (CUI) allows minimal processor overhead with

RA M- like interface timings .

9.1 Bus Operations

9.1.1 Read

The W30 flash memory device has several read configurations:

•Asynchronous pa ge mode read.

•Syn chronous burst mo de read — outputs four, eight, sixteen, or continuous words, fr om main

blocks and parameter blocks.

Several read modes are available in each part ition:

•Read-array mode: read accesses retur n flash m emory array data from the addressed

locations.

•Read i d enti fier mode: reads return manuf acture r and devic e identi fier dat a, bloc k loc k statu s,

and protecti on register data . Identifie r information can be acce ssed starting at a 4-Mbi t

partition base addresses; the flash memory array is not acc essible in read id entifier mode.

•Read query mode: reads re tu rn th e flash device CF I d ata. CFI in formation can be accessed

starting at a 4-Mbi t partition ba se addresses; the flash memory array is not acces s ible in read

query m o de .

•Read status register m od e: reads return status regi ster data from the addressed partition. The

arr ay da ta fo r th at pa rt i ti o n is no t ac ce s si bl e. A sy s t em p r oc ess o r ca n che ck th e st atu s regi s t er

to determine the state of an add r essed partition, or to monitor program and erase progress.

Tab le 17. Bus Op erati ons Sum m ary

Bus Operation RST# CL K ADV# CE# OE# WE# WAIT DQ[15:0] Notes

Read

Asynchronous VIH X L L L H Asserted Output -

Synchronous VIH Running L L L H Driven Output 1

Burst Suspend VIH Halted X L H H Active Output -

Write VIH X L L H L Asserted Input 2

Output Disable VIH XXL H HAssertedHigh-Z3

Standby VIH XXH X XHigh-ZHigh-Z3

Reset VIL XXX X XHigh-ZHigh-Z3,4

Notes:

1. WAIT is valid o nly dur ing synchronous array-read operations.

2. Refer to the Table 19, “Bus Cycle Definitions” on page 55 for valid D Q [15: 0] duri ng a write operation.

3. X = Don’t Care (H or L).

4. RST# m ust be at VSS ± 0.2 V to meet the maximum specified power-down current.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 51

All partitions support the syn chronous burst mode that interna lly sequences addresses with respec t

to the input CLK to select and s upply data to the outputs.

Identifier codes, query data, and status regis ter r ea d operations execute as singl e-s ynchronous or

asynchronous read cycle s. WAIT is asserted durin g these read s.

Acce ss to the modes listed above is independent of VPP. An appropriate CUI co mmand places the

flash device in a read mode. At initial powe r-up or after reset, the flash device default s to

asynchronous read-array mode.

Asserting CE# enable s flash device read ope rations. The flash device int ernally decodes upper

addr ess inp uts to determine which part ition is acce ssed.

•Asserting ADV# opens the internal address latches.

•Asserting OE# activates the outputs, and gates the selected data onto the I /O bus .

•In as ynchronou s mode, the ad dress i s lat ched when ADV# i s dea ssert ed (when t he fla sh dev ice

is co nfigured to use ADV#).

•In sync hronous mode, the add ress is la tc hed by ei ther th e ri sing edge o f ADV# or the risi ng (or

falling) CLK edge while ADV# remains ass erted, whichev er occurs first.

WE# and RST# must be deass erted during read ope rations.

Note: If only as ynchronous reads are to be perform ed in your sy st em, CL K must be tied to a valid VIH

level, the WAIT signal can be floated, and AD V# must be tied to ground.

9.1.2 Burst Suspend

The Bu rst Sus pend fea ture al lows the sy stem to t empora rily s uspend a synchronous bur st oper ation

if the system needs to us e the flash device a ddress and data b us for other pu rpos es . Burst accesse s

can be suspended during the initi al latency (befo r e da ta is received) or after the flash device has

output data. When a burst ac cess is suspended, internal array sensing conti nues and any previously

latched internal dat a is retained .

Burst Suspe nd occurs when CE# is asserted, the curre nt address has been latched (either ADV#

risi ng edge or valid CLK edge), CL K is halted, and OE# is deasserted. CLK can be ha lted when it

is at VIH or VIL. To resume the burst ac ce ss, OE# is reasserted and CLK is restarted. Subsequent

CLK edges resume the burs t sequence where it left off.

W ithin the flash device, CE# gates the WAIT sig nal. Therefore, during Burst Suspend, WAIT

remains a ssert ed and d oes not re vert t o a hig h-impedance state wh en OE# is dea sserted. This WAIT

state can cause contenti on with another flash device attempting to control the system READY

signal during a Burst Suspend. System us ing the Burst Suspend feature must not connect the flash

device WAIT signal directly to the system READY signal.

Refer to Fi gure 15, “Burst Suspend” on page 39.

9.1.3 Standby

De-asserting CE# dese lects th e fla sh device and place s it in standby mode, substantially reduc ing

flas h device power cons umption. In sta ndby m ode, outputs are plac ed in a high-impedance state

independent of OE#. If deselected during a progr am or erase algorithm, the fla sh device consumes

active power until the program or erase operation completes.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel e ss Fl ash Memor y (W 30) Datasheet

52 Or der Numbe r: 290702, Revision: 011

9.1.4 Reset

The flash device enters a re se t m ode when RST# is ass erted. In reset mode, internal cir cuitry is

turned off and outputs are placed in a high-impedance state.

After returning from reset, a time tPHQV is required until outputs ar e val id, and a delay (tPHWV) is

r equired before a write sequence ca n be initiate d. After this wake-up interval, normal opera tion is

r estored. The fl ash devic e defa ults to read- array m ode, t he statu s regi ster is set t o 80h, a nd th e Read

Configuration Register defau lts to asynchronous page-m ode reads.

I f RST# is as s erted during an eras e or program operation, the ope ration aborts and the memory

contents at the a borted block or addre ss are invalid. See Figure 21, “Reset Operations Waveforms”

on pag e 47 for detailed information regard ing reset timings.

As on any automated device, RST# must be asserted during system reset. When the system comes

out of rese t, the process or expects to read from the flash memory array. Automated flash memory

devices provide status in formation when read during program or e rase operations. If a CPU reset

occurs with no flas h memory reset, the CPU might not be properly ini tialize d, because the flash

me mory devic e m ight be providing st atus information instead of arra y data. 1.8 Volt Int el Flash

me mory devic es allow proper CPU initializa tion following a system re s et through the use of the

RST# input. In this applicat ion, RST# is contr olled by the sa me CPU reset signal, RESE T#.

9.1.5 Write

A wr ite occur s when CE# and WE# are asserted and OE# is deass er ted. Flash memory co ntrol

com mands are written to the CUI using standard microprocessor write tim ings. Proper use of the

ADV# input is needed for proper latching of the addre sses. Refer to Section 7.3, “AC Write

Characteristics” on page 40 for det ails. T he add ress and data are l atche d on the risin g edge of WE #.

Write operations ar e asynchronous ; CLK is ignored (but can be kep t ac tive/toggling).

The CUI does not occupy an addressable memory location within any partition. The system

pr oce ssor must access it at the correct address ran ge, depending on th e kind of command executed.

Pro gramming o r eras ing can occur in only one part ition a t a time. Ot her part it ions mus t be in o ne of

t h e read modes or erase s u spend mod e.

Table 18, “Command Codes and Descriptions” on page 53 shows the av ailable commands.

Appendix A, “Write State Machine” on page 90 provides information about moving between

different opera ting modes using CUI comm ands.

9.2 Flash Device Commands

The flash device on-chip WSM manage s eras e and program algorithms. This local CPU (WSM)

controls the f lash device in -s ystem read, program, and era s e operations. Bus cycl es to or from the

f lash memory device c onform to standard microproc essor bus cycles. The RST#, CE#, OE#, WE#,

and ADV# cont rol signal s di cta te data flow into and out of the flash device. WAIT info rms the

CPU of valid data during burst reads. Table 17, “Bus Operations Summ ary” on page 50

summ arizes bus operations .

To select flash device ope rations, write specific commands into the flash device CUI. Table 18,

“Command Codes and Descriptions” on page 53 lis ts all poss ible command codes and

descriptions. Table 19, “Bus Cyc le Definitions ” on pa ge 55 list s command definitions. Because

com mands are partition-specific, you must iss ue write commands wit hin the target address range.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 53

Table 18. Command Codes and Descriptions (Sheet 1 of 2)

Operation Code Flash Device

Command Description

Read

FFh R ead Array Pla ces the selected partit ion in r ead-a rray mode.

70h Read Status

mod e after a P rogra m or Erase command i s issued to it .

90h Read Identifier Places the sele cted partiti on in rea d identifier mo de. Fla sh dev ice rea ds from

partition addresses output the manufacturer/device codes, configuration register

data, block lock status, or protection register data on D[15:0].

98h Read Query Places the addr essed p ar tition in re ad query mode. Fla s h dev ice rea ds from the

partition addresses output the CFI information on D[7:0].

50h Clear Status

The WSM c an set th e block lock (S R[1]), V PP (SR[3]), program (SR[4]), and

erase (SR[5]) status bits of the status register, but WSM cannot clear these bits.

SR[5:3, 1] can be clear ed only by a flash device rese t or through the Cle ar Status

Re gist er co mma nd.

Program

40h Word Program

Setup

• T he firs t cycle of this pr ef erre d pr ogram command prepare s the CUI for a

progra m operation.

• T he secon d cycle latches the address and data, an d executes the WSM

progra m algor it hm at this locat ion.

Status r egist er updates occur when CE# or OE# is t oggled. Af ter p rogra m m ing,

use a Read Array command to read th e arra y data.

10h Alternate

Setup Equivalent to a P r ogram Set up command (4 0h).

30h EFP Setup

This program command activates E FP m ode.

• T he first writ e cycle set s up the comma nd.

• If the second cycle is an EFP Confirm c ommand (D0h) , subsequent w rites

provide program data.

All other commands are ignored after EFP mode begins.

D0h EFP Confirm If the f ir st command was EF P Set up (30h), the C UI l atches the addr ess an d data,

and prepares th e flash dev ice for EF P mod e.

Erase

20h Era se Setup This com m and prepare s th e CUI for Block Erase. T he flash device erases t he

block that the Erase Conf ir m command addresses. If th e next comm and is not

Erase Confirm, the CUI sets status register bits SR[5:4] to indicate a command

sequence err or, and places the partiti on in the rea d status re gister m ode.

D0h Erase Confirm

If the firs t c om mand was Era s e Setu p (20h) , the CUI lat ches the address and

data, an d erases the block i ndic at ed by the er ase confi rm cycle addr ess. During

program or eras e, the partitio n responds only to Read Status Register , Pro gr am

Suspend, and Erase Suspend commands. CE# or OE# toggle updates the status

re gist er dat a.

Suspend B0h Program

Suspend or

Erase

Suspend

This command, issued at any flas h dev ice addr ess, suspends the cur r ently

exec uting program or era se operat ion. Sta tus regist er data indicates that the

operation was succ essful ly suspended if SR[2 ] (p rogr am suspen d) or SR[6]

(erase suspend) and S R[7] ar e set. T he WSM re mains in the suspended stat e

regardless of the control signal states (except RST#).

D0h Suspend

Resume Th is command, issued at any flas h device address, r esumes t he sus pended

program or eras e operati on.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel e ss Fl ash Memor y (W 30) Datasheet

54 Or der Numbe r: 290702, Revision: 011

Block Locking

60h Lock Setup This command pr epares t he CUI lock configuration. I f the next command i s not

Lock Block, Unl oc k Block, or Lock-Do wn, the CUI sets SR[5:4] to indicate a

comm and sequence er r or.

01h Lock Bl ock If the previous command was Lock Setup (60h), the CUI locks the addressed

block.

D0h Unlock Blo ck If th e previo us command was Lock Set up (60h), the CUI latches th e address and

unlocks the addressed block. I f previously l ocked-down, the opera tion has no

effect.

2Fh Lock-Down If th e previo us command was Lock Setup (60h), the CUI latc hes the address and

locks-down the addres sed block.

Protection C0h Protection

Program

Setup

This c ommand prep ares th e CUI for a prote c t ion regi ster pr ogram operati on. The

second cycle latches address and data, an d starts the WS M pr otection register

progra m or lock algorithm. Toggli ng CE# or O E# updates t he flash device st atus

regist er data. To re ad arr ay data afte r prog ra m m ing, issue a Read Array

command.

Configuration

60h Configuration

Setup This command prepares the CUI for flash device configuration. If Set

Configuration Register is not the next command, the CUI sets SR[5:4] to indicate

a c ommand sequence erro r.

03h Set

Configuration

If the previous c ommand w as Configuration Set up (60h) , the CUI latches the

address and writes the data f rom A[ 15:0] i nto the configuration reg ist er.

Subsequent rea d operations access the array data.

Note: Do no t use unassigned com m ands. Intel reserve s the ri ght to redefi ne these code s fo r futur e functions.

Tab le 18. Comman d Cod es and Descri ptions (Sheet 2 of 2)

Operation Code Flash Device

Command Description

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 55

Table 19. Bus Cycle Defi nition s

Operation Command Bus

Cycles

First Bus Cycle Second Bus Cycle

Oper Addr1Data2,3 Oper Addr1Data2,3

Read

Read Array/Reset > 1WritePnA FFhRead

Read

Address Array

Data

Read Identifier > 2 Wri te PnA 90h Read PBA+IA IC

Read Query > 2 Write PnA 9 8h Read PBA+ Q A QD

Read Sta tus Regist er 2 W r it e PnA 70h Re ad PnA SR D

Cle ar Status Regist er 1 W r it e XX 50h

Program

and

Erase

Block Erase 2 Write BA 20h Write BA D0h

Word Program 2 Write W A 40h/10h Write WA WD

EFP >2 Write WA 30h Write WA D0h

Program/Erase Suspend 1 Write XX B0h

Program/Erase Resume 1 Write XX D0h

Lock

Lock Block 2 Write BA 60 h Wr ite BA 01h

Unlock Block 2 Write BA 60h Write BA D0h

Lock-Down Block 2 W rite BA 60h Write BA 2Fh

Protection Protection Program 2 Write PA C0h Write PA PD

Lock Protection P r ogram 2 Writ e LPA C0h W rite LPA FFFDh

Configuration Set Co nfiguration

Notes:

1. First-c ycle command addresses mus t be the sam e as the t ar get addr ess of the operation. Examples:

—The fi rst-cy cle address fo r the Rea d Ident if ier comma nd must be the same as the Id entif icatio n code address ( IA ).

—The first-cycle address fo r the Wor d Pro gram command m ust be the sam e as the w ord address (W A) to be

programmed.

—The fi rst-cycle address fo r the Erase/Progr am Suspend command m ust be the same as the address wi t hin the block

to be suspended.

XX = An y valid addre ss w ithin th e flash device.

IA = Id entific ati on code addre ss.

BA = Block Addre ss. Any addre ss within a specific bl ock.

LPA = The Lock Prot ection Address is ob tained from the CFI (throu gh the R ead Query command). The W30 flash

memory device family LPA is at 0080h.

PA = Us er progr ammable 4-word pr otection addre s s.

PnA = Any addr ess within a specific partit ion.

PBA = Partition Base Addre ss. The f irst address of a particular partition .

QA = Query code address.

WA = Word ad dr ess of mem ory loca ti on to be written.

2. SRD = Sta t us re gist er dat a.

WD = Data to be wri tte n at locatio n WA.

IC = Identifier code data.

PD = User program mable 4-w or d prote ction data.

QD = Quer y cod e data on D[7:0].

CD = Conf igura tion register cod e data pr esented on flas h device addresses A[1 5:0]. A[ M AX: 16] address bits can

select any partition. See Tab le 27, “Read Conf igura ti on Register Defi nitio ns” on page 81 for co nfiguration

3. Do not use commands othe r than th ose shown above. Other commands a re reser ved by Inte l f or future flash device

implementations.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel e ss Fl ash Memor y (W 30) Datasheet

56 Or der Numbe r: 290702, Revision: 011

9.3 Command Sequencing

Wh en issu in g a 2 -c y cl e w r it e seq u enc e to th e fla sh de vi c e , a read o pe r at io n can o ccur between the

two wr ite cycle s. The se tup phase of a 2-cycl e write sequenc e pla ces the addre ssed partition into

r ea d-status mod e, so if th e sam e part ition is read before the second confirm write cycle is issued,

st atus register data i s ret urned. Re ads f rom othe r parti tio ns, ho wever , c an retur n ac tual a rray dat a, if

the addre ssed partition is already in read-array mode . Figure 25 and Figure 26 illust r ate th ese two

conditions.

By contrast, a writ e bus cycle must not interrupt a 2-cycle write sequence . Such an interruption

caus es a command sequence error to appear in the status register. Figure 27 illustrates a comm an d

sequence error.

Figure 25. Normal Write and Read Cycles

Figure 26. Interleavin g a 2-Cycle Write Sequence wi th an Array Read

Partition A Partiti o n A Pa rti tion A

20h

D0h FFh

Blo c k Era s e Se t up Bloc k Erase C onfirm Read Array

ddress [A]

WE# [W]

OE# [G]

Data [Q]

Partiti on B

Par t ition A

Partition B

Partition A

FFh

20h

Array Data

D0h

R ead Array Erase Set up Bus Re ad Erase C onfirm

ddre ss [A]

WE# [W ]

OE# [G]

Data [Q]

Figu re 27 . Imp rope r Com m a n d S e qu e nci ng

Parti tion X

Partition Y

Partition X

20h

FFh

D0h SR Data

ddress [A]

WE# [W]

OE# [G]

Data [D/Q]

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 57

10.0 Read Operations

10.1 Read Array

The Read Array command places (or resets) the partition in read-array mode and is used to re ad

data fr om the flash memory array. Upon init ial flash device power-up, or after re set (RST#

transitions from VIL to VIH), all partitions default to asynchronous read-array m ode.

To read array data from the flash de vice:

1. Write the Read Array command (FF h) to the CUI and specify the desi red word address.

1. Read fro m that address.

Note: If a pa rtition is alre ady in read-array mode, you do not need to issue the Read Array comm and to

re ad f r om that partition .

If the Read Arra y com mand is wr itt en to a parti ti on that is e rasin g or pr ogramming , the fla sh devic e

pres ents invalid data on the bus until the program or er as e operation completes.

After the pr ogram or eras e finishes in that partition, valid array data can then be read. If an Erase

Suspend or Pro gram Su sp end command suspends the WSM, a subse quent Read Array command

places the addressed partition in read-array mode.

The Read Arra y com mand functions independent ly of VPP.

10.2 Read Device ID

The read identifie r mod e outputs the manufacturer/ device ide ntifier, block lock status , protection

regis ter codes, and conf iguration register dat a. The identifier in formation is con tained withi n a

sep arate memory s pace on the flash device, and can be acces sed along the 4-Mbit partition address

range supplied by the Read Identifier command (90h) address. Reads from addresses in Tab le 20

retrieve ID information. Issu ing a Read Identifier command to a part ition that is program mi ng or

erasin g pla ces the out puts of th at part ition in re ad ID mode whi le the pa rtiti on conti nue s to pro gram

or erase in the backgr ound.

Table 20. Flash Device Identification Codes (Sheet 1 of 2)

Item Address1

Data Description

Base Offset

Manufacturer ID Partition 00h 0089h Intel

Device ID Partition 01h

8852h 32-Mbit TPD

8853h 32-Mbit BPD

8854h 64-Mbit TPD

8855h 64-Mbit BPD

8856h 128-Mbit TPD

8857h 128-Mbit BPD

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

58 Or der Numbe r: 290702, Revision: 011

10 .3 Read Query (CFI)

The W30 flash memory device contains a separate CFI query database that acts as an on-chip

d atasheet. To acce ss the CF I information wi thin the W30 flash memory device, issue th e Read

Query c ommand and supply a specific address.

The address is const ructed from th e base addre ss of a partition plus a part icular offset

corresponding to the desired CFI field.

Appendix B, “Common Flash Interface” on page 93 sho ws accessible CFI fields and their addre ss

of fsets. Issuing the Read Query comm and to a part ition that is programming or eras ing puts that

partition in read query mode whil e the partition continue s to program or erase in the background.

10.4 Read Status Register

The flash device status register displays program and erase operation status. The s tatus of a

partition can be read after writing the Read Status Register com mand to any location within the

address range of that parti tion. Read -status mode is the default read mode fol lowing a Program,

Erase, or Lock Block command sequence. Subsequent single reads from that partition ret urn the

partition s tatus unti l another valid command is written.

The r ead-status mode supports single s ynchronous and single asynchronous reads only; it does not

support burst read s.

The firs t falling edge of OE# or CE# latc hes and updates S tatus Regi ster data. T he ope ration does

not affect the modes of other partitions. Bec ause the S tatus Regis ter is 8 bits wide, only DQ [7:0]

contain valid status regis ter data; DQ [15:8] contain z eros. See Table 21, “Status Re gister

Definitions” on page 59 and Table 22, “S tatus Register Descri ptions” on page 59.

Blo ck Lock Statu s(2)Block 02h D0 = 0 Block is unlocke d

D0 = 1 Blo ck is locke d

Blo ck Lock-Do wn Status(2)Block 02h D1 = 0 Block is not locked-down

D1 = 1 Block is lo cked dow n

Co nfig ur a t ion R eg i s t e r Partit ion 0 5h Regist er Dat a

Protection Register Lock Status Partition 80h Lock Data

Protection Register Partition 81h - 88h Register Data Mul tip le reads requir e d to read

the entire 128-bi t Pr otection

Notes:

1. The address is constru cted from a base address pl us an offset. For example, to read the Bl ock Lock

Status f or bloc k numb er 38 in a BP D, set th e address to the BBA ( 0F8000h) plus the offset (02h),

whi c h in thi s example is 0F8002h. Then ex amine b it 0 of the data to determi ne whether the block is

locked.

2. See Sec tion 13.1.4, “Block Lock Stat us” on page 75 f or valid l ock status.

Tab le 20. Flash Device Identifica tion Codes (Sheet 2 of 2)

Item Address1

Data Description

Base Offset

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 59

Each 4- Mbit parti tion cont ains its own stat us registe r . Bit s SR[6:0] are unique to each pa rtitio n, but

SR[7], the Device WSM S tatus (DWS) bi t, perta ins to the entire flash memory device. SR[7]

provides the program and erase status of the entire flash de vice. By contrast, the Partition WSM

S tatus (PWS) bit, SR[0], provides program and eras e status of the addressed partition only. Status

regis ter bi ts SR[6:1 ] prese nt inform ation about par tit ion -specifi c pro gram, era se, suspe nd, VPP, and

block-lock st ates. Table 23, “Status Register Device WSM and Partition Write St atus Description”

on page 60 describes the DWS (SR[7]) and PWS (SR[0]) combinations.

Table 21. Statu s Register Definitions

DWS ESS ES PS VPPS PSS DPS PWS

76543210

Table 22. Status Register Descriptions

Bit Name State Description

7DWS

Device WSM Status 0 = Device WSM is Busy

1 = Device WSM is Ready

• SR[7] indicates e rase or pr ogram com plet ion in

the flash device.

• SR[6:1] ar e invalid while SR [7] = 0.

See Table 23 for valid SR[7] and SR[0] combinations.

6ESS

Er ase Suspend Status 0 = Era se in pro gr ess/complete d

1 = Er ase s uspended

Af ter is suing an Era se Suspend command, the WSM

halts and sets SR[7] and SR[6]. SR[6] remains set until

the fl ash device recei ves an Era se Resume com m and.

5ES

E r as e Status 0 = Era s e succes sful

1 = Er ase erro r

• SR[5] is set if an attempted erase failed.

• A Command Sequence Error is indicated when

SR[7 ,5: 4] are set.

4PS

Pr ogram Status 0 = Program successful

1 = Program error SR[4] is set if the WSM fa ile d to program a word.

3VPPS

VPP Sta tus 0 = VPP OK

1 = VPP low d etect, operati on abort ed

The WSM indicate s t he VPP level after program or

e rase com pl e t es.

SR[3] does not provide continuous VPP feedback and

is not guarant eed when VPP≠VPPL/VPPH

2PSS

Program Suspend

Status

0 = Program in progress/ completed

1 = Progr am su spen ded

Af ter receiving a Program Suspend command, t he

W SM ha lts ex ecu tio n and se ts SR[ 7] an d S R[ 2]. Thes e

bits remain set un til a Resume co mmand is received.

1DPS

Dev ice Pr otect Status

0 = Unlocked

1 = Abort ed erase/ pr ogram at temp t on

a locked block

If an erase or program operation is attempted to a

locked block (if WP# = VIL), the WSM sets SR[1] and

aborts the opera tion.

0PWS

Partition Write Sta tus

0 = This partition is busy, but only if

SR[7]=0

1 = Another partition is busy, but only if

SR[7]=0

The add r essed pa r titi on is era s ing or progr am ming. I n

EFP mode, SR[0] indicates that a data-stream word

has finished pr ogramm ing or ver ifying, d epending on

the particu lar EFP phase.

See Table 23 for valid SR[7] and SR[0] combinations.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

60 Or der Numbe r: 290702, Revision: 011

10.5 Clea r Sta tu s Reg ist er

The Clear Status Register command clears the status register and leaves all partition output states

unchanged. The WSM can set all status register bits and clear bits SR[7:6,2,0]. Because bits

SR[ 5,4,3,1] indicate various error conditions , they can be cleared only by the Clea r Status Re gis ter

comm and. By allowing system software to reset these bits, several operations (such a s

cum ulatively programmin g se veral addre sses or erasing mult iple blocks in sequence) can be

performed before reading the status register to determine whether an error occu rred.

I f an error is detected, the Status Regis ter must be cle ared before beginning another command or

sequence. Flash device reset (RST# = VIL) also clears the status register. This command functions

independent ly of VPP.

Tab le 23. Status Register Devi ce WS M and Pa rtition Write Status Description

DWS

(SR[7]) PWS

(SR[0]) Description

The addressed partition is performing a program/erase operation.

EFP : the flas h device has fi nished programming o r ver ifyin g data, o r i s r eady for d ata.

A partition ot her than the one curr ently addressed is perf or m ing a pr ogram/erase oper ation.

EFP : the flas h device is eit her progr amming or ver ifying dat a.

No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR[6,2])

indicate wheth er other partiti ons are suspended.

EFP : th e flash device has exited EFP m ode.

Does not occur in standar d pr ogram or erase m odes.

EFP: thi s combi na tio n does not occur.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 61

11.0 Program Operations

11.1 W ord Program

Wh e n th e Wor d Pr o g ram co mm an d is issued , th e WSM execu t es a sequ en ce of in t er n al ly tim e d

events to p r ogr am a word at the des ir ed address, and to verify that the b its are suff iciently

program m ed. Programming the fla s h me mo ry array changes specifically addressed bits to 0; 1 b its

do not change the memory cell conte nts.

Programming can occur in only one partition at a time. All other partitions must be in eit her a read

mode or erase s uspend mode. Only one partition can be in erase suspend mode at a time.

To examine the status register can be examined for program progress, read any a ddress within the

partition that is busy progra mming. However, while most status regist er bits are partition-s pecific,

th e Device WSM Status bit, S R[ 7], is device-specific. That is, if the status register is read from any

other partit ion, SR[7 ] indica tes the pro gram sta tus of the en tir e flash m emory dev ice. This s tatus bit

permits the system CPU to monitor the program progress while reading the status of other

partitions.

CE# or OE# toggl e (during polling) updates the status register. Several commands can be i ssued to

a partiti on that is pro gramm ing: Read Status Regi ster, Program Suspe nd, Rea d Identifier, an d Read

Query. The Read Array command can also be issued, but the read data is indeterminat e.

After programming compl ete s, three status register bits can signi fy various poss ible error

conditions:

•SR[4] indicates a program failure if set.

•If SR[3] is set, the WSM could not execute the Word Program command, because VPP was

outside the acceptable limits.

•If SR[ 1] is set, the progr am was abo r ted, becaus e the WSM attempted to program a locked

block.

After the sta tus register data is examined, clear it using the Clear Status Regis ter command before

issuing a new command. The partition remains in sta tus registe r mode until another command is

written to that pa rtition. Any command can be issued after th e s tatus register indic ates program

completion.

If CE# is deasserted while the flash device is programming, the flash devices do not enter standby

mode until the program operation complet es .

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

62 Or der Numbe r: 290702, Revision: 011

Figu re 28 . Word P rog ra m Fl owcha rt

Suspend

Program

Loop

Start

Write 40h,

Word Address

Write Data

Word Address

Read Status

SR[7] =

Full Program

Status Check

(if desired)

Program

Complete

FULL PROGRAM STATUS CHECK PROCEDURE

Suspend

Program

Read Status

Program

Successful

SR[3] =

SR[1] =

SR[4] =

Yes

Range

Error

Device

Protect Error

Program

Error

WO RD PROGRAM PRO CEDURE

SR[3] MUST be cleared before the WSM will allow further

program attempts

Only the Clear Staus Register command clears SR[4:3,1].

If an error is detected, clear the status register before

attempting a program retry or other error recovery.

Standby

Bus

Operation Command

Check SR[3]

1 = V

error

Check SR[4]

1 = Data program error

Comments

Repeat for subsequent programming operations.

Full status register check can be done after each program or

after a sequence of program operations.

Comments

Bus

Operation Command

Data = 40h

Addr = Location to program (WA)

Write Program

Setup

Data = Data to program (WD)

Addr = Location to program (WA)

Write Data

Read SRD

Toggle CE# or OE# to update SRD

Read

Check SR[7]

1 = WSM ready

0 = WSM busy

Standby

Standby Check SR[1]

1 = Attempted program to locked block

Program aborted

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 63

11.2 Factory Programming

The sta ndard factory programming mode uses the same commands and algorithm as the Word

Program mode (40h/10h). When VPP is at VPPL, program and era s e cu rrents are drawn through

VCC. If VPP is driven by a logic signal, VPPL must remain above the VPPLMin value to perfo rm

in-system flash memory modifications. When VPP is connected to a 12 V power supply, the flash

device draws program and erase c urrent direct ly from VPP, which elim inates the ne ed for a n

external swi tching trans istor to control the VPP voltag e.

Figure 37, “Examples of VPP Power S upply Configurations” on page 80 shows exa mp les of flash

device power supply us age in various configurations.

The 12-V VPP mode enhances programming performance during the short time period typically

found in manufacturing processes. Howe ver, this mod e is not intended for extended use.12 V can

be applied to VPP during progr am and era se operations as spec ified in Section 5.2, “Operating

Conditions” on page 26. VPP can be c onnected to 12 V for a total of tPPH hours maximum.

Stressing the flash device beyond the se limits mi ght cause permanent damage.

11.3 Enh an c ed Fact or y Pr o gram (E FP )

EFP substantially improves flash device programming perform anc e through a number of

enhancements to the conventional 12-Volt word program algorithm . The more e fficient WSM

algorithm in EFP eliminat es the traditional overhead delays of the conventional word program

mode in bot h the host pr ogra mming syst em and the f lash d evi ce. Ch anges to t he conve nti onal word

programming flowchar t and internal WSM routine were devel oped because of today's beat-ra te-

sen sitive manufacturing environments ; a balance between programming speed an d cycling

performance was attained.

The host programmer writ es data to the flash device and checks the Stat us Register to determine

when the dat a has compl eted progra mming. Thi s modification cuts wri te bus cycles approximately

in half.

•Following each internal program pulse, the WSM increments the flash device address to the

next phys ical loc ation.

•Progr amming e qui pment ca n t hen sequ ent ially stre am pr ogram d ata t hroughout an entir e b lock

without having to s etup and pre sent each new address.

In combin at ion, t hese enhancemen ts re duce m uch of t he hos t progra mmer ove rhead, enabl ing more

of a data streaming appr oach to flash device programming.

EFP further speeds up program mi ng by performing internal code verifi cation. With this feature,

PROM program mers can rely on the flash device to verify that it has be en programmed properly.

From the flash dev ice side , EFP stream lines inte rna l overhead by el imina ting the delays previous ly

assoc iated with switching voltages between programming and verify levels at each memory-word

location.

EFP cons ists of four phase s: setup, program, verify, and exit. Refer to Figure 29, “Enhanced

Factory Pro gram Fl owchart” on page 66 for a detailed graphical representation of how to

implement EFP.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

64 Or der Numbe r: 290702, Revision: 011

11.3.1 EFP Requirements and Consider ations

11.3.2 Setup

After recei vin g the EF P Set up (30h) a nd EF P Conf irm (D0h) command sequenc e, SR[7] tra nsit ions

f rom a 1 to a 0, indi cating tha t the WSM is busy with EFP algorithm startup. A delay be fore

checking SR[7] is required to allow the WSM time to perform all of its setups and checks (VPP

level and block loc k st at us). If an error is detec te d, status register bits SR[4], SR[3], and/or SR[1]

are set, and the EFP operation terminates.

Note: Aft er the EFP Setup and Confirm com mand sequence, reads from the flash device autom atically

output status register data. Do not issue the Read Status Register command, because this command

is interpreted as data to program at WA0.

11.3.3 Program

After setup c ompletion, the host program ming system must check SR[0] to determine the

data-stream ready status (SR[0]=0). Each s ubsequent write after this check is a program-data wr ite

to the flash memory arra y. Each cell within the memory word to be programmed to 0 recei ves one

WSM pulse; additional pulses, if required, occur in the verify phase.

SR[0]=1 indicates that the WSM is busy applying the program puls e.

The host programmer must poll the flash device status register for the program done state after

each data-stream write.

SR[ 0]=0 indicates that the appr opriate cell(s ) within the accessed me mo ry location ha ve

r eceived the ir single WSM pr ogram pulse, and tha t the flash device is ready for the next word.

Although the host ca n chec k full status for errors at any time, this check is necessary only on a

block basis, after E FP exit .

Addres ses must remain within the target bloc k. Supplying an address outsi de of the target block

immediately terminates the program phase; the WSM then enters the EFP verify phase.

Table 24. EFP Requirements and Considerations

E FP Requ ire me nts E FP Co nside r ati ons

Ambient temperature: TA = 25 °C ±5 °C Blo ck cycling below 100 era s e cy cles 1

VCC within specified operating range RWW not supported2

VPP within specified VPPH range EFP prog r ams one bl ock at a time

Targ et block unlocked EFP cannot be suspended

1. Reco m m ended fo r optimum performance. Some degradati on in

performance might occur if this limit is exceeded, but the internal

algorithm will cont inue to work p roper ly.

2. Code or data cannot be read from another partition during EFP.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 65

The addres s can either remain c onstant or inc r ement. The flash device compa r es the incoming

address to the address stored from the setup phase (WA0).

•If the addresses match, the WSM programs the new data word at the next sequential memory

location.

•If the addresses differ, the WSM jumps to the new address location.

The program phase concludes when the host programming system writes to a diffe rent block

address. The data supplie d must be FFFFh. Upon program phase completion, the flash device

enters the EFP verify phase.

11.3.4 Verify

A high percentage of the flash memory bits program on the first WSM pulse. However, EFP

in ternal verificat ion identifies ce lls that do not completely progr am on th eir first attempt, and

applies additional pulses as required.

The verify phase is ide ntical in flow to the program phase, except that instead of programming

in co min g data, the WSM compar es the v er ify-stream data to th e d ata t h at was previo u sly

programmed into the block.

•If the dat a co mpar es correctly, the host programmer proceeds to the next word.

•If the dat a does not match, the host waits while the WSM applies one or more additional

pulses.

The hos t pr ogrammer must reset its initial verify-word add ress to the sa me starting location

supplied durin g the program phase. It then reissues each data word in the same ord er as during the

program pha se. Like progra mming, the host can write each subsequent data word to WA0 or it can

increment through the block addresses.

The verification phase concludes when the interfacing program mer writes to a different block

address. The data supplied must be FF FFh. Upon completion of the verify pha se, the flash device

en ters the EF P exit pha se.

11.3.5 Exit

SR[7] =1 indicates that the fl ash device has returned to normal ope rating cond itions. Perform a ful l

status check at this time, to verify that the entire block programmed successfully. After EFP exit,

any val id CUI command can be issued.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

66 Or der Numbe r: 290702, Revision: 011

Figure 29. Enhanced Factory Program Flowchart

EFP Setup EFP Program EFP Verify

EFP Exit

1. WA

= first Word Address to be programm ed w ithin the target block. The BBA (Block Base

Address) must remain constant throughout the program phase data stream; WA can be held

constant at the first address location, or it can be written to sequence up through the addresses

w ithin the block. Writing to a BBA not equal to that of the block currently being w ritten to

term inates the EF P program phase, and instru ct s th e device to enter the EFP v erify p hase.

2. For proper verification to occur , the verify data stream must be presented to the device in the

same sequence as that of the program p hase data stream. Writing to a BBA not equal to WA

terminates the EFP verify ph ase, and instructs the device to exit EFP .

3. Bits that did not fully program w ith the single WSM pulse of the EFP program phase receive

additional program-pulse attempts during the EFP verify phase. The device will report any

program failure by setting SR[4]=1; this check can be performed during the full status check after

EFP has been exited for that block, and will indicate an y error w it h in the en t ire d ata stream.

Comments

Bus

State

Repeat for subsequent operations.

After EFP exit, a Full Status Check can

d et e rmin e if any p ro gram erro r occurred.

See the Ful l Statu s Ch eck p roced u re in t he

Word Prog ram flowchart.

Write

Standby

Read

Write

(note 2)

Read

Standby

Write

Read

Standby

EFP

Setup

Program

Done?

Exit

Program

Phase

Last

Data?

Exit

Verify

Phase

EFP

Exited?

Write EFP

Confirm

Read

Standby EFP

Setup

Done?

Read

Standby Verify

Stream

Ready?

Write Unlock

Block

Write

(note 1)

Standby Last

Data?

Standby

(note 3) Verify

Done?

SR[0]=1=N

Wri te D a ta

Address = WA

Last

Data?

Write FFFFh

Address

≠

BBA

Program

Done?

Read

Status Register

SR[0]=0=Y

SR[0]=1=N

Wri te D a ta

Address = WA

Verify

Done?

Last

Data?

Read

Status Register

Write FFFFh

Address

≠

BBA

Verify Stream

Ready?

Read

Status Register

SR[7]=0=N

Fu ll S t at u s Ch eck

Procedure

Operation

Complete

Read

Status Register

EFP

Exited?

SR[7]=1=Y

SR[0]=1=N

Start

Write 30h

Address = WA

= 12V

Unlock B lock

Wri te D 0 h

Address = WA

EFP Setup

Done?

Read

Status Register

SR[7]=1=N

Exit

EFP Program EFP Verify EFP Exi tEFP Setup

ENHANCED FACTORY PROGRAMMING PROCEDURE

Comments

Bus

State

Data = 30h

Address = WA

Data = D0h

Address = WA

Status Register

Check S R[ 7]

0 = EF P read y

1 = EF P not ready

= 12V

Unlock block

Check S R[ 0]

0 = Program done

1 = Program not done

Status Register

Data = FFFFh

Ad dress n ot with in same

BBA

Data = Data to program

Address = WA

Device autom atically

increments address.

Comments

Bus

State

Data = Word to verify

Address = WA

Status Register

Device autom atically

increments address.

Data = FFFFh

Ad dress n ot with in same

BBA

Status Register

Check S R[ 0]

0 = Ready for verify

1 = Not ready for verify

Check S R[ 0]

0 = Verify done

1 = Verify not done

Status Register

Check S R[ 7]

0 = Exit not finished

1 = Exit compl eted

Check V

& Lock

errors (S R [ 3, 1 ] )

Data Stream

Ready?

Read

Status Register

SR[0] =0=Y

SR[7]=0=Y

SR[0]=1=N

Standby

Read

Data

Stream

Ready?

Check S R[ 0]

0 = Ready for dat a

1 = Not ready for dat a

Status Register

SR[0]=0=Y

SR[0] =0=Y

EFP setup time

Standby EFP setup time

Standby Error

Condition

Check

If SR[7] = 1:

Check SR[3,1]

SR[3] = 1 = V

error

SR[1] = 1 = locked block

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 67

12.0 Program and Erase Operations

12.1 Program/Erase Suspend and Resum e

The Program Suspend and Eras e Suspend commands halt an in-progr ess program or eras e

operation. The command can be is sued at any flash devic e addres s. The partition corresponding to

th e ad dress o f th e command remain s in i t s previous stat e. A sus p end command allows data to be

acc essed from memory locations othe r than the loca tion being programmed or the block be ing

erased.

•A program operation can be suspe nded only to perform a read ope ration.

•An erase operation can be suspended to perform either a program or a read operation within

any block, except the block that is erase suspend ed.

•A program comman d nes ted within a suspended eras e can subsequently be suspended to r ea d

yet another location.

Once a program or erase pro cess sta rts, the Suspe nd command reque sts tha t the WSM sus pends the

program or erase se quence at predet ermined points in the algorithm. The partition that is act ually

suspended conti nues to output st atus regist er data afte r the Suspend command is written. An

operation is suspended when status bits SR[7] and SR[6] and/or SR[2] are set.

To read data from blocks within the partition (other than an erase-suspended block), write a Read

Array command. Block erase cannot resume unti l the pr ogram operations initiated during erase

sus p en d are co mplet e.

•Read Array, Read Status Register, Read Identifier ( ID), Read Query, a n d Program Resume are

valid commands during Program or Erase Suspend.

•Additiona lly, Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block,

Unlock Block, and Lock -Down Block are vali d com m ands during eras e s usp end.

To read data from a block in a partition that is not programming or erasing, the operation does not

need to be suspended.

•If the o ther pa rtitio n is alre ady in read array, ID, or Que ry mode , issuing a valid address returns

co r r esp on ding dat a.

•If the other partit ion is not in a read mode, one of the read commands must be issue d to the

partition befo re data can be read.

During a susp end, CE# = VIH places the fla sh de vice i n standby s tat e, whic h reduce s acti ve curre nt .

VPP must remain at its program level and WP# must remain unchanged while in su spend mode.

A resume command ins tructs the WSM to continue programming or erasing, and clears st atus

When read at the partition that is progr ammi ng or erasing, the fl as h device outp uts data

corresponding to the last mode for that parti tion. If the sta tus register error bits are set, th e status

regis ter can be cleared before issuing the next instruction. RST# must remain at VIH. See Figure

30, “ Program Suspend / Resume Flowchart” on page 68, an d F igure 31, “Erase Suspend / Resume

Flow chart” on page 69.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

68 Or der Numbe r: 290702, Revision: 011

I f a suspended partition was placed in Read Array, Read Stat us Regis ter, Read Identifier (ID), or

Rea d Query during the suspe nd, the flash device remains in that mode, and outputs data

corresponding to that mode after the pro gram or erase operati on res um es.

After res umi ng a suspended operat ion, issue th e read command appropr iate to the read operation.

To read status afte r res um ing a suspended operation, issue a Read Status Regist er command (70h)

to return the suspe nded partit ion to status mo de.

Figure 30. Program Suspen d / Resume Fl owc hart

Read Status

SR[7] =

SR[2] =

Write FFh

Susp Partition

Read Array

Data

Program

Completed

Done

Reading

Write FFh

Pgm'd Partition

Write D0h

Any Address

Program

Resumed Read Array

Data

Yes

PROGRAM SUSPEND / RESUME PROCEDURE

Write Program

Resume Data = D0h

Addr = any device address

Bus

Operation Command Comments

Write Program

Suspend

Data = B0h

Addr = Any address within programmin

partition

Standby Check SR[7]

1 = WSM ready

0 = WSM busy

Standby Check SR[2]

1 = Program suspended

0 = Program completed

Write Read

Array

Data = FFh

Addr = Any device address (except wor

being programmed)

Read Read array data from block other than

the one being programmed

Read Read SRD

Toggle CE# or OE# to update SRD

Addr = Any address in same partition

Start

Write B0h

Any Address

Write 70h

Same Partition

Write Read

Status Data = 70h

Addr = Any address in same partition

If the suspended partition was placed in Read Array mode

Write Read

Status

Return partition to status mode:

Data = 70h

Addr = addr ess within same partition

Write 70h

Same Partition

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 69

Figure 31. E rase S uspend / Resume Flowch art

Erase

Completed

Write FFh

Erased Partition

Read Array

Data

Read

Program

Loop

Read Array

Data

Yes

Start

Write B0h

Any Address

Read Status

SR[7] =

SR[6] =

Write D0h

Any Address

Erase Resumed

Read or

Program?

Done?

Write

Standby

Write

Erase

Suspend

Read Array

or Program

Erase

Resume

Data = B0h

Addr = Any address

Data = FFh or 40h

Addr = Any device address (except

block being erased)

Check SR[7]

1 = WSM ready

0 = WSM busy

Check SR[6]

1 = Erase suspended

0 = Erase comp leted

Data = D0h

Addr = Any address

Bus

Operation Command Comments

Read Read SRD

Toggle CE# or OE# to update SRD

Addr = Any address in same partition

Read or

Write Read array or program data from/to

block other than the one being erased

ERASE SUSPEND / RESU ME PROCEDURE

Write 70h

Same Partition

Write Read

Status Data = 70h

Addr = Any address in same partition

Write 70h

Same Partition

If the suspended partition was placed in

Read Array mode or a Program Loop:

Write Read

Status

Return partition to status mode:

Data = 70h

Addr = Address within same partition

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

70 Or der Numbe r: 290702, Revision: 011

12.2 Blo ck Era se

The 2- cyc le block erase command sequence, consisting of Erase Setup (20h) and Erase Confirm

( D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode

at a ti me ; other partitions must be in a rea d mode . Th e Era se Confirm com mand internally latch es

the ad d r ess of th e bl o ck to er ase . Er ase f or c es al l b it s w it hi n the bl o ck to 1.

SR [7] is cl ear ed wh i le th e erase exec u te s .

Aft er writing the Erase Confir m command, the selected partition is placed in read status reg ister

mode . Reads pe rformed to th at partit ion return the current sta tu s data. The a ddres s given durin g the

Erase Confirm command does not need to be the same address used in the Er ase S etup command.

For example, if the Er as e Confirm command is given to partition B, then the selected blo ck in

partition B is erased, even if the Erase Setup command was to partition A.

The 2-cycle erase sequence cannot be interrupted with a bus write ope ration. For example, to

execute properly, an Erase Setup comm and m us t be immediately followed by the Erase Confirm

comm and. If a different comm and is issued between the setup and confirm comm ands, the

f ollowing occurs:

•The p ar t it io n is pl aced in re ad - st atu s mod e .

•The status register signals a comm and s equence error.

•All subsequent erase commands to that partition are ignored until the status register is cleared.

To detect block erase completion, the CP U analyzes SR[7] of that partition. If an error bit

(S R[5,3,1]) was flagged, the status register can be cleared by issuing the Clear Status Register

com mand before atte mpting the next operation. The partit ion remains in re ad-stat us mode until

another command is written to its CUI . Any CUI instruction ca n follow after erasing completes.

The CUI can be set to read-array mode to prevent inadverten t status register reads.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 71

Figure 32. Block Erase Flow cha rt

SR[3,1]

must

be cleared before the WSM will allow further

erase attempts.

Only the Clear Status Register command clears SR[5:3,1].

If an error is detected, clear the Status register before

attempting an erase retry or other error recovery.

Start

FULL ERASE STATUS CHECK PROCEDU RE

Repeat for s ubsequent block erasures.

Full status register check can be done after each block erase

or after a sequence of block erasures.

Suspend

Erase

0Yes

Suspend

Erase

Loop

Write 20h

Block Address

Write D0h and

Block Address

Read Status

SR[7] =

Full Eras e

Status Check

(if desired)

Block Erase

Complete

Read Status

Block Erase

Successful

SR[1] = Erase of

Locked Block

Aborted

BLOCK ERASE P ROCEDU RE

Bus

Operation Command Comments

Write Block

Erase

Setup

Data = 20h

Addr = Block to be erased (BA)

Write Erase

Confirm Data = D0h

Addr = Block to be erased (BA)

Read Read SRD

Toggle CE# or OE# to update SRD

Standby Check SR[7]

1 = WSM ready

0 = WSM busy

Bus

Operation Command Comments

SR[3] = V

Range

Error

SR[5:4] = Command

Sequence Error

SR[5] = Block Erase

Error

Standby Check SR[3]

1 = V

error

Standby Check SR[5:4]

Both 1 = C ommand sequence error

Standby Check SR[5]

1 = Block erase error

Standby Check SR[1]

1 = Attempted erase of locked block

Erase aborted

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

72 Or der Numbe r: 290702, Revision: 011

12.3 Read-While-Write and Read-While-Erase

The I nte l® Wireless Flash Memory (W30) s upports flexible multi-partition dual-operation

architec ture. By di viding the flash m emory into many se parate partitions, t he flash device can read

f rom one partition while programing (Read-Whil e-Writ e) or erasi ng (Read-While-Eras) in anothe r

partition. Both of these features greatly enh anc e dat a s torage performance.

The W30 flash memory device does not support simultaneous program and erase ope rations.

Attempting to perform operations such as these results in a command sequence error. Only one

partition can be progr am mi ng or erasing while another parti tion is reading. Howeve r, one partition

can be in erase suspend mode while a second partition is performing a program operation, and yet

another parti tion is executing a read command. Table 18, “Command Codes and Descriptions” on

page 53 describes the command codes ava ilable for a ll functions .

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 73

13.0 Security Modes

The W30 flash memory device offe rs bot h hardware and software sec urity features to protect the

flash memory data.

•To use th e softw ar e secu rity f eature, execute the Lock Block command .

•To use the hardware security feature, execute the Lock-Down Block comm and and assert the

WP# signal.

Refer to Figu r e 3 3, “B lo ck Lo ck i n g Stat e D ia g ram” on pa g e 74 for a state diagram of the flash

device security features. Also see Figure 34, “Locking Operations Flowc hart” on page 77.

13.1 Block Lock Operations

Individual ins tant block locking protects code and data by allo wing any block to be locked or

unlocked with no latency. This locking schem e offers two leve ls of protection:

•Soft ware -only control of block locki ng (us eful for frequently changed data bl ocks ).

•Hardware interaction before locking can be ch anged (protects infrequently changed code

blocks).

The following s ections di scuss the l ocking syst em opera tio n. The t erm stat e [abc] specifies locking

states, such as state [001]. In this syntax:

•a= WP# value.

•b = block lock-down status bit D1.

•c = Blo ck Lo ck s tatus register bit D0.

Fig ure 33, “Block Locking State Diagra m” on page 74 defines possible locking states.

The fol lowing summarize s the loc king functionality.

•All blocks power-up in a locked state.

•Unlock commands can unlock thes e blocks, and lock co mmands can lock them again.

•The L oc k -D own comman d lo ck s a bl o ck an d prev ent s it fro m be in g unl o ck ed w h en W P# is

asserted.

— Locked-down blocks can be unlocked or locked with com mands as long as W P# is

deasserted.

— When WP# is asserted, previously locked-dow n blocks return to lock-down.

— The lock-do wn st atus bit clea rs only when the flash devi ce is reset or powe r ed-down.

Bl o ck lock registers are not af f ected by th e VPP level. The se r egisters can be modified and read

even if VPP < VPPLK.

The lockin g st atus of each bl ock can be set to locke d, unloc ked, and loc k-do wn, as describe d in the

following sections. See Figure 34, “Locking Operations Flowchart ” on page 77.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

74 Or der Numbe r: 290702, Revision: 011

13.1.1 Lock

All blocks default to locked (st ate [x01]) afte r initial power-up or reset. Locked blocks are fully

pr otected from alteration. Attempted program or eras e operations to a locke d block return an error

in SR[1].

•To lock unloc ked blocks , us e the Lock Block command sequenc e.

•To change the statu s of a locked block to unlocke d or lock-down, use the appropriate software

commands.

13.1.2 Unlock

Unlocked blocks (s tates [x00] and [110]) can be programmed or erased. All unlocke d blocks return

to th e lo c ked state w h en th e f la s h de vi ce is res e t or po w e r ed - d o w n.

•To change the status of an unlocked block to th e locked or locked-down state , use the

appropriate software comm ands.

•To unlock a lo cked block, write the Unlock Block command se quence if the block is not

locked-down.

Figure 33. Block Locking State Diagram

Notes: 1. [a ,b ,c] repres ents [W P#, D1, D0]. X = Don’t Care.

2. D1 indicates block Lock-dow n status .

- D1 = 0, Lock-dow n has not been issued t o this bloc k.

- D 1 = 1, Lock-dow n has been is s ued to t his block.

3. D0 indicates block l oc k s tatus.

- D0 = 0, bl oc k i s un lo c k ed .

- D0 = 1, bl oc k i s l oc ked.

4. Locked-do wn = Har dware + Software locked.

5. [011] states sh ou ld be tracke d by syst em softwar e to d eter mi ne differen ce be tween

Hardware Locked and Loc k ed -Dow n s tat es.

Software Block Lock (0x60/0x01 ) or Software Block Unlock (0x60/0xD0

)

Software Block Lock-Down (0x60/0x2F)

WP # hard war e c ontro l

[X00]

ower-Up/Reset

Unlocked

[111] [110 ]

Software

Locked

[011]

Hardware

Locked5

Unlocked

WP# Ha rdw are Control

[X01]

Locked

[011]

Locked-

Down4,5

B507

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 75

13.1.3 Lock-Down

Locked-down blocks (state [011]) offer an addi tional leve l of write protection beyond the

protec tion of a regula r locked block. If a bloc k is locked-down, the software cannot change the

state of the block if WP# is asserted.

•To lock-down a locked or unlocked bloc k, write the Lock-Down Block command sequence.

•If a block was set to loc ked-down, then later changed to unlocked, issue the Lock -down

comman d before assert ing WP#, to put that block back in th e locked-down state.

•Wh e n W P# is d ea ss er t ed , loc k ed - d o w n blo c ks cha n ge to th e lo ck e d st ate, and ca n th en be

unlocked usin g the Unlock Block comman d.

13.1.4 Block Lock Status

The lock status of eve r y block can be read in read ide ntifier mode.

Note: To enter this mode, issue the Read Identifier command to the flash device.

Subsequent reads at BBA + 02h output t he lock status of that block. For example, to read the bloc k

lock s tatus of block 10, the ad dres s sent to the flash device must be 50002h (for a top-parameter

device).

The lowest two da ta bits of the r ead data, DQ1 and DQ0, repr esent the lock status .

•DQ0 indicates t he block lock status. This bit is set using the Lock Block comm and and cleared

using the Block Unlock command. It is also set whe n entering the lock-down state.

•DQ1 indicates lock-down status and is set using the Lock-Down command.

The lock-down stat us bi t cannot be clear ed by s oftware–only by a flash de vice reset or

power-down. See Table 25.

Table 25. Write Protection Truth Table

V PP WP# RS T# Wri t e Prote cti on

XXV

IL Device is inaccessible

VIL XV

IH Word program and block erase are prohibited

IL VIH All lock-down blocks are locked

IH VIH All lock-down blocks can be unlocked

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

76 Or der Numbe r: 290702, Revision: 011

13.1.5 Lock During Erase Suspend

Block lock configurations can be performed during an erase suspend operation, using the standard

locking command se quences to unloc k, lock, or lock-down a block . Thi s feat ure is useful when

another block requires immediate updating.

To change block locking during an erase operation:

1. Writ e th e Eras e Suspen d command .

2. Check SR[6] to determine that the eras e operation has suspe nded.

3. Write the desir ed loc k command sequenc e to a block.

The lock status changes.

4. After completing lock, unlock, read, or program operations, resum e the erase operation w ith

t h e Eras e Resu me comma n d (D0h) .

I f a bloc k is locke d or locked-down during a suspended erase of the s ame block, the locking status

bits change immediately. When the erase operation resumes, it completes normally.

Loc king oper ations cannot occur during program suspend. Appendix A, “Write State Machine” on

page 90 shows valid c omman ds during erase suspend.

13.1.6 Status Register Error Checking

Using nested locking or pr ogram command sequenc es during eras e s uspend can introduce

am biguity into sta tus register res ults.

Bec aus e locking changes require 2-cyc le command sequences—for example, 60h followed by 01h

to lock a block—following the Confi guration Setup command (60h) wit h an invalid comm and

produces a command sequence error (S R[5:4]=11b).

I f a Lock Block command error occ urs during erase suspend, the flash device sets SR[4] and SR[5]

to 1 eve n after the erase res um es . When erase is complete, possible errors dur ing the erase cannot

be det ected from the sta tus register, bec aus e of the previous locki ng command error. A similar

situation occurs if a program operation error is nested within an erase sus pend.

13.1.7 WP# Lock-Down Control

The Write P r otect signal, WP#, adds an a dditional la yer of block security. WP# affects only blocks

that previously had the Lock-Down command written to them.

•After the lock-do wn status bit is set for a block, asserting WP# forces that block into the

lock-down state [011] and prevents it fr om being unlocked.

•After WP# is deasserted, the state of the block reverts to locked [111]. Software commands

can then unlock the block (for erase or progra m operations) a nd subsequently re-lock it.

Only flash devic e reset or power-down can clear the lock-down status bit and render W P#

ineffective.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 77

13.2 Protection Register

The W30 flash memory de vice inclu des a 128-bit Protectio n Register. This protection register is

use d to increase system security and for ide ntificatio n purposes. The protection register value can

match the flash device to the system CPU or ASIC to prevent flash device substitution.

•The l ower 64 bit s wit hin t he prote ction regis ter are programme d by Inte l wi th a uniq ue number

in ea ch fl as h d ev i ce .

•The upper 64 OTP bits within the protection register are le ft for the customer to program.

Once programmed, the cust omer segment can be locked to prevent further programming.

Note: The indivi dual bits of the user segment of the protection register are OTP, not the register in total.

The user can prog ram each OTP bit individually, one at a time, if desired. However, after the

protection reg ister is locked, the entire user segme nt is locked and no more user bits can be

programmed.

The protection register shares some of the same internal flash device resources as the parameter

partition. Therefore, RWW is allowed only between t he protection re gister a nd the main partitions.

Table 26 describes the operations allowed in the protection register, parameter partition, and main

partition during RWW and RWE.

Figure 34. Locking Opera tions Flowc hart

Optional

Start

Write 60h

Block Address

Write 90h

BBA + 02 h

Read Block Lock

Status

Locking

Change?

Lock Change

Complete

Write 01,D0,2Fh

Block Address

Writ e FFh

Partition Address

Yes

Write

(Optional)

Read

(Optional)

Standby

(Optional)

Write

Lock

Setup

Lock,

Un lock, or

Lockdown

Confirm

Read ID

Plane

Block Lock

Status

Read

Array

Data = 60h

Addr = Block to lock/unlock/lock-down (BA)

Data = 01h (Lock block)

D0h (Unlock block)

2Fh (Lockdown block)

Addr = Block to lock/unlock/lock-down (BA)

Data = 90h

Addr = BBA + 02h

Block Lock status data

Addr = BBA + 02h

Confirm locking change on DQ[1:0].

(See Block Locking State Transitions Table

for valid combinations.)

Data = FFh

Addr = Any address in same partition

Bus

Operation Command Comments

LOCKING OPERATIONS PROCEDURE

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

78 Or der Numbe r: 290702, Revision: 011

13.2.1 Reading the Protection Register

Writing the Rea d Ident ifi er co mmand allo ws the pr otect ion registe r dat a to be rea d 16 bits at a time

f rom addre s se s shown in Table 20, “Fla sh Devic e Ident ifica tio n Codes” on pa ge 57. The protec tio n

r egister is read from the Read Identifier command, and can be read in any partition.Writ ing the

Read Arra y com mand returns the flash device to read-array mode.

13.2.2 Programing the Protection Register

I ssue the Prot ection Pro gram com m and only at the param eter partit ion follo wed by the data to be

pr ogrammed at the specified location. Thi s comma nd programs the uppe r 64 bits of the pr otection

r egister 16 bi ts at a ti me. Table 20, “Flash Device Identification Codes” on page 57 shows

allowable addresses. See also Figure 35, “ Protection Register P r ogramming Flowcha r t” on

page 79. Issuing a Protection Progr am command out si de the address space of the register res ults in

a sta tus register error (SR[4]=1).

13.2.3 Locking the Protection Register

•PR-LK.0 is programmed to 0 by Intel to protect the unique flash device number.

•PR-LK.1 can be programmed by the user to lock the user portion (upper 64 bits) of the

protection register (See Figure 36, “Protecti on Register Loc king). This bi t is se t u s in g th e

Protection Program command to program a value of FFFDh into PR-LK.

After PR-LK register bits are programmed (locked), the stored values in the protection register

cannot be changed. Protection Program commands written to a locked section result in a status

Tab le 26. Simultaneous Operation s Allowed with the Protection Registe r

Protection

Parameter

Partition

Array Data

Main

Partitions Description

Read See

Description Write/Erase While p rog r amm ing o r er as ing in a m ai n p arti tio n, t he prote ct ion r egi ster c an be

read from any other partition. Reading the parameter partition data is not

allowed if the pro tecti on regi ster i s being r ead from addr esses wit hin the

parameter partition.

See

Description Read Write/Erase While pr ogr amming or erasing in a mai n partiti on, read operat ions are all owed

in th e paramet er partit ion. A ccessing th e prot ection registers from parameter

par t it ion ad dr ess es i s not allow ed.

Read Read Write/Erase While programming or erasing in a m ain part it ion, re ad ope ratio ns are all ow ed

in th e paramet er partit ion. A ccessing th e prot ection regi st ers is allowed, but

only in a partition that is different from the partition being programmed or

erased, and also different from the parameter partition.

Write No Access

Allowed Read While progra m ming the protection register, reads ar e allow ed only in the other

main partitions. Access to the parameter partition is not allowed, because

programming of the protection register can occur only in the par amete r

partition, so that the parameter partition exists in status mode.

No Access

Allowed Write/Erase Read While programmi ng or era sing the par ameter partitio n, reads of the pr otec ti on

registers are not allowed in any par ti tion. Re ad s i n ot he r main par tit ions ar e

supported.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 79

Fig ure 35 . Prot ection R egi st er Pr og ra m m i ng Fl owchart

FULL STATUS CHECK PROCEDURE

Protection Program operations addresses must be within the

protection register address space. Addresses outside this

space will return an error.

Repeat for subsequent programming operations.

Full status register check can be done after each program or

after a sequence of p rogram operations.

SR[3] MUST be cleared before the WSM will allow further

program attempts.

Only the Clear Staus Register command clears SR[4:3,1].

If an error is detected, clear the status register before

attempting a program retry or other error recovery.

Yes

1,1

1,0

1,1

PROTECTION REGISTER PROGRAMMING PROCEDURE

Start

Write C0h

Addr=Prot addr

Write Protect.

Address / Data

Read Status

SR[7] = 1?

Full Status

Check

(if desired)

Program

Complete

Read SRD

Program

Successful

SR[4:3] =

SR[4,1] =

Range Error

Programming Error

Locked-Register

Program Aborted

Standby

Bus

Operation Command

SR[1] SR[3] SR[4]

011V

Error

0 0 1 Protection register

program error

Comments

Write

Standby

Protection

Program

Setup

Protection

Program

Data = C0h

Addr = Protection address

Data = Data to program

Addr = Protection address

Check SR[7]

1 = WSM Ready

0 = WSM Busy

Bus

Operation Command Comments

Read Read SRD

Toggle CE# or OE# to update SRD

Standby 1 0 1 Register locked;

Operation aborted

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

80 Or der Numbe r: 290702, Revision: 011

13.3 VPP Protection

The I nte l® Wireless Flash Memory (W30) provides in- system pr ogram and era se at VPPL. For

factory programming, the W30 flash mem ory device also includes a low-cost, backward-

compatible 12 V programming feature.(See “Factory Programmin g” on page 63.) The EFP f eature

can also be used to greatly improve factory program perform ance, as explained in Se ct i on 11.3,

“Enhanced Factory Program (EFP)” on page 63.

I n addition to flexible block locki ng, holding the VPP programming voltage low can provide

hardware write protection of all fla sh - device blocks . If VPP is below VPPLK, program or erase

opera tions result in an error displayed in SR[3]. (See Figure 37.)

Note: If the VCC supply can sink adequate curr ent, you can use an appropriatel y valued r esistor.

Figure 36. Protection Register Locking

0x84

0x88

0x85

0x81

0x80 PR Lock Register 0

User-Programmable

In tel Fa cto ry- P ro g ramm e d

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Figu re 37. Ex a m pl es of VP P Po wer S uppl y Co nf i gu ra ti ons

•

12 V fa st pr ogramming

•

Absolute write protection with V

≤

PPLK

Syst em supply

(Note 1)

VCC

VPP

12 V supply

•

Low voltage and 12 V fast programming

Syst em supply

12 V supply

•

Low-voltage programming

•

Absolute write protection via logic signal

System supply

Prot# (logic signal)

•

Low-voltage programming

System supply

≤

10K

Ω

VCC

VPP

VCC

VPP

VCC

VPP

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 81

14.0 Set Read Configuration Register

The Set Read Configuration Register (RCR) command sets the burst order, frequency

configuration, burst lengt h, and other parameters.

A two-bus cyc le command sequence initiates this operation . The read configuration register data is

plac ed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles.

1. The Set Read Configuration Register command is written, along with the configuration data

(on the address bus ).

2. A seco nd wr ite confirm s the operation a nd again present s the read configuration register dat a

on the address b u s.

3. The read configuration register data is latched on the rising edge of ADV#, CE#, or WE#

(whichever occurs first).

This command functions i ndependently of the a pplied V PP volt age. Af ter executing this com ma nd,

the flash device returns to read-array mode.

To examine the contents of the read configuration register, write the Read Identifier command and

then read location 05h. (See Table 27 and Table 28.)

Table 27. Read Configuration Register Definitions

Read

Mode Res’d First Access Latency

Count WAIT

Polarity Data

Output

Config

WAIT

Confi

gBurst

Seq Clock

Confi

gRes’

dRes’

dBurst

Wrap Burst Length

RM R LC2 LC1 LC0 WP DOC WC BS CC R R BW BL2 BL1 BL0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

82 Or der Numbe r: 290702, Revision: 011

Tab le 28. Read Configur ation Register Descr iptions

Bit Name Description1Notes

15 RM

Read Mode 0 = Synchronous Burst Reads Enabled

1 = Asynchronous Reads Enabled (Default) 2,6

14 RReserved 5

13-11 LC[2:0]

First Access Latency

Count

001 = Reserved

010 = Code 2

011 = Code 3

100 = Code 4

101 = Code 5

111 = Reserved (Default) 6

10 WP

WAIT Signal Polari ty 0 = WAIT si gnal is asserte d low

1 = WAIT signal is asser ted high (Default ) 3

9DOC

Data Output Configuration 0 = Hold Data for One Clock

1 = Hold Data for Two Clock (Default) 6

8WC

WAIT Co nfiguration 0 = WAIT Asserted During Delay

1 = W AIT Asserted One Data Cycle before Delay (Default) 6

7BS

Burst Sequence 1 = Linear Bur st Order (Default )

6CC

Clock

Configuration

0 = Burst Starts and Data Output on Falling C lock Edge

1 = Burst Starts and Data Output on Rising Clock Edge (Default)

5RReserved 5

4RReserved 5

3BW

Burst Wrap 0 = Wrap bursts within burst length set by CR[2:0]

1 = Don’t wrap accesses wi thin burst length set by CR[2:0].(D efault)

2-0 BL[2:0]

Burst Length

001 = 4-Word Burst

010 = 8-Word Burst

011 = 16-Word Burst (Available on the 130 nm lithography)

111 = Continuous Burst (Def ault)

Notes:

1. Undo cument ed combinat ions of bit s are rese r v ed by Inte l for future impleme ntations.

2. Synchronous and page read mode configurations affect r eads from m ain blocks and parameter bl ocks. Sta tus Regist er

and configuration reads support single read cycles. RCR[15]=1 disables the configuration set by RCR[14:0].

3. Data is not ready when WAIT is asserted.

4. Set the synchron ous burst length. In asynchronous page mod e, the burst length equals four wor ds.

5. Set all reserved Read Configuration Register bits to zero.

6. Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010), data

hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before delay (RCR[8] =1) is not supported.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 83

14.1 Rea d Mode (RCR[15])

All pa rtitions support two high-pe rformance read configurations:

•synchronous burs t mode

•asy nchronous page mod e (default)

RCR[15] sets the read configur ation to one of the se modes.

S tatus re gi ster , query, an d i dentifi er m odes su pport onl y a sync hronous and s ingle- synchr onous r ead

operations.

14.2 First Access Latency Count (RCR[13:11])

The First Access Latency Count (RCR[13:11]) configuration tells the flash device how many

cloc ks must elapse fr om ADV# de-asser tion (VIH) before driving the first data wo r d on to its data

pins. The input clock frequency determ ines this value. See Tab le 27, “Read Confi gurati on Regi ster

Definitions” on page 81 for latency values.

Figure 38 shows data output late ncy from ADV# assertion for different latencies. Refe r to Section

14.2.1, “Latency Count Settings” on page 84 for Latency Code S ettin gs.

Note: Other First Access Latency Conf iguration settings are reserved.

)

Figure 38. First Access Latency Configuration

Code 5

Code 4

Code 3

Code 2

Valid

Address

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Address [A]

ADV# [V]

CLK [ C]

D[15:0] [Q]

Note: The 16-word boundary is the end of the flash device sense word-line.

14.2.1 Latency Count Settings

Figu re 39. Word Bound ary

0123456789ABCDEF

16 Word Boundary

Word 0 - 3 Word 4 - 7 Word 8 - B Word C - F

4 Word Boundary

Tab le 29. Latency Cou nt Settings

tAVQV/tCHQV (85ns/22ns) tAVQV/tCHQV (70ns/20ns) tAVQV/tCHQV (90ns/22ns) Unit

La tenc y Co unt

Settings 2 3 , 4, 5 2, 3, 4, 5 2 3, 4, 5

Frequency < 31 < 33 < 40 < 29 < 33 MHz

Figure 40. Dat a Output with LC Setting at Code 3

AMAX- 0 (A)

DQ15-0 (D/Q)

CLK (C)

CE# (E)

ADV# (V)

R103

Valid

Output Valid

Output

High Z

tADD-DELAY tDATA

1nd0st 2rd 3th 4th

Valid Address

Code 3

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 85

14.3 WAIT Signal Polarity (RCR[10])

•If the WT bit is c leared ( RCR[ 10]=0), then WAIT is configured to be ass erted low. A 0 on the

WAIT si gnal indicates that data is not ready and the da ta bus co ntains inva lid data.

•Conv er s el y, if RCR [ 1 0] is set, then WA IT is asser t ed hi g h.

In eithe r case, if WAIT is deas se rted, the n data is read y and valid. WAIT is asserted during

asy nchronous page mode reads .

14.4 WAIT Si gnal Function

The WAIT signal indi cates data valid wh en the flash devi ce is operating in syn chronous mode

(RCR[15]= 0), and whe n addre ssing a parti tion that is currently in read-array mode. Th e WAIT

signal is deasserted only when data is valid on the bus.

•When the flas h device is operating in synchronous non-read-ar r ay mode, such as read status ,

read ID, or read query, WAIT is set to an asserted state, as dete rm ine d by RCR[10]. See Figure

14, “WAIT Signal in Synchronous Non-Read Array Oper ation Waveform” on page 38.

•When the flash device is operating in asynchronous page mode or asynchronous single word

re ad mode, WAIT is set to an asserted state, a s determined by RCR[10]. See Figure 10, “Page-

Mode Read Operation Waveform” on page 34, and Figure 8, “Asynchronous Read Operation

Waveform” on page 32 .

From a system perspective, the WAIT signal is in the asserted state (based on RCR[10]) when the

flash device is operating in sync hronous non-read-array mode (such as Read I D, Read Query, or

Read St atus ), or if the flash de vic e is ope rating in async hronous mode (R CR[15]=1) . In the se c ases,

the s ys tem software must ignore (mask) the WAIT signal, bec ause WAIT does not conve y any

use f ul information about the validity of what is appearing on the data bus.

CONDITION WAIT

CE# = VIH

CE# = VIL Tri-State

Active

OE# No-Effect

Synchronous Arra y Read Active

Synchronou s Non- Array R ead A sserted

All Asynchronous Read and all Write Asserted

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

86 Or der Numbe r: 290702, Revision: 011

14.5 Data Hold (RCR[9])

The Data Outpu t Configura ti on (DOC) bit (RC R[9]) dete rmine s whether a da ta word re mains va lid

on the da ta bus for one or two clock cy cle s. The minimum data set-up tim e on the processor, and

the flash m emory clock-to-data output delay, determine whether one or two clocks are needed.

•A DOC s et at 1-clock data hold corresponds to a 1-clock data cycle.

•A DOC s et at 2-clock data hold corresponds to a 2-clock data cycle.

The setting of this config uration bit depends on the sy stem and CPU characterist ics. For

clar i fi c at io n , se e Figure 41. The following is a method for determining this configuration setting.

To set the flash device at 1-c lock data hold for subsequent reads, the foll owing condition must be

satisfied:

tCHQV (ns) + tDATA (ns) < One CLK Period (ns)

As an example, use a clock freq uenc y of 54 MHz and a cloc k period of 25 ns. Assume the data

output hold time is one clock. Apply this dat a to the formula above for the subsequent reads:

20 ns + 4 ns ≤ 25 ns

This equation is sat is f ied, and data output is available and val id at eve r y clock period. If tDATA is

long, hold for two cycles. During page-mode reads, t he initial acce ss time ca n be deter mi ned using

the f o rmu la :

tAD D- DELAY (n s )tDATA (ns) + tAVQV (ns)

Sub se quent reads in page mode ar e defi ned by:

tAPA (ns) + tDATA (ns) (minimum time)

Note: W AIT shown asserted high (RCR[10]=1).

Figu re 41. D ata Output Co nf i gu ra tio n wi t h WAIT Si gn a l Del a y

DQ15-0 [Q]

CLK [C]

Valid

Output Valid

Output

DQ15-0 [Q] Valid

Output

1 CLK

Data Hold

WAIT (CR.8 = 1 )

WAIT (CR.8 = 0)

tCHQV

WAIT (CR.8 = 0)

WAIT (CR.8 = 1)

2 CLK

Data Hold

tCHTL/H

Note 1

Valid

Output

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 87

14.6 WAIT Delay (RCR[8])

The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all synchronous

read-array modes. T his bit setti ng depends on the system and CPU cha r acteristics. The WAIT can

be asserted either during, or one data cycl e before, a va lid output.

In synchronous linear read array (no-wra p mode RCR[3]=1) of 4-word, 8-word, 16-word, or

continuous-word burst mode, an outp ut delay might occ ur when a burst se quence cross es its first

flash device-row boundary (16-word boundary).

•If the burs t s tart address is 4-word boundary aligned, the dela y does not occur.

•If the start address is misaligned to a 4-word bounda ry, the delay occurs once per burs t-mode

read sequence. The WAIT signal informs the system of this delay.

14.7 Burst Sequence (RCR[7])

The bu rst sequence specifie s t he s ynchronous -burst mode dat a order (see Table 30, “Seq uence and

B u rst Le ngth” on page 88 ). When operating in a linea r burs t mo de, either 4-word, 8-word, or

16- word burst lengt h with the burst wrap bit (RCR[3]) set, or in continuous burst mode, the flash

device might incur an output delay when the burs t sequence crosses the first 16-wo rd boundary.

(See F igure 39, “Word Boundary” on page 84 for word boundary description.)

Whether this delay occur s de pends on the star ting addres s.

•If the starting address is aligned to a 4-word bounda ry, there is no delay.

•If the starting addres s is th e e nd of a 4-wor d boundary, the output del ay is one clock cycle less

th an the Fir st Access Latency Count; this is the wor st- case delay.

The delay ta kes place only once, and only if the burst sequence crosses a 16-word bounda ry. The

WAIT pin informs the system of this delay. For timing diagrams of WAIT functionality, see the s e

figures:

•Fig ure 11, “Single Synchronous Read-Array Operation Waveform” on page 35

•Fig ure 12, “Synchronous 4-Word Burst Re ad Operation Wavefor m” on page 36

•Figure 13, “WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform” on

page 37

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

88 Or der Numbe r: 290702, Revision: 011

Note: Available on the 130 nm lithography .

14.8 Clock Edg e (RCR[6])

Configuring the va lid clock edg e enables a flexible mem ory interface to a wide r ange of burst

CPUs. Cloc k configuration s ets t he flas h device to start a burst cycle, output data, and assert WAIT

on the ri si ng or falling edge of the c lock.

Tab le 30. Seque nce an d Burst Length

Start

Addr.

(Dec)

Burst Addressing Sequence (Decimal)

4-Word Burst

CR[2:0]=001b 8-Word Burst

CR[2:0]=010b 16-Word Burst1

CR[2:0]=011b Co nt in uo us Bur s t

CR[2:0]=111b

Linear Linear Linear Linear

Wrap (CR[3]=0)

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-...

1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3...14-15-0 1-2-3-4-5-6-7-...

2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4...15-0-1 2-3-4-5-6-7-8-...

3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5...15-0-1-2 3-4-5-6-7-8-9-...

44-5-6-7-0-1-2-3 4-5-6...15-0-1-2-3 4-5-6-7-8-9-10...

55-6-7-0-1-2-3-4 5-6-7...15-0-1...4 5-6-7-8-9-10-11...

66-7-0-1-2-3-4-5 6-7-8...15-0-1...5 6-7-8-9-10-11-12-...

77-0-1-2-3-4-5-6 7-8-9...15-0-1...6 7-8-9-10-11-12-13...

...

14 14-15-0-1...13 14-15-16-17-18-19-20-...

15 15-0-1-2-3...14 15-16-17-18-19-...

No-Wrap (CR[3]=1)

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-...

1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3...15-16 1-2-3-4-5-6-7-...

2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4...16-17 2-3-4-5-6-7-8-...

3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5...17-18 3-4-5-6-7-8-9-...

44-5-6-7-8-9-10-

11 4-5-6...18-19 4-5-6-7-8-9-10...

55-6-7-8-9-10-11-

12 5-6-7...19-20 5-6-7-8-9-10-11...

66-7-8-9-10-11-

12-13 6-7-8...20-21 6-7-8-9-10-11-12-...

77-8-9-10-11-12-

13-14 7-8-9...21-22 7-8-9-10-11-12-13...

...

14 14-15...28-29 14-15-16-17-18-19-20-...

15 15-16...29-30 15-16-17-18-19-20-21-...

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 89

14.9 Burst Wrap (RCR[3])

The bu rst wrap bit determines whether 4-word, 8- word, or 16-word burst accesses wrap within the

bur st -length boundary, or they cro ss word-length boundaries to per f orm linear accesses .

No-wrap mode (RCR[3]=1) enables WAIT to hol d of f the system pr ocess or, as it does in the

continuous burst mode, unt il valid data is available .

In no-wrap mode (RCR[ 3] =0), the flash device oper ates similarly to continu ous linear burst mode,

but consumes less power during 4-word, 8-word, or 16-word bursts.

For example, if RCR[3]=0 (wrap mode) and RCR[2:0] = 1h (4-word bur st), possible linear burst

sequenc es are 0-1-2-3, 1-2-3 -0, 2-3- 0-1, 3-0-1-2.

If RCR[3]=1 (no-wrap mode) and RCR[2:0] = 1h (4-word burst length), the n possible li near burst

sequenc es are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. RCR[3]=1 not only enables li mited non-

aligned sequential bursts, but also reduces power by mini mi zing the number of internal read

operations.

Setting RCR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst

seq uenc es. However, significant ly m ore power might be consum ed. The 1- 2-3-4 s equence, for

example, c onsumes power during the initial acces s , again during the internal pipeline lookup as the

processor reads word 2, and pos s ibly again, depe nding on system tim ing, near the end of the

sequence as the flash device pipelines the next 4-word sequenc e. RCR[3]=1 while in 4-word burst

mode (no-wrap mode) reduces this excess power cons um ption.

14.10 Burst Length (RCR[2:0])

The burst length is the number of words the fla s h device outpu ts in a synchronous read ac cess.

4-wor d, 8-word, 16-word, an d continuous-word are supported.

In 4-wor d, 8-word, or 16-word burst configuration, the burst wrap bit (RCR[3]) determines

whethe r burst accesses wrap within word-length boundaries, or they cross word-length boundaries

to pe r for m a linear access.

After an address is spec ified, the flas h device outp uts data until it reaches the en d of its burstable

address space. Continuous burst acces ses are lin ear only (burs t wrap bit RCR[3] is ignored dur ing

continuous burst) and do not wra p within word-length boundaries (see Table 30, “Sequence and

B u rst Le ngth” on page 88 ).

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

90 Or der Numbe r: 290702, Revision: 011

Appendix A Write State Machine

Table 31 shows the command s tate transitions, based on incoming commands. Only one partition

can be actively programming or e rasing at a time.

Tab le 31. Next State Table (Sheet 1 of 2)

Chip

Next State after Command Input

Read

Array(3) Program

Setup(4,5) Erase

Setup(4,5)

Enhanced

Factory

Pgm

Setup(4)

BE Confirm,

P/E Resume,

ULB

Confirm(9)

Program/

Erase

Suspend

Read

Status

Clear

Status

Read

ID/Query

(FFH) (10H/40H) (20H) (30H) (D0H) (B0H) (70H) (50H) (90H, 98H

)

Ready Ready Program

Setup Erase

Setup EFP

Setup Ready

Lock/CR Setup Ready (Lock Error) Ready Ready (Lock Error)

Setup OTP Busy

Busy

Setup Program Busy

Busy Program Busy Pgm Susp Program Busy

Suspend Program Suspend Pgm Busy Program Suspend

Setup Ready (Error) Erase Busy Ready (Error)

Busy Erase Busy Erase Susp Eras e Busy

Suspend Erase

Suspend

Pgm in

Eras e

Susp Setup Erase Suspend Erase Busy Erase Suspend

Setup Program in Erase Suspend Busy

Busy Program in Erase Suspend Bus y Pgm Susp in

Erase Susp Program in Erase Sus pend Busy

Suspend Program Suspend in Eras e Suspend Pgm in Erase

Susp Busy

Program Suspend in Erase Suspend

Erase Suspend (Lock Error) Erase Sus p Erase Suspend

(Lock Error)

Setup Ready (Error) EFP Busy Ready (Error)

EFP Busy

(7)

EFP Verify

Verify Busy

(7)

Output

Next State after Command Input

Status

ID/Query

Write State Machine (WSM) Next State Table

Output Next State Table(1)

Lock/CR Setup,

Lock/CR Setup in Erase Susp

OTP Busy

Current Chip

State(8)

Ready,

Pgm Busy,

Pgm Suspend,

Erase Busy,

Erase Suspend,

Pgm In Erase Susp Busy,

Pgm Susp In Erase Susp

Pgm Setup,

Erase Setup,

OTP Setup,

Pgm in Erase Susp Setup,

EFP Setup,

EFP Busy,

Verify Busy

Lock/CR Setup in Erase

Suspend

Erase

Program

Program in

Erase Suspend

OTP

Enhanced

Factory

Program

Output

does not

change

Array(3) Status Output does not change St atus

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 91

Notes:

1. The output state shows the type of data that appears at the outputs if the partition address is the same as the command

address.

— A partition can be placed in Read Array , Read S tatus or Read ID/CFI, depending on the command issued.

— Each partition st ays in its last output st ate (Array, ID/C FI or Status) u ntil a ne w com m and changes it. The next WS M

state does not depend on the output sta te of th e partiti on.

— For exampl e, if the partition #1 outp ut state is Read Array and the par ti tion #4 output st ate is Read Sta tus, every read

fro m part ition #4 (wi thout issuing a new com mand) outputs the Status regist er.

Table 31. Next State Table (Sheet 2 of 2)

Chip

Next State after Command Input

Lock,

Unlock,

Lock-down,

CR set u p(5)

OTP

Setup(5)

Lock

Block

Confirm(9)

Lock-

Down

Block

Confirm(9)

Write CR

Confirm(9)

Enhanced

Fact Pgm

Exit (blk add

<> WA0)

Illegal

commands or

EFP data(2)

(60H) (C0H) (01H ) (2FH) (03H) (XXXXH) (other codes)

Ready Lock/CR

Setup OTP

Setup Ready

Lock/CR Setup Ready (Loc k Error) Ready Ready Ready Ready (Lock Error)

Setup OTP Busy

Busy Ready

Setup P rogram Busy N/A

Busy Program Busy Ready

Suspend Program Suspend

Setup Ready (Error)

Busy Er ase Busy Erase Busy Read y

Suspend Lock/CR

Setup in

Erase Susp Erase Suspend

Setup Program in Erase Suspend Busy

Busy Program in Erase Suspend Busy Erase

Suspend

Suspend Program Suspend in Erase Suspend

Er ase Suspend

(Lock Error)

Erase Susp Erase Susp Erase Susp Eras e Suspend (Loc k Error)

Setup Ready (Error)

EFP Busy

(7) EFP Verify

EFP Busy

(7)

EFP Verify

Verify Bus y

(7) Ready

EFP Verify

(7) Ready

Output

Next State after Command Input

Status

Status Array Status

Write State Machine (WSM) Next State Table

Output Next State Table(1)

Program

Erase

Program in

Erase Suspend

Current Chip

State(8)

OTP

Lock/CR Setup in Erase

Suspend

Enhanced

Factory

Program

Output does

not change

Output does

not change

WSM

Operation

Completes

N/A

Output does not change ArrayStatus

Pgm Setup,

Erase Setup,

OTP Setup,

Pgm in Erase Susp Setup,

EFP Setup,

EFP Busy,

Verify Busy

Lock/CR Setup,

Lock/CR Setup in Erase Susp

OTP Busy

Ready,

Pgm Busy,

Pgm Suspend,

Erase Busy,

Erase Suspend,

Pgm In Erase Susp Busy ,

Pgm Susp In Erase Susp

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

92 Or der Numbe r: 290702, Revision: 011

2. Il legal comma nds are any c ommands not de fi ned in the com mand se t.

3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in

undetermined data when a partition address is read.

4. Both cycles of two-cycle comma nds must be issued to the same pa r ti tion a ddress. If the two cycles ar e issued to di fferent

partitions, the address used for the second write cycle determines the active partition. Both partitions output status

informatio n when read.

5. If th e WSM i s active, bot h cycles of a tw o-cycle c ommand are ignored. T his feat ure differs from previous Intel flash

memory devices.

6. The Clear Status command clears status register error bits, except when the WSM is running (Pgm Busy , Erase Busy , Pgm

Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In Erase

Suspend).

7. EF P w rite s ar e allow ed only when status re gister bit SR.0 = 0. EFP is b usy if th e Block Address = the address at th e EFP

Confirm command. Any other co m m ands ar e trea ted as data.

8. The current state is the state of the WSM, not the state of the partition.

9. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then

mo ve to th e Ready State .

10. In Er ase susp end mode, the onl y valid two- cycle com m ands are Program Word, Lock/Unlock/Lockdown Bloc k, and C R

Writ e. Both cycles of other two -cycle com mands (Program OTP & conf irm, EFP Setup & confirm, Erase setup & confirm )

are ignored . In Program su spend or P rogr am suspend in Eras e sus pend, bot h cycles of al l two -cycle c ommands are

ignored.

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 93

Appendix B Common Flash Interface

This appendix defi nes the data struc ture or database returned by the Common Flash Interfac e

(CFI) Query command. System software par se s this structure to gai n critical information, s uch as

block size, density, x8/x16, and electrical specifications.

Once th is inf ormati on has been obta ined, the s oftware c an determ ine whic h command sets to us e to

enable flash device writes, enable block eras es, and otherwise control the flash device . Th e Query

is pa rt of an ove rall specification for mul tiple command s et a nd control interface descriptions,

which is ca lled the Common Flash Interface, or CFI.

B.1 Query Structure Output

The Query database allows system software to obtain information for controlling the flash device.

This s ection describes the flash device CFI-compliant interface that allows access to Query data.

Query da ta are presented on the lowest-order data outputs (D Q0-7) only. The numerical offset

value is the address relative to the maximum bus width that the flash device supports. On the W30

family of flash memory devices, the Query table device starting address is a 10h, which is a word

address for x16 flash devi ce s.

For a word-wide (x16) flash device, the first two Query-st ructure byt es , ASCII Q and R, appear on

the low byte at word addresses 10h and 11h.

•This CFI-compliant flash device outpu ts 00h data on upper byte s.

•The flash device outputs ASCII Q in the low byt e (DQ0-7) and 00h in the high byte (DQ8-15).

At Query addresses c ontaining two or more bytes of information, the leas t significant data byte is

pres ented at the lower address, and the most s ignificant data byte is presented at t he higher addre ss.

In all of the following tables, addresses and data are represented in he xadecimal notation, so the h

suffix has been dropped. In addit ion, because the upper byte of word-wid e flash device s is always

00h, the leading 00 has been dropped from the table notation, and only the lower byte value is

shown. Any x16 flash device outputs can be assumed to have 00h on the upper byte in this mode.

Table 32. Summary of Query Structure Output as a Function of the Flash Device and Mode

Device Hex

Offset Hex

Code ASCII

Value

Device A ddresses 00010:

00011:

00012:

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

94 Or der Numbe r: 290702, Revision: 011

B.2 Query Structure Overview

The Query comm and causes the flash device to display the Common Fla sh Interface (CFI) Que ry

structure or database. Table 34 summarizes the structure sub-sec tions and address locations .

Tab le 34. Que ry Structure

Notes:

1. Refer to the Se ction B.1, “Query Structure Ou tput” on page 93 and offset 28h, for the detailed definition

of the offset address as a function of th e flash device bus width and mode.

2. BA = Block Address beginning location (for example, 08000h is the block 1’beginning location when the

block size is 32K-word).

3. Offset 15 defi nes P, wh ich points to the Primary Intel-specif ic Extended Quer y Tab le.

Table 33. Example of Query Structure Output of x16- and x8 Flash Devices

Word Addressing: Byte Addressing:

Offset Hex Code Value Offset Hex Code Value

AX—A0D15—D0AX—A0D7—D0

00010h 0051 “Q” 00010h 51 Q

00011h 0052 “R” 00011h 52 R

00012h 0059 “Y” 00012h 59 Y

00013h P IDLO PrVendor 00013h P IDLO PrVendor

00014h P IDHI ID # 00014h P IDLO ID #

00015h PLO PrVendor 00015h P IDHI ID #

00016h PHI TblAdr 00016h ... ...

00017h A IDLO AltVendor 00017h

00018h A IDHI ID # 00018h

... ... ... ...

Offset

Su b-Sectio n Name

Description

(1)

00000h Manufacturer Code

00001h De vice Code

(BA+2)h

(2)

Bl oc k Stat us r eg i s ter

Block-s p ecific infor matio n

00004-Fh Reserved Reserved for vendor-specific information

00010h CFI query identification string Command set ID and vendor data offset

0001B h System interface information Device timing & voltage information

00027h De vice geom etry de finition Flash device layout

P(3) Primary Intel-specific Extended Query Table Vendor- defined addition al infor mation specific

to th e Pr imary Ve ndor Algo rithm

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 95

B.3 Block Status Register

The Bl ock Status Register indicates whether an era se operation co mpleted succes s f ully, a given

block is lo cke d, or a gi ven block can be acces s ed for flash mem ory program/eras e ope rations.

Block Erase Status (BSR.1) allows system software to determine the success of the last block erase

operation. Use BSR.1 just afte r power-up to verify that the VCC supply was not a ccident ally

removed during an erase opera tion.

Ta ble 35. Block Status Register

Notes:

1. BA = Block Address beginning location (for example, 08000h is the block 1 beginning location when the

block size is 32K-w or d).

B.4 CFI Query Identificati on Stri ng

The Identificat ion Stri ng verifies that the component supports t he Commo n Fl ash Interface

spe cification. I t also indicates the specification version and support ed vendor-s pecifie d comma nd

set(s).

Offset Length Description Add.

Value

(BA+2)h

(1)

1 Blo c k Loc k S tatus R eg ister BA +2 --00 or -- 01

BA +2 (bit 0): 0 or 1

BA +2 (bit 1): 0 or 1

B SR 2– 7: Res er v ed f or f u t u r e us e BA +2 (bit 2– 7 ) : 0

BSR.0 Block lock status

0 = Unlocked

1 = Lock ed

B SR .1 B l ock lock - do wn status

0 = Not loc ke d down

1 = Lock ed dow n

Table 36. CFI Identification

Offset Length Description Add. Hex

Code Value

10h 3 Query-unique ASC II string ”QRY ” 10:

11:

12:

--51

--52

--59

13h 2 Primary vendor command set and control interface ID code.

16-bit ID code for vendor-s pec if ied algor ithms 13:

14: --03

--00

15h 2 Extended Query Tabl e pr imary algorithm address 15:

16: --39

--00

17h 2 Alter nate vendor comma nd set and control interface ID code.

0000h mean s no second vendor -specifie d algori thm ex ists 17:

18: --00

--00

19h 2 Seco ndary alg or ithm Extended Query Tabl e address.

0000h means none ex ists 19:

1A: --00

--00

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

96 Or der Numbe r: 290702, Revision: 011

Table 37. System Interface Information

Offset Length Description Add.

Hex

Code Valu

1Bh 1 1B: --17 1.7V

1Ch 1 1C: --19 1.9V

1Dh 1 1D: --B4 11.4

1Eh 1 1E: --C6 12.6

1Fh 1

“n” such that typical single word program time-out = 2

µ- sec

1F: --04 16µs

20h 1

“n” such that typical max. buffer wri te time-out = 2

µ- sec

20: --00 NA

21h 1

“n” such that typical block erase ti me-out = 2

m-sec

21: --0A 1s

22h 1

“n” such that typical full chip erase time-out = 2

m-s ec

22: --00 NA

23h 1

“n” such that maximum word program t ime-out = 2

times typical

23: --04 256µ

24h 1

“n” such th at maximum buf fer write time-out = 2

ti mes typic al

24: --00 NA

25h 1

“n” such that maximum block erase time-out = 2

times typical

25: --03 8s

26h 1

“n” such that ma ximu m chip erase time-o ut = 2

time s typical

26: --00 NA

VCC l ogi c suppl y minimum pr ogram/er ase vol tage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

VCC l ogi c suppl y ma xi mum pr ogram/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

VPP [ progr am m ing ] suppl y m inimum progr am/eras e voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

VPP [programming] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 97

B.5 Flash Device Geometry Definition

Table 38. Flash Device Geometry Definition

Offset Length Description

Code

27h 1

“n” such that device size = 2

in number of bytes

27:

See table below

76543210

28h 2 ————x64x32x16x828:--01x16

15 14 13 12 11 10 9 8

————————29:--00

2Ah 2

“n” such that max imum number of bytes in writ e buffer = 2

2A:

--00

2B: --00

2Ch 1 2C:

2Dh 4 E rase Block Region 1 Information 2D :

bits 0–15 = y, y+1 = number of identical-siz e erase blocks 2E:

bits 16–31 = z, region erase block (s) size are z x 256 by tes 2F:

30:

31h 4 Erase Block Region 2 Information 31:

bits 0–15 = y, y+1 = number of identical-siz e erase blocks 32:

bits 16–31 = z, region erase block (s) size are z x 256 by tes 33:

34:

35h 4 Reserved for future erase block region information 35:

36:

37:

38:

See table below

Number of erase block regions (x) within device:

1. x = 0 means no erase blocking; the device erases in bulk

2. x specifies the number of device regions with one or

more contiguous same-size erase blocks.

3. Symm etricall y block ed partitions have one bloc king region

Flash device interface code as si gnment:

"n" such that n+1 specifies the bit field that repres ents the flash

device width capabilities as described in the table:

Address

32 Mbit

–B

–T

–B

–T

–B

–T

27: --16 --16 --17 --17 --18 --18

28: --01 --01 --01 --01 --01 --01

29: --00 --00 --00 --00 --00 --00

2A: --00 --00 --00 --00 --00 --00

2B: --00 --00 --00 --00 --00 --00

2C: --02 --02 --02 --02 --02 --02

2D: --07 --3E --07 --7E --07 --FE

2E: --00 --00 --00 --00 --00 --00

2F: --20 --00 --20 --00 --20 --00

30: --00 --01 --00 --01 --00 --01

31: --3E --07 --7E --07 --FE --07

32: --00 --00 --00 --00 --00 --00

33: --00 --20 --00 --20 --00 --20

34: --01 --00 --01 --00 --01 --00

35: --00 --00 --00 --00 --00 --00

36: --00 --00 --00 --00 --00 --00

37: --00 --00 --00 --00 --00 --00

38: --00 --00 --00 --00 --00 --00

64 Mbit

128 M bit

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

98 Or der Numbe r: 290702, Revision: 011

B.6 Intel-Specific Extended Query Table

Tab le 39. Primar y Vendor-Specific Extended Qu ery

Offset

(1)

Length

Description

Hex

P = 39h

(Optional flash features and commands)

Add.

Code

Value

(P+0)h 3 Pri mary extended query table 39: --50 "P"

(P+1)h Unique ASCII string “PRI“ 3A: --52 "R"

(P+2)h 3B: --49 "I"

(P+3)h 1 Major version number, ASCII 3C: --31 " 1"

(P+4)h 1 Minor version number, ASCII 3D: --33 "3"

(P+5)h 4 Opti onal feature and command support (1=yes, 0=no) 3E: --E6

(P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 3F: --03

(P+7)h “1” then another 31 bit fiel d of Optional features follows at 40: --00

(P+8)h the end of the bit–30 field. 41: --00

bit 0 Chip erase supported bit 0 = 0 No

bit 1 Suspend erase supported bit 1 = 1 Yes

bit 2 Suspend program supported bit 2 = 1 Yes

bit 3 Legacy lock/unl ock supported bit 3 = 0 N o

bit 4 Queued erase supported bit 4 = 0 No

bit 5 Instant i ndividual bl ock locking supported bit 5 = 1 Yes

bit 6 Protecti on bits supported bit 6 = 1 Y es

bit 7 Pagemode read supported bit 7 = 1 Yes

bit 8 Synchronous read supported bit 8 = 1 Yes

bit 9 Simultaneous operat ions supported bit 9 = 1 Yes

(P+9)h 1 42: --01

bit 0 Program supported after erase suspend bit 0 = 1 Yes

(P+A)h 2 Block st atus register mask 43: --03

(P+B)h bits 2–15 are Reserved; undefined bits are “0” 44: --00

bit 0 Block Lock-Bi t Status regi ster active bit 0 = 1 Yes

bit 1 Block Lock-Down Bit Status acti ve bit 1 = 1 Yes

(P+C)h 1 45: --18 1.8V

(P+D)h 1 46: --C0 12.0

Supported functions aft er suspend: read Array, Status, Query

Other supported operations are:

bits 1–7 reserved; undefined bits are “0”

VCC logic supply highest performance program/erase voltage

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volt s

VPP optimum program/erase supply voltage

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 99

Table 41. Burst Read Information for Non-Multiplexed Flash Device

Table 42. Partition and Erase-Block Region Information

Table 40. Protection Register Information

Offset(1)

P = 39h Length Description (Optional flash device features and commands) Add. Hex

Code Value

(P+E)h 1 Number of Protection regi ster fields in JEDEC ID space.

00h indicates that 256 protection fields are available 47: --01 1

(P+F)h

(P+10)h

(P+11)h

(P+12)h

4 Protection Field 1: Prot ection Desc ription

This field describes user- available O ne Time Programmab le (OTP)

Protection register bytes.

• S ome bytes are pr e-pr ogramm ed with fl ash device-unique

serial numbers.

• Other bytes are user programmable.

Bits 0-15 point to the Protection register Lock byte, the first byte in

the sectio n. The foll owing bytes are factory pre- progr ammed and

user-programmable.

• bits 0--7 = Lock/bytes Jedec-plane physical low address

• bits 8- -15 = Lock/bytes Jedec- plane phys ical high address

• bits 16--23 = n such that 2n = fact ory pre-programmed by tes

• bits 24--31 = n such that 2n = user programmable bytes

48:

49:

4A:

4B:

--80

--00

--03

80h

00h

8 by te

Offset

(1)

Length

Description

Hex

P = 39h

(Opt i o n al fl as h f ea tur e s and com m ands)

Add.

Code

Value

(P+13)h 1 4C: --03 8 byt

(P+14)h 1 4D: --04 4

(P+15)h 1 4E: --01 4

(P+16)h 1 Synchronous mode read capability configurat ion 2 4F: --02 8

(P+17)h 1 Synchronous mode read capability configurat ion 3 50: --03 16

(P+18)h 1 Synchronous mode read capabil ity configuration 4 51: --07 Con

Page Mode Read capability

bi ts 0–7 = “ n” suc h that 2n HEX v alue repre s ents the number of

read-page by tes. See offset 28h fo r device word width to

deter mine pag e-mode data output width. 00h in dicates no

read page buffer.

Number of synchronous mod e r ead configuration fiel ds that

fo llow . 00h indicates no bur s t capability .

Synchronous mode read capability configuration 1

Bits 3–7 = Rese rved

bits 0–2 “n” such tha t 2n+1 HEX value represents the

maxi m um num ber of co ntin uo us syn chr o nous r ea ds wh en

the device is configu red for it s max imum wor d widt h. A value

of 07h indicates that the device is capable of continuous

linear bur sts that will output dat a until th e inter nal burst

c ount e r reach es the end of t he device ’ s bu r s t a ble addr e s s

space. Th is field’s 3-bit value can be written directly to the

Read Configurat ion Reg ister bi ts 0–2 if the device is

c onfig ured f o r it s m a xi mum word wid t h . Se e offs e t 28 h f o r

wor d widt h to determine the burst da ta output w idth.

Offset

(1)

See table below

P = 39h

Description

Address

Bottom

Top

(Opt ional fl as h f ea t ur e s an d comm an d s )

Len

Bot Top

(P+19)h (P+19)h 1 52: 52:Number of de vice har dw are- par tit ion re gions within th e de vice.

x = 0: a single hardware partition device (no fields follow).

x specifies the number of device partition regions containing

one or more contiguous erase block regions.

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

100 Order Numbe r: 290702, Revision: 011

Tab le 43. Pa rtition Region 1 Information

Offset

(1)

See table below

P = 39h

Description

Address

Bottom

Top

(O ption a l fl ash features and commands)

Len

Bot Top

(P+1A)h (P+1A)h N u m ber of identi c al par titi ons within t h e par tit ion re gi on 2 53: 53:

(P+1B)h (P+1B)h 54: 54:

(P+1C)h (P+1C)h 1 55: 55:

(P+1D)h (P+1D)h 1 56: 56:

(P+1E)h (P+1E)h 1 57: 57:

(P+1F)h (P+1F)h 1 58: 58:

(P+2 0) h (P+ 20) h Partitio n Region 1 Er as e B l ock Type 1 I nfor mat ion 4 59: 59:

(P+2 1) h (P+ 21) h bi ts 0–15 = y, y+ 1 = num ber of i de ntical -size er as e block s 5A : 5 A :

(P+22)h (P+22)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 5B: 5B:

(P+23)h (P+23)h 5C: 5C:

(P+24)h (P+24)h Part i tion 1 ( Er a s e B loc k Type 1) 25D:5D:

(P+25)h (P+25)h Minimu m bloc k er a se c ycles x 100 0 5E: 5E:

(P+26)h (P+26)h 1 5F: 5F:

(P+27)h (P+27)h 1 60: 60:

(P+2 8) h Par ti tion R eg ion 1 E ras e B loc k Type 2 Informatio n 4 61:

(P+2 9) h bi ts 0–15 = y, y+ 1 = num ber of identic a l- s ize er ase bl o ck s 62 :

(P+ 2A)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 63:

(P+ 2B)h (bot tom parameter de vice only) 64:

(P+2C)h

Partition

(Erase block Type 2)

65:

(P+2 D ) h Minim um block er a se c ycles x 1 00 0 66 :

(P+2E)h 167:

(P+2F)h 168:

Simult aneous program or eras e operations allowed in ot her

partitio ns whil e a par ti t i on in th is reg io n is in Prog r am m od e

bits 0–3 = nu m ber of sim ul t aneous P r o gr a m oper a t ions

bits 4–7 = nu m ber of sim ul t aneous E r a s e oper a t ions

Simult aneous program or eras e operations allowed in ot her

partitio ns whil e a par ti t i on in th is reg io n is in Eras e m od e

bits 0–3 = nu m ber of sim ul t aneous P r o gr a m oper a t ions

bits 4–7 = nu m ber of sim ul t aneous E r a s e oper a t ions

Nu m ber of pro gram or er a se op er at i ons allow ed in a par tit ion

bits 0–3 = nu m ber of sim ul t aneous P r o gr a m oper a t ions

bits 4–7 = nu m ber of sim ul t aneous E r a s e oper a t ions

P artit i o n 1 ( eras e block Type 1) bits per c ell; int er n al E CC

bits 0–3 = bit s pe r ce l l i n erase r eg ion

bi t 4 = reserved for “internal ECC used” (1=yes, 0=no)

bi ts 5– 7 = reserve for future use

Partition 1 (erase block Type 1) page mode and synchronous

mode capabilities defined in Table 10.

bit 0 = pa ge- m o de hos t read s per mi tt e d ( 1= yes , 0= no)

bi t 1 = synchronous host reads permitted (1=yes, 0=no)

bit 2 = s yn chr o nous hos t writes per mit t e d ( 1= yes , 0= no)

bits 3–7 = reserved for future use

P artit i o n 1 ( Er a s e block Type 2) bits per c ell

bits 0–3 = bit s pe r ce l l i n erase r eg ion

bi t 4 = reserved for “internal ECC used” (1=yes, 0=no)

bi ts 5– 7 = reserve for future use

P artit i o n 1 ( Er a se bloc k Ty pe 2) pag emod e an d syn c hr ono us

mode capabilities defined in Table 10

bit 0 = pa ge- m o de hos t read s per mi tt e d ( 1= yes , 0= no)

bi t 1 = synchronous host reads permitted (1=yes, 0=no)

bit 2 = s yn chr o nous hos t writes per mit t e d ( 1= yes , 0= no)

bits 3–7 = reserved for future use

Types of erase block regions in this Partition Region.

x = 0 = no erase blocking; the Partition Region erases in bulk

x = numbe r of er a se block r egions w/ co ntig uo us same-s ize

erase blocks. Symmetrica lly blocked par ti ti ons have one

bl ocking region. Partition size = (Type 1 blocks)x(Type 1

block size s) + (Type 2 blocks)x ( Type 2 block siz es) +…+

(Typ e n blocks)x(Type n block sizes)

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 1 01

Table 44. Partition Region 2 Information

Offset

(1)

See table below

P = 39h

Description

Address

Bottom

Top

(O ptional flash fea t ures and commands)

Len

Bot Top

(P+30)h (P+28)h Number of identical partitions within the partition region 2 69: 61:

(P+31)h (P+29)h 6A: 62:

(P+32)h (P+2A)h 1 6B: 63:

(P+33)h (P+2B)h 1 6C: 64:

(P+34)h (P+2C)h 1 6D: 65:

(P+35)h (P+2D)h 1 6E: 66:

(P +36) h (P+ 2E) h P ar ti t i o n R eg ion 2 E ras e B l ock Type 1 I nfor mat io n 4 6F : 67:

(P+3 7) h ( P+2F) h bi t s 0– 15 = y, y+ 1 = num ber of identic a l- s ize er as e block s 70 : 68:

(P+ 38)h (P+30) h bit s 16–31 = z, r egion er ase block(s) size are z x 256 bytes 71: 69:

(P+39)h (P+31)h 72: 6A:

(P+3A)h (P+32)h

P artit ion 2 ( Er a s e block Type 1)

2 73: 6B:

(P+3 B ) h (P+ 33 ) h Mi nimu m block er as e cyc les x 100 0 74 : 6C:

(P+3C)h (P+34)h 1 75: 6D:

(P+3D)h (P+35)h 1 76: 6E:

(P+36)h Partition Region 2 Erase Block Type 2 Information 4 6F:

(P+37)h bits 0–15 = y, y+1 = number of identical-size erase blocks 70:

(P +38)h bit s 16–31 = z , region erase block(s) size are z x 256 bytes 71:

(P+39)h 72:

(P+3A)h Par titio n 2 (E ras e B l oc k Ty pe 2) 273:

(P+3B)h Minimum block erase cycles x 1000 74:

(P+3C)h 1 75:

(P+3D)h 1 76:

(P+3E)h (P+3E)h Features Space def initions (Reserved for future use) TBD 77: 77:

(P+3F)h (P+3F)h

Res erved for futu re use

Resv'd 78: 78:

Part it ion 2 (Erase Bl ock Ty pe 2) bits per cell

bits 0– 3 = bits pe r ce ll i n eras e r eg i o n

bi t 4 = reserved for “internal ECC used” (1=yes, 0=no)

bits 5–7 = reserved for future use

Partition 2 (Erase block Type 2) pagemode and synchronous

mode capabilities as defined in Table 10.

bit 0 = page-mode host reads permitted (1=yes, 0=no)

bi t 1 = synchronous host reads permitted (1=yes, 0=no)

bi t 2 = synchronous host writes permitted (1=yes, 0=no )

bits 3–7 = reserved for future use

Simult aneous program or era se operati ons allowed in other

partitio ns whil e a pa rtition in th is reg io n is in Eras e m od e

bits 0– 3 = num ber of sim ultaneous P r o gr a m oper a t i ons

bits 4– 7 = num ber of sim ultaneous E r a s e oper a t i ons

Ty pes of era se block regio ns in this Partitio n Region.

x = 0 = no er ase blo cking; the Partitio n Region era ses in bulk

x = number of erase block regions w/ contiguous sam e-size

erase blocks. Symmetrica lly blocked par ti tions have one

bl ocking region. Partition size = (Type 1 blocks)x(Type 1

block size s) + (Type 2 blocks)x (Type 2 block siz es) +…+

(Typ e n blocks)x(T ype n block sizes)

P artit ion 2 ( Er a s e block Type 1) bits per c ell

bits 0– 3 = bits pe r ce ll i n eras e r eg i o n

bi t 4 = reserved for “internal ECC used” (1=yes, 0=no)

bi ts 5– 7 = reserve for futu re use

Partition 2 (erase block Type 1) pagemode and synchronous

mode capabilities as defined in Table 10.

bit 0 = page-mode host reads permitted (1=yes, 0=no)

bi t 1 = synchronous host reads permitted (1=yes, 0=no)

bi t 2 = synchronous host writes permitted (1=yes, 0=no)

bits 3–7 = reserved for future use

Simult aneous program or era se operati ons allowed in other

partitio ns whil e a pa rtition in th is reg io n is in Prog ram mod e

bits 0– 3 = num ber of sim ultaneous P r o gr a m oper a t i ons

bits 4– 7 = num ber of sim ultaneous E r a s e oper a t i ons

Nu m ber of pro gram or er a s e oper a t i ons allow ed i n a pa r tit ion

bits 0– 3 = num ber of sim ultaneous P r o gr a m oper a t i ons

bits 4– 7 = num ber of sim ultaneous E r a s e oper a t i ons

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

102 Order Numbe r: 290702, Revision: 011

Tab le 45. Pa rtition and Erase-Block Reg ion Information

Notes:

1. The P variable is a pointer which is d efined at C FI offset 15h.

2. TPD - Top parameter device.

BPD - Bottom parameter device.

3. Partit ion: Ea ch pa r tition is 4 Mb in size. It can contain main blocks OR a combina ti on of both m ain and

parameter blocks.

4. Parti tion Re gion : Sym m et rical par ti tions for m a par tit ion r eg ion.

— Partition re gion A. conta ins all partitions that are made up of ma in blocks only.

— Partition region B. contains the partition that is made up of the parameter and the main blocks.

Address

32 Mbit

–B

–T

–B

–T

–B

–T

52: --02 --02 --02 --02 --02 --02

53: --01 --07 --01 --0F --01 --1F

54: --00 --00 --00 --00 --00 --00

55: --11 --11 --11 --11 --11 --11

56: --00 --00 --00 --00 --00 --00

57: --00 --00 --00 --00 --00 --00

58: --02 --01 --02 --01 --02 --01

59: --07 --07 --07 --07 --07 --07

5A: --00 --00 --00 --00 --00 --00

5B: --20 --00 --20 --00 --20 --00

5C: --00 --01 --00 --01 --00 --01

5D: --64 --64 --64 --64 --64 --64

5E: --00 --00 --00 --00 --00 --00

5F: --01 --01 --01 --01 --01 --01

60: --03 --03 --03 --03 --03 --03

61: --06 --01 --06 --01 --06 --01

62: --00 --00 --00 --00 --00 --00

63: --00 --11 --00 --11 --00 --11

64: --01 --00 --01 --00 --01 --00

65: --64 --00 --64 --00 --64 --00

66: --00 --02 --00 --02 --00 --02

67: --01 --06 --01 --06 --01 --06

68: --03 --00 --03 --00 --03 --00

69: --07 --00 --0F --00 --1F --00

6A: --00 --01 --00 --01 --00 --01

6B: --11 --64 --11 --64 --11 --64

6C: --00 --00 --00 --00 --00 --00

6D: --00 --01 --00 --01 --00 --01

6E: --01 --03 --01 --03 --01 --03

6F: --07 --07 --07 --07 --07 --07

70: --00 --00 --00 --00 --00 --00

71: --00 --20 --00 --20 --00 --20

72: --01 --00 --01 --00 --01 --00

73: --64 --64 --64 --64 --64 --64

74: --00 --00 --00 --00 --00 --00

75: --01 --01 --01 --01 --01 --01

76: --03 --03 --03 --03 --03 --03

64Mbit 128Mbit

28F640W30, 28F320W30, 28F128W30

Datasheet Intel® Wireless Flash Memory (W30) June 2005

Order Number : 2907 02, Revision: 011 1 03

Appen dix C Ordering Informati on

Figure 42. VF BGA Ordering Information

Fig ure 43. SCS P Or deri ng Info rm ati on

ackage:

E = VF BGA, Leaded

P r oduct Line Des i gnator:

For all Intel Flash Products

Device Density:

20 = 32Mbit

40 = 64Mbit

28 = 128Mbit

Pr od uct F am i ly:

W30 = Intel

Wire less Flas

Memory with 3 Volt I/O

Parameter Location:

T = Top Parameter

B = Bottom Parameter

Pro ces s Id ent ifier:

D = 0.13

Access S peed (ns)

(70,85)

G E 2 8 F 6 4 0 W 3 0 T D 7 0

H = VF BGA, Pb-Free

Package:

R D = SC S P, Leaded

PF = S CSP, Pb-Free

Product Line:

48 F = F lash Only

Fl ash D ensity:

= No die

= 64 Mbit

= 128 Mbit

Product Fami ly Desi gnato r:

= Inte l

W ire l e ss F l ash M emo ry

Voltage:

Z = 3 V olt I/ O

Ba llou t I ndicator:

Q= QUAD+

Pa ram e ter Loc a tio

T = Top Parameter

B = Bottom Parameter

D evice Details:

0 = Initial Version

Flash 1 &

Flash 3 &

Flash 1

Flash 2

Flash 3

Flash 4

P F 4 8 F 2 0 0 0 W 0 Z B Q 0

= 32 Mbit

28F640W30, 28F320W30, 28F128W30

June 2005 Intel® Wirel es s Flas h Memor y (W30) Datasheet

104 Order Numbe r: 290702, Revision: 011

Tab le 46. W30 Flash Memor y Fami ly: Available Prod uct Ord ering Inform ation

I/O

Voltage

(V) Flash Density Package

Size (mm) Ballout

Name Ballout

Type Part Number

3.0

32 Mbit 9x7.7x1.0 VF BGA Leaded

GE28F320W30BD70

GE28F320W30TD70

GE28F320W30BD85

GE28F320W30TD85

Lead Free PH28F320W30BD70

PH28F320W30TD70

10x8x1.2 SCSP Lead Free PF48F1000W0ZBQ0

PF48F1000W0ZTQ0

64 Mbit

9x7.7x1.0 VF BGA Leaded GE28F640W30BD70

GE28F640W30TD70

Lead Free PH28F640W30BD70

PH28F640W30TD70

10x8x1.2 SCSP Lead Free PF48F2000W0ZBQ0

PF48F2000W0ZTQ0

128 M bit 9x11x1.0 VF BGA Leaded GE28F128W30BD70

GE28F128W30TD70

10x8x1.2 SCSP Leaded RD48F3000W0ZBQ0

RD48F3000W0ZTQ0