Intel(R) Wireless Flash Memory (W30) 28F640W30, 28F320W30, 28F128W30 Datasheet Product Features High Performance Read-While-Write/Erase -- Burst Frequency at 40 MHz -- 70 ns Initial Access Speed -- 25 ns Page-Mode Read Speed -- 20 ns Burst-Mode Read Speed -- Burst-Mode and Page-Mode in All Blocks and across All Partition Boundaries -- Burst Suspend Feature -- Enhanced Factory Programming: 3.5 s per Word Program Time -- Programmable WAIT Signal Polarity Flash Power -- VCC = 1.70 V - 1.90 V -- VCCQ = 2.20 V - 3.30 V -- Standby Current (130 nm) = 8 A (typ.) -- Read Current = 7 mA (4 word burst, typical) Flash Software -- 5 s/9 s (typ.) Program/Erase Suspend Latency Time -- Intel(R) Flash Data Integrator (FDI) and Common Flash Interface (CFI) Compatible Quality and Reliability -- Operating Temperature: -40 C to +85 C -- 100K Minimum Erase Cycles -- 130 nm ETOXTM VIII Process -- 180 nm ETOXTM VII Process Flash Architecture -- Multiple 4-Mbit Partitions -- Dual Operation: RWW or RWE -- Parameter Block Size = 4-Kword -- Main block size = 32-Kword -- Top or Bottom Parameter Blocks Flash Security -- 128-bit Protection Register: 64 Unique Device Identifier Bits; 64 User OTP Protection Register Bits -- Absolute Write Protection with VPP at Ground -- Program and Erase Lockout during Power Transitions -- Individual and Instantaneous Block Locking/Unlocking with Lock-Down Density and Packaging -- 130 nm: 32Mb, 64Mb, and 128Mb in VF BGA Package; 64Mb, 128Mb in QUAD+ Package -- 180 nm: 32Mb and 128Mb Densities in VF BGA Package; 64Mb Density in BGA* Package -- 56 Active Ball Matrix, 0.75 mm Ball-Pitch -- 16-bit Data Bus The Intel(R) Wireless Flash Memory (W30) device combines state-of-the-art Intel(R) Flash technology to provide a versatile memory solution for high performance, low power, board constraint memory applications. The W30 flash memory device offers a multi-partition, dual-operation flash architecture that enables the flash device to read from one partition while programming or erasing in another partition. This Read-While-Write or Read-While-Erase capability makes it possible to achieve higher data throughput rates compared to single partition devices. Two processors can interleave code execution, because program and erase operations can now occur as background processes. The W30 flash memory device incorporates an Enhanced Factory Programming (EFP) mode to improve 12 V factory programming performance. This feature helps eliminate manufacturing bottlenecks associated with programming high-density flash memory devices. The EFP program time is 3.5 s per word, compared to the standard factory program time of 8.0 s per word, so EFP mode saves significant factory programming time for improved factory efficiency. The W30 flash memory device also includes block lock-down and programmable WAIT signal polarity, and is supported by an array of software tools. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number: 290702, Revision: 011 June 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL (R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) Wireless Flash Memory (W30) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Intel, ETOX, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2005, Intel Corporation.All rights reserved. June 2005 2 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Contents 1.0 Introduction ............................................................................................................................... 8 1.1 1.2 1.3 Document Purpose ............................................................................................................... 8 Nomenclature ....................................................................................................................... 8 Conventions .......................................................................................................................... 9 2.0 Functional Overview ............................................................................................................ 10 2.1 2.2 Overview ............................................................................................................................. 10 Memory Map and Partitioning ............................................................................................. 11 3.0 Package Information ............................................................................................................ 14 3.1 3.2 W30 Flash Memory Device - 130 nm Lithography ............................................................. 14 W30 Flash Memory Device - 180 nm Lithography ............................................................. 16 4.0 Ballout and Signal Descriptions...................................................................................... 19 4.1 4.2 Signal Ballout ......................................................................................................................19 Signal Descriptions ............................................................................................................. 21 5.0 Maximum Ratings and Operating Conditions ...........................................................25 5.1 5.2 Absolute Maximum Ratings ................................................................................................ 25 Operating Conditions .......................................................................................................... 26 6.0 Electrical Specifications ..................................................................................................... 27 6.1 6.2 DC Current Characteristics .................................................................................................27 DC Voltage Characteristics.................................................................................................28 7.0 AC Characteristics ................................................................................................................ 29 7.1 7.2 7.3 7.4 Read Operations - 130 nm Lithography..............................................................................29 Read Operations - 180 nm Lithography..............................................................................30 AC Write Characteristics..................................................................................................... 40 Erase and Program Times .................................................................................................. 44 8.0 Power and Reset Specifications .....................................................................................45 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Active Power ....................................................................................................................... 45 Automatic Power Savings (APS) ........................................................................................ 45 Standby Power ................................................................................................................... 45 Power-Up/Down Characteristics ......................................................................................... 46 8.4.1 System Reset and RST# ....................................................................................... 46 8.4.2 VCC, VPP, and RST# Transitions .........................................................................46 Power Supply Decoupling................................................................................................... 46 Reset Specifications ........................................................................................................... 47 AC I/O Test Conditions ....................................................................................................... 48 Flash Device Capacitance .................................................................................................. 49 9.0 Flash Device Operations .................................................................................................... 50 9.1 Datasheet Bus Operations ................................................................................................................... 50 9.1.1 Read ......................................................................................................................50 9.1.2 Burst Suspend ....................................................................................................... 51 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 3 28F640W30, 28F320W30, 28F128W30 9.2 9.3 9.1.3 Standby.................................................................................................................. 51 9.1.4 Reset ..................................................................................................................... 52 9.1.5 Write ...................................................................................................................... 52 Flash Device Commands.................................................................................................... 52 Command Sequencing ....................................................................................................... 56 10.0 Read Operations .................................................................................................................... 57 10.1 10.2 10.3 10.4 10.5 Read Array.......................................................................................................................... 57 Read Device ID................................................................................................................... 57 Read Query (CFI) ............................................................................................................... 58 Read Status Register.......................................................................................................... 58 Clear Status Register.......................................................................................................... 60 11.0 Program Operations ............................................................................................................. 61 11.1 11.2 11.3 Word Program .................................................................................................................... 61 Factory Programming ......................................................................................................... 63 Enhanced Factory Program (EFP) ..................................................................................... 63 11.3.1 EFP Requirements and Considerations ................................................................ 64 11.3.2 Setup ..................................................................................................................... 64 11.3.3 Program ................................................................................................................. 64 11.3.4 Verify...................................................................................................................... 65 11.3.5 Exit......................................................................................................................... 65 12.0 Program and Erase Operations ....................................................................................... 67 12.1 12.2 12.3 Program/Erase Suspend and Resume ............................................................................... 67 Block Erase......................................................................................................................... 70 Read-While-Write and Read-While-Erase .......................................................................... 72 13.0 Security Modes....................................................................................................................... 73 13.1 13.2 13.3 Block Lock Operations........................................................................................................ 73 13.1.1 Lock ....................................................................................................................... 74 13.1.2 Unlock.................................................................................................................... 74 13.1.3 Lock-Down............................................................................................................. 75 13.1.4 Block Lock Status .................................................................................................. 75 13.1.5 Lock During Erase Suspend .................................................................................. 76 13.1.6 Status Register Error Checking ............................................................................. 76 13.1.7 WP# Lock-Down Control ....................................................................................... 76 Protection Register ............................................................................................................. 77 13.2.1 Reading the Protection Register............................................................................ 78 13.2.2 Programing the Protection Register....................................................................... 78 13.2.3 Locking the Protection Register............................................................................. 78 VPP Protection ................................................................................................................... 80 14.0 Set Read Configuration Register .................................................................................... 81 14.1 14.2 14.3 14.4 14.5 14.6 June 2005 4 Read Mode (RCR[15]) ........................................................................................................ 83 First Access Latency Count (RCR[13:11]).......................................................................... 83 14.2.1 Latency Count Settings.......................................................................................... 84 WAIT Signal Polarity (RCR[10]).......................................................................................... 85 WAIT Signal Function ......................................................................................................... 85 Data Hold (RCR[9])............................................................................................................. 86 WAIT Delay (RCR[8]) ......................................................................................................... 87 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 14.7 14.8 14.9 14.10 Burst Sequence (RCR[7]) ................................................................................................... 87 Clock Edge (RCR[6]) .......................................................................................................... 88 Burst Wrap (RCR[3])........................................................................................................... 89 Burst Length (RCR[2:0]) ..................................................................................................... 89 Appendix A Write State Machine ........................................................................................... 90 Appendix B Common Flash Interface.................................................................................. 93 Appendix C Ordering Information....................................................................................... 103 Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 5 28F640W30, 28F320W30, 28F128W30 Revision History Date of Revision Version 09/19/00 -001 Description Initial release 28F3208W30 product references removed (product was discontinued) 28F640W30 product added Revised Table 2, Signal Descriptions (DQ15-0, ADV#, WAIT, S-UB#, S-LB#, VCCQ) Revised Section 3.1, Bus Operations Revised Table 5, Command Bus Definitions, Notes 1 and 2 Revised Section 4.2.2, First Latency Count (LC2-0); revised Figure 6, Data Output with LC Setting at Code 3; added Figure 7, First Access Latency Configuration Revised Section 4.2.3, WAIT Signal Polarity (WT) Added Section 4.2.4, WAIT Signal Function Revised Section 4.2.5, Data Output Configuration (DOC) Added Figure 8, Data Output Configuration with WAIT Signal Delay Revised Table 13, Status Register DWS and PWS Description Revised entire Section 5.0, Program and Erase Voltages Revised entire Section 5.3, Enhanced Factory Programming (EFP) 03/14/01 -002 Revised entire Section 8.0, Flash Security Modes Revised entire Section 9.0, Flash Protection Register; added Table 15, Simultaneous Operations Allowed with the Protection Register Revised Section 10.1, Power-Up/Down Characteristics Revised Section 11.3, DC Characteristics. Changed ICCS,ICCWS, ICCES Specs from 18 A to 21A; changed ICCR Spec from 12 mA to 15 mA (burst length = 4) Added Figure 20, WAIT Signal in Synchronous Non-Read Array Operation Waveform Added Figure 21, WAIT Signal in Asynchronous Page-Mode Read Operation Waveform Added Figure 22, WAIT Signal in Asynchronous Single-Word Read Operation Waveform Revised Figure 23, Write Waveform Revised Section 12.4, Reset Operations Clarified Section 13.2, SRAM Write Operation, Note 2 Revised Section 14.0, Ordering Information Minor text edits Deleted SRAM Section Added 128M DC and AC Specifications 04/05/02 -003 Added Burst Suspend Added Read While Write Transition Waveforms Various text edits Revised Device ID 04/24/02 -004 Revised Write Speed Bin Various text edits Added Latency Count Tables 10/20/02 -005 Updated Packing Ball-Out and Dimension Various text edits Minor text clarifications June 2005 6 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Date of Revision Version Description Revised Table 20, DC Current Characteristics, ICCS Revised Table 20, DC Current Characteristics, ICCAPS 01/14/03 -006 Removed Intel Burst order Minor text edits Updated Package Drawing and Dimensions Revised Table 22, Read Operations, tAPA 03/22/03 -007 Added note to table 15, Configuration Register Descriptions Added note to section 3.1.1, Read Updated Block Lock Operations (Sect. 7.1 and Fig. 11) 11/17/03 -008 Updated improved AC timings Added QUAD+ package option, and Appendix D Minor text edits including new product-naming conventions 05/06/04 -009 05/17/04 -010 06/2005 -011 Corrected Absolute Maximum Rating for VCCQ (Sect. 10.1, Table 18) Minor text edits Restructured the datasheet according to new layout. Timing Diagram Nomenclature Synergy with other product families Added Ordering information Minor Text Edits Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 7 28F640W30, 28F320W30, 28F128W30 1.0 Introduction 1.1 Document Purpose This datasheet contains information about the Intel(R) Wireless Flash Memory (W30) device family. Throughout this document, this device family is referred to as the W30 flash memory device. * * * * * This chapter provides a flash memory overview. Chapter 2.0 through Chapter 8.0 describe the memory functionality. Chapter 6.0 describes the electrical specifications for extended temperature product offerings. Appendix A describes the Write State Machine (WSM), Appendix B describes the Intel(R) Common Flash Interface (CFI) as it applies to the W30 flash memory device. * Appendix C provides ordering information for the Intel(R) Wireless Flash Memory (W30) device family. 1.2 Nomenclature Acronyms that describe product features or usage are defined here: * * * * * * * * * * * * * * * * * June 2005 8 APS - Automatic Power Savings BBA - Block Base Address CFI - Common Flash Interface CUI - Command User Interface DU - Do not Use EFP - Enhanced Factory Programming FDI - Flash Data Integrator NC - No Connect OTP - One-Time Programmable PBA - Partition Base Address RCR - Read Configuration Register RWE - Read-While-Erase RWW - Read-While-Write SCSP - Stacked Chip Scale Package SRD - Status Register Data VF BGA - Very-thin, Fine-pitch, Ball Grid Array WSM - Write State Machine Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 1.3 Conventions The following abbreviated terms and phrases are used throughout this document: * * * * 1.8 V refers to the VCC operating voltage range of 1.7 V - 1.9 V (except where noted). 3.0 V refers to the VCCQ operating voltage range of 2.2 V - 3.3 V. VPP = 12 V refers to 12 V 5%. When referring to registers, the term set means the bit is a logical 1, and cleared means the bit is a logical 0. * The terms pin and signal are often used interchangeably to refer to the external signal connections on the package. (Ball is the term used for BGA). * A word is 2 bytes, or 16 bits. * Signal names are in all CAPS (for example, WAIT). * Voltage applied to the signal is subscripted (for example, VPP). Throughout this document, references are made to top, bottom, parameter, and partition. To clarify these references, the following conventions have been adopted: * A block is a group of bits (or words) that erase simultaneously with one block erase instruction. * * * * A main block contains 32 Kwords. A parameter block contains 4 Kwords. The Block Base Address (BBA) is the first address of a block. A partition is a group of blocks that share erase and program circuitry and a common status register. * The Partition Base Address (PBA) is the first address of a partition. For example, on a 32-Mbit top-parameter flash device, partition number 5 has a PBA of 0x140000. * The top partition is located at the highest physical flash device address. This partition can be a main partition or a parameter partition. * The bottom partition is located at the lowest physical flash device address. This partition can be a main partition or a parameter partition. * A main partition contains only main blocks. * A parameter partition contains a mixture of main blocks and parameter blocks. * A top parameter device (TPD) has the parameter partition at the top of the memory map with the parameter blocks at the top of that partition. This flash device type was formerly referred to as a top-boot flash device. * A bottom parameter device (BPD) has the parameter partition at the bottom of the memory map with the parameter blocks at the bottom of that partition. This flash device type was formerly referred to as a bottom-boot block flash device. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 9 28F640W30, 28F320W30, 28F128W30 2.0 Functional Overview This section provides an overview of the W30 flash memory device features and architecture. 2.1 Overview The W30 flash memory device provides Read-While-Write (RWW) and Read-White-Erase (RWE) capability. This capability provides high-performance synchronous and asynchronous reads in package-compatible densities using a 16-bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4-Kword parameter blocks are located in the parameter partition at either the top or bottom of the memory map. The rest of the memory array is grouped into 32-Kword main blocks. The memory architecture for the W30 flash memory device consists of multiple 4-Mbit partitions, the exact number depending on the flash device density. By dividing the memory array into partitions, program or erase operations can take place simultaneously during read operations. Burst reads can traverse partition boundaries, but user application code is responsible for ensuring that burst reads do not extend into a partition that is actively programming or erasing. Although each partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in a read mode. Augmented erase-suspend functionality further enhances the RWW capabilities of the W30 flash memory device. An erase can be suspended to perform a program or read operation within any block, except a block that is erase-suspended. A program operation nested within a suspended erase can subsequently be suspended to read yet another memory location. After power-up or reset, the W30 flash memory device defaults to asynchronous read configuration. Writing to the flash memory device Read Configuration Register (RCR) enables synchronous burst-mode read operation. In synchronous mode, the CLK input increments an internal burst address generator. CLK also synchronizes the flash memory device with the host CPU and outputs data on every, or on every other, valid CLK cycle after an initial latency. A programmable WAIT output signals to the CPU when data from the flash memory device is ready. In addition to its improved architecture and interface, the W30 flash memory device incorporates Enhanced Factory Programming (EFP), a feature that enables fast programming and low-power designs. The EFP feature provides fast program performance, which can increase the manufacturing throughput of a factory. The W30 flash memory device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V. With the 1.8-V option, VCC and VPP can be tied together for an ultra-low-power design. In addition to voltage flexibility, the dedicated VPP input provides extensive data protection when VPP < VPPLK. A 128-bit protection register can implement new security techniques and data protection schemes: * A combination of factory-programmed and user-OTP data cells provide unique flash device identification, help implement fraud or cloning prevention schemes, or help protect content. * Zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. * An additional block lock-down capability provides hardware protection where software commands alone cannot change the block protection status. June 2005 10 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 The flash device Command User Interface (CUI) links the system processor to the internal flash memory operation. A valid command sequence written to the CUI initiates the flash device Write State Machine (WSM) operation, which automatically executes the algorithms, timings, and verifications necessary to manage flash memory program and erase. An internal status register provides ready/busy indication results of the operation (success, fail, and so on). Three power-saving features- Automatic Power Savings (APS), standby, and RST#- can significantly reduce power consumption. * The flash device automatically enters APS mode following read cycle completion. * Standby mode begins when the system deselects the flash memory by de-asserting CE#. * Driving RST# low produces power savings similar to standby mode. It also resets the part to read-array mode (important for system-level reset), clears internal status registers, and provides an additional level of flash device write protection. 2.2 Memory Map and Partitioning The W30 flash memory device is divided into 4-Mbit physical partitions. This partitioning allows simultaneous RWW or RWE operations, and enables users to segment code and data areas on 4-Mbit boundaries. The flash memory array is asymmetrically blocked, which enables system code and data integration within a single flash device. Each block can be erased independently in block erase mode. Simultaneous program and erase operations are not allowed; only one partition at a time can be actively programming or erasing. See Table 1, "Bottom Parameter Memory Map" on page 12 and Table 2, "Top Parameter Memory Map" on page 13. * The 32-Mbit flash device has eight partitions. * The 64-Mbit flash device has 16 partitions. * The 128-Mbit flash device has 32 partitions. Each flash device density contains one parameter partition and several main partitions. The 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks. The bulk of the flash memory array is divided into main blocks that can store code or data, and parameter blocks that allow storage of frequently updated small parameters that are normally stored in EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. . Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 11 28F640W30, 28F320W30, 28F128W30 Table 1. Bottom Parameter Memory Map June 2005 12 64 Mbit Blk # 128 Mbit 32 262 7F8000-7FFFFF .. . Blk # .. . 32 Mbit .. . Blk # 32 135 400000-407FFF 3F8000-3FFFFF 134 3F8000-3FFFFF .. . .. . .. . .. . 134 .. . 32 32 71 200000-207FFF 71 200000-207FFF 1F8000-1FFFFF 70 1F8000-1FFFFF 70 1F8000-1FFFFF .. . 100000-107FFF 32 38 0F8000-0FFFFF 38 0F8000-0FFFFF 38 0F8000-0FFFFF 0C0000-0C7FFF 32 30 0B8000-0BFFFF 30 0B8000-0BFFFF 30 0B8000-0BFFFF 32 22 078000-07FFFF 22 078000-07FFFF 22 078000-07FFFF 038000-03FFFF 14 038000-03FFFF .. . 14 32 8 008000-00FFFF 8 008000-00FFFF 8 008000-00FFFF 4 7 007000-007FFF 7 007000-007FFF 7 007000-007FFF .. . 038000-03FFFF .. . 14 .. . 32 .. . 040000-047FFF .. . 15 .. . 040000-047FFF .. . 15 .. . 040000-047FFF .. . 15 .. . 32 .. . .. . 080000-087FFF .. . 23 .. . 080000-087FFF .. . 23 .. . 080000-087FFF .. . 23 .. . 32 .. . .. . 31 .. . 0C0000-0C7FFF .. . 31 .. . 0C0000-0C7FFF .. . 31 .. . 32 .. . .. . .. . 39 .. . .. . 100000-107FFF .. . .. . 39 .. . .. . 100000-107FFF .. . 39 .. . 32 .. . .. . 70 .. . 32 .. . Four Partitions One Partition One Partition Parameter Partition One Partition One Partition Main Partitions Eight Partitions Sixteen Partitions Size (KW) 4 0 000000-000FFF 0 000000-000FFF 0 000000-000FFF Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Top Parameter Memory Map 4 70 1FF000-1FFFFF 134 3FF000-3FFFFF 262 7FF000-7FFFFF 7F8000-7F8FFF 254 7F0000-7F7FFF 7C0000-7C7FFF 32 55 1B8000-1BFFFF 119 3B8000-3BFFFF 247 7B8000-7BFFFF 780000-787FFF 32 47 178000-17FFFF 111 378000-37FFFF 239 778000-77FFFF 39 138000-13FFFF 103 338000-33FFFF 231 738000-73FFFF 700000-707FFF 32 31 0F8000-0FFFFF 95 2F8000-2FFFFF 223 6F8000-6FFFFF 32 0 600000-607FFF 32 63 1F8000-1FFFFF 191 5F8000-5FFFFF 32 0 .. . 192 000000-007FFF 128 400000-407FFF 32 127 3F8000-3FFFFF .. . 200000-207FFF .. . 64 .. . 000000-007FFF .. . .. . 224 .. . 300000-307FFF .. . 96 .. . 100000-107FFF .. . 32 .. . 32 .. . .. . 32 .. . 740000-747FFF .. . 232 .. . 340000-347FFF .. . 104 .. . 140000-147FFF .. . 40 .. . 32 .. . .. . 240 .. . 380000-387FFF .. . 112 .. . 18000-187FFF .. . 48 .. . 32 .. . .. . 248 .. . 3C0000-3C7FFF .. . 120 .. . 1C0000-1C7FFF .. . 56 .. . 32 .. . .. . 255 3F0000-3F7FFF .. . 3F8000-3F8FFF 126 .. . 127 1F0000-1F7FFF .. . 1F8000-1F8FFF 62 .. . 63 .. . 4 32 .. . .. . 128 Mbit .. . Blk # .. . 64 Mbit .. . Blk # .. . 32 Mbit .. . Blk # .. . Size (KW) .. . One Partition One Partition Four Partitions Sixteen Partitions Eight Partitions Main Partitions One Partition One Partition Parameter Partition Table 2. 32 0 000000-007FFF Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 13 28F640W30, 28F320W30, 28F128W30 3.0 Package Information 3.1 W30 Flash Memory Device - 130 nm Lithography Figure 1. 32 Mb, 64 Mb, and 128 Mb VF BGA Package Drawing B a ll A 1 Co rner B a ll A 1 Co rner S1 D 1 E 2 3 4 5 6 7 8 8 A A B B C C D D E E F F G G 7 6 5 4 3 2 S2 1 e b Top V iew - Bum p S ide D own Bottom Vie w - Ba ll Sid e Up A1 A2 A S eatin g Y P lan e Table 3. 2 Mb, 64 Mb, and 128 Mb VF BGA Package Specifications Millimeters Dimension Inches Symbol Min Nom Max Min Nom Max Package Height A - - 1.000 - - 0.0394 Ball Height A1 0.150 - - 0.0059 - - Package Body Thickness A2 - 0.665 - - 0.0262 - Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Width (32 Mb, 64 Mb) D 7.600 7.700 7.800 0.2992 0.3031 0.3071 Package Body Width (128 Mb) D 10.900 11.000 11.100 0.4291 0.4331 0.4370 Package Body Length (32 Mb, 64 Mb, 128 Mb) E 8.900 9.000 9.100 0.3504 0.3543 0.3583 Pitch [e] - 0.750 - - 0.0295 - Ball (Lead) Count N - 56 - - 56 - Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along D (32 Mb, 64 Mb) S1 1.125 1.225 1.325 0.0443 0.0482 0.0522 Corner to Ball A1 Distance Along D (128 Mb) S1 2.775 2.2875 2.975 0.1093 0.1132 0.1171 Corner to Ball A1 Distance Along E (32 Mb, 64 Mb,128 Mb) S2 2.150 2.250 2.350 0.0846 0.0886 0.0925 June 2005 14 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 2. 32Mb, 64Mb and 128Mb QUAD+ Package Drawing S1 A1 Index Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F D F G G H H J J K K L L M M e b E Bottom View - Ball Up Top View - Ball Down A2 A1 A Y Drawing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Datasheet Symbol A A1 A2 b D E e N Y S1 S2 Min Millimeters Nom Max 1.200 0.200 0.325 9.900 7.900 1.100 0.500 Notes Min Inches Nom Max 0.0472 0.0079 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 0.425 10.100 8.100 0.0128 0.3898 0.3110 0.100 1.300 0.700 0.0433 0.0197 0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236 0.0167 0.3976 0.3189 0.0039 0.0512 0.0276 June 2005 15 28F640W30, 28F320W30, 28F128W30 3.2 W30 Flash Memory Device - 180 nm Lithography Figure 3. 64Mb BGA* CSP Package Drawing and Dimensions P in # 1 In d ic a to r s1 D 1 2 3 4 5 6 7 P in # 1 C o rn e r s2 8 8 7 6 5 4 3 2 1 A A B B C D C D E E E F F G G e b T o p V ie w - S ilic o n b a ck s id e B o tto m V ie w - B u m p sid e U p C o m p le te In k M a rk N o t A1 A2 A Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E June 2005 16 Y P la n S id e V ie w Symbol A A1 A2 b D E [e] N Y S1 S2 S e a ti Millimeters Min 0.850 0.150 0.612 0.300 7.600 8.900 1.125 2.150 Nom Max 1.000 0.712 0.350 7.700 9.000 0.750 56 0.812 0.400 7.800 9.100 Inches Min 0.0335 0.0059 0.0241 0.0118 0.2992 0.3503 0.100 1.325 2.350 0.0443 0.0846 1.225 2.250 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Notes Nom Max 0.0394 0.0280 0.0138 0.3031 0.3543 0.0295 56 0.0320 0.0157 0.3071 0.3583 0.0482 0.0886 0.0039 0.0522 0.0925 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 4. 32Mb VF BGA Package Drawing Ball A1 Corner Ball A1 Corner S1 D 1 E 2 3 4 5 6 7 8 8 A A B B C C D D E E F F G G 7 6 5 4 3 2 1 S2 e b To p View - Bump Side Down Bottom View - Ball Side Up A1 A2 A S eating Y P lane Side V iew Note: Drawing not to scale Figure 5. 128Mb VF BGA Package Drawing Ball A1 Corner 1 E S1 D 2 3 4 5 6 7 8 9 10 10 A A B B C C D D E E F F G G 9 8 7 6 5 4 3 Ball A1 Corner S2 2 1 e H H J J b Top View - Bump Side Down Bottom View - Ball Side Up A1 A2 A Seating Plane Y Side View Note: Drawing not to scal e Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 17 28F640W30, 28F320W30, 28F128W30 Table 4. 32Mb and 128Mb VF BGA Package Dimensions Millimeters Dimension Inches Symbol Min Nom Max Min Nom Max Package Height A 0.850 - 1.000 0.0335 - 0.0394 Ball Height A1 0.150 - - 0.0059 - - Package Body Thickness A2 0.615 0.665 0.715 0.0242 0.0262 0.0281 Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Width 32Mb D 7.600 7.700 7.800 0.2992 0.3031 0.3071 Package Body Length32Mb E 8.900 9.000 9.100 0.3503 0.3543 0.3583 Package Body Width 128Mb D 12.400 12.500 12.600 0.4882 0.4921 0.4961 Package Body Length 128Mb E 11.900 12.000 12.100 0.4685 0.4724 0.4764 Pitch [e] - 0.750 - - 0.0295 - Ball (Lead) Count 32Mb N - 56 - - 56 - Ball (Lead) Count 128Mb N - 60 - - 60 - Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along D 32Mb S1 1.125 1.225 1.325 0.0443 0.0482 0.0522 Corner to Ball A1 Distance Along E 32Mb S2 2.150 2.250 2.350 0.0846 0.0886 0.0925 Corner to Ball A1 Distance Along D 128Mb S1 2.775 2.875 2.975 0.1093 0.1132 0.1171 Corner to Ball A1 Distance Along E 128Mb S2 2.900 3.000 3.1000 0.1142 0.1181 0.1220 June 2005 18 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 4.0 Ballout and Signal Descriptions 4.1 Signal Ballout The W30 flash memory device is available in the 56-ball VF BGA and BGA Chip Scale Package with 0.75 mm ball pitch, or the QUAD+ SCSP package. Figure 6 shows the VF BGA and BGA package ballout. Figure 7 shows the QUAD+ package ballout. Figure 6. 1 56-Ball VF BGA/ BGA Ballout 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A A11 A8 VSS VCC VPP A18 A6 A4 A4 A6 A18 VPP VCC VSS A8 A11 B B A12 A9 A20 CLK RST# A17 A5 A3 A3 A5 A17 RST# CLK A20 A9 A12 C C A13 A10 A21 ADV# WE# A19 A7 A2 A2 A7 A19 WE# ADV# A21 A10 A13 D D A15 A14 WAIT A16 DQ12 WP# A22 A1 A1 A22 WP# DQ12 A16 WAIT A14 A15 E E VCCQ DQ15 DQ6 DQ4 DQ2 DQ1 CE# A0 A0 CE# DQ1 DQ2 DQ4 DQ6 DQ15 VCCQ F F VSS DQ14 DQ13 DQ11 DQ10 DQ9 DQ0 OE# OE# DQ0 DQ9 DQ10 DQ11 DQ13 DQ14 VSS G G DQ7 VSSQ DQ5 VCC DQ3 VCCQ Top View - Ball Side Down Complete Ink Mark Not Shown DQ8 VSSQ VSSQ DQ8 VCCQ DQ3 VCC DQ5 VSSQ DQ7 Bottom View - Ball Side Up Notes: 1. On lower density flash memory devices, the upper address balls can be treated as NC. (that is, on 32-Mbit density, A22 and A21 are NC). 2. See Appendix C, "Ordering Information" on page 103 for mechanical specifications for the package. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 19 28F640W30, 28F320W30, 28F128W30 Figure 7. 88-Ball (80 Active Balls) QUAD+ Ballout A 1 2 3 4 5 DU DU A4 A18 A19 VSS A5 R-LB# A23 VSS A3 A17 A24 F-VPP, F-VPEN A2 A7 A25 F-WP# A1 A6 A0 D8 D2 D10 R-OE# D0 D1 D9 6 7 8 DU DU A21 A11 A22 A12 A9 A13 B F1-VCC F2-VCC C S-CS2 CLK D R-WE# P1-CS# E ADV# A20 A10 A15 R-UB# F-RST# F-WE# A8 A14 A16 D5 D13 WAIT F2-CE# D3 D12 D14 D7 F2-OE# D11 D4 D6 D15 VCCQ F G H J S-CS1# F1-OE# K F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode, P-CRE L M VSS VSS DU DU VCCQ F1-VCC VSS VSS VSS VSS DU DU Top View - Ball Side Down Legend: Global SRAM/PSRAM specific Flash specific Notes: 1. On lower density flash memory devices, the upper address balls can be treated as NC (that is, on 64-Mb density, A[25:23]are NC) 2. See Appendix C, "Ordering Information" on page 103 for mechanical specifications for the package. June 2005 20 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 4.2 Signal Descriptions * Table 5 describes the signals for the 56-ball VF BGA and BGA Chip Scale Package. * Table 6 describes the signals for the QUAD+ package ballout. Table 5. Signal Descriptions - BGA Package & VF BGA Package (Sheet 1 of 2) Symbol Type A[22:0] Input Name and Function ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0] DATA INPUTS/OUTPUTS: D[15:0] Input/ Output * Inputs data and commands during write cycles. * Outputs data during reads. Data pins are High-Z when the flash device or its outputs are deselected. Data is internally latched during writes. ADV# Input CE# Input ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous read operations, all addresses are latched on the rising edge of ADV#, or the next valid CLK edge with ADV# low, whichever occurs first. CHIP ENABLE: * Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps. * De-asserting CE# deselects the flash device, places it in standby mode, and tri-states all outputs. CLK Input OE# Input CLOCK: CLK synchronizes the flash device to the system bus frequency during synchronous reads and increments an internal address generator. During synchronous read operations, addresses are latched on ADV#'s rising edge or CLK's rising (or falling) edge, whichever occurs first. OUTPUT ENABLE: * When asserted, OE# enables the flash device output data buffers during a read cycle. * When OE# is deasserted, data outputs are placed in a high-impedance state. RST# Input RESET: When low, RST# resets internal automation and inhibits write operations. This reset provides data protection during power transitions. De-asserting RST# enables normal operation and places the flash device in asynchronous read-array mode. WAIT Output WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to be asserted-high or asserted-low, based on bit 10 of the Read Configuration Register. WAIT is tri-stated if CE# is deasserted. WAIT is not gated by OE#. WE# Input WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the rising edge of WE#. WP# Input WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See Section 13.1, "Block Lock Operations" on page 73 for details on block locking. ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Flash memory contents cannot be altered when VPP < VPPLK. Do not attempt block erase and program operations at invalid VPP voltages. VPP Power/ Input Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL min to perform in-system flash device modification. VPP can be 0 V during read operations. VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 12 V might reduce block cycling capability. VCC Power FLASH DEVICE POWER SUPPLY: Writes are inhibited at VCC < VLKO. Do not attempt flash device operations at invalid VCC voltages. VCCQ Power OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. VSS Power GROUND: Pins for all internal flash device circuitry must be connected to system ground. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 21 28F640W30, 28F320W30, 28F128W30 Table 5. Signal Descriptions - BGA Package & VF BGA Package (Sheet 2 of 2) Symbol Type Name and Function VSSQ Power OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal can be tied directly to VSS. DU -- DO NOT USE: Do not use this pin. Do not connect this pin to any power supplies, signals, or other pins; this pin must be floated. NC -- NO CONNECT: No internal connection; can be driven or floated. Table 6. Symbol Signal Descriptions - QUAD+ Package (Sheet 1 of 3) Type Description ADDRESS INPUTS: Inputs for all die addresses during read and write operations. A[MAX:MIN] Input * * * 128-Mbit Die : AMAX = A22 64-Mbit Die : AMAX = A21 32-Mbit Die : AMAX = A20 A0 is the lowest-order 16-bit wide address. A[25:24] denote high-order addresses reserved for future flash device densities. DATA INPUTS/OUTPUTS: DQ[15:0] Input/ Output * Inputs data and commands during write cycles. * Outputs data during read cycles. Data signals float when the flash device or its outputs are deselected. Data are internally latched during writes on the flash device. FLASH CHIP ENABLE: Low-true input. F[3:1]-CE# low selects the associated flash memory die. * When asserted, flash memory internal control logic, input buffers, decoders, and sense amplifiers are active. F[3:1]-CE# Input * When deasserted, the associated flash die is deselected, power is reduced to standby levels, and data and WAIT outputs are placed in high-Z state. * F1-CE# selects or deselects flash die #1. * F2-CE# selects or deselects flash die #2 and is RFU on combinations with only one flash die. * F3-CE# selects or deselects flash die #3 and is RFU on stacked combinations with only one or two flash dies. SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 respectively). S-CS1# S-CS2 * When either/both SRAM Chip Select signals are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. Input * When either/both SRAM Chip Select signals are deasserted, the SRAM is deselected and its power is reduced to standby levels. S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are RFU on stacked combinations without SRAM die. PSRAM CHIP SELECT: Low-true input. * When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. P[2:1]-CS# Input * When deasserted, the PSRAM is deselected and its power is reduced to standby levels. * P1-CS# selects PSRAM die #1 and is available only on stacked combinations with PSRAM die. This ball is an RFU on stacked combinations without PSRAM. * P2-CS# selects PSRAM die #2 and is available only on stacked combinations with two PSRAM dies. This ball is an RFU on stacked combinations without PSRAM or with a single PSRAM. June 2005 22 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Table 6. Symbol Signal Descriptions - QUAD+ Package (Sheet 2 of 3) Type Description FLASH OUTPUT ENABLE: Low-true input. * Fx-OE# low enables the output buffers on the selected flash memory device. F[2:1]-OE# Input * F[2:1]-OE# high disables the output buffers on the selected flash memory device, placing them in High-Z. * F1-OE# controls the outputs of flash die #1. * F2-OE# controls the outputs of flash die #2 and flash die #3. F2-OE# is available on stacked combinations with two or three flash die, and is RFU on stacked combinations with only one flash die. RAM OUTPUT ENABLE: Low-true input. * R-OE# low enables the output buffers on the selected RAM. R-OE# Input * R-OE# high disables the RAM output buffers, and places the selected RAM outputs in High-Z. R-OE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only stacked combinations. FLASH WRITE ENABLE: Low-true input. F-WE# Input F-WE# controls writes to the selected flash die. Address and data are latched on the rising edge of F-WE#. RAM WRITE ENABLE: Low-true input. R-WE# Input R-WE# controls writes to the selected RAM die. R-WE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only stacked combinations. CLOCK: Synchronizes the flash die with the system bus clock in synchronous read mode and increments the internal address generator. CLK Input * During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. * During asynchronous mode read operations, addresses are latched on the rising edge ADV#, or are continuously flow-through when ADV# is kept asserted. WAIT: Output signal. WAIT Output Indicates invalid data during synchronous array or non-array flash memory reads. Read Configuration Register bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is deasserted; WAIT is not gated by F-OE#. * In synchronous array or non-array flash memory read modes, WAIT indicates invalid data when asserted and valid data when deasserted. * In asynchronous flash memory page read, and all flash memory write modes, WAIT is asserted. FLASH WRITE PROTECT: Low-true input. F-WP# enables/disables the lock-down protection mechanism of the selected flash die. F-WP# Input * F-WP# low enables the lock-down mechanism where locked down blocks cannot be unlocked using software commands. * F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked using software commands. ADDRESS VALID: Low-true input. ADV# Input * During synchronous flash memory read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. * During asynchronous flash memory read operations, addresses are latched on the rising edge of ADV#, or are continuously flow-through when ADV# is kept asserted. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 23 28F640W30, 28F320W30, 28F128W30 Table 6. Symbol Signal Descriptions - QUAD+ Package (Sheet 3 of 3) Type Description RAM UPPER / LOWER BYTE ENABLES: Low-true input. During RAM read and write cycles: R-UB# R-LB# Input * R-UB# low enables the RAM high order bytes on D[15:8]. * R-LB# low enables the RAM low-order bytes on D[7:0]. R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die, and are RFU on flash-only stacked combinations. FLASH RESET: Low-true input. F-RST# Input * F-RST# low initializes flash device internal circuitry and disables flash device operations. * F-RST# high enables flash device operation. Exit from reset places the flash device in asynchronous read array mode. P-Mode (PSRAM Mode): Low-true input. P-Mode programs the Configuration Register, and enters/exits the Low Power Mode of the PSRAM die. P-Mode, P-CRE P-Mode is available on stacked combinations with asynchronous-only PSRAM die. Input * P-CRE (PSRAM Configuration Register Enable): High-true input. * P-CRE is high, write operations load the Refresh Control Register or Bus Control Register. * P-CRE applies only on combinations with synchronous PSRAM die. P-Mode, P-CRE is an RFU on stacked combinations without PSRAM die. F-VPP, F-VPEN FLASH PROGRAM AND ERASE POWER: Valid F-V PP voltage on this ball enables flash memory device program/erase operations. Power Flash memory array contents cannot be altered when F-VPP(F-VPEN) < VPPLK (VPENLK). Do not attempt erase / program operations at invalid F-VPP (F-VPEN) voltages. F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP products. FLASH LOGIC POWER: * F1-VCC supplies power to the core logic of flash die #1. * F2-VCC supplies power to the core logic of flash die #2 and flash die #3. F[2:1]-VCC Power Write operations are inhibited when F-VCC < VLKO. Do not attempt flash device operations at invalid F-VCC voltages. F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked combinations with only one flash die. SRAM POWER SUPPLY: Supplies power for SRAM operations. S-VCC Power P-VCC Power P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked combinations without PSRAM die. VCCQ Power FLASH DEVICE I/O POWER: Supply power for the flash device input and output buffers. VSS Power FLASH DEVICE GROUND: Connect to system ground. Do not float any VSS connection. RFU -- RESERVED for FUTURE USE: Reserved for future flash device functionality/ enhancements. Contact Intel regarding the use of balls designated RFU. DU -- DO NOT USE: Do not connect to any other signal, or power supply; must be left floating. S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked combinations without SRAM die. PSRAM POWER SUPPLY: Supplies power for PSRAM operations. June 2005 24 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the flash device beyond the Absolute Maximum Ratings in Table 7 might cause permanent damage. These are stress ratings only. Notice: This datasheet contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Table 7. Absolute Maximum Ratings Parameter Maximum Rating Temperature under Bias -40 C to +85 C Storage Temperature -65 C to +125 C Voltage on Any Pin (except V CC, VCCQ, VPP) -0.5 V to +3.8 V Note VPP Voltage -0.2 V to +14 V VCC Voltage -0.2 V to +2.45 V 1,2,3 1 VCCQ Voltage -0.2 V to +3.8 V 1 Output Short Circuit Current 100 mA 4 Notes: 1. All specified voltages are relative to VSS. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP pins. During transitions, this level might undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins is VCC +0.5 V which, during transitions, might overshoot to VCC +2.0 V for periods < 20 ns. 2. Maximum DC voltage on VPP might overshoot to +14.0 V for periods < 20 ns. 3. VPP program voltage is normally VPPL. VPP can be 12 V 0.6 V for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. 4. Output shorted for no more than one second. No more than one output shorted at a time. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 25 28F640W30, 28F320W30, 28F128W30 5.2 Operating Conditions Do not operate the W30 flash memory device beyond the Operating Conditions in Table 8. Extended exposure beyond these Operating Conditions might affect flash device reliability. Table 8. Extended Temperature Operation Parameter1 Symbol Min Nom Max Unit Notes C - TA Operating Temperature -40 25 85 VCC VCC Supply Voltage 1.7 1.8 1.90 VCCQ I/O Supply Voltage 2.2 3.0 3.3 3 3 V VPPL VPP Voltage Supply (Logic Level) 0.90 1.80 1.95 2 VPPH Factory Programming VPP 11.4 12.0 12.6 2 tPPH Maximum VPP Hours VPP = 12 V - - 80 Main and Parameter Blocks VPP < VCC 100,000 - - Main Blocks VPP = 12 V - - 1000 Parameter Blocks VPP = 12 V - - 2500 Block Erase Cycles Hours 2 2 Cycles 2 2 Notes: 1. See Section 6.1, "DC Current Characteristics" on page 27 and Section 6.2, "DC Voltage Characteristics" on page 28 for specific voltage-range specifications. 2. VPP is normally VPPL. VPP can be connected to 11.4 V-12.6 V for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. 3. Contact your Intel field representative for VCC/VCCQ operations down to 1.65 V. 4. See the tables in Section 6.0, "Electrical Specifications" on page 27 and in Section 7.0, "AC Characteristics" on page 29 for operating characteristics June 2005 26 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 6.0 Electrical Specifications 6.1 DC Current Characteristics Table 9. DC Current Characteristics (Sheet 1 of 2) VCCQ= 3.0 V Parameter (1) Sym ILI Input Load ILO Output Leakage 180 nm ICCS 130 nm ICCS 180 nm ICCAPS Note 9 DQ[15:0] VCC Standby APS Synchronous CLK = 40 MHz 2 2 Unit Test Conditions Typ Max Typ Max - 2 - 2 A VCC = VCC Max VCCQ = VCCQMax VIN = VCCQ or GND - 10 - 10 A VCC = VCC Max VCCQ = VCCQMax VIN = VCCQ or GND 6 21 6 30 A 8 50 8 70 VCC = VCC Max VCCQ = VCCQMax CE# = VCCQ RST# =VCCQ 6 21 6 30 A 8 50 8 70 VCC = VCC Max VCCQ = VCCQMax CE# = VSSQ RST# =VCCQ All other inputs =VCCQ or V SSQ 4 7 4 10 mA 4 Word Read 7 15 7 15 mA Burst length = 4 9 16 9 16 mA Burst length = 8 11 19 11 19 mA Burst length =16 12 22 12 22 mA Burst length = Continuous 18 40 18 40 mA VPP = VPPL, Program in Progress 8 15 8 15 mA VPP = VPPH, Program in Progress 18 40 18 40 mA V PP = VPPL, Block Erase in Progress 8 15 8 15 mA VPP = VPPH, Block Erase in Progress 11 Asynchronous Page Mode f=13 MHz Average VCC Read 128 Mbit 10 130 nm ICCAPS ICCR 32/64 Mbit VCC = VCCMax CE# = VIL OE# = VIH Inputs = VIH or V IL ICCW VCC Program 3,4,5 ICCE VCC Block Erase 3,4,5 ICCWS VCC Program Suspend 6 6 21 6 30 A CE# = VCC, Program Suspended ICCES VCC Erase Suspend 6 6 21 6 30 A CE# = VCC, Erase Suspended 3 0.2 5 0.2 5 A VPP < VCC - 2 15 2 15 A VPP < VCC IPPS VPP Standby (IPPWS, IPPES) VPP Program Suspend IPPR VPP Read VPP Erase Suspend Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 27 28F640W30, 28F320W30, 28F128W30 Table 9. DC Current Characteristics (Sheet 2 of 2) VCCQ= 3.0 V Sym Parameter (1) Note IPPW VPP Program 4 IPPE VPP Erase 4 32/64 Mbit 128 Mbit Typ Max Typ Max 0.05 0.10 0.05 0.10 Unit mA 8 22 16 37 0.05 0.10 0.05 0.10 8 22 8 22 Test Conditions VPP = VPPL, Program in Progress VPP = VPPH, Program in Progress mA VPP = VPPL, Erase in Progress VPP = VPPH, Erase in Progress Notes: 1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25C. 2. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. See ICCRQ specification for details. 3. Sampled, not 100% tested. 4. VCC read + program current is the sum of VCC read and VCC program currents. 5. VCC read + erase current is the sum of VCC read and VCC erase currents. 6. ICCES is specified with the flash device deselected. If the flash device is read while in erase suspend, the current is ICCES plus ICCR. 7. VPP < VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges. 8. VIL can undershoot to -0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less. 9. If VIN>VCC the input load current increases to 10 A max. 10. ICCS is the average current measured over any 5ms time interval 5 s after a CE# de-assertion. 11. Refer to section Section 8.2, "Automatic Power Savings (APS)" on page 45 for ICCAPS measurement details. 6.2 DC Voltage Characteristics Table 10. DC Voltage Characteristics VCCQ= 3.0 V Sym Note 32/64 Mbit 128 Mbit Unit Min Max Min Max Test Conditions V IL Input Low 8 0 0.4 0 0.4 V VIH Input High - VCCQ - 0.4 VCCQ VCCQ - 0.4 VCCQ V VOL Output Low - - 0.1 - 0.1 V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VOH Output High - VCCQ - 0.1 - VCCQ - 0.1 - V VCC = VCCMin VCCQ = VCCQMin IOH = -100 A VPPLK VPP Lock-Out 7 - 0.4 - 0.4 V VLKO VCC Lock - 1.0 - 1.0 - V VILKOQ VCCQ Lock - 0.9 - 0.9 - V Note: June 2005 28 Parameter (1) For all numbered note references in this table, refer to the notes in Table 9, "DC Current Characteristics" on page 27. Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 7.0 AC Characteristics 7.1 Read Operations - 130 nm Lithography Table 11. Read Operations - 130 nm Lithography (Sheet 1 of 2) 32-Mbit 64-Mbit # Sym Parameter 128-Mbit 1 -70 -85 -70 Units Notes Min Max Min Max Min Max 70 - 85 - 70 - ns 6 Asynchronous Specifications R1 tAVAV Read Cycle Time R2 tAVQV Address to Output Valid - 70 - 85 - 70 ns 6 R3 tELQV CE# Low to Output Valid - 70 - 85 - 70 ns 6 R4 tGLQV OE# Low to Output Valid - 30 - 30 - 30 ns 3 R5 tPHQV RST# High to Output Valid - 150 - 150 - 150 ns - R6 tELQX CE# Low to Output Low-Z 0 - 0 - 0 - ns 4 R7 tGLQX OE# Low to Output Low-Z 0 - 0 - 0 - ns 3,4 R8 tEHQZ CE# High to Output High-Z - 20 - 20 - 20 ns 4 R9 tGHQZ OE# High to Output High-Z - 14 - 14 - 14 ns 3,4 R10 tOH CE# (OE#) High to Output Low-Z 0 - 0 - 0 - ns 3,4 R11 tEHEL CE# Pulse Width High 20 - 20 - 20 - ns 5 R12 tELTV CE# Low to WAIT Valid - 20 - 22 - 22 ns 5 R13 tEHTZ CE# High to WAIT High-Z - 25 - 25 - 25 ns 4,5 Latching Specifications R101 tAVVH Address Setup to ADV# High 10 - 10 - 12 - ns - R102 tELVH CE# Low to ADV# High 10 - 10 - 12 - ns - R103 tVLQV ADV# Low to Output Valid - 70 85 - 70 ns 6 R104 tVLVH ADV# Pulse Width Low 10 - 10 - 12 - ns - R105 tVHVL ADV# Pulse Width High 10 - 10 - 12 - ns - R106 tVHAX Address Hold from ADV# High 9 - 9 - 9 - ns 2 R108 tAPA Page Address Access Time - 25 - 25 - 25 ns - Clock Specifications R200 fCLK CLK Frequency - 40 - 33 - 40 MHz - R201 tCLK CLK Period 25 - 30 - 25 - ns - R202 tCH/L CLK High or Low Time 9.5 - 9.5 - 9.5 - ns - R203 tCHCL CLK Fall or Rise Time - 3 - 5 - 5 ns - Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 29 28F640W30, 28F320W30, 28F128W30 Table 11. Read Operations - 130 nm Lithography (Sheet 2 of 2) 32-Mbit 64-Mbit # Parameter 1 Sym -70 128-Mbit -85 -70 Min Max Min Max Min Max Units Notes Synchronous Specifications R301 tAVCH Address Valid Setup to CLK 9 - 9 - 10 - ns - R302 tVLCH ADV# Low Setup to CLK 10 - 10 - 10 - ns - R303 tELCH CE# Low Setup to CLK 9 - 9 - 9 - ns - R304 tCHQV CLK to Output Valid - 20 - 22 - 20 ns - R305 tCHQX Output Hold from CLK 5 - 5 - 5 - ns - R306 tCHAX Address Hold from CLK 10 - 10 - 10 - ns 2 R307 tCHTV CLK to WAIT Valid - 20 - 22 - 22 ns - Notes: 1. See Figure 22, "AC Input/Output Reference Waveform" on page 48 for timing measurements and maximum allowable input slew rate. 2. Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first. 3. OE# can be delayed by up to tELQV - tGLQV after the falling edge of CE# without impact to tELQV. 4. Sampled, not 100% tested. 5. Applies only to subsequent synchronous reads. 6. During the initial access of a synchronous burst read, data from the first word might begin to be driven onto the data bus as early as the first clock edge after tAVQV. 7.2 Read Operations - 180 nm Lithography Table 12. Read Operations - 180 nm Lithography (Sheet 1 of 2) 32-Mbit 64-Mbit # Parameter 1 Sym -70 128-Mbit -85 -90 Units Notes Min Max Min Max Min Max 70 - 85 - 90 - ns 6 Asynchronous Specifications R1 tAVAV Read Cycle Time R2 tAVQV Address to Output Valid - 70 - 85 - 90 ns 6 R3 tELQV CE# Low to Output Valid - 70 - 85 - 90 ns 6 R4 tGLQV OE# Low to Output Valid - 30 - 30 - 30 ns 3 R5 tPHQV RST# High to Output Valid - 150 - 150 - 150 ns - R6 tELQX CE# Low to Output Low-Z 0 - 0 - 0 - ns 4 R7 tGLQX OE# Low to Output Low-Z 0 - 0 - 0 - ns 3,4 R8 tEHQZ CE# High to Output High-Z - 20 - 20 - 20 ns 4 R9 tGHQZ OE# High to Output High-Z - 14 - 14 14 ns 3,4 June 2005 30 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Table 12. Read Operations - 180 nm Lithography (Sheet 2 of 2) 32-Mbit 64-Mbit # Parameter 1 Sym -70 128-Mbit -85 -90 Min Max Min Max Min Max Units Notes R10 tOH CE# (OE#) High to Output Low-Z 0 - 0 - 0 - ns 3,4 R11 tEHEL CE# Pulse Width High 20 - 20 - 20 - ns 5 R12 tELTV CE# Low to WAIT Valid - 20 - 22 - 22 ns 5 R13 tEHTZ CE# High to WAIT High-Z - 25 - 25 - 25 ns 4,5 Latching Specifications R101 tAVVH Address Setup to ADV# High 10 - 10 - 12 - ns - R102 tELVH CE# Low to ADV# High 10 - 10 - 12 - ns - R103 tVLQV ADV# Low to Output Valid - 70 - 85 - 90 ns 6 R104 tVLVH ADV# Pulse Width Low 10 - 10 - 12 - ns - R105 tVHVL ADV# Pulse Width High 10 - 10 - 12 - ns - R106 tVHAX Address Hold from ADV# High 9 - 9 - 9 - ns 2 R108 tAPA Page Address Access Time - 25 - 25 - 30 ns - - 40 - 33 - 33 MHz - - 30 - 30 - ns - 9.5 Clock Specifications R200 fCLK CLK Frequency R201 tCLK CLK Period 25 R202 tCH/L CLK High or Low Time 9.5 - R203 tCHCL CLK Fall or Rise Time - 3 - 9.5 - ns - 5 - 5 ns - Synchronous Specifications R301 tAVCH Address Valid Setup to CLK 9 - 9 - 10 - ns - R302 tVLCH ADV# Low Setup to CLK 10 - 10 - 10 - ns - R303 tELCH CE# Low Setup to CLK 9 - 9 - 9 - ns - R304 tCHQV CLK to Output Valid - 20 - 22 - 22 ns - R305 tCHQX Output Hold from CLK 5 - 5 5 - ns - R306 tCHAX Address Hold from CLK 10 - 10 - 10 - ns 2 R307 tCHTV CLK to WAIT Valid - 20 - 22 - 22 ns - Notes: 1. See Figure 22, "AC Input/Output Reference Waveform" on page 48 for timing measurements and maximum allowable input slew rate. 2. Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first. 3. OE# can be delayed by up to tELQV- tGLQV after the falling edge of CE# without impact to tELQV. 4. Sampled, not 100% tested. 5. Applies only to subsequent synchronous reads. 6. During the initial access of a synchronous burst read, data from the first word might begin to be driven onto the data bus as early as the first clock edge after tAVQV. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 31 28F640W30, 28F320W30, 28F128W30 Figure 8. Asynchronous Read Operation Waveform R1 Address [A] VIH Valid Address V IL R2 CE# [E] VIH V IL R3 OE# [G] R8 VIH R4 V IL R7 WE# [W] R9 VIH V IL WAIT [T] V OH High Z High Z Note 1 VOL Data [D/Q] V OH High Z Valid Output VOL R5 RST# [P] R10 VIH V IL Notes: . 1. WAIT shown asserted (RCR[10]=0) 2. ADV# assumed to be driven to VIL in this waveform June 2005 32 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 9. Latched Asynchronous Read Operation Waveform R1 A[MAX:2] [A] VIH VIL A[1:0] [A] Valid Address Valid Address VIH Valid Address VIL Valid Address R2 R101 R105 ADV# [V] R106 VIH VIL R104 R103 CE# [E] VIH R3 VIL R102 R4 R8 R6 OE# [G] VIH VIL R7 WE# [W] R9 VIH VIL Data [Q] VOH High Z Valid Output VOL R5 RST# [P] R10 VIH VIL Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 33 28F640W30, 28F320W30, 28F128W30 Figure 10. Page-Mode Read Operation Waveform R1 A[MAX:2] [A] VIH Valid Address VIL R2 A[1:0] [A] VIH Valid Address VIL Valid Address Valid Address Valid Address R101 R105 ADV# [V] R106 VIH VIL R104 R103 CE# [E] VIH R3 VIL R102 R4 R8 R6 OE# [G] VIH VIL R7 WE# [W] R9 VIH VIL WAIT [T] VOH High Z Note 1 High Z R108 VOL Data [D/Q] VOH High Z Valid Output VOL R5 RST# [P] Valid Output Valid Output Valid Output R10 VIH VIL Note: 1. June 2005 34 WAIT shown asserted (RCR[10] = 0). Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 11. Single Synchronous Read-Array Operation Waveform R13 R12 Notes: 1. Section 14.2, "First Access Latency Count (RCR[13:11])" on page 83 describes how to insert clock cycles during the initial access. 2. WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data. 3. In this waveform, an x-word burst is initiated to the main array and it is terminated by a CE# de-assertion after the first word in the burst. If this access had been done to Status, ID, or Query reads, the asserted (low) WAIT signal would have remained asserted (low) as long as CE# is asserted (low). Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 35 28F640W30, 28F320W30, 28F128W30 Figure 12. Synchronous 4-Word Burst Read Operation Waveform R11 R12 R13 Notes: 1. Section 14.2, "First Access Latency Count (RCR[13:11])" on page 83 describes how to insert clock cycles during the initial access. 2. WAIT (shown asserted; RCR[10] = 0) can be configured to assert either during, or one data cycle before, valid data. June 2005 36 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 13. WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform R12 Notes: 1. Section 14.2, "First Access Latency Count (RCR[13:11])" on page 83 describes how to insert clock cycles during the initial access. 2. WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data. (This example assumes a wait delay of two clocks.) Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 37 28F640W30, 28F320W30, 28F128W30 Figure 14. WAIT Signal in Synchronous Non-Read Array Operation Waveform R13 R12 Notes: 1. Section 14.2, "First Access Latency Count (RCR[13:11])" on page 83 describes how to insert clock cycles during the initial access. 2. WAIT shown asserted (RCR[10]=0). June 2005 38 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 15. Burst Suspend R304 R305 R305 R305 CLK R1 R2 Address [A] R101 R105 R106 ADV# R3 R8 CE# [E] R4 R9 R4 R9 OE# [G] R13 R12 WAIT [T ] WE# [W] R7 R6 DATA [D/Q] Note: 1. Datasheet R304 Q0 Q1 R304 Q1 Q2 During Burst Suspend, the Clock signal can be held high or low. Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 39 28F640W30, 28F320W30, 28F128W30 7.3 AC Write Characteristics Table 13. AC Write Characteristics 32-Mbit 64-Mbit 128-Mbit # Sym Parameter 1,2 Unit Notes -70 W1 tPHWL (tPHEL) RST# High Recovery to WE# (CE#) Low -85 / -90 Min Max Min Max 3 150 - 150 - 0 - 0 - ns 4 45 - 60 - ns ns W2 tELWL (tWLEL) CE# (WE#) Setup to WE# (CE#) Low W3 tWLWH (tELEH) WE# (CE#) Write Pulse Width Low W4 tDVWH (tDVEH) Data Setup to WE# (CE#) High 45 - 60 - ns W5 tAVWH (tAVEH ) Address Setup to WE# (CE#) High 45 - 60 - ns W6 tWHEH (tEHWH ) CE# (WE#) Hold from WE# (CE#) High 0 - 0 - ns W7 tWHDX (tEHDX) Data Hold from WE# (CE#) High 0 - 0 - ns W8 tWHAX (tEHAX) Address Hold from WE# (CE#) High 0 - 0 - ns W9 tWHWL (tEHEL) WE# (CE#) Pulse Width High 5,6,7 25 - 25 - ns W10 tVPWH (tVPEH ) 3 200 - 200 - ns W11 tQVVL VPP Hold from Valid SRD 3,8 0 - 0 - ns W12 tQVBL WP# Hold from Valid SRD 3,8 0 - 0 - ns W13 tBHWH (tBHEH) WP# Setup to WE# (CE#) High 3 200 - 200 - ns W14 tWHGL (tEHGL) Write Recovery before Read - 0 - 0 - ns - tAVQV + 50 - ns VPP Setup to WE# (CE#) High W16 tWHQV WE# High to Valid Data 3,6,10 tAVQV + 40 W18 tWHAV WE# High to Address Valid 3,9,10 0 - 0 - ns W19 tWHCV WE# High to CLK Valid 3,10 20 - 20 - ns W20 tWHVH WE# High to ADV# High 3,10 20 - 20 - ns Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Write timing characteristics during erase suspend are the same as during write-only operations. A write operation can be terminated with either CE# or WE#. Sampled, not 100% tested. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL. System designers must take this into account, and can insert a software No-Op instruction to delay the first read after issuing a command. For commands other than resume commands. VPP must be held at VPPL or VPPH until block erase or program success is determined. Applicable during asynchronous reads following a write. tWHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and tWHVH both refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge, whichever occurs first). June 2005 40 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 16. Write Operations Waveform CLK [C] VIH VIL W19 Note 1 Address [A] VIH VIL Note 2 Note 3 Valid Address Note 4 Note 5 Valid Address Valid Address W5 W18 R101 R105 ADV# [V] R106 W8 VIH VIL R104 CE# (WE#) [E(W)] W20 VIH Note 6 VIL W2 OE# [G] W6 VIH VIL W3 W14 W9 WE# (CE#) [W(E)] VIH Note 6 VIL W1 Data [Q] W7 W16 VIH Data In Valid SRD Data In VIL W4 RST# [P] VIH VIL WP# [B] W13 W12 W10 W11 VIH VIL VPPH VPP [V] VPPLK VIL Notes: 1. 2. 3. 4. 5. 6. 7. Datasheet VCC power-up and standby. Write Program or Erase Setup command. Write valid address and data (for program) or Erase Confirm command. Automated program/erase delay. Read status register data (SRD) to determine program/erase operation completion. OE# and CE# must be asserted and WE# must be deasserted for read operations. CLK is ignored (but can be kept active/toggling). Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 41 28F640W30, 28F320W30, 28F128W30 Figure 17. Asynchronous Read to Write Operation Waveform R1 R2 W5 W8 Address [A] R3 R8 CE# [E} R4 R9 OE# [G] W3 W2 W6 WE# [W] R7 R6 W7 R10 Data [D/Q] W4 D Q R5 RST# [P] Figure 18. Asynchronous Write to Read Operation W5 W8 R1 Address [A] W2 W6 R10 CE# [E} W3 W18 WE# [W] W14 OE# [G] W7 W4 Data [D/Q] R4 R2 R3 D R9 R8 Q W1 RST # [P] June 2005 42 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 19. Synchronous Read to Write Operation Latency Count R301 R302 R306 CLK [C] R2 W5 R101 W18 Address [A] R105 R106 R104 R102 W20 ADV# [V] R303 R3 R11 W6 CE# [E] R4 R8 OE# [G] W15 W19 W9 W8 W3 W2 WE# R12 R307 WAIT [T] R304 R13 R7 Data [D/Q] Figure 20. R305 W7 Q D D Synchronous Write To Read Operation Latency Count R302 R301 R2 CLK W5 W8 R306 Address [A] W20 R106 R104 ADV# W6 W2 R303 R11 CE# [E} W18 W19 W3 WE# [W] R4 OE# [G ] R12 R307 WAIT [T] W7 W4 Data [D/Q ] R304 R3 D Q R304 R305 Q W1 RST# [P] Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 43 28F640W30, 28F320W30, 28F128W30 7.4 Erase and Program Times Table 14. Erase and Program Times Operation Symbol Description1 Parameter VPPH VPPL Notes Unit Typ Max Typ Max Erasing and Suspending W500 tERS/PB 4-Kword Parameter Block 2,3 0.3 2.5 0.25 2.5 s W501 tERS/MB 32-Kword Main Block 2,3 0.7 4 0.4 4 s W600 tSUSP/P Program Suspend 2 5 10 5 10 s W601 tSUSP/E Erase Suspend 2 5 20 5 20 s W200 tPROG/W Single Word 2 12 150 8 130 s W201 tPROG/PB 4-Kword Parameter Block 2,3 0.05 .23 0.03 0.07 s W202 tPROG/MB 32-Kword Main Block 2,3 0.4 1.8 0.24 0.6 s 4 N/A N/A 3.5 16 s N/A N/A 15 - ms Erase Time Suspend Latency Programming Program Time 5 Enhanced Factory Programming Program Operation Latency W400 tEFP/W Single Word W401 tEFP/PB 4-Kword Parameter Block 2,3 W402 tEFP/MB 32-Kword Main Block 2,3 N/A N/A 120 - ms W403 tEFP/SETUP EFP Setup - N/A N/A - 5 s W404 tEFP/TRAN Program to Verify Transition - N/A N/A 2.7 5.6 s W405 tEFP/VERIFY Verify - N/A N/A 1.7 130 s Notes: 1. Unless noted otherwise, all parameters are measured at TA = +25 C and nominal voltages, and are sampled, not 100% tested. 2. Excludes external system-level overhead. 3. Exact results might vary based on system overhead. 4. W400-Typ is the calculated delay for a single programming pulse. W400-Max includes the delay when programming within a new word-line. 5. Some EFP performance degradation might occur if block cycling exceeds 10. June 2005 44 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 8.0 Power and Reset Specifications Intel(R) Wireless Flash Memory (W30) devices have a layered approach to power savings that can significantly reduce overall system power consumption. * The APS feature reduces power consumption when the flash device is selected but idle. * If CE# is deasserted, the memory enters its standby mode, where current consumption is even lower. * Asserting RST# provides current savings similar to standby mode. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 8.1 Active Power With CE# at V IL and RST# at VIH, the flash device is in the active mode. Refer to Section 6.1, "DC Current Characteristics" on page 27, for ICC values. When the flash device is in active state, it consumes the most power from the system. Minimizing flash device active current therefore reduces system power consumption, especially in battery-powered applications. 8.2 Automatic Power Savings (APS) Automatic Power Saving (APS) provides low power operation during a read active state. ICCAPS is the average current measured over any 5 ms time interval, 5 s after CE# is deasserted. During APS, average current is measured over the same time interval 5 s after the following events: * There is no internal read, program or erase activity. * CE# is asserted. * The address lines are quiescent, and at VIL or VIH. OE# can be driven during APS. 8.3 Standby Power When CE# is deasserted, the flash device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 s after CE# is deasserted. During standby, average current is measured over the same time interval 5 s after CE# is deasserted. When the flash device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation completes. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 45 28F640W30, 28F320W30, 28F128W30 8.4 Power-Up/Down Characteristics The flash device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required if VCC and VPP are connected together; so it does not matter whether VPP or VCC powers-up first. If VPP is not connected to the system supply, then VCC must attain VCCMIN before applying VCCQ and VPP. Do not drive flash device inputs before supply voltage = VCCQMIN. Power supply transitions can occur only when RST# is low. 8.4.1 System Reset and RST# The use of RST# during system reset is important with automated program/erase flash devices, because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, the CPU is not properly initialized, because the flash memory might be providing status information instead of array data. Note: To allow proper CPU/flash device initialization at system reset, connect RST# to the system CPU RESET# signal. System designers must guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be low for a command write, driving either signal to VIH inhibits writes to the flash device. The CUI architecture provides additional protection, because memory contents can be altered only after successful completion of the two-step command sequences. The flash device is also disabled until RST# is brought to VIH, regardless of its control input states. By holding the flash device in reset (RST# connected to system PowerGood) during power-up/ down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 8.4.2 VCC, VPP, and RST# Transitions The CUI latches commands issued by system software, and is not altered by VPP or CE# transitions or WSM actions. Read-array mode is the power-up default state after the flash device exits from reset mode or after VCC transitions above VLKO (Lockout voltage). After completing program or block erase operations (even after VPP transitions below V PPLK), the Read Array command must reset the CUI to read-array mode if flash memory array access is desired. 8.5 Power Supply Decoupling When the flash device is accessed, many internal conditions change. Circuits are enabled to charge pumps and switch voltages. This internal activity produces transient noise. To minimize the effect of this transient noise, device decoupling capacitors are required. Transient current magnitudes depend on the flash device output capacitive and inductive loading. Two-line control and proper decoupling capacitor selection suppresses these transient voltage peaks. Note: June 2005 46 Each flash device must have a 0.1 F ceramic capacitor connected between each power (VCC, VCCQ, VPP) , and ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors must be as close as possible to the package signals. Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 8.6 Reset Specifications Table 15. Reset Specifications # P1 tPLPH P2 tPLRH P3 Notes: 1. 2. 3. 4. 5. 6. Parameter1 Symbol tVCCPH RST# Low to Reset during Read Notes Min Max Unit 1, 2, 3, 4 100 - ns RST# Low to Reset during Block Erase 1, 3, 4, 5 - 20 s RST# Low to Reset during Program 1, 3, 4, 5 - 10 s VCC Power Valid to Reset 1,3,4,5,6 60 - s These specifications are valid for all product versions (packages and speeds). The flash device might reset if tPLPH < tPLPHMin, but this is not guaranteed. Not applicable if RST# is tied to VCC. Sampled, but not 100% tested. If RST# is tied to VCC, the flash device is not ready until tVCCPH occurs after when V CC > VCC Min. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC > VCC Min. Figure 21. Reset Operations Waveforms P1 (A) Reset during read mode RST# [P] R5 VIH VIL P2 (B) Reset during program or block erase P1 P2 RST# [P] R5 VIH VIL P2 (C) Reset during program or block erase P1 P2 Abort Complete RST# [P] Abort Complete R5 VIH VIL P3 (D) VCC Power-up to RST# high Datasheet VCC VCC 0V Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 47 28F640W30, 28F320W30, 28F128W30 8.7 AC I/O Test Conditions Figure 22. AC Input/Output Reference Waveform VCCQ Test Points VCCQ/2 Input VCCQ/2 Output 0V Note: Figure 23. Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCC = VCCMin. Transient Equivalent Testing Load Circuit VCCQ R1 Device Under Test Out CL Note: Table 16. See Table 16 for component values. Test Configuration Component Values for Worst Case Speed Conditions Test Configuration V CCQMin Standard Test Note: Figure 24. R2 CL (pF) R1 (k) R1 (k) 30 25 25 C L includes jig capacitance. Clock Input AC Waveform R201 CLK [C] VIH VIL R202 June 2005 48 R203 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 8.8 Flash Device Capacitance TA = +25 C, f = 1 MHz Parameter Typ Max Unit Condition Input Capacitance 6 8 pF VIN = 0.0 V COUT Output Capacitance 8 12 pF VOUT = 0.0 V CCE CE# Input Capacitance 10 12 pF VIN = 0.0 V Symbol CIN Datasheet Sampled, not 100% tested. Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 49 28F640W30, 28F320W30, 28F128W30 9.0 Flash Device Operations This chapter provides an overview of flash device operations. The W30 flash memory device family includes an on-chip Write State Machine (WSM) to manage block erase and program algorithms. The WSM Command User Interface (CUI) allows minimal processor overhead with RAM-like interface timings. 9.1 Bus Operations Table 17. Bus Operations Summary Bus Operation RST# CLK ADV# CE# OE# WE# WAIT DQ[15:0] Notes Asynchronous VIH X L L L H Asserted Output - Synchronous VIH Running L L L H Driven Output 1 Burst Suspend VIH Halted X L H H Active Output - Write VIH X L L H L Asserted Input 2 Output Disable VIH X X L H H Asserted High-Z 3 Standby VIH X X H X X High-Z High-Z 3 Reset VIL X X X X X High-Z High-Z 3,4 Read Notes: 1. 2. 3. 4. WAIT is valid only during synchronous array-read operations. Refer to the Table 19, "Bus Cycle Definitions" on page 55 for valid DQ[15:0] during a write operation. X = Don't Care (H or L). RST# must be at VSS 0.2 V to meet the maximum specified power-down current. 9.1.1 Read The W30 flash memory device has several read configurations: * Asynchronous page mode read. * Synchronous burst mode read -- outputs four, eight, sixteen, or continuous words, from main blocks and parameter blocks. Several read modes are available in each partition: * Read-array mode: read accesses return flash memory array data from the addressed locations. * Read identifier mode: reads return manufacturer and device identifier data, block lock status, and protection register data. Identifier information can be accessed starting at a 4-Mbit partition base addresses; the flash memory array is not accessible in read identifier mode. * Read query mode: reads return the flash device CFI data. CFI information can be accessed starting at a 4-Mbit partition base addresses; the flash memory array is not accessible in read query mode. * Read status register mode: reads return status register data from the addressed partition. The array data for that partition is not accessible. A system processor can check the status register to determine the state of an addressed partition, or to monitor program and erase progress. June 2005 50 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 All partitions support the synchronous burst mode that internally sequences addresses with respect to the input CLK to select and supply data to the outputs. Identifier codes, query data, and status register read operations execute as single-synchronous or asynchronous read cycles. WAIT is asserted during these reads. Access to the modes listed above is independent of V PP. An appropriate CUI command places the flash device in a read mode. At initial power-up or after reset, the flash device defaults to asynchronous read-array mode. Asserting CE# enables flash device read operations. The flash device internally decodes upper address inputs to determine which partition is accessed. * Asserting ADV# opens the internal address latches. * Asserting OE# activates the outputs, and gates the selected data onto the I/O bus. * In asynchronous mode, the address is latched when ADV# is deasserted (when the flash device is configured to use ADV#). * In synchronous mode, the address is latched by either the rising edge of ADV# or the rising (or falling) CLK edge while ADV# remains asserted, whichever occurs first. WE# and RST# must be deasserted during read operations. Note: If only asynchronous reads are to be performed in your system, CLK must be tied to a valid VIH level, the WAIT signal can be floated, and ADV# must be tied to ground. 9.1.2 Burst Suspend The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation if the system needs to use the flash device address and data bus for other purposes. Burst accesses can be suspended during the initial latency (before data is received) or after the flash device has output data. When a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it is at VIH or V IL. To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent CLK edges resume the burst sequence where it left off. Within the flash device, CE# gates the WAIT signal. Therefore, during Burst Suspend, WAIT remains asserted and does not revert to a high-impedance state when OE# is deasserted. This WAIT state can cause contention with another flash device attempting to control the system READY signal during a Burst Suspend. System using the Burst Suspend feature must not connect the flash device WAIT signal directly to the system READY signal. Refer to Figure 15, "Burst Suspend" on page 39. 9.1.3 Standby De-asserting CE# deselects the flash device and places it in standby mode, substantially reducing flash device power consumption. In standby mode, outputs are placed in a high-impedance state independent of OE#. If deselected during a program or erase algorithm, the flash device consumes active power until the program or erase operation completes. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 51 28F640W30, 28F320W30, 28F128W30 9.1.4 Reset The flash device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. After returning from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWV) is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored. The flash device defaults to read-array mode, the status register is set to 80h, and the Read Configuration Register defaults to asynchronous page-mode reads. If RST# is asserted during an erase or program operation, the operation aborts and the memory contents at the aborted block or address are invalid. See Figure 21, "Reset Operations Waveforms" on page 47 for detailed information regarding reset timings. As on any automated device, RST# must be asserted during system reset. When the system comes out of reset, the processor expects to read from the flash memory array. Automated flash memory devices provide status information when read during program or erase operations. If a CPU reset occurs with no flash memory reset, the CPU might not be properly initialized, because the flash memory device might be providing status information instead of array data. 1.8 Volt Intel Flash memory devices allow proper CPU initialization following a system reset through the use of the RST# input. In this application, RST# is controlled by the same CPU reset signal, RESET#. 9.1.5 Write A write occurs when CE# and WE# are asserted and OE# is deasserted. Flash memory control commands are written to the CUI using standard microprocessor write timings. Proper use of the ADV# input is needed for proper latching of the addresses. Refer to Section 7.3, "AC Write Characteristics" on page 40 for details. The address and data are latched on the rising edge of WE#. Write operations are asynchronous; CLK is ignored (but can be kept active/toggling). The CUI does not occupy an addressable memory location within any partition. The system processor must access it at the correct address range, depending on the kind of command executed. Programming or erasing can occur in only one partition at a time. Other partitions must be in one of the read modes or erase suspend mode. Table 18, "Command Codes and Descriptions" on page 53 shows the available commands. Appendix A, "Write State Machine" on page 90 provides information about moving between different operating modes using CUI commands. 9.2 Flash Device Commands The flash device on-chip WSM manages erase and program algorithms. This local CPU (WSM) controls the flash device in-system read, program, and erase operations. Bus cycles to or from the flash memory device conform to standard microprocessor bus cycles. The RST#, CE#, OE#, WE#, and ADV# control signals dictate data flow into and out of the flash device. WAIT informs the CPU of valid data during burst reads. Table 17, "Bus Operations Summary" on page 50 summarizes bus operations. To select flash device operations, write specific commands into the flash device CUI. Table 18, "Command Codes and Descriptions" on page 53 lists all possible command codes and descriptions. Table 19, "Bus Cycle Definitions" on page 55 lists command definitions. Because commands are partition-specific, you must issue write commands within the target address range. June 2005 52 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Table 18. Operation Command Codes and Descriptions (Sheet 1 of 2) Code Flash Device Command FFh Read Array Places the selected partition in read-array mode. 70h Read Status Register Places the selected partition in status register read mode. The partition enters this mode after a Program or Erase command is issued to it. 90h Read Identifier Places the selected partition in read identifier mode. Flash device reads from partition addresses output the manufacturer/device codes, configuration register data, block lock status, or protection register data on D[15:0]. 98h Read Query Places the addressed partition in read query mode. Flash device reads from the partition addresses output the CFI information on D[7:0]. 50h Clear Status Register The WSM can set the block lock (SR[1]), VPP (SR[3]), program (SR[4]), and erase (SR[5]) status bits of the status register, but WSM cannot clear these bits. SR[5:3,1] can be cleared only by a flash device reset or through the Clear Status Register command. 40h Word Program Setup * The first cycle of this preferred program command prepares the CUI for a program operation. * The second cycle latches the address and data, and executes the WSM program algorithm at this location. Status register updates occur when CE# or OE# is toggled. After programming, use a Read Array command to read the array data. 10h Alternate Setup Equivalent to a Program Setup command (40h). 30h EFP Setup This program command activates EFP mode. * The first write cycle sets up the command. * If the second cycle is an EFP Confirm command (D0h), subsequent writes provide program data. All other commands are ignored after EFP mode begins. D0h EFP Confirm If the first command was EFP Setup (30h), the CUI latches the address and data, and prepares the flash device for EFP mode. 20h Erase Setup This command prepares the CUI for Block Erase. The flash device erases the block that the Erase Confirm command addresses. If the next command is not Erase Confirm, the CUI sets status register bits SR[5:4] to indicate a command sequence error, and places the partition in the read status register mode. D0h Erase Confirm If the first command was Erase Setup (20h), the CUI latches the address and data, and erases the block indicated by the erase confirm cycle address. During program or erase, the partition responds only to Read Status Register, Program Suspend, and Erase Suspend commands. CE# or OE# toggle updates the status register data. B0h Program Suspend or Erase Suspend This command, issued at any flash device address, suspends the currently executing program or erase operation. Status register data indicates that the operation was successfully suspended if SR[2] (program suspend) or SR[6] (erase suspend) and SR[7] are set. The WSM remains in the suspended state regardless of the control signal states (except RST#). D0h Suspend Resume This command, issued at any flash device address, resumes the suspended program or erase operation. Read Program Erase Suspend Datasheet Description Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 53 28F640W30, 28F320W30, 28F128W30 Table 18. Operation Command Codes and Descriptions (Sheet 2 of 2) Code Flash Device Command Description 60h Lock Setup This command prepares the CUI lock configuration. If the next command is not Lock Block, Unlock Block, or Lock-Down, the CUI sets SR[5:4] to indicate a command sequence error. 01h Lock Block If the previous command was Lock Setup (60h), the CUI locks the addressed block. D0h Unlock Block If the previous command was Lock Setup (60h), the CUI latches the address and unlocks the addressed block. If previously locked-down, the operation has no effect. 2Fh Lock-Down If the previous command was Lock Setup (60h), the CUI latches the address and locks-down the addressed block. C0h Protection Program Setup This command prepares the CUI for a protection register program operation. The second cycle latches address and data, and starts the WSM protection register program or lock algorithm. Toggling CE# or OE# updates the flash device status register data. To read array data after programming, issue a Read Array command. 60h Configuration Setup This command prepares the CUI for flash device configuration. If Set Configuration Register is not the next command, the CUI sets SR[5:4] to indicate a command sequence error. 03h Set Configuration Register If the previous command was Configuration Setup (60h), the CUI latches the address and writes the data from A[15:0] into the configuration register. Subsequent read operations access the array data. Block Locking Protection Configuration Note: Do not use unassigned commands. Intel reserves the right to redefine these codes for future functions. June 2005 54 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Table 19. Bus Cycle Definitions Operation Read Program and Erase Lock Bus Cycles Command First Bus Cycle Second Bus Cycle Oper Addr 1 Data2,3 Oper Addr1 Data2,3 Read Array/Reset >1 Write PnA FFh Read Read Address Array Data Read Identifier >2 Write PnA 90h Read PBA+IA IC Read Query >2 Write PnA 98h Read PBA+QA QD Read Status Register 2 Write PnA 70h Read PnA SRD Clear Status Register 1 Write XX 50h Block Erase 2 Write BA 20h Write BA D0h Word Program 2 Write WA 40h/10h Write WA WD EFP >2 Write WA 30h Write WA D0h Program/Erase Suspend 1 Write XX B0h Program/Erase Resume 1 Write XX D0h Lock Block 2 Write BA 60h Write BA 01h Unlock Block 2 Write BA 60h Write BA D0h Lock-Down Block 2 Write BA 60h Write BA 2Fh Protection Program 2 Write PA C0h Write PA PD Lock Protection Program 2 Write LPA C0h Write LPA FFFDh Set Configuration Register 2 Write CD 60h Write CD 03h Protection Configuration Notes: 1. First-cycle command addresses must be the same as the target address of the operation. Examples: --The first-cycle address for the Read Identifier command must be the same as the Identification code address (IA). --The first-cycle address for the Word Program command must be the same as the word address (WA) to be programmed. --The first-cycle address for the Erase/Program Suspend command must be the same as the address within the block to be suspended. XX = Any valid address within the flash device. IA = Identification code address. BA = Block Address. Any address within a specific block. LPA = The Lock Protection Address is obtained from the CFI (through the Read Query command). The W30 flash memory device family LPA is at 0080h. PA = User programmable 4-word protection address. PnA = Any address within a specific partition. PBA = Partition Base Address. The first address of a particular partition. QA = Query code address. WA = Word address of memory location to be written. 2. SRD = Status register data. WD = Data to be written at location WA. IC = Identifier code data. PD = User programmable 4-word protection data. QD = Query code data on D[7:0]. CD = Configuration register code data presented on flash device addresses A[15:0]. A[MAX:16] address bits can select any partition. See Table 27, "Read Configuration Register Definitions" on page 81 for configuration register bits descriptions. 3. Do not use commands other than those shown above. Other commands are reserved by Intel for future flash device implementations. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 55 28F640W30, 28F320W30, 28F128W30 9.3 Command Sequencing When issuing a 2-cycle write sequence to the flash device, a read operation can occur between the two write cycles. The setup phase of a 2-cycle write sequence places the addressed partition into read-status mode, so if the same partition is read before the second confirm write cycle is issued, status register data is returned. Reads from other partitions, however, can return actual array data, if the addressed partition is already in read-array mode. Figure 25 and Figure 26 illustrate these two conditions. Figure 25. Normal Write and Read Cycles Address [A] Partition A Partition A Partition A WE# [W] OE# [G] Data [Q] Figure 26. 20h D0h FFh Block Erase Setup Block Erase Conf irm Read Array Interleaving a 2-Cycle Write Sequence with an Array Read Address [A] Partition B Partition A Partition B Partition A WE# [W] OE# [G] Data [Q] FFh 20h Array Data D0h Read Array Erase Setup Bus Read Erase Conf irm By contrast, a write bus cycle must not interrupt a 2-cycle write sequence. Such an interruption causes a command sequence error to appear in the status register. Figure 27 illustrates a command sequence error. Figure 27. Improper Command Sequencing Address [A] Partition X Partitio n Y Partition X Partition X WE# [W] OE# [G] Data [D/Q] June 2005 56 20h FFh D0h Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 SR Data Datasheet 28F640W30, 28F320W30, 28F128W30 10.0 Read Operations 10.1 Read Array The Read Array command places (or resets) the partition in read-array mode and is used to read data from the flash memory array. Upon initial flash device power-up, or after reset (RST# transitions from V IL to VIH), all partitions default to asynchronous read-array mode. To read array data from the flash device: 1. Write the Read Array command (FFh) to the CUI and specify the desired word address. 1. Read from that address. Note: If a partition is already in read-array mode, you do not need to issue the Read Array command to read from that partition. If the Read Array command is written to a partition that is erasing or programming, the flash device presents invalid data on the bus until the program or erase operation completes. After the program or erase finishes in that partition, valid array data can then be read. If an Erase Suspend or Program Suspend command suspends the WSM, a subsequent Read Array command places the addressed partition in read-array mode. The Read Array command functions independently of VPP. 10.2 Read Device ID The read identifier mode outputs the manufacturer/device identifier, block lock status, protection register codes, and configuration register data. The identifier information is contained within a separate memory space on the flash device, and can be accessed along the 4-Mbit partition address range supplied by the Read Identifier command (90h) address. Reads from addresses in Table 20 retrieve ID information. Issuing a Read Identifier command to a partition that is programming or erasing places the outputs of that partition in read ID mode while the partition continues to program or erase in the background. Table 20. Flash Device Identification Codes (Sheet 1 of 2) Address1 Item Manufacturer ID Device ID Datasheet Data Base Offset Partition 00h Partition 01h Description 0089h Intel 8852h 32-Mbit TPD 8853h 32-Mbit BPD 8854h 64-Mbit TPD 8855h 64-Mbit BPD 8856h 128-Mbit TPD 8857h 128-Mbit BPD Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 57 28F640W30, 28F320W30, 28F128W30 Table 20. Flash Device Identification Codes (Sheet 2 of 2) Address1 Item Data Base Offset Block Lock Status(2) Block 02h Block Lock-Down Status(2) Block 02h Configuration Register Partition 05h Register Data Protection Register Lock Status Partition 80h Lock Data Protection Register Partition 81h - 88h Register Data Description D0 = 0 Block is unlocked D0 = 1 Block is locked D1 = 0 Block is not locked-down D1 = 1 Block is locked down Multiple reads required to read the entire 128-bit Protection Register. Notes: 1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number 38 in a BPD, set the address to the BBA (0F8000h) plus the offset (02h), which in this example is 0F8002h. Then examine bit 0 of the data to determine whether the block is locked. 2. See Section 13.1.4, "Block Lock Status" on page 75 for valid lock status. 10.3 Read Query (CFI) The W30 flash memory device contains a separate CFI query database that acts as an on-chip datasheet. To access the CFI information within the W30 flash memory device, issue the Read Query command and supply a specific address. The address is constructed from the base address of a partition plus a particular offset corresponding to the desired CFI field. Appendix B, "Common Flash Interface" on page 93 shows accessible CFI fields and their address offsets. Issuing the Read Query command to a partition that is programming or erasing puts that partition in read query mode while the partition continues to program or erase in the background. 10.4 Read Status Register The flash device status register displays program and erase operation status. The status of a partition can be read after writing the Read Status Register command to any location within the address range of that partition. Read-status mode is the default read mode following a Program, Erase, or Lock Block command sequence. Subsequent single reads from that partition return the partition status until another valid command is written. The read-status mode supports single synchronous and single asynchronous reads only; it does not support burst reads. The first falling edge of OE# or CE# latches and updates Status Register data. The operation does not affect the modes of other partitions. Because the Status Register is 8 bits wide, only DQ [7:0] contain valid status register data; DQ [15:8] contain zeros. See Table 21, "Status Register Definitions" on page 59 and Table 22, "Status Register Descriptions" on page 59. June 2005 58 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Each 4-Mbit partition contains its own status register. Bits SR[6:0] are unique to each partition, but SR[7], the Device WSM Status (DWS) bit, pertains to the entire flash memory device. SR[7] provides the program and erase status of the entire flash device. By contrast, the Partition WSM Status (PWS) bit, SR[0], provides program and erase status of the addressed partition only. Status register bits SR[6:1] present information about partition-specific program, erase, suspend, V PP, and block-lock states. Table 23, "Status Register Device WSM and Partition Write Status Description" on page 60 describes the DWS (SR[7]) and PWS (SR[0]) combinations. Table 21. Status Register Definitions DWS ESS ES PS VPPS PSS DPS PWS 7 6 5 4 3 2 1 0 Table 22. Status Register Descriptions Bit 7 6 5 4 3 2 1 0 Name DWS Device WSM Status ESS Erase Suspend Status ES Erase Status PS Program Status VPPS VPP Status PSS Program Suspend Status DPS Device Protect Status PWS Partition Write Status Datasheet State Description 0 = Device WSM is Busy 1 = Device WSM is Ready * SR[7] indicates erase or program completion in the flash device. * SR[6:1] are invalid while SR[7] = 0. See Table 23 for valid SR[7] and SR[0] combinations. 0 = Erase in progress/completed 1 = Erase suspended After issuing an Erase Suspend command, the WSM halts and sets SR[7] and SR[6]. SR[6] remains set until the flash device receives an Erase Resume command. 0 = Erase successful 1 = Erase error * SR[5] is set if an attempted erase failed. * A Command Sequence Error is indicated when SR[7,5:4] are set. 0 = Program successful 1 = Program error SR[4] is set if the WSM failed to program a word. 0 = VPP OK 1 = VPP low detect, operation aborted The WSM indicates the VPP level after program or erase completes. SR[3] does not provide continuous VPP feedback and is not guaranteed when VPPVPPL/VPPH 0 = Program in progress/completed 1 = Program suspended After receiving a Program Suspend command, the WSM halts execution and sets SR[7] and SR[2]. These bits remain set until a Resume command is received. 0 = Unlocked 1 = Aborted erase/program attempt on a locked block If an erase or program operation is attempted to a locked block (if WP# = VIL), the WSM sets SR[1] and aborts the operation. 0 = This partition is busy, but only if SR[7]=0 1 = Another partition is busy, but only if SR[7]=0 The addressed partition is erasing or programming. In EFP mode, SR[0] indicates that a data-stream word has finished programming or verifying, depending on the particular EFP phase. See Table 23 for valid SR[7] and SR[0] combinations. Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 59 28F640W30, 28F320W30, 28F128W30 Table 23. Status Register Device WSM and Partition Write Status Description DWS (SR[7]) PWS (SR[0]) 0 0 The addressed partition is performing a program/erase operation. EFP: the flash device has finished programming or verifying data, or is ready for data. 0 1 A partition other than the one currently addressed is performing a program/erase operation. EFP: the flash device is either programming or verifying data. 1 0 No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR[6,2]) indicate whether other partitions are suspended. EFP: the flash device has exited EFP mode. 1 1 Does not occur in standard program or erase modes. EFP: this combination does not occur. 10.5 Description Clear Status Register The Clear Status Register command clears the status register and leaves all partition output states unchanged. The WSM can set all status register bits and clear bits SR[7:6,2,0]. Because bits SR[5,4,3,1] indicate various error conditions, they can be cleared only by the Clear Status Register command. By allowing system software to reset these bits, several operations (such as cumulatively programming several addresses or erasing multiple blocks in sequence) can be performed before reading the status register to determine whether an error occurred. If an error is detected, the Status Register must be cleared before beginning another command or sequence. Flash device reset (RST# = V IL) also clears the status register. This command functions independently of VPP. June 2005 60 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 11.0 Program Operations 11.1 Word Program When the Word Program command is issued, the WSM executes a sequence of internally timed events to program a word at the desired address, and to verify that the bits are sufficiently programmed. Programming the flash memory array changes specifically addressed bits to 0; 1 bits do not change the memory cell contents. Programming can occur in only one partition at a time. All other partitions must be in either a read mode or erase suspend mode. Only one partition can be in erase suspend mode at a time. To examine the status register can be examined for program progress, read any address within the partition that is busy programming. However, while most status register bits are partition-specific, the Device WSM Status bit, SR[7], is device-specific. That is, if the status register is read from any other partition, SR[7] indicates the program status of the entire flash memory device. This status bit permits the system CPU to monitor the program progress while reading the status of other partitions. CE# or OE# toggle (during polling) updates the status register. Several commands can be issued to a partition that is programming: Read Status Register, Program Suspend, Read Identifier, and Read Query. The Read Array command can also be issued, but the read data is indeterminate. After programming completes, three status register bits can signify various possible error conditions: * SR[4] indicates a program failure if set. * If SR[3] is set, the WSM could not execute the Word Program command, because VPP was outside the acceptable limits. * If SR[1] is set, the program was aborted, because the WSM attempted to program a locked block. After the status register data is examined, clear it using the Clear Status Register command before issuing a new command. The partition remains in status register mode until another command is written to that partition. Any command can be issued after the status register indicates program completion. If CE# is deasserted while the flash device is programming, the flash devices do not enter standby mode until the program operation completes. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 61 28F640W30, 28F320W30, 28F128W30 Figure 28. Word Program Flowchart WORD PROGRAM PROCEDURE Bus Command Operation Start Write 40h, Word Address Write Program Setup Data = 40h Addr = Location to program (WA) Write Data Data = Data to program (WD) Addr = Location to program (WA) Write Data Word Address Read Suspend Program Loop Read Status Register Standby No SR[7] = 0 Suspend Program Comments Read SRD Toggle CE# or OE# to update SRD Check SR[7] 1 = WSM ready 0 = WSM busy Yes Repeat for subsequent programming operations. 1 Full status register check can be done after each program or after a sequence of program operations. Full Program Status Check (if desired) Program Complete FULL PROGRAM STATUS CHECK PROCEDURE Read Status Register SR[3] = Bus Command Operation 1 SR[4] = Standby Check SR[3] 1 = VPP error Standby Check SR[4] 1 = Data program error Standby Check SR[1] 1 = Attempted program to locked block Program aborted VPP Range Error 0 1 Program Error 1 Device Protect Error Comments 0 SR[1] = 0 Program Successful June 2005 62 SR[3] MUST be cleared before the WSM will allow further program attempts Only the Clear Staus Register command clears SR[4:3,1]. If an error is detected, clear the status register before attempting a program retry or other error recovery. Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 11.2 Factory Programming The standard factory programming mode uses the same commands and algorithm as the Word Program mode (40h/10h). When VPP is at VPPL, program and erase currents are drawn through VCC. If VPP is driven by a logic signal, V PPL must remain above the VPPLMin value to perform in-system flash memory modifications. When VPP is connected to a 12 V power supply, the flash device draws program and erase current directly from VPP, which eliminates the need for an external switching transistor to control the VPP voltage. Figure 37, "Examples of VPP Power Supply Configurations" on page 80 shows examples of flash device power supply usage in various configurations. The 12-V VPP mode enhances programming performance during the short time period typically found in manufacturing processes. However, this mode is not intended for extended use.12 V can be applied to V PP during program and erase operations as specified in Section 5.2, "Operating Conditions" on page 26. VPP can be connected to 12 V for a total of tPPH hours maximum. Stressing the flash device beyond these limits might cause permanent damage. 11.3 Enhanced Factory Program (EFP) EFP substantially improves flash device programming performance through a number of enhancements to the conventional 12-Volt word program algorithm. The more efficient WSM algorithm in EFP eliminates the traditional overhead delays of the conventional word program mode in both the host programming system and the flash device. Changes to the conventional word programming flowchart and internal WSM routine were developed because of today's beat-ratesensitive manufacturing environments; a balance between programming speed and cycling performance was attained. The host programmer writes data to the flash device and checks the Status Register to determine when the data has completed programming. This modification cuts write bus cycles approximately in half. * Following each internal program pulse, the WSM increments the flash device address to the next physical location. * Programming equipment can then sequentially stream program data throughout an entire block without having to setup and present each new address. In combination, these enhancements reduce much of the host programmer overhead, enabling more of a data streaming approach to flash device programming. EFP further speeds up programming by performing internal code verification. With this feature, PROM programmers can rely on the flash device to verify that it has been programmed properly. From the flash device side, EFP streamlines internal overhead by eliminating the delays previously associated with switching voltages between programming and verify levels at each memory-word location. EFP consists of four phases: setup, program, verify, and exit. Refer to Figure 29, "Enhanced Factory Program Flowchart" on page 66 for a detailed graphical representation of how to implement EFP. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 63 28F640W30, 28F320W30, 28F128W30 11.3.1 EFP Requirements and Considerations Table 24. EFP Requirements and Considerations EFP Requirements EFP Considerations Ambient temperature: TA = 25 C 5 C Block cycling below 100 erase cycles 1 VCC within specified operating range RWW not supported2 VPP within specified VPPH range EFP programs one block at a time Target block unlocked EFP cannot be suspended 1. 2. 11.3.2 Recommended for optimum performance. Some degradation in performance might occur if this limit is exceeded, but the internal algorithm will continue to work properly. Code or data cannot be read from another partition during EFP. Setup After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7] transitions from a 1 to a 0, indicating that the WSM is busy with EFP algorithm startup. A delay before checking SR[7] is required to allow the WSM time to perform all of its setups and checks (VPP level and block lock status). If an error is detected, status register bits SR[4], SR[3], and/or SR[1] are set, and the EFP operation terminates. Note: After the EFP Setup and Confirm command sequence, reads from the flash device automatically output status register data. Do not issue the Read Status Register command, because this command is interpreted as data to program at WA0. 11.3.3 Program After setup completion, the host programming system must check SR[0] to determine the data-stream ready status (SR[0]=0). Each subsequent write after this check is a program-data write to the flash memory array. Each cell within the memory word to be programmed to 0 receives one WSM pulse; additional pulses, if required, occur in the verify phase. SR[0]=1 indicates that the WSM is busy applying the program pulse. The host programmer must poll the flash device status register for the program done state after each data-stream write. SR[0]=0 indicates that the appropriate cell(s) within the accessed memory location have received their single WSM program pulse, and that the flash device is ready for the next word. Although the host can check full status for errors at any time, this check is necessary only on a block basis, after EFP exit. Addresses must remain within the target block. Supplying an address outside of the target block immediately terminates the program phase; the WSM then enters the EFP verify phase. June 2005 64 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 The address can either remain constant or increment. The flash device compares the incoming address to the address stored from the setup phase (WA0). * If the addresses match, the WSM programs the new data word at the next sequential memory location. * If the addresses differ, the WSM jumps to the new address location. The program phase concludes when the host programming system writes to a different block address. The data supplied must be FFFFh. Upon program phase completion, the flash device enters the EFP verify phase. 11.3.4 Verify A high percentage of the flash memory bits program on the first WSM pulse. However, EFP internal verification identifies cells that do not completely program on their first attempt, and applies additional pulses as required. The verify phase is identical in flow to the program phase, except that instead of programming incoming data, the WSM compares the verify-stream data to the data that was previously programmed into the block. * If the data compares correctly, the host programmer proceeds to the next word. * If the data does not match, the host waits while the WSM applies one or more additional pulses. The host programmer must reset its initial verify-word address to the same starting location supplied during the program phase. It then reissues each data word in the same order as during the program phase. Like programming, the host can write each subsequent data word to WA0 or it can increment through the block addresses. The verification phase concludes when the interfacing programmer writes to a different block address. The data supplied must be FFFFh. Upon completion of the verify phase, the flash device enters the EFP exit phase. 11.3.5 Exit SR[7]=1 indicates that the flash device has returned to normal operating conditions. Perform a full status check at this time, to verify that the entire block programmed successfully. After EFP exit, any valid CUI command can be issued. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 65 28F640W30, 28F320W30, 28F128W30 Figure 29. Enhanced Factory Program Flowchart ENHANCED FACTORY PROGRAMMING PROCEDURE EFP Setup EFP Program EFP Verify EFP Exit Start Read Status Register Read Status Register Read Status Register SR[0]=1=N Write 30h Address = WA 0 SR[0]=1=N Write D0h Address = WA 0 EFP setup time SR[7]=0=Y Read Status Register EFP Setup Done? N SR[0]=1=N Data Stream Ready? Check V PP & Lock errors (SR[3,1]) EFP Exited? SR[0] =0=Y SR[7]=1=Y Write Data Address = WA 0 Write Data Address = WA 0 Full Status Check Procedure Read Status Register Read Status Register Operation Complete Program Done? Verify Done? SR[0]=0=Y SR[0]=0=Y N Last Data? Last Data? Y SR[7]=1=N SR[7]=0=N Verify Stream Ready? SR[0] =0=Y SR[0]=1=N VPP = 12V Unlock Block Y Write FFFFh Address BBA Write FFFFh Address BBA Exit EFP Setup Bus State Comments EFP Program Bus State Read Write Unlock Block VPP = 12V Unlock block Write EFP Setup Data = 30h Address = WA 0 Standby EFP Data = D0h Confirm Address = WA 0 Write (note 1) Write Standby EFP setup time Read Standby EFP Setup Done? Status Register Check SR[7] 0 = EFP ready 1 = EFP not ready If SR[7] = 1: Error Check SR[3,1] Standby Condition SR[3] = 1 = V PP error Check SR[1] = 1 = locked block Comments Status Register Data Stream Ready? Read Standby Standby Write Standby Data = Data to program Address = WA 0 Write (note 2) Status Register Device automatically increments address. Exit Data = FFFFh Program Address not within same Phase BBA Comments Read Check SR[0] 0 = Ready for data 1 = Not ready for data Check SR[0] Program 0 = Program done Done? 1 = Program not done Last Data? EFP Verify Bus State Status Register Verify Stream Ready? Check SR[0] 0 = Ready for verify 1 = Not ready for verify Data = Word to verify Address = WA 0 Read Status Register Standby (note 3) Verify Done? Check SR[0] 0 = Verify done 1 = Verify not done Standby Last Data? Device automatically increments address. Write Exit Verify Phase Data = FFFFh Address not within same BBA EFP Exit 1. WA0 = first Word Address to be programmed within the target block. The BBA (Block Base Address) must remain constant throughout the program phase data stream; WA can be held constant at the first address location, or it can be written to sequence up through the addresses within the block. Writing to a BBA not equal to that of the block currently being written to terminates the EFP program phase, and instructs the device to enter the EFP verify phase. 2. For proper verification to occur , the verify data stream must be presented to the device in the same sequence as that of the program phase data stream. Writing to a BBA not equal to WA terminates the EFP verify phase, and instructs the device to exit EFP . 3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive additional program-pulse attempts during the EFP verify phase. The device will report any program failure by setting SR[4]=1; this check can be performed during the full status check after EFP has been exited for that block, and will indicate any error within the entire data stream. June 2005 66 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Read Standby Status Register EFP Exited? Check SR[7] 0 = Exit not finished 1 = Exit completed Repeat for subsequent operations. After EFP exit, a Full Status Check can determine if any program error occurred. See the Full Status Check procedure in the Word Program flowchart. Datasheet 28F640W30, 28F320W30, 28F128W30 12.0 Program and Erase Operations 12.1 Program/Erase Suspend and Resume The Program Suspend and Erase Suspend commands halt an in-progress program or erase operation. The command can be issued at any flash device address. The partition corresponding to the address of the command remains in its previous state. A suspend command allows data to be accessed from memory locations other than the location being programmed or the block being erased. * A program operation can be suspended only to perform a read operation. * An erase operation can be suspended to perform either a program or a read operation within any block, except the block that is erase suspended. * A program command nested within a suspended erase can subsequently be suspended to read yet another location. Once a program or erase process starts, the Suspend command requests that the WSM suspends the program or erase sequence at predetermined points in the algorithm. The partition that is actually suspended continues to output status register data after the Suspend command is written. An operation is suspended when status bits SR[7] and SR[6] and/or SR[2] are set. To read data from blocks within the partition (other than an erase-suspended block), write a Read Array command. Block erase cannot resume until the program operations initiated during erase suspend are complete. * Read Array, Read Status Register, Read Identifier (ID), Read Query, and Program Resume are valid commands during Program or Erase Suspend. * Additionally, Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, and Lock-Down Block are valid commands during erase suspend. To read data from a block in a partition that is not programming or erasing, the operation does not need to be suspended. * If the other partition is already in read array, ID, or Query mode, issuing a valid address returns corresponding data. * If the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. During a suspend, CE# = V IH places the flash device in standby state, which reduces active current. VPP must remain at its program level and WP# must remain unchanged while in suspend mode. A resume command instructs the WSM to continue programming or erasing, and clears status register bits SR[2] (or SR[6]) and SR[7]. The Resume command can be written to any partition. When read at the partition that is programming or erasing, the flash device outputs data corresponding to the last mode for that partition. If the status register error bits are set, the status register can be cleared before issuing the next instruction. RST# must remain at VIH. See Figure 30, "Program Suspend / Resume Flowchart" on page 68, and Figure 31, "Erase Suspend / Resume Flowchart" on page 69. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 67 28F640W30, 28F320W30, 28F128W30 If a suspended partition was placed in Read Array, Read Status Register, Read Identifier (ID), or Read Query during the suspend, the flash device remains in that mode, and outputs data corresponding to that mode after the program or erase operation resumes. After resuming a suspended operation, issue the read command appropriate to the read operation. To read status after resuming a suspended operation, issue a Read Status Register command (70h) to return the suspended partition to status mode. Figure 30. Program Suspend / Resume Flowchart PROGRAM SUSPEND / RESUME PROCEDURE Bus Command Operation Start Write Write B0h Any Address Write Write 70h Same Partition SR[7] = Read Status 0 Data = 70h Addr = Any address in same partition Read SRD Toggle CE# or OE# to update SRD Addr = Any address in same partition Read Read Status Register Comments Data = B0h Program Addr = Any address within programming Suspend partition Standby Check SR[7] 1 = WSM ready 0 = WSM busy Standby Check SR[2] 1 = Program suspended 0 = Program completed 1 SR[2] = 0 Program Completed 1 Write Write FFh Susp Partition Read Array Read array data from block other than the one being programmed Read Read Array Data Done Reading Write Data = FFh Addr = Any device address (except word being programmed) Program Resume Data = D0h Addr = any device address If the suspended partition was placed in Read Array mode: No Write Yes Write D0h Any Address Write FFh Pgm'd Partition Program Resumed Read Array Data Read Status Return partition to status mode: Data = 70h Addr = address within same partition Write 70h Same Partition June 2005 68 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 31. Erase Suspend / Resume Flowchart ERASE SUSPEND / RESUME PROCEDURE Bus Command Operation Start Write Write B0h Any Address Write Write 70h Same Partition Erase Data = B0h Suspend Addr = Any address Read Status Read Status Register SR[6] = Read Array Data Read or Program? No Check SR[7] 1 = WSM ready 0 = WSM busy Standby Check SR[6] 1 = Erase suspended 0 = Erase completed Write Data = FFh or 40h Read Array Addr = Any device address (except or Program block being erased) Erase Completed 0 1 Read Standby 0 1 Read or Write Program Program Loop Data = 70h Addr = Any address in same partition Read SRD Toggle CE# or OE# to update SRD Addr = Any address in same partition Read SR[7] = Comments Write Read array or program data from/to block other than the one being erased Erase Data = D0h Resume Addr = Any address If the suspended partition was placed in Read Array mode or a Program Loop: Done? Yes Write D0h Any Address Write FFh Erased Partition Erase Resumed Read Array Data Write Read Status Return partition to status mode: Data = 70h Addr = Address within same partition Write 70h Same Partition Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 69 28F640W30, 28F320W30, 28F128W30 12.2 Block Erase The 2-cycle block erase command sequence, consisting of Erase Setup (20h) and Erase Confirm (D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode at a time; other partitions must be in a read mode. The Erase Confirm command internally latches the address of the block to erase. Erase forces all bits within the block to 1. SR[7] is cleared while the erase executes. After writing the Erase Confirm command, the selected partition is placed in read status register mode. Reads performed to that partition return the current status data. The address given during the Erase Confirm command does not need to be the same address used in the Erase Setup command. For example, if the Erase Confirm command is given to partition B, then the selected block in partition B is erased, even if the Erase Setup command was to partition A. The 2-cycle erase sequence cannot be interrupted with a bus write operation. For example, to execute properly, an Erase Setup command must be immediately followed by the Erase Confirm command. If a different command is issued between the setup and confirm commands, the following occurs: * The partition is placed in read-status mode. * The status register signals a command sequence error. * All subsequent erase commands to that partition are ignored until the status register is cleared. To detect block erase completion, the CPU analyzes SR[7] of that partition. If an error bit (SR[5,3,1]) was flagged, the status register can be cleared by issuing the Clear Status Register command before attempting the next operation. The partition remains in read-status mode until another command is written to its CUI. Any CUI instruction can follow after erasing completes. The CUI can be set to read-array mode to prevent inadvertent status register reads. June 2005 70 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 32. Block Erase Flowchart BLOCK ERASE PROCEDURE Bus Command Comments Operation Block Data = 20h Write Erase Addr = Block to be erased (BA) Setup Start Write 20h Block Address Write Write D0h and Block Address Erase Confirm Read Suspend Erase Loop Read Status Register No SR[7] = 0 Suspend Erase Standby Data = D0h Addr = Block to be erased (BA) Read SRD Toggle CE# or OE# to update SRD Check SR[7] 1 = WSM ready 0 = WSM busy Yes Repeat for subsequent block erasures. 1 Full status register check can be done after each block erase or after a sequence of block erasures. Full Erase Status Check (if desired) Block Erase Complete FULL ERASE STATUS CHECK PROCEDURE Read Status Register SR[3] = Bus Command Operation 1 SR[5:4] = Standby Check SR[3] 1 = VPP error Standby Check SR[5:4] Both 1 = Command sequence error Standby Check SR[5] 1 = Block erase error VPP Range Error 0 1 Command Sequence Error 1 Block Erase Error Comments 0 SR[5] = 0 SR[1] = 0 Block Erase Successful Datasheet 1 Erase of Locked Block Aborted Check SR[1] 1 = Attempted erase of locked block Erase aborted SR[3,1] must be cleared before the WSM will allow further erase attempts. Standby Only the Clear Status Register command clears SR[5:3,1]. If an error is detected, clear the Status register before attempting an erase retry or other error recovery. Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 71 28F640W30, 28F320W30, 28F128W30 12.3 Read-While-Write and Read-While-Erase The Intel(R) Wireless Flash Memory (W30) supports flexible multi-partition dual-operation architecture. By dividing the flash memory into many separate partitions, the flash device can read from one partition while programing (Read-While-Write) or erasing (Read-While-Eras) in another partition. Both of these features greatly enhance data storage performance. The W30 flash memory device does not support simultaneous program and erase operations. Attempting to perform operations such as these results in a command sequence error. Only one partition can be programming or erasing while another partition is reading. However, one partition can be in erase suspend mode while a second partition is performing a program operation, and yet another partition is executing a read command. Table 18, "Command Codes and Descriptions" on page 53 describes the command codes available for all functions. June 2005 72 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 13.0 Security Modes The W30 flash memory device offers both hardware and software security features to protect the flash memory data. * To use the software security feature, execute the Lock Block command. * To use the hardware security feature, execute the Lock-Down Block command and assert the WP# signal. Refer to Figure 33, "Block Locking State Diagram" on page 74 for a state diagram of the flash device security features. Also see Figure 34, "Locking Operations Flowchart" on page 77. 13.1 Block Lock Operations Individual instant block locking protects code and data by allowing any block to be locked or unlocked with no latency. This locking scheme offers two levels of protection: * Software-only control of block locking (useful for frequently changed data blocks). * Hardware interaction before locking can be changed (protects infrequently changed code blocks). The following sections discuss the locking system operation. The term state [abc] specifies locking states, such as state [001]. In this syntax: * a = WP# value. * b = block lock-down status bit D1. * c = Block Lock status register bit D0. Figure 33, "Block Locking State Diagram" on page 74 defines possible locking states. The following summarizes the locking functionality. * All blocks power-up in a locked state. * Unlock commands can unlock these blocks, and lock commands can lock them again. * The Lock-Down command locks a block and prevents it from being unlocked when WP# is asserted. -- Locked-down blocks can be unlocked or locked with commands as long as WP# is deasserted. -- When WP# is asserted, previously locked-down blocks return to lock-down. -- The lock-down status bit clears only when the flash device is reset or powered-down. Block lock registers are not affected by the V PP level. These registers can be modified and read even if VPP < V PPLK. The locking status of each block can be set to locked, unlocked, and lock-down, as described in the following sections. See Figure 34, "Locking Operations Flowchart" on page 77. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 73 28F640W30, 28F320W30, 28F128W30 Figure 33. Block Locking State Diagram Power-Up/Reset Locked [X01] Locked Down 4,5 [011] Hardware Locked 5 [011] WP# Hardware Control Unlocked [X00] Software Locked [111] Unlocked [110 ] Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) WP# hardware control Notes: 1. [a,b,c] represents [WP#, D1, D0]. X = Don't Care. 2. D1 indicates block Lock -down status. - D1 = 0, Lock -down has not been issued to this block . - D1 = 1, Lock -down has been issued to this block . 3. D0 indicates block lock status. - D0 = 0, block is unlocked. - D0 = 1, block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference between Hardware Locked and Locked -Down states. B5070 13.1.1 Lock All blocks default to locked (state [x01]) after initial power-up or reset. Locked blocks are fully protected from alteration. Attempted program or erase operations to a locked block return an error in SR[1]. * To lock unlocked blocks, use the Lock Block command sequence. * To change the status of a locked block to unlocked or lock-down, use the appropriate software commands. 13.1.2 Unlock Unlocked blocks (states [x00] and [110]) can be programmed or erased. All unlocked blocks return to the locked state when the flash device is reset or powered-down. * To change the status of an unlocked block to the locked or locked-down state, use the appropriate software commands. * To unlock a locked block, write the Unlock Block command sequence if the block is not locked-down. June 2005 74 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 13.1.3 Lock-Down Locked-down blocks (state [011]) offer an additional level of write protection beyond the protection of a regular locked block. If a block is locked-down, the software cannot change the state of the block if WP# is asserted. * To lock-down a locked or unlocked block, write the Lock-Down Block command sequence. * If a block was set to locked-down, then later changed to unlocked, issue the Lock-down command before asserting WP#, to put that block back in the locked-down state. * When WP# is deasserted, locked-down blocks change to the locked state, and can then be unlocked using the Unlock Block command. 13.1.4 Block Lock Status The lock status of every block can be read in read identifier mode. Note: To enter this mode, issue the Read Identifier command to the flash device. Subsequent reads at BBA + 02h output the lock status of that block. For example, to read the block lock status of block 10, the address sent to the flash device must be 50002h (for a top-parameter device). The lowest two data bits of the read data, DQ1 and DQ0, represent the lock status. * DQ0 indicates the block lock status. This bit is set using the Lock Block command and cleared using the Block Unlock command. It is also set when entering the lock-down state. * DQ1 indicates lock-down status and is set using the Lock-Down command. The lock-down status bit cannot be cleared by software-only by a flash device reset or power-down. See Table 25. Table 25. Datasheet Write Protection Truth Table VPP WP# RST# Write Protection X X VIL Device is inaccessible VIL X VIH Word program and block erase are prohibited X VIL VIH All lock-down blocks are locked X VIH VIH All lock-down blocks can be unlocked Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 75 28F640W30, 28F320W30, 28F128W30 13.1.5 Lock During Erase Suspend Block lock configurations can be performed during an erase suspend operation, using the standard locking command sequences to unlock, lock, or lock-down a block. This feature is useful when another block requires immediate updating. To change block locking during an erase operation: 1. Write the Erase Suspend command. 2. Check SR[6] to determine that the erase operation has suspended. 3. Write the desired lock command sequence to a block. The lock status changes. 4. After completing lock, unlock, read, or program operations, resume the erase operation with the Erase Resume command (D0h). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits change immediately. When the erase operation resumes, it completes normally. Locking operations cannot occur during program suspend. Appendix A, "Write State Machine" on page 90 shows valid commands during erase suspend. 13.1.6 Status Register Error Checking Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Because locking changes require 2-cycle command sequences--for example, 60h followed by 01h to lock a block--following the Configuration Setup command (60h) with an invalid command produces a command sequence error (SR[5:4]=11b). If a Lock Block command error occurs during erase suspend, the flash device sets SR[4] and SR[5] to 1 even after the erase resumes. When erase is complete, possible errors during the erase cannot be detected from the status register, because of the previous locking command error. A similar situation occurs if a program operation error is nested within an erase suspend. 13.1.7 WP# Lock-Down Control The Write Protect signal, WP#, adds an additional layer of block security. WP# affects only blocks that previously had the Lock-Down command written to them. * After the lock-down status bit is set for a block, asserting WP# forces that block into the lock-down state [011] and prevents it from being unlocked. * After WP# is deasserted, the state of the block reverts to locked [111]. Software commands can then unlock the block (for erase or program operations) and subsequently re-lock it. Only flash device reset or power-down can clear the lock-down status bit and render WP# ineffective. June 2005 76 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Figure 34. Locking Operations Flowchart LOCKING OPERATIONS PROCEDURE Start Bus Command Operation Write 60h Block Address Write Write 01,D0,2Fh Block Address Write Optional Write 90h BBA + 02h Write (Optional) Read Block Lock Status Locking Change? Lock Setup Comments Data = 60h Addr = Block to lock/unlock/lock-down (BA) Lock, Data = 01h (Lock block) Unlock, or D0h (Unlock block) Lockdown 2Fh (Lockdown block) Confirm Addr = Block to lock/unlock/lock-down (BA) Read ID Plane Data = 90h Addr = BBA + 02h Read Block Lock Block Lock status data (Optional) Status Addr = BBA + 02h No Confirm locking change on DQ[1:0]. (See Block Locking State Transitions Table for valid combinations.) Standby (Optional) Yes Write Write FFh Partition Address Read Array Data = FFh Addr = Any address in same partition Lock Change Complete 13.2 Protection Register The W30 flash memory device includes a 128-bit Protection Register. This protection register is used to increase system security and for identification purposes. The protection register value can match the flash device to the system CPU or ASIC to prevent flash device substitution. * The lower 64 bits within the protection register are programmed by Intel with a unique number in each flash device. * The upper 64 OTP bits within the protection register are left for the customer to program. Once programmed, the customer segment can be locked to prevent further programming. Note: The individual bits of the user segment of the protection register are OTP, not the register in total. The user can program each OTP bit individually, one at a time, if desired. However, after the protection register is locked, the entire user segment is locked and no more user bits can be programmed. The protection register shares some of the same internal flash device resources as the parameter partition. Therefore, RWW is allowed only between the protection register and the main partitions. Table 26 describes the operations allowed in the protection register, parameter partition, and main partition during RWW and RWE. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 77 28F640W30, 28F320W30, 28F128W30 Table 26. Simultaneous Operations Allowed with the Protection Register Protection Register Parameter Partition Array Data Main Partitions Description Read See Description Write/Erase While programming or erasing in a main partition, the protection register can be read from any other partition. Reading the parameter partition data is not allowed if the protection register is being read from addresses within the parameter partition. See Description Read Write/Erase While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the protection registers from parameter partition addresses is not allowed. Read Read Write/Erase While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the protection registers is allowed, but only in a partition that is different from the partition being programmed or erased, and also different from the parameter partition. Write No Access Allowed Read While programming the protection register, reads are allowed only in the other main partitions. Access to the parameter partition is not allowed, because programming of the protection register can occur only in the parameter partition, so that the parameter partition exists in status mode. No Access Allowed Write/Erase Read While programming or erasing the parameter partition, reads of the protection registers are not allowed in any partition. Reads in other main partitions are supported. 13.2.1 Reading the Protection Register Writing the Read Identifier command allows the protection register data to be read 16 bits at a time from addresses shown in Table 20, "Flash Device Identification Codes" on page 57. The protection register is read from the Read Identifier command, and can be read in any partition.Writing the Read Array command returns the flash device to read-array mode. 13.2.2 Programing the Protection Register Issue the Protection Program command only at the parameter partition followed by the data to be programmed at the specified location. This command programs the upper 64 bits of the protection register 16 bits at a time. Table 20, "Flash Device Identification Codes" on page 57 shows allowable addresses. See also Figure 35, "Protection Register Programming Flowchart" on page 79. Issuing a Protection Program command outside the address space of the register results in a status register error (SR[4]=1). 13.2.3 Locking the Protection Register * PR-LK.0 is programmed to 0 by Intel to protect the unique flash device number. * PR-LK.1 can be programmed by the user to lock the user portion (upper 64 bits) of the protection register (See Figure 36, "Protection Register Locking). This bit is set using the Protection Program command to program a value of FFFDh into PR-LK. After PR-LK register bits are programmed (locked), the stored values in the protection register cannot be changed. Protection Program commands written to a locked section result in a status register error (SR[4]=1, SR[5]=1). June 2005 78 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 . Figure 35. Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Bus Command Comments Operation Protection Data = C0h Program Write Addr = Protection address Setup Start Write C0h Addr=Prot addr Write Write Protect. Register Address / Data Read Read Status Register Standby SR[7] = 1? No Protection Data = Data to program Program Addr = Protection address Read SRD Toggle CE# or OE# to update SRD Check SR[7] 1 = WSM Ready 0 = WSM Busy Protection Program operations addresses must be within the protection register address space. Addresses outside this space will return an error. Yes Repeat for subsequent programming operations. Full Status Check (if desired) Full status register check can be done after each program or after a sequence of program operations. Program Complete FULL STATUS CHECK PROCEDURE Bus Command Operation Read SRD Standby SR[4:3] = 1,1 SR[4,1] = Program Successful Datasheet 1,0 1,1 SR[1] SR[3] SR[4] 0 1 1 VPP Error VPP Range Error Standby SR[4,1] = Comments Programming Error Locked-Register Program Aborted Standby 0 0 1 Protection register program error 1 0 1 Register locked; Operation aborted SR[3] MUST be cleared before the WSM will allow further program attempts. Only the Clear Staus Register command clears SR[4:3,1]. If an error is detected, clear the status register before attempting a program retry or other error recovery. Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 79 28F640W30, 28F320W30, 28F128W30 Figure 36. Protection Register Locking 0x88 User-Programmable 0x85 0x84 Intel Factory-Programmed 0x81 PR Lock Register 0 0x80 13.3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPP Protection The Intel(R) Wireless Flash Memory (W30) provides in-system program and erase at VPPL. For factory programming, the W30 flash memory device also includes a low-cost, backwardcompatible 12 V programming feature.(See "Factory Programming" on page 63.) The EFP feature can also be used to greatly improve factory program performance, as explained in Section 11.3, "Enhanced Factory Program (EFP)" on page 63. In addition to flexible block locking, holding the VPP programming voltage low can provide hardware write protection of all flash-device blocks. If VPP is below VPPLK, program or erase operations result in an error displayed in SR[3]. (See Figure 37.) Figure 37. Examples of VPP Power Supply Configurations System supply 12 V supply VCC VPP System supply Prot# (logic signal) VCC VPP 10K * 12 V fast programming * Absolute write protection with V PP VPPLK System supply VCC * Low-voltage programming * Absolute write protection via logic signal System supply VCC (Note 1) 12 V supply VPP * Low voltage and 12 V fast programming Note: June 2005 80 VPP * Low-voltage programming If the VCC supply can sink adequate current, you can use an appropriately valued resistor. Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 14.0 Set Read Configuration Register The Set Read Configuration Register (RCR) command sets the burst order, frequency configuration, burst length, and other parameters. A two-bus cycle command sequence initiates this operation. The read configuration register data is placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. 1. The Set Read Configuration Register command is written, along with the configuration data (on the address bus). 2. A second write confirms the operation and again presents the read configuration register data on the address bus. 3. The read configuration register data is latched on the rising edge of ADV#, CE#, or WE# (whichever occurs first). This command functions independently of the applied VPP voltage. After executing this command, the flash device returns to read-array mode. To examine the contents of the read configuration register, write the Read Identifier command and then read location 05h. (See Table 27 and Table 28.) Table 27. Read Configuration Register Definitions Read Mode Res'd RM R LC2 LC1 15 14 13 12 Datasheet WAIT Polarity Data Output Config WAIT Confi g Burst Seq Clock Confi g Res' d Res' d Burst Wrap LC0 WP DOC WC BS CC R R BW BL2 BL1 BL0 11 10 9 8 7 6 5 4 3 2 1 0 First Access Latency Count Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Burst Length June 2005 81 28F640W30, 28F320W30, 28F128W30 Table 28. Read Configuration Register Descriptions Description1 Bit Name 15 RM Read Mode 14 R 13-11 LC[2:0] First Access Latency Count 001 = Reserved 010 = Code 2 011 = Code 3 10 WP WAIT Signal Polarity 0 = WAIT signal is asserted low 1 = WAIT signal is asserted high (Default) 3 9 DOC Data Output Configuration 0 = Hold Data for One Clock 1 = Hold Data for Two Clock (Default) 6 8 WC WAIT Configuration 0 = WAIT Asserted During Delay 1 = WAIT Asserted One Data Cycle before Delay (Default) 6 7 BS Burst Sequence 6 CC Clock Configuration 5 R Reserved 5 4 R Reserved 5 3 BW Burst Wrap 2-0 BL[2:0] Burst Length 0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) Reserved Notes 2,6 5 100 = Code 4 101 = Code 5 111 = Reserved (Default) 6 1 = Linear Burst Order (Default) 0 = Burst Starts and Data Output on Falling Clock Edge 1 = Burst Starts and Data Output on Rising Clock Edge (Default) 0 = Wrap bursts within burst length set by CR[2:0] 1 = Don't wrap accesses within burst length set by CR[2:0].(Default) 001 = 4-Word Burst 010 = 8-Word Burst 011 = 16-Word Burst (Available on the 130 nm lithography) 111 = Continuous Burst (Default) 4 Notes: 1. Undocumented combinations of bits are reserved by Intel for future implementations. 2. Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status Register and configuration reads support single read cycles. RCR[15]=1 disables the configuration set by RCR[14:0]. 3. Data is not ready when WAIT is asserted. 4. Set the synchronous burst length. In asynchronous page mode, the burst length equals four words. 5. Set all reserved Read Configuration Register bits to zero. 6. Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010), data hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before delay (RCR[8] =1) is not supported. June 2005 82 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 14.1 Read Mode (RCR[15]) All partitions support two high-performance read configurations: * synchronous burst mode * asynchronous page mode (default) RCR[15] sets the read configuration to one of these modes. Status register, query, and identifier modes support only asynchronous and single-synchronous read operations. 14.2 First Access Latency Count (RCR[13:11]) The First Access Latency Count (RCR[13:11]) configuration tells the flash device how many clocks must elapse from ADV# de-assertion (VIH) before driving the first data word onto its data pins. The input clock frequency determines this value. See Table 27, "Read Configuration Register Definitions" on page 81 for latency values. Figure 38 shows data output latency from ADV# assertion for different latencies. Refer to Section 14.2.1, "Latency Count Settings" on page 84 for Latency Code Settings. Figure 38. First Access Latency Configuration CLK [C] Address [A] Valid Address ADV# [V] D[15:0] [Q] D[15:0] [Q] D[15:0] [Q] D[15:0] [Q] Note: Code 2 Code 3 Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Code 4 Code 5 Valid Output Other First Access Latency Configuration settings are reserved. ) Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 83 Figure 39. Word Boundary Word 0 - 3 0 1 2 Word 4 - 7 3 4 5 Word 8 - B 6 7 8 9 Word C - F A B C D E F 16 Word Boundary 4 Word Boundary Note: The 16-word boundary is the end of the flash device sense word-line. 14.2.1 Latency Count Settings Table 29. Latency Count Settings tAVQV/tCHQV (85ns/22ns) tAVQV/tCHQV (90ns/22ns) tAVQV/tCHQV (70ns/20ns) Latency Count Settings 2 3, 4, 5 2, 3, 4, 5 2 3, 4, 5 Frequency < 31 < 33 < 40 < 29 < 33 Figure 40. Unit MHz Data Output with LC Setting at Code 3 tADD-DELAY CLK (C) 0st tDATA 2rd 1nd 3th 4th CE# (E) ADV# (V) AMAX-0 (A) Valid Address Code 3 DQ15-0 (D/Q) High Z R103 Valid Output Valid Output 28F640W30, 28F320W30, 28F128W30 14.3 WAIT Signal Polarity (RCR[10]) * If the WT bit is cleared (RCR[10]=0), then WAIT is configured to be asserted low. A 0 on the WAIT signal indicates that data is not ready and the data bus contains invalid data. * Conversely, if RCR[10] is set, then WAIT is asserted high. In either case, if WAIT is deasserted, then data is ready and valid. WAIT is asserted during asynchronous page mode reads. 14.4 WAIT Signal Function The WAIT signal indicates data valid when the flash device is operating in synchronous mode (RCR[15]=0), and when addressing a partition that is currently in read-array mode. The WAIT signal is deasserted only when data is valid on the bus. * When the flash device is operating in synchronous non-read-array mode, such as read status, read ID, or read query, WAIT is set to an asserted state, as determined by RCR[10]. See Figure 14, "WAIT Signal in Synchronous Non-Read Array Operation Waveform" on page 38. * When the flash device is operating in asynchronous page mode or asynchronous single word read mode, WAIT is set to an asserted state, as determined by RCR[10]. See Figure 10, "PageMode Read Operation Waveform" on page 34, and Figure 8, "Asynchronous Read Operation Waveform" on page 32. From a system perspective, the WAIT signal is in the asserted state (based on RCR[10]) when the flash device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or Read Status), or if the flash device is operating in asynchronous mode (RCR[15]=1). In these cases, the system software must ignore (mask) the WAIT signal, because WAIT does not convey any useful information about the validity of what is appearing on the data bus. CONDITION Datasheet WAIT CE# = VIH CE# = VIL Tri-State Active OE# No-Effect Synchronous Array Read Active Synchronous Non-Array Read Asserted All Asynchronous Read and all Write Asserted Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 85 28F640W30, 28F320W30, 28F128W30 14.5 Data Hold (RCR[9]) The Data Output Configuration (DOC) bit (RCR[9]) determines whether a data word remains valid on the data bus for one or two clock cycles. The minimum data set-up time on the processor, and the flash memory clock-to-data output delay, determine whether one or two clocks are needed. * A DOC set at 1-clock data hold corresponds to a 1-clock data cycle. * A DOC set at 2-clock data hold corresponds to a 2-clock data cycle. The setting of this configuration bit depends on the system and CPU characteristics. For clarification, see Figure 41. The following is a method for determining this configuration setting. To set the flash device at 1-clock data hold for subsequent reads, the following condition must be satisfied: tCHQV (ns) + tDATA (ns) < One CLK Period (ns) As an example, use a clock frequency of 54 MHz and a clock period of 25 ns. Assume the data output hold time is one clock. Apply this data to the formula above for the subsequent reads: 20 ns + 4 ns 25 ns This equation is satisfied, and data output is available and valid at every clock period. If tDATA is long, hold for two cycles. During page-mode reads, the initial access time can be determined using the formula: tADD-DELAY (ns)t DATA (ns) + tAVQV (ns) Subsequent reads in page mode are defined by: tAPA (ns) + tDATA (ns) Figure 41. (minimum time) Data Output Configuration with WAIT Signal Delay CLK [C] WAIT (CR.8 = 1) Note 1 tCHQV WAIT (CR.8 = 0) 1 CLK Data Hold Note 1 Valid Output DQ15-0 [Q] WAIT (CR.8 = 0) 2 CLK Data Hold Note: June 2005 86 Valid Output Note 1 tCHTL/H WAIT (CR.8 = 1) Valid Output tCHQV DQ15-0 [Q] Note 1 Valid Output Valid Output WAIT shown asserted high (RCR[10]=1). Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 14.6 WAIT Delay (RCR[8]) The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all synchronous read-array modes. This bit setting depends on the system and CPU characteristics. The WAIT can be asserted either during, or one data cycle before, a valid output. In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-word, 8-word, 16-word, or continuous-word burst mode, an output delay might occur when a burst sequence crosses its first flash device-row boundary (16-word boundary). * If the burst start address is 4-word boundary aligned, the delay does not occur. * If the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read sequence. The WAIT signal informs the system of this delay. 14.7 Burst Sequence (RCR[7]) The burst sequence specifies the synchronous-burst mode data order (see Table 30, "Sequence and Burst Length" on page 88). When operating in a linear burst mode, either 4-word, 8-word, or 16-word burst length with the burst wrap bit (RCR[3]) set, or in continuous burst mode, the flash device might incur an output delay when the burst sequence crosses the first 16-word boundary. (See Figure 39, "Word Boundary" on page 84 for word boundary description.) Whether this delay occurs depends on the starting address. * If the starting address is aligned to a 4-word boundary, there is no delay. * If the starting address is the end of a 4-word boundary, the output delay is one clock cycle less than the First Access Latency Count; this is the worst-case delay. The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. The WAIT pin informs the system of this delay. For timing diagrams of WAIT functionality, see these figures: * Figure 11, "Single Synchronous Read-Array Operation Waveform" on page 35 * Figure 12, "Synchronous 4-Word Burst Read Operation Waveform" on page 36 * Figure 13, "WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform" on page 37 Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 87 28F640W30, 28F320W30, 28F128W30 Table 30. Sequence and Burst Length Burst Addressing Sequence (Decimal) 4-Word Burst CR[2:0]=001b 8-Word Burst CR[2:0]=010b 16-Word Burst1 CR[2:0]=011b Continuous Burst CR[2:0]=111b Linear Linear Linear Linear 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3...14-15-0 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4...15-0-1 2-3-4-5-6-7-8-... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5...15-0-1-2 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6...15-0-1-2-3 4-5-6-7-8-9-10... 5 5-6-7-0-1-2-3-4 5-6-7...15-0-1...4 5-6-7-8-9-10-11... 6 6-7-0-1-2-3-4-5 6-7-8...15-0-1...5 6-7-8-9-10-11-12-... 7 7-0-1-2-3-4-5-6 7-8-9...15-0-1...6 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20-... 15 15-0-1-2-3...14 15-16-17-18-19-... 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3...15-16 1-2-3-4-5-6-7-... 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4...16-17 2-3-4-5-6-7-8-... 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5...17-18 3-4-5-6-7-8-9-... 4 4-5-6-7-8-9-1011 4-5-6...18-19 4-5-6-7-8-9-10... 5 5-6-7-8-9-10-1112 5-6-7...19-20 5-6-7-8-9-10-11... 6 6-7-8-9-10-1112-13 6-7-8...20-21 6-7-8-9-10-11-12-... 7 7-8-9-10-11-1213-14 7-8-9...21-22 7-8-9-10-11-12-13... ... 14-15...28-29 14-15-16-17-18-19-20-... 15 15-16...29-30 15-16-17-18-19-20-21-... 14.8 ... 14 ... ... No-Wrap (CR[3]=1) 0 ... Note: ... 14-15-0-1...13 ... 14 ... ... Wrap (CR[3]=0) Start Addr. (Dec) Available on the 130 nm lithography. Clock Edge (RCR[6]) Configuring the valid clock edge enables a flexible memory interface to a wide range of burst CPUs. Clock configuration sets the flash device to start a burst cycle, output data, and assert WAIT on the rising or falling edge of the clock. June 2005 88 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 14.9 Burst Wrap (RCR[3]) The burst wrap bit determines whether 4-word, 8-word, or 16-word burst accesses wrap within the burst-length boundary, or they cross word-length boundaries to perform linear accesses. No-wrap mode (RCR[3]=1) enables WAIT to hold off the system processor, as it does in the continuous burst mode, until valid data is available. In no-wrap mode (RCR[3]=0), the flash device operates similarly to continuous linear burst mode, but consumes less power during 4-word, 8-word, or 16-word bursts. For example, if RCR[3]=0 (wrap mode) and RCR[2:0] = 1h (4-word burst), possible linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2. If RCR[3]=1 (no-wrap mode) and RCR[2:0] = 1h (4-word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. RCR[3]=1 not only enables limited nonaligned sequential bursts, but also reduces power by minimizing the number of internal read operations. Setting RCR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst sequences. However, significantly more power might be consumed. The 1-2-3-4 sequence, for example, consumes power during the initial access, again during the internal pipeline lookup as the processor reads word 2, and possibly again, depending on system timing, near the end of the sequence as the flash device pipelines the next 4-word sequence. RCR[3]=1 while in 4-word burst mode (no-wrap mode) reduces this excess power consumption. 14.10 Burst Length (RCR[2:0]) The burst length is the number of words the flash device outputs in a synchronous read access. 4-word, 8-word, 16-word, and continuous-word are supported. In 4-word, 8-word, or 16-word burst configuration, the burst wrap bit (RCR[3]) determines whether burst accesses wrap within word-length boundaries, or they cross word-length boundaries to perform a linear access. After an address is specified, the flash device outputs data until it reaches the end of its burstable address space. Continuous burst accesses are linear only (burst wrap bit RCR[3] is ignored during continuous burst) and do not wrap within word-length boundaries (see Table 30, "Sequence and Burst Length" on page 88). Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 89 28F640W30, 28F320W30, 28F128W30 Appendix A Write State Machine Table 31 shows the command state transitions, based on incoming commands. Only one partition can be actively programming or erasing at a time. Table 31. Next State Table (Sheet 1 of 2) Chip Next State after Command Input Write State Machine (WSM) Next State Table Current Chip (8) Read Array Program (3) Setup (4,5) Erase Setup (4,5) Enhanced BE Confirm, Factory P/E Resume, Pgm ULB State Setup Ready (FFH) (10H/40H) (20H) (30H) Ready Program Setup Erase Setup EFP Setup Lock/CR Setup OTP (4) Ready (Lock Error) Confirm (9) (D0H) Program/ Erase Suspend Read Status (B0H) (70H) Register Read ID/Query (6) (50H) (90H, 98H) Ready Ready Setup Clear Status Ready (Lock Error) OTP Busy Busy Setup Program Program Busy Busy Program Busy Program Suspend Pgm Busy Setup Ready (Error) Erase Busy Busy Suspend Erase Suspend Pgm in Erase Susp Setup Erase Suspend Pgm Susp in Erase Susp Program in Erase Suspend Busy Program in Erase Suspend Busy Program Suspend in Erase Suspend Pgm in Erase Susp Busy Program Suspend in Erase Suspend Erase Suspend (Lock Error) Erase Susp Erase Suspend (Lock Error) EFP Busy Ready (Error) Lock/CR Setup in Erase Suspend Enhanced Factory Program Erase Busy Erase Busy Program in Erase Suspend Busy Busy Suspend Ready (Error) Erase Susp Erase Suspend Setup Program Busy Program Suspend Erase Busy Erase Program in Erase Suspend Pgm Susp Suspend Setup Ready (Error) (7) EFP Busy EFP Busy EFP Verify Verify Busy (7) Output Next State Table (1) Output Next State after Command Input Pgm Setup, Erase Setup, OTP Setup, Pgm in Erase Susp Setup, EFP Setup, EFP Busy, Verify Busy Status Lock/CR Setup, Lock/CR Setup in Erase Susp Status OTP Busy Ready, Pgm Busy, Pgm Suspend, Erase Busy, Erase Suspend, Pgm In Erase Susp Busy, Pgm Susp In Erase Susp June 2005 90 Status Array (3) Status Output does not change Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Status Output does not change ID/Query Datasheet 28F640W30, 28F320W30, 28F128W30 Table 31. Next State Table (Sheet 2 of 2) Chip Next State after Command Input Write State Machine (WSM) Next State Table Current Chip (8) State Lock, Unlock, Lock-down, CR setup Setup (5) (9) Confirm (5) (60H) (C0H) Ready Lock/CR Setup OTP Setup Lock/CR Setup Ready (Lock Error) OTP LockDown Block Lock Block OTP Write CR (9) Confirm (9) Confirm (01H) (2FH) (03H) Enhanced Fact Pgm Exit (blk add <> WA0) (XXXXH) Illegal commands or EFP data (2) (other codes) Ready Ready Ready Setup Ready N/A Ready (Lock Error) OTP Busy Busy Program Ready Setup Program Busy N/A Busy Program Busy Ready Suspend Program Suspend Setup Ready (Error) Busy Erase Suspend Program in Erase Suspend N/A Erase Busy Lock/CR Setup in Erase Susp Erase Busy Erase Suspend Setup Program in Erase Suspend Busy Busy Program in Erase Suspend Busy Suspend Lock/CR Setup in Erase Suspend Enhanced Factory Program WSM Operation Completes Ready N/A Erase Suspend Program Suspend in Erase Suspend Erase Suspend (Lock Error) Erase Susp Erase Susp Erase Susp Setup Erase Suspend (Lock Error) N/A Ready (Error) (7) EFP Busy EFP Busy EFP Verify Verify Busy (7) (7) EFP Verify EFP Busy Ready EFP Verify (7) Ready Output Next State Table (1) Output Next State after Command Input Pgm Setup, Erase Setup, OTP Setup, Pgm in Erase Susp Setup, EFP Setup, EFP Busy, Verify Busy Status Lock/CR Setup, Lock/CR Setup in Erase Susp Status Array Status OTP Busy Ready, Pgm Busy, Pgm Suspend, Erase Busy, Erase Suspend, Pgm In Erase Susp Busy, Pgm Susp In Erase Susp Status Output does not change Array Output does not change Output does not change Notes: 1. The output state shows the type of data that appears at the outputs if the partition address is the same as the command address. -- A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued. -- Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next WSM state does not depend on the output state of the partition. -- For example, if the partition #1 output state is Read Array and the partition #4 output state is Read Status, every read from partition #4 (without issuing a new command) outputs the Status register. Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 91 28F640W30, 28F320W30, 28F128W30 2. 3. 4. 5. 6. 7. 8. 9. 10. Illegal commands are any commands not defined in the command set. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in undetermined data when a partition address is read. Both cycles of two-cycle commands must be issued to the same partition address. If the two cycles are issued to different partitions, the address used for the second write cycle determines the active partition. Both partitions output status information when read. If the WSM is active, both cycles of a two-cycle command are ignored. This feature differs from previous Intel flash memory devices. The Clear Status command clears status register error bits, except when the WSM is running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend). EFP writes are allowed only when status register bit SR.0 = 0. EFP is busy if the Block Address = the address at the EFP Confirm command. Any other commands are treated as data. The current state is the state of the WSM, not the state of the partition. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then move to the Ready State. In Erase suspend mode, the only valid two-cycle commands are Program Word, Lock/Unlock/Lockdown Block, and CR Write. Both cycles of other two-cycle commands (Program OTP & confirm, EFP Setup & confirm, Erase setup & confirm) are ignored. In Program suspend or Program suspend in Erase suspend, both cycles of all two-cycle commands are ignored. June 2005 92 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Appendix B Common Flash Interface This appendix defines the data structure or database returned by the Common Flash Interface (CFI) Query command. System software parses this structure to gain critical information, such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software can determine which command sets to use to enable flash device writes, enable block erases, and otherwise control the flash device. The Query is part of an overall specification for multiple command set and control interface descriptions, which is called the Common Flash Interface, or CFI. B.1 Query Structure Output The Query database allows system software to obtain information for controlling the flash device. This section describes the flash device CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width that the flash device supports. On the W30 family of flash memory devices, the Query table device starting address is a 10h, which is a word address for x16 flash devices. For a word-wide (x16) flash device, the first two Query-structure bytes, ASCII Q and R, appear on the low byte at word addresses 10h and 11h. * This CFI-compliant flash device outputs 00h data on upper bytes. * The flash device outputs ASCII Q in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the h suffix has been dropped. In addition, because the upper byte of word-wide flash devices is always 00h, the leading 00 has been dropped from the table notation, and only the lower byte value is shown. Any x16 flash device outputs can be assumed to have 00h on the upper byte in this mode. Table 32. Summary of Query Structure Output as a Function of the Flash Device and Mode Device Device Addresses Datasheet Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Hex Offset Hex Code ASCII Value 00010: 00011: 00012: 51 52 59 Q R Y June 2005 93 28F640W30, 28F320W30, 28F128W30 Table 33. Example of Query Structure Output of x16- and x8 Flash Devices Word Addressing: Offset Hex Code AX--A0 B.2 Byte Addressing: Value D15--D 0 Offset Hex Code AX--A0 Value D7--D0 00010h 0051 "Q" 00010h 51 Q 00011h 0052 "R" 00011h 52 R 00012h 0059 "Y" 00012h 59 Y 00013h P IDLO PrVendor 00013h P IDLO PrVendor 00014h P IDHI ID # 00014h P IDLO ID # 00015h PLO PrVendor 00015h P IDHI ID # ... ... 00016h PHI TblAdr 00016h 00017h A IDLO AltVendor 00017h 00018h A IDHI ID # 00018h ... ... ... ... Query Structure Overview The Query command causes the flash device to display the Common Flash Interface (CFI) Query structure or database. Table 34 summarizes the structure sub-sections and address locations. Table 34. Query Structure Offset 00000h 00001h (2) (BA+2)h 00004-Fh 00010h 0001Bh 00027h P (3) Sub-Section Name (1) Description Manufacturer Code Device Code Block Status register Block-specific information Reserved Reserved for vendor-specific information CFI query identification string Command set ID and vendor data offset System interface information Device timing & voltage information Device geometry definition Flash device layout Vendor-defined additional information specific Primary Intel-specific Extended Query Table to the Primary Vendor Algorithm Notes: 1. Refer to the Section B.1, "Query Structure Output" on page 93 and offset 28h, for the detailed definition of the offset address as a function of the flash device bus width and mode. 2. BA = Block Address beginning location (for example, 08000h is the block 1'beginning location when the block size is 32K-word). 3. Offset 15 defines P, which points to the Primary Intel-specific Extended Query Table. June 2005 94 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 B.3 Block Status Register The Block Status Register indicates whether an erase operation completed successfully, a given block is locked, or a given block can be accessed for flash memory program/erase operations. Block Erase Status (BSR.1) allows system software to determine the success of the last block erase operation. Use BSR.1 just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. Table 35. Block Status Register Offset Length Description (1) (BA+2)h 1 Block Lock Status Register BSR.0 Block lock status 0 = Unlocked 1 = Locked BSR.1 Block lock-down status 0 = Not locked down 1 = Locked down BSR 2-7: Reserved for future use Add. Value BA+2 --00 or --01 BA+2 (bit 0): 0 or 1 BA+2 (bit 1): 0 or 1 BA+2 (bit 2-7): 0 Notes: 1. BA = Block Address beginning location (for example, 08000h is the block 1 beginning location when the block size is 32K-word). B.4 CFI Query Identification String The Identification String verifies that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). . Table 36. Datasheet CFI Identification Add. Hex Code Value Query-unique ASCII string "QRY" 10: 11: 12: --51 --52 --59 Q R Y 2 Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms 13: 14: --03 --00 15h 2 Extended Query Table primary algorithm address 15: 16: --39 --00 17h 2 Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists 17: 18: --00 --00 19h 2 Secondary algorithm Extended Query Table address. 0000h means none exists 19: 1A: --00 --00 Offset Length 10h 3 13h Description Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 95 28F640W30, 28F320W30, 28F128W30 Table 37. System Interface Information Offset Length Description 1Bh 1 1Ch 1 1Dh 1 1Eh 1 1Fh 20h 21h 22h 23h 24h 25h 26h 1 1 1 1 1 1 1 1 VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n -sec n "n" such that typical max. buffer write time-out = 2 -sec n "n" such that typical block erase time-out = 2 m-sec n "n" such that typical full chip erase time-out = 2 m-sec n "n" such that maximum word program time-out = 2 times typical n "n" such that maximum buffer write time-out = 2 times typical n "n" such that maximum block erase time-out = 2 times typical n "n" such that maximum chip erase time-out = 2 times typical June 2005 96 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Hex Add. Code Value 1B: --17 1.7V 1C: --19 1.9V 1D: --B4 11.4V 1E: --C6 12.6V 1F: 20: 21: 22: 23: 24: 25: 26: --04 16s --00 NA --0A 1s --00 NA --04 256s --00 NA --03 8s --00 NA Datasheet 28F640W30, 28F320W30, 28F128W30 B.5 Flash Device Geometry Definition Table 38. Flash Device Geometry Definition Offset 27h Length Description n 1 "n" such that device size = 2 in number of bytes Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: 28h 2Ah 2 2Ch 1 2Dh 31h 35h Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: Datasheet 2 4 4 4 7 6 5 4 3 2 1 0 -- -- -- -- x64 x32 x16 x8 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- n "n" such that maximum number of bytes in write buffer = 2 Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Reserved for future erase block region information 32 Mbit -B -T --16 --16 --01 --01 --00 --00 --00 --00 --00 --00 --02 --02 --07 --3E --00 --00 --20 --00 --00 --01 --07 --3E --00 --00 --20 --00 --00 --01 --00 --00 --00 --00 --00 --00 --00 --00 64 Mbit -B -T --17 --17 --01 --01 --00 --00 --00 --00 --00 --00 --02 --02 --07 --7E --00 --00 --20 --00 --00 --01 --07 --7E --00 --00 --20 --00 --00 --01 --00 --00 --00 --00 --00 --00 --00 --00 Code 27: See table below 28: --01 x16 29: 2A: 2B: 2C: --00 --00 --00 0 See table below 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: See table below See table below See table below 128 Mbit -B -T --18 --18 --01 --01 --00 --00 --00 --00 --00 --00 --02 --02 --07 --FE --00 --00 --20 --00 --00 --01 --07 --FE --00 --00 --20 --00 --00 --01 --00 --00 --00 --00 --00 --00 --00 --00 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 97 28F640W30, 28F320W30, 28F128W30 B.6 Intel-Specific Extended Query Table Table 39. Primary Vendor-Specific Extended Query June 2005 98 Offset(1) P = 39h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h Length (P+9)h 1 (P+A)h (P+B)h 2 3 1 1 4 (P+C)h 1 (P+D)h 1 Description (Optional flash features and commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 10-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of Optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Add. 39: 3A: 3B: 3C: 3D: 3E: 3F: 40: 41: bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 42: Hex Code Value --50 "P" --52 "R" --49 "I" --31 "1" --33 "3" --E6 --03 --00 --00 =0 No =1 Yes =1 Yes =0 No =0 No =1 Yes =1 Yes =1 Yes =1 Yes =1 Yes --01 bit 0 43: 44: bit 0 bit 1 45: =1 --03 --00 =1 =1 --18 Yes 46: --C0 12.0V Yes Yes 1.8V Datasheet 28F640W30, 28F320W30, 28F128W30 Table 40. Table 41. Protection Register Information Offset(1) P = 39h Length Description (Optional flash device features and commands) Add. Hex Code Value (P+E)h 1 Number of Protection register fields in JEDEC ID space. 00h indicates that 256 protection fields are available 47: --01 1 (P+F)h (P+10)h (P+11)h (P+12)h 4 48: 49: 4A: 4B: --80 --00 --03 --03 80h 00h 8 byte 8 byte Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection register bytes. * Some bytes are pre-programmed with flash device-unique serial numbers. * Other bytes are user programmable. Bits 0-15 point to the Protection register Lock byte, the first byte in the section. The following bytes are factory pre-programmed and user-programmable. * bits 0--7 = Lock/bytes Jedec-plane physical low address * bits 8--15 = Lock/bytes Jedec-plane physical high address * bits 16--23 = n such that 2n = factory pre-programmed bytes * bits 24--31 =n such that 2n = user programmable bytes Burst Read Information for Non-Multiplexed Flash Device (1) Table 42. Offset P = 39h (P+13)h Length (P+14)h 1 (P+15)h 1 (P+16)h (P+17)h (P+18)h 1 1 1 1 Description (Optional flash features and commands) Page Mode Read capability n bits 0-7 = "n" such that 2 HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Synchronous mode read capability configuration 1 Bits 3-7 = Reserved n+1 bits 0-2 "n" such that 2 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the Read Configuration Register bits 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 4D: --04 4 4E: --01 4 4F: 50: 51: --02 --03 --07 8 16 Cont Partition and Erase-Block Region Information (1) Offset P = 39h Description Bottom Top (Optional flash features and commands) (P+19)h (P+19)h Number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions. Datasheet Hex Add. Code Value 4C: --03 8 byte Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 See table below Address Bot Top Len 1 52: 52: June 2005 99 28F640W30, 28F320W30, 28F128W30 Table 43. Partition Region 1 Information (1) Offset P = 39h Description Bottom Top (Optional flash features and commands) (P+1A)h (P+1A)h Number of identical partitions within the partition region (P+1B)h (P+1B)h (P+1C)h (P+1C)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1D)h (P+1D)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1E)h (P+1E)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1F)h (P+1F)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+20)h (P+20)h Partition Region 1 Erase Block Type 1 Information (P+21)h (P+21)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+22)h (P+22)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+23)h (P+23)h (P+24)h (P+24)h Partition 1 (Erase Block Type 1) Minimum block erase cycles x 1000 (P+25)h (P+25)h (P+26)h (P+26)h Partition 1 (erase block Type 1) bits per cell; internal ECC bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+27)h (P+27)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+28)h Partition Region 1 Erase Block Type 2 Information (P+29)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+2A)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+2B)h (bottom parameter device only) Partition 1 (Erase block Type 2) (P+2C)h (P+2D)h Minimum block erase cycles x 1000 Partition 1 (Erase block Type 2) bits per cell (P+2E)h bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+2F)h Partition 1 (Erase block Type 2) pagemode and synchronous mode capabilities defined in Table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use June 2005 100 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 See table below Address Bot Top Len 2 53: 53: 54: 54: 1 55: 55: 1 56: 56: 1 57: 57: 1 58: 58: 4 1 59: 5A: 5B: 5C: 5D: 5E: 5F: 59: 5A: 5B: 5C: 5D: 5E: 5F: 1 60: 60: 4 1 61: 62: 63: 64: 65: 66: 67: 1 68: 2 2 Datasheet 28F640W30, 28F320W30, 28F128W30 Table 44. Partition Region 2 Information (1) Offset P = 39h Description Bottom Top (Optional flash features and commands) (P+30)h (P+28)h Number of identical partitions within the partition region (P+31)h (P+29)h (P+32)h (P+2A)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+33)h (P+34)h (P+35)h (P+36)h (P+37)h (P+38)h (P+39)h (P+3A)h (P+3B)h (P+3C)h (P+3D)h (P+3E)h (P+3F)h Datasheet See table below Address Bot Top Len 2 69: 61: 6A: 62: 1 6B: 63: (P+2B)h Simultaneous program or erase operations allowed in other 1 partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+2C)h Simultaneous program or erase operations allowed in other 1 partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+2D)h Types of erase block regions in this Partition Region. 1 x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+2E)h Partition Region 2 Erase Block Type 1 Information 4 (P+2F)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+30)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+31)h 2 (P+32)h Partition 2 (Erase block Type 1) (P+33)h Minimum block erase cycles x 1000 (P+34)h Partition 2 (Erase block Type 1) bits per cell 1 bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+35)h Partition 2 (erase block Type 1) pagemode and synchronous 1 mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+36)h Partition Region 2 Erase Block Type 2 Information 4 (P+37)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+38)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+39)h (P+3A)h Partition 2 (Erase Block Type 2) 2 (P+3B)h Minimum block erase cycles x 1000 (P+3C)h Partition 2 (Erase Block Type 2) bits per cell 1 bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserved for future use (P+3D)h Partition 2 (Erase block Type 2) pagemode and synchronous 1 mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+3E)h Features Space definitions (Reserved for future use) TBD Resv'd (P+3F)h Reserved for future use Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 6C: 64: 6D: 65: 6E: 66: 6F: 70: 71: 72: 73: 74: 75: 67: 68: 69: 6A: 6B: 6C: 6D: 76: 6E: 6F: 70: 71: 72: 73: 74: 75: 76: 77: 78: 77: 78: June 2005 101 28F640W30, 28F320W30, 28F128W30 Table 45. Partition and Erase-Block Region Information Address 52: 53: 54: 55: 56: 57: 58: 59: 5A: 5B: 5C: 5D: 5E: 5F: 60: 61: 62: 63: 64: 65: 66: 67: 68: 69: 6A: 6B: 6C: 6D: 6E: 6F: 70: 71: 72: 73: 74: 75: 76: 32 Mbit -B --02 --01 --00 --11 --00 --00 --02 --07 --00 --20 --00 --64 --00 --01 --03 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --03 64Mbit -T --02 --07 --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --03 --01 --00 --11 --00 --00 --02 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --20 --00 --64 --00 --01 --03 -B --02 --01 --00 --11 --00 --00 --02 --07 --00 --20 --00 --64 --00 --01 --03 --06 --00 --00 --01 --64 --00 --01 --03 --0F --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --03 -T --02 --0F --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --03 --01 --00 --11 --00 --00 --02 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --20 --00 --64 --00 --01 --03 128Mbit -B -T --02 --02 --01 --1F --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --07 --07 --00 --00 --20 --00 --00 --01 --64 --64 --00 --00 --01 --01 --03 --03 --06 --01 --00 --00 --00 --11 --01 --00 --64 --00 --00 --02 --01 --06 --03 --00 --1F --00 --00 --01 --11 --64 --00 --00 --00 --01 --01 --03 --07 --07 --00 --00 --00 --20 --01 --00 --64 --64 --00 --00 --01 --01 --03 --03 Notes: 1. The P variable is a pointer which is defined at CFI offset 15h. 2. TPD - Top parameter device. BPD - Bottom parameter device. 3. Partition: Each partition is 4 Mb in size. It can contain main blocks OR a combination of both main and parameter blocks. 4. Partition Region: Symmetrical partitions form a partition region. -- Partition region A. contains all partitions that are made up of main blocks only. -- Partition region B. contains the partition that is made up of the parameter and the main blocks. June 2005 102 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet 28F640W30, 28F320W30, 28F128W30 Appendix C Ordering Information Figure 42. VF BGA Ordering Information G E 2 8 F 6 4 0 W 3 0 T D 7 0 Package: Access Speed( ns) GE = VF BGA, Leaded PH = VF BGA, Pb- Free (70,85) Process Identifier : D = 0. 13 m Product Line Designator : For all Intel Flash Products Parameter Location : T = Top Parameter B = Bottom Parameter Device Density : 320 = 32Mbit 640 = 64Mbit 128 = 128Mbit W 30 = Intel(R) Wireless Flash Memory with 3 Volt I/O Flash 3 & 4 Flash 1 & 2 Flash 4 Flash 3 Flash 2 SCSP Ordering Information Flash 1 Figure 43. Product Family : P F 4 8 F 2 0 0 0 W 0 Z B Q 0 Device Details: Package: RD = SCSP , Leaded PF = SCSP, Pb- Free 0 = Initial Version Product Line: Q = QUAD+ Ballout Indicator: 48 F = Flash Only Parameter Location: T = Top Parameter B = Bottom Parameter Flash Density: 0 1 2 3 = No die = 32 Mbit = 64 Mbit = 128 Mbit Voltage: Z = 3 Volt I/ O Product Family Designator : W = Intel (R) Datasheet Wireless Flash Memory Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 June 2005 103 28F640W30, 28F320W30, 28F128W30 Table 46. I/O Voltage (V) W30 Flash Memory Family: Available Product Ordering Information Flash Density Package Size (mm) 9x7.7x1.0 Ballout Name Ballout Type Part Number Leaded GE28F320W30BD70 GE28F320W30TD70 GE28F320W30BD85 GE28F320W30TD85 Lead Free PH28F320W30BD70 PH28F320W30TD70 Lead Free PF48F1000W0ZBQ0 PF48F1000W0ZTQ0 Leaded GE28F640W30BD70 GE28F640W30TD70 Lead Free PH28F640W30BD70 PH28F640W30TD70 VF BGA 32 Mbit 10x8x1.2 SCSP 3.0 9x7.7x1.0 VF BGA 64 Mbit 10x8x1.2 SCSP Lead Free PF48F2000W0ZBQ0 PF48F2000W0ZTQ0 9x11x1.0 VF BGA Leaded GE28F128W30BD70 GE28F128W30TD70 10x8x1.2 SCSP Leaded RD48F3000W0ZBQ0 RD48F3000W0ZTQ0 128 Mbit June 2005 104 Intel(R) Wireless Flash Memory (W30) Order Number: 290702, Revision: 011 Datasheet