VPC3205C - Micronas Semiconductor

VPC 3205C,

VPC 3215C

Video Processor Family

Edition Oct. 19, 1998

6251-457-2PD

PRELIMINARY DATA SHEET

MICRONAS

VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET
2Micronas
Contents
Page Section Title
1. Introduction
1.1. System Architecture
1.2. Video Processor Family
1.3. VPC Applications
2. Functional Description
2.1. Analog Front-End
2.1.1. Input Selector
2.1.2. Clamping
2.1.3. Automatic Gain Control
2.1.4. Analog-to-Digital Converters
2.1.5. Digitally Controlled Clock Oscillator
2.1.6. Analog Video Output
2.2. Adaptive Comb Filter
2.3. Color Decoder
2.3.1. IF-Compensation
2.3.2. Demodulator
2.3.3. Chrominance Filter
2.3.4. Frequency Demodulator
2.3.5. Burst Detection
2.3.6. Color Killer Operation
2.3.7. PAL Compensation/1-H Comb Filter
2.3.8. Luminance Notch Filter
2.3.9. Skew Filtering
2.4. Horizontal Scaler
2.5. Blackline Detector
2.6. Control and Data Output Signals
2.6.1. Line-Locked Clock Generation
2.6.2. Sync Signals
2.6.3. DIGIT3000 Output Format
2.6.4. Line-Locked 4:2:2 Output Format
2.6.5. Line-Locked 4:1:1 Output Format
2.6.6. Output Code Levels
2.6.7. Output Signal Levels
2.6.8. Test Pattern Generator
2.6.9. Priority Bus Codec
2.7. PAL+ Support
2.7.1. Output Signals for PAL+/Color+ Support
2.8. Video Sync Processing
3. Serial Interface
3.1. I2C-Bus Interface
3.2. Control and Status Registers
3.2.1. Calculation of Vertical and East-West Deflection Coefficients
3.2.2. Scaler Adjustment

Contents, continued
Page Section Title
PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C
Micronas 3
4. Specifications
4.1. Outline Dimensions
4.2. Pin Connections and Short Descriptions
4.3. Pin Descriptions (pin numbers for PLCC68 package)
4.4. Pin Configuration
4.5. Pin Circuits
4.6. Electrical Characteristics
4.6.1. Absolute Maximum Ratings
4.6.2. Recommended Operating Conditions
4.6.3. Recommended Crystal Characteristics
4.6.4. Characteristics
4.6.4.1. Characteristics, 5 MHz Clock Output
4.6.4.2. Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1)
4.6.4.3. Characteristics, Reset Input, Test Input
4.6.4.4. Characteristics, Priority, FPDAT Input/Output
4.6.4.5. Characteristics, VGAV Input
4.6.4.6. Characteristics, I2C Bus Interface
4.6.4.7. Characteristics, Analog Video Inputs
4.6.4.8. Characteristics, Analog Front-End and ADCs
4.6.4.9. Characteristics, Output Pin Specification
4.6.4.10. Characteristics, Input Pin Specification
4.6.4.11. Characteristics, Clock Output Specification
5. Application Circuit
5.1. VGA mode with VPC3215C
6. Data Sheet History

VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

4Micronas

Video Processor Family

Release Note: Revision bars indicate significant

changes to the previous edition.

1. Introduction

The VPC 32x5 is a high-quality, single-chip video

front-end, which is targeted for 4:3 and 16:9, 50/60 and

100/120 Hz TV sets. It can be combined with other

members of the DIGIT3000 IC family (such as CIP

3250A, DDP 3300A, TPU 3040) and/or it can be used

with 3rd-party products.

The main features of the VPC 32x5 are

– all-digital video processing

– high-performance adaptive 4H comb filter Y/C sepa-

rator with adjustable vertical peaking

– multi-standard color decoder PAL/NTSC/SECAM

including all substandards

– 4 composite, 1 S-VHS input, 1 composite output

– integrated high-quality A/D converters and associ-

ated clamp and AGC circuits

– multi-standard sync processing

– linear horizontal scaling (0.25 ... 4), as well as

non-linear horizontal scaling ‘panorama vision’

– PAL+ preprocessing (VPC 3215)

– line-locked clock, data and sync output (VPC 3215)

– display/deflection control (VPC 3205)

– submicron CMOS technology

–I

2C-Bus Interface

– one 20.25 MHz crystal, few external components

– 68-pin PLCC package

1.1. System Architecture

Fig. 1–1 shows the block diagram of the video proces-

sor.

1.2. Video Processor Family

The VPC video processor family supports 15/32 kHz

systems and is available with different comb filter

options. The 50 Hz/single scan versions provide con-

trolling for the display and the vertical/east west deflec-

tion of DDP 3300A. The 100 Hz/double scan versions

have a line-locked clock output interface and the

PAL+ preprocessing option. Table 1–1 gives an over-

view of the VPC video processor family.

Fig. 1–1: VPC 32x5C block diagram

Table 1–1: VPC Processor Family

Features 50 Hz/

single scan 100 Hz/

double scan

4H comb filter VPC 3205C VPC 3215C

2H comb filter VPC 3200A VPC 3210A

no comb filter VPC 3201A VPC 3211A

Adaptive

Combfilter

V2/Y

CVBS

Out

Output

Formatter

Horizontal

Scaler

Panorama

mode

NTSC

PAL

SECAM

Color

Decoder

2*ADC,

8 bit

Front-End

I2C

20.25

MHz

Clock Gen.

DCO

Sync Processing

line-locked clock synthesis

YUV

clock

H/V

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 5

1.3. VPC Applications

Fig. 1–2 depicts several VPC applications. Since the

VPC functions as a video front-end, it must be comple-

mented with additional functionality to form a complete

TV set.

The DDP 33x0 contains the video b ack-end with video

postprocessing (contrast, peaking, DTI,...), H/V-deflec-

tion, RGB insertion (SCART, Text, PIP,...) and tube

control (cutoff, white drive, beam current limiter). It

generates a beam scan velocity modulation output

from th e digital YCrCb and RG B signals. Note that this

signal is not generated from the external analog RGB

inputs.

The CIP 3250A provides a high quality analog RGB

interface with character insertion capability. This allows

appropriate processing of external sources, such as

MPEG2 set-top boxes in transparent (4:2:2) quality.

Furthermore, it translates RGB/Fastblank signals to

the common digital video bus and makes those signals

available for 100 Hz upconversion or double scan pro-

cessing. In some European countries (Italy), this fea-

ture is mandatory.

The IP indicates memory based image processing,

such as scan rate conversion, vertical processing

(Zoom), or PAL+ reconstruction.

Examples:

–Europe: 15 kHz/50 Hz → 32 kHz/100 Hz interlaced

–US: 15 kHz/60 Hz → 32 kHz/60 Hz non-interlaced

Note that the VPC supports memory based applica-

tions through line-locked clocks, syncs, and data. CIP

may run either with the native DIGIT3000 clock but

also with a line-locked clock system.

Fig. 1–2: VPC 32xx applications

a) 15 kHz application Eur ope

b) double scan application (US, Japan)

c) 100 Hz application (Europe) with RGB inputs

RGB

H/V

RGB

Defl.

H/V

Defl.

DDP

3310B

DDP

3310B

DDP

3300A

VPC

321x

CIP

3250A

VPC

321x

CVBS

RGB

CVBS

RGB

VPC

320x

VPC 3205C, VPC 3215C PRELIMINAR Y DATA SHEET

6Micronas

2. Functional Description

2.1. Analog Front-End

This block provides the analog interfaces to all video

inputs and mainly carries out analog-to digital conver-

sion for the following digital video processing. A block

diagram is given in Fig. 2–1.

Most of the functional blocks in the front-end are digi-

tally controlled (clamping, AGC, and clock-DCO). The

control loops are closed by the Fast Processor (‘FP’)

embedded in the decoder.

2.1.1. Input Selector

Up to five analog inputs can be connected. Four inputs

are for input of composite video or S-VHS luma signal.

These in puts are clamped to the sync back p orch and a re

amplified by a variable gain amplifier. One input is for

connection of S-VHS carrier-chrominance signal. This

input is internally biased an d has a fix ed gain amplif ier.

2.1.2. Clamping

The composite video input signals are AC coupled to

the IC. The clamp ing volta ge is sto red on the coupling

capaci tors and is generate d by digitally controlled cur -

rent sources. The clamping level is the back porch of

the video signal. S-VHS chroma is also AC coupled.

The input pin is internally biased to the center of the

ADC input range.

2.1.3. Automatic Gain Control

A digitally working automatic gain control adjusts the

magnitude of the selected baseband by +6/–4.5 dB in

64 logarithmic steps to the optimal range of the ADC.

The gain of the video input stage including the ADC is

213 steps/V with the AGC set to 0 dB.

2.1.4. Analog-to-Digital Converters

Two ADCs are provided to digitize the input signals.

Each converter runs with 20.25 MHz and has 8 bit res-

olution. An integrated bandgap circuit generates the

required reference voltages for the converters. The

two ADCs are of a 2-stage subranging type.

2.1.5. Digitally Controlled Clock Oscillator

The clock generation is also a par t of the analog front

end. The crystal oscillator is controlled digitally by the

contr ol proces so r; the c lo ck f re que nc y can be ad j us t ed

within ±150 ppm.

2.1.6. Analog Video Output

The input signal of the Luma ADC is available at the

analog v ideo ou tput pin . The sig nal at th is pi n must be

buffered by a source follower. The output voltage is

2 V, thus the signal can be used to drive a 75 Ω line.

The magnitude is adjusted with an AGC in 8 steps

together with the main AGC.

Fig. 2–1: Analog front-end

VIN3

VIN2

VIN1

CIN

VIN4

bias ADC

ADC

gain

clamp

input

frequency

reference

generation

DVCO

±150

ppm

AGC

+6/–4.5 dB

di gital CVBS or Luma

digital Chroma

system cl oc ks

20.25 MHz

Analog Video

Output

CVBS/Y

Chroma

mux

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 7

2.2. Adaptive Comb Filter

The 4H adaptive comb filter is used for high-quality

luminance/chrominance separation for PAL or NTSC

compos ite video s ignals. The c omb filter i mproves the

luminance resolution (bandwidth) and reduces interfer-

ences like cross-luminance and cross-color. The adap-

tive algori thm eliminat es most of the men tioned erro rs

without introducing new artifacts or noise.

A block diagram of the comb filter is shown in Fig. 2–2.

The fil ter uses four line delays to process the i nfor ma-

tion of three video lines. To have a fixed phase rela-

tionship of the color subcarrier in the three channels,

the system clock (20.25 MHz) is fractionally locked to

the color subcarrier. This allows the processing of all

color s tandar ds an d substa ndard s using a si ngle crys-

tal frequency.

The CVBS signal in the three channels is filtered at the

subcarrier frequency by a set of bandpass/notch fil-

ters. The output of the three channels is used by the

adaption logic to select the weighting that is used to

reconstruct the luminance/chrominance signal from

the 4 bandpass/notch filter signals. By using soft mix-

ing of the 4 signals switching artifacts of the adaption

algorithm are completely suppressed.

The comb filter uses the middle line as reference,

therefore, the comb filter delay is two lines. If the comb

filter is switched off, the delay lines are used to pass

the luma/chroma signals from the A/D converters to

the luma/chroma outputs. Thus, the processing delay

is always two lines.

In order to obtain the best-suited picture quality , the

user has the possibility to influence the behaviour of

the adaption algorithm going from moderate combing

to strong combing. Therfore, the following three para-

meters may be adjusted:

–HDG ( horizontal difference gain )

–VDG ( vertical difference gain )

–DDR ( diagonal dot reducer )

HDG ty pically d efines the c omb str ength on h orizontal

edges. It determines the amount of the remaining

cross- luminance and the shar pness on edges re spec-

tively. As HDG increases, the comb strength, e. g.

cross luminance reduction and sharpness, increases.

VDG ty picall y deter mines the comb filter b ehaviour on

vertical edges. As VDG increases, the comb strength,

e. g. the amount of hanging dots, decreases.

After selecting the combfilter performance in horizontal

and vertical direction, the diagonal picture perfor-

mance m ay fur t her be o pti mized by adjustin g DDR. As

DDR increases, the dot crawl on diagonal colored

edges is reduced.

To enhance the vertical resolution of the the picture,

the VPC 32x5 provides a vertical peaking circuitry. The

filter gain is adjustable between 0 – +6 dB and a coring

filter suppresses small amplitudes to reduce noise arti-

facts. In relatio n to the c omb fi lter, this ver ti cal peaking

wide ly con tr ibutes to an opt ima l two-dim ensio nal reso -

lution hom oge nei ty.

2.3. Color Decoder

In this block, the standard luma/chroma separation

and multi-standard color demodulation is carried out.

The color demodulation uses an asynchronous clock,

thus allowing a unified architecture for all color stan-

dards.

A block diagram of the color decoder is shown in Fig.

2–4. The luma as well as the chroma processing, is

shown here. The color decoder also provides several

special modes, e.g. wide band chrom a format whi ch is

intended for S-VHS wide bandwidth chroma. Also, fil-

ter se ttings ar e available for processi ng a PAL+ helper

signal.

If the adaptive comb filter is used for luma chroma

separation, the color decoder uses the S-VHS mode

processing. The output of the color decoder is YCrCb

in a 4:2:2 format.

Fig. 2–2: Block diagram of the adaptive comb filter (PAL mode)

2H Delay Line

CVBS Input

Chroma Input

Bandpass

Bandpass/

Luma / Chroma Mixers

Luma Outpu t

Chroma Output

Filter

Notch Filter

Bandpass

Filter

Adaption Log ic

VPC 3205C, VPC 3215C PRELIMINAR Y DATA SHEET

8Micronas

2.3.1. IF-Compensation

With off-air or mistuned reception, any attenuation at

higher frequencies or asymmetry around the color sub-

carrier is compensated. Four different settings of the

IF-compensation are possible (see Fig. 2–3):

–flat (no compensation)

–6 dB/octave

–12 dB/octave

–10 dB/MHz

The last setting gives a very large boost to high fre-

quencies. It is provided for SECAM signals that are

decoded using a SAW filter specified originally for the

PAL standa rd .

Fig. 2–3: Frequency response of chroma IF-com-

pensation

2.3.2. Demodulator

The entire signal (which might still contain luma) is

quadrature-mixed to the baseband. The mixing fre-

quency is equal to the subcarrier for PAL and NTSC,

thus ach ieving the chroma dem odu lati on . For SECAM,

the mixing frequency is 4.286 MHz giving the quadra-

ture baseband components of the FM modulated

chroma. After the mixer, a lowpass filter selects the

chroma components; a downsampling stage converts

the color difference signals to a multiplexed half rate

data stream.

The su bcarr ier freque ncy in th e demodula tor is gene r-

ated by direct digital synthesis; therefore, substan-

dards such as PAL 3.58 or NTSC 4.43 can also be

demodulated.

2.3.3. Chrominance Filter

The demodulation is followed by a lowpass filter for the

color difference signals for PAL/NTSC. SECAM re-

quires a mod ified lowpas s func tion wi th bel l-filter cha r-

acteristic. At the output of the lowpass filter, all luma

information is eliminated.

The lowpass filters are calculated in time multiplex for

the two color signals. Three bandwidth settings (nar-

row, normal, broad) are available for each standard

(see Fig. 2–5). For PAL/NTSC, a wide band chroma fil-

ter can be selected. This filter is intended for high

bandwidth chroma signals, e.g. a nonstandard wide

bandwidth S-VHS signal.

Fig. 2–4: Color decoder

ColorPLL/ColorACC

1 H Delay

MUXMUX

CrossSwitch

Notch

Filter

Luma / CVBS Luma

Chroma

MIXER Lowpass Filter

Phase/Freq

Demodulator

ACC

Chroma

IF Compensation

DC-Reject

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 9

Fig. 2–5: Frequency response of chroma filters

2.3.4. Frequency Demodulator

The frequency demodulator for demodulating the SE-

CAM si gnal is implemented as a CORDIC -struc ture. It

calculat es the phase and magnitud e of the quadrature

components by coordinate rotation.

The phase output of the CORDIC processor is differ-

entiated to obtain the demodulated frequency. After

the deemphasis filter, the Dr and Db signals are scaled

to standard CrCb amplitudes and fed to the cross-

over-switch.

2.3.5. Burst Detection

In the PAL/NTSC-system the burst is the reference for

the color signal. The phase and magnitude outputs of

the CORDIC are gated with the color key and used for

controlling the phase-lock-loop (APC) of the demodula-

tor and the automatic color cont rol (ACC) in PAL/NTSC .

The ACC has a control range of +30 ... –6 dB.

For SECAM decoding, the frequency of the burst is

measur ed. Thu s, the cu rrent c hroma c arr ier freque ncy

can be identified and is used to control the SECAM

processing. The burst measurements also control the

color killer operation; they can be used for automatic

standard detection as well.

2.3.6. Color Killer Operation

The color killer uses the burst-phase/burst-frequency

measur em ent to id enti fy a PAL/NTSC or S ECA M c olo r

signal . For PAL/NTSC, the co lor is switched off (kil led)

as long as the color subcarrier PLL is not locked. For

SECAM, the killer is controlled by the toggle of the

burst frequency. The burst amplitude measurement is

used to switch-off the color if the burst amplitude is

below a programmable threshold. Thus, color will be

killed for very noisy signals. The color amplitude killer

has a programmable hysteresis.

2.3.7. PAL Compensation/1-H Comb Filter

The col or decoder us es one fully in tegrated delay line.

Only active video is stored.

The delay line application depends on the color stan-

dard:

–NTSC: 1-H comb filter or color compensation

–PAL: colo r com pensation

–SECAM: crossover-switch

In th e N TS C c om p en sa t ed m od e, F ig . 2–6 c), the color

signal is averaged for two adjacent lines. Thus,

cross- color disto r tion and chrom a noise is reduc ed. In

the N TSC 1-H comb filter m ode, Fig . 2–6 d), the delay

line is in the composite signal path, thus allowing

reduction of cross-color components, as well as

cross-luminance. The loss of vertical resolution in the

lumina nce chan nel is com pensated by add ing the ver-

tical de tail sign al with r emoved color information . If the

4H adaptive comb filter is used, the 1-H NTSC comb

filter has to be deselected.

PAL/NTSC

SECAM

VPC 3205C, VPC 3215C PRELIMINAR Y DATA SHEET

10 Micronas

Fig. 2–6: NTSC color decoding options

Fig. 2–7: PAL color decoding options

Fig. 2–8: SECAM color decoding

2.3.8. Luminance Notch Filter

If a composite video signal is applied, the color infor-

mation is suppressed by a programmable notch filter.

The position of the filter center frequency dep ends on

the subcarrier frequency for PAL/NTSC. For SECAM,

the notch is directly controlled by the chroma carrier

frequency. This considerably reduces the cross-lumi-

nance. Th e frequenc y responses for all three sys tems

are shown in Fig. 2–9.

Fig. 2–9: Frequency responses of the luma

notch filte r for PAL, NTSC, SECAM

2.3.9. Skew Filtering

The sy stem cl ock is free- runn ing and not locked to th e

TV line frequency. Therefore, the ADC sampling pat-

tern is not orthogonal. The decoded YCrCb sign al s ar e

converted to an orthogonal sampling raster by the

skew filters, which are part of the scaler block.

The skew filters are controlled by a skew parameter

and allow the application of a group delay to the input

signals without introducing waveform or frequency

response distortion.

The am ount of phas e shift of th is filter is c ontrolled by

the hor izontal PLL1. The ac curacy of the fil ters is 1/32

clocks for luminance and 1/4 clocks for chroma. Thus

the 4:2:2 YCrCb data is in an orthogonal pixel format

even in the case of no nstandard input s ignals such as

VCR.

chroma

Notch

filter

Chroma

Process.

CVBS Y

1 H

Delay

CVBS

Chroma

Process.

Notch

filter Y

Chroma

Process.

Luma Y

8C C

r b

C C

r b

C C

r b

Notch

filter

1 H

Delay

Chroma

Process.

CVBS Y

C C

r b

d) comb filter

c) compensated

a) conventional b) S-VHS

Chroma

Notch

filter

1 H

Delay

Chroma

Process.

CVBS Y

Chroma

Process.

Luma Y

81 H

Delay

C C

r b

C C

r b

a) conv enti ona l

b) S-VHS

MUX

Notch

filter

1 H

Delay

Chroma

Process.

CVBS Y

C C

r b

MHz

024 68 10

–10

–20

–30

–40

MHz

024 68 10

–10

–20

–30

–40

PAL/NTSC notch filter

SECAM notch filter

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 11

2.4. Horizontal Scaler

The 4:2:2 YCr Cb signal from the co lor decoder is pro-

cessed by the horizontal scaler. The scaler block

allows a linear or nonlinear horizontal scaling of the

input video signal in the range of 0.25 to 4. Nonlinear

scaling, also called “panorama vision”, provides a

geometrical distortion of the input picture. It is used to

fit a picture with 4:3 format on a 16:9 screen by stretch-

ing the picture geometry at the borders. Also, the

inverse effect can be produced by the scaler. A sum-

mary of scaler modes is given in Table 2–1.

The scaler contains a programmable decimation filter,

a 1-li ne FIFO memor y, and a programmable inter pola-

tion filter. The scaler input filter is also used for pixel

skew correction, see 2.3.9. The decimator/interpolator

str uct ure al lows op tim al us e of the F IFO m emo ry. The

controlling of the scaler is done by the internal Fast

Processor.

2.5. Blackline Detector

In ca se of a letterbox for mat input v ideo, e.g. Cinema-

scope, PAL+ etc., black areas at the upper and lower

part of the picture are visib le . It is suitable to remove or

reduce these areas by a vertical zoom and/or shift

operation.

The VPC 32xx supports this feature by a letterbox

detector. The circuitry detects black video lines by

measuring the signal amplitude during active video.

For every field the number of black lines at the upper

and lower par t of the picture ar e measured, co mpared

to the previous measurement and the minima are

stored in the I2C-register BLKLIN. To adjust the picture

amplitude, the external controller reads this register,

calcu lates the ver tical scali ng coefficient and transfers

the new settings, e.g. vertical sawtooth parameters,

horizontal scaling coefficient etc., to the VPC.

Letterbox signals containing logos on the left or right

side of the black areas are processed as black lines,

while subtitles, inserted in the black areas, are pro-

cessed as non-black lines. Therefore the subtitles are

visible on the screen. To suppress the subtitles, the

vertical zoom coefficient is calculated by selecting the

larger number of black lines only. Dark video scenes

with a low contrast level compared to the letterbox

area are indicated by the BLKPIC bit.

2.6. Control and Data Output Signals

The VPC 32xx supports two output modes: In

DIGIT3000 mode, the output interfaces run at the main

syste m clock, in line-locked mode, the VPC generates

an asynchronous line-locked clock that is used for the

output interfaces.

2.6.1. Line-Locked Clock Generation

An on-chip rate multiplier will be used to synthesize

any desired output clock frequency of 13.5/16/18 MHz.

A double clock frequency output is a vailable to support

100 Hz systems. The synthesizer is controlled by the

embedded RISC controller, which also controls all

front-end loops (clamp, AGC, PLL1, etc.). This allows

the ge neration of a line- locked outpu t clock regardles s

of the system clock (20.25 MHz) which is used for

comb filter operation and color decoding. The control

of scal ing and output c lock freq uency is kept indepen-

dent to allow aspect ratio conversion combined with

sample rate conversion. The line-locked clock circuity

gene rates con trol sign als, e.g. hor i zontal/ver tic al syn c,

active video output, it is also the interface from the

internal (20.25 MHz) clock to the external line-locked

clock sys tem.

If no line-locked clock is required, i.e. in the DIGIT3000

mode, the system runs at the 20.25 MHz main clock.

The horizontal timing reference in this mode is pro-

vided by the front-sync signal. In this case, the

line-locked clock block and all interfaces run from the

20.25 MHz main clock. The synchronization signals

from the line-locked clock block are still available, but

for every line the internal counters are reset with the

main-sync signal. A double clock signal is not available

in DIGIT 3000 mode.

Table 2–1: Scaler modes

Mode Scale

Factor Description

Compression

4:3 → 16:9 0.75

linear 4:3 source displayed on

a 16:9 tube,

with side panels

Panorama

4:3 →16:9 non-

linear

compr

4:3 source displayed on

a 16:9 tube,

Borders distorted

Zoom

4:3 → 4:3 1.33

linear Letterbox source (PAL+)

displayed on a 4:3 tube,

vertical overscan with

cropping of side panels

Panorama

4:3 → 4:3 non-

linear

zoom

Letterbox source (PAL+)

displayed on a 4:3 tube,

vert ical overscan, bor-

ders distorted, no crop-

ping

20.25 →

13.5 MHz 0.66 sample rate conversion

to line-locked clock

VPC 3205C, VPC 3215C PRELIMINAR Y DATA SHEET

12 Micronas

2.6.2. Sync Signals

The front end will provide a number of sync/control sig-

nals which are output with the output clock. The sync

signals are generated in the line-locked clock block.

–Href : horizontal sync

–AVO: active video out (programmable)

–HC: horizontal clamp (programmable)

–Vref : vertical sync

–INTLC: interlace

–HELPER: PAL+ helper lines

All horizontal signals are not qualified with field infor-

mation, i.e. the signals are present on all lines. The

horizontal timing is shown in Fig. 2–10. Details of the

horizontal/vertical timing are given in Fig. 2–14.

2.6.3. DIGIT3000 Output Format

The picture bus format between all DIGIT3000 ICs is

4:2:2 YCrCb with 20.25 MHz samples/s. Only active

video i s transferred, sy nchronized by the syst em main

sync signal (MSY) which indicates the start of valid

data for each scan line and which initializes the color

multiplex. The video data is orthogonally sampled

YCrCb, the output format is given in Table 2–2. The

number of active samples per line i s 1080 for all st an-

dards (525 and 625).

The output can be switched to 4:1:1 mode with the out-

put format according to Table 2–3.

Via the M SY line, serial d ata is transferred which con-

tains information about the main picture such as cur-

rent line number, odd/even field etc.). It is generated

by the deflection circuitry and represents the or thogo-

nal timebase for the entire system.

2.6.4. Line-Locked 4:2:2 Output Format

In line-locked mode, the VPC 32xx will produce the

industry standard pixel stream for YCrCb data . The d if-

ference to DIGIT30 00 native mode is onl y the number

of active samples, which of course, depends on the

chosen scalin g factor. Thus, Table 2–2 is valid for both

4:2:2 modes.

2.6.5. Line-Locked 4:1:1 Output Format

The orthogonal 4:1:1 output f ormat is compatible to the

industry standard. The YCrCb samples are skew-cor-

rected and in terpola t ed to an orthog ona l sa mpl in g ras-

ter (see Table 2–3).

note: C*xY (x = pixel number and y = bit number)

2.6.6. Output Code Levels

Output Code Levels correspond to ITU-R code levels:

Y = 16...240

Black Level = 16

CrCb = 128±112

An overview over the output code levels is given in

Table 2–4.

2.6.7. Output Signal Levels

All data and sync lines operate at TTL compliant lev-

els. With an opt ional exter nal 3.3 V supply for the out-

put pins, reduced voltage swings can be obtained.

2.6.8. Test Pattern Generator

The YCrCb outputs can be switched to a test mode

where YCrCb data are generated digitally in the

VPC32xx. Test patterns include luma/chroma ramps,

flat field, and a pseudo color bar.

Table 2–2: Orthogonal 4:2:2 output format

Luma Y1Y2Y3Y4

Chroma Cb1 Cr1 Cb3 Cr3

Table 2–3: 4:1:1 Orthogonal output format

Luma

Chroma Y1Y2Y3Y4

C3, C7

C2, C6

C1, C5

C0, C4

Cb17

Cb16

Cr17

Cr16

Cb15

Cb14

Cr15

Cr14

Cb13

Cb12

Cr13

Cr12

Cb11

Cb10

Cr11

Cr10

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 13

2.6.9. Priority Bus Codec

The V PC d ata ou tp uts are co nt roll ed b y the priority bus

interface. This interface allows a maximum of 8 signa l

sources to be connected on a common video YCrCb

bus. The 3-bit priority bus signal controls the arbitra-

tion and source switching of the video sources on a

pixel-by-pixel basis. The priority bus makes features

possible, such as

–real time digital PIP insertion

–Teletext/Mixed-mode picture insertion.

In general, each source has its own YCrCb bus

request. This bus request may either be software or

hardware co ntrolled , i.e. a fast blank signal. Data c olli-

sion on the bus is avoided by a bus arbiter that pro-

vides the individual bus grant in accordance to the

user defined source priority.

Each master sends a bus request using his individual

priority ID onto the bus and immediately reads back

the bus state . Only in case of a positive arbitration, e.g.

the master reads back his own priority ID, the bus is

granted to the master.

2.7. PAL+ Support

For PAL+ , the V PC 3 21x provide s ba sic hel per pr epr o-

cessing:

–A/D conversion (shared with the existing ADCs)

–mixing with subcarrier frequency

–lowpass filter 2.5 MHz

–gain control by chroma ACC

–delay compensation to composite video path

–helper window (line# identification)

–output at the luma output port

Help er signa ls ar e pro cessed l ike the main vi deo lu ma

signals, i.e. they are subject to scaling, sample rate

conversion and orthogonalization if activated. The

adaptive comb filter processing is switched off for the

helper lines.

It is expected that fur ther helpe r processing (e.g. non-

linear expansion, matched filter) is performed outside

the VPC.

2.7.1. Output Signals for PAL+/Color+ Support

For a PAL+/Color+ signal, the 625 line PAL image con-

tains a 16/9 core picture of 431 lines which is in stan-

dard PAL format. The upper and lower 72 lines contain

the PAL+ helper sign al, and line 23 contains signalling

information for the PAL+ transmission.

For PAL+ mode, the Y signal of the core picture, which

is during lines 60–274 and 37 2–586, is replac ed by the

orthogonal composite video input signal. In order to fit

the sign al to the 8-bit port width, the ADC signal am pli-

tudes are used. During the helper window, which is in

lines 24–59, 275–310, 336–371, 58 7–622, the demodu-

lated helper is signal processed by the horizontal scaler

and the output circuitry. It is available at the luma output

port. The processing in the helper reference lines 23

and 623 is different for the wide screen signaling part

and the black reference and helper burst signals. The

code levels are given in detail in Table 2–4, the output

signal f or the helper ref erence line is shown in Fig. 2–11.

Table 2–4: Output signal code levels for PAL/PAL+ signal

Output Signal Luma Outputs Y[7:0] Chroma Outputs C[7:0]

Output Format Black/Zero

Level Amplitude Output Format Amplitude

Standard YCrCb

(100% Chroma binary 16 224 offset binary 128±112

signed ±112

CVBS, CrCb binary 64 149 (luma) offset binary 128±112

signed ±112

Demodulated

Helper signed 0 ±109 ––

Helper WSS binary 68 149 (WSS:106) ––

Helper b lack level,

Ref. Burst offset binary 128 19 (128–109) ––

VPC 3205C, VPC 3215C PRELIMINAR Y DATA SHEET

14 Micronas

Fig. 2–10: Horizontal timing for line-locked mode

Fig. 2–11: PAL+ helper reference line output signal

131

line length (programmable)0

line length/2

horizontal pixel counter

horizontal sync (HS)

horizontal clamp (HC)

newline (internal signal)

active video out (AVO)

vertical sync (VS), field 1

vertical sync (VS), field 2

field 1

field 2

start / stop programmable

start of video output (programmable)

start / stop programmable

174

255

Helper Burst

(demodulated)

WSS Signal

128

binary format

255

signed format

black level

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 15

2.8. Video Sync Processing

Fig. 2–12 shows a block diagram of the front-e nd sync

processing. To extract the sync information from the

video signal, a linear phase lowpass filter eliminates all

noise and video contents above 1 MHz. The sync is

separated by a slicer; the sync phase is measured. A

variable window can be selected to improve the noise

immunity of the slicer. The phase comparator mea-

sures the f alling edge of sync, as well as the integrated

sync pul se.

The sync phase error is filtered by a phase-locked loop

that is computed by the FP. All timing in the front-end is

derived from a counter that is part of this PLL, and it

thus counts synchronously to the video signal.

A separate hardware block measures the signal back

porch and also allows gathering the maximum/mini-

mum of the video signal. This information is processed

by the FP and used for gain control and clamping.

For ver tical sync separation, the sliced video signal is

integrated. The FP uses the integrator value to derive

vertical sync and field information.

The information extracted by the video sync process-

ing is multiplexed onto the hardware front sync signal

(FSY) and is distributed to the rest of the video pro-

cessing system. The format of the front sync signal is

given in Fig. 2–13.

The data for the vertical deflection, the sawtooth, and

the East-West correction signal is calculated by the

VPC 32xx. The data is buffered in a FIFO and trans-

ferred to the back-end IC DDP 3300 A by a single wire

interface.

Frequency and phase characteristics of the analog

video signal are derived from PLL1. The results are fed

to the sca ler un it for data interpolati on an d orth ogo nal -

ization and to the clock synthesizer for line-locked

clock generation. Horizontal and vertical syncs are

latched with the line-locked clock.

Fig. 2–12: Sync separation block diagram

Fig. 2–13: Front sync format

phase

comparator

lowpass counter

frontend

timing

front sync

lowpass

1 MHz

syncslicer

horizontal

sync

separation

vertical

sync

separation FIFO

Sawtooth

video

input

skew

front

sync

generator

vertical

serial

data

vertical

sawtooth

E/W

Parabola

Calculation

clamping, colorkey, FIFO_wri te

PLL1

clamp &

signal

meas.

vblank

field

clock

synthesizer

syncs clock

H/V syncs

input

analog

video

FSY

skew skew

LSB not

used FV

MSB

(not in scale) F0 reserved

0 = field 1

1 = field 2

F: field #

0 = off

1 = on

V: vertical sync

Parity

VPC 3205C, VPC 3215C PRELIMINAR Y DATA SHEET

16 Micronas

Fig. 2–14: Vertical timing of VPC 32x5 shown in reference to input video.

Video output signals are delayed by 3-h for comb filter version (VPC 32x5).

314 315 316 317313311 318 335 336310CCIR 319 320

1234623 5 6 23 24CCIR 78

field 1

field 2

>1 clk

> 1clk

Vertical Sync (VS)

Interlace (INTLC)

Active Video Output (AVO)

helper ref line 23, 623 (internal signal) signal matches output video

The following signals are identical for field1 / field2

helper lines 23–59, 275–310, 336–37 1, 587–623, signal matches output video

624 625

312

Interlace (INTLC)

Vertical Sync (VS)

Front-Sync (F SY)

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

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3. S erial Interface

3.1. I2C-Bus Interface

Communication between the VPC and the external

controller is done via I2C-bus. The VPC has an

I2C-bus slave interface and uses I2C clock synchroni-

zation to slow down the interface if required. The

I2C-bus interface uses one level of subaddress: one

I2C-bus address is used to address the IC and a sub-

address selects one of the internal registers. The

I2C-bus chip address is given below:

The registers of the VPC have 8 or 16-bit data size;

16-bit registers are accessed by reading/writing two

8-bit data words.

Figure 3–1 sh ows I2C-bus protocols for read and wr ite

operations of the interface; the read operation requires

an extra start condition and repetition of the chip

address with read command set.

3.2. Control and Status Re gisters

Table 3–1 gives defini tions of the VPC con trol an d sta-

tus registers. The number of bits indicated for each

in hardware, i.e. a 9-bit register must always be

accessed using two data bytes but the 7 MSB will be

‘don’t care’ o n write operations and ‘0’ on read opera-

tions. Write registers that can be read back are indi-

cated in Table 3–1.

Functions implemented by software in the on-chip con-

trol microprocessor (FP) are explained in Table 3–2.

A hardware reset initializes all control registers to 0.

The automatic chip initialization loads a selected set of

registers with the default values given in Table 3–1.

The register modes given in Table 3–1 are

–w: write only register

–w/r: write/read data register

–r : read data from VPC

–v: register is latched with vertical sync

The mnemonics used in the Intermetall VPC demo

software are given in the last column.

Fig. 3–1: I2C-bus protocols

A6 A5 A4 A3 A2 A1 A0 R/W

10001111/0

SDA

SCL

1000 111

WAck

AckW 0111 1100

0111 1100

Ack

1 or 2 byte Data

1000 111 R high byte Data

low byte Data

Ack

Nak

Start

Stop

Ack

Nak P

I2C write access

subaddress 7c

I2C read access

subaddress 7c

Ack

VPC 3205C, VPC 3215C PRELIMINAR Y DATA SHEET

18 Micronas

Table 3–1: Control and status registers

I2C Sub-

address Number

of bits Mode Function Default Name

FP Interface

h’35 8 r FP status

bit [0] write request

bit [1] read request

bit [2] b usy

–FPSTA

h’36 16 w bit[8:0] 9-bit FP read address

bit[11:9] reserved, set to zero –FPRD

h’37 16 w bit[8:0] 9-bit FP write address

bit[11:9] reserved, set to zero –FPWR

h’38 16 w/r bit[11:0] FP data register, reading/writing to this

write address. Only 16 bit of data are

transferred per I2C telegram.

–FPDAT

Black Line Detector

h’12 16 w/r read only register, do not write to this register! After reading,

LOWLIN and UPLIN are reset to 127 to start a new measure-

ment.

bit[6:0] number of lower black lines

bit[7] always 0

bit[14:8] number of upper black lines

bit[15] 0/1 normal/black picture

–BLKLIN

LOWLIN

UPLIN

BLKPIC

Pin Circuits

h’1F 16 w/r SYNC pins (HS, HC, AVO, HELP, INTLC, VS):

bit[2:0] 0..7 output strength for SYNC Pins

(7 = tristate, 6 = weak ... 0 = strong)

bit[3] 0/1 pushpull/tristate f or AVO Pin

bit[4] 0/1 pushpull/tristate f or other SYNC Pins

bit[5] 0/1 synchronization/no synchronization with

horizontal HS for signals VS and INTLC

CLOCK pins (LLC1, LLC2):

bit[6] 0/1 pushpull/tristate for LLC1

bit[7] 0/1 pushpull/tristate for LLC2

DATA pins (LB[7:0], CB[7:0]):

bit[10:8] 0..7 output strength for DATA pins

(7 = tristate, 6 = weak ... 0 = strong)

bit[11] 0/1 tristate/pushpull for DATA pins

bit[12] 0/1 half- cy cle pul l-up(DI GI T3000)/pushpu ll for

LB, CB (LCC)

bit[13] reserved (set to 0)

bit[14:15] output strength for LLC1: (–2,–1,0,1)

TRPAD

SNCSTR

AVODIS

SNCDIS

VASYSEL

LLC1DIS

LLC2DIS

DATSTR

DATEN

LCPUDIS

LLC1STR

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 19

h’20 8 w/r SYNC GENERATOR CONTROL:

bit[1:0] 00 AVO and active Y/C data at same time

01 AVO precedes Y/C data one clock cycle

10 AVO precedes Y/C data two clock cycles

11 AVO precedes Y/C data three clock cycles

bit[2] 0/1 positive/negative polarity for HS signal

bit[3] 0/1 positive/negative polarity for HC signal

bit[4] 0/1 positive/negative polarity for AVO signal

bit[5] 0/1 positiv e/negative polarity for VS signal

bit[6] 0/1 positive/negative polarity for HELP signal

bit[7] 0/1 positive/negative polarity for INTLC signal

SYNCMODE

AVOPRE

HSINV

HCINV

AVOINV

VSINV

HELPINV

INTLCINV

h’30 8 w/r V-SYNC DELAY CONTROL:

bit[7:0] VS delay (8 LLC clock cycles per LSB) 0 VSDEL

VSDEL

Priority Bus

h’23 8 w/r priority bus overwrite register

bit [7:0] 8 bit mask, bit[x] = 1 : overwrite priority x 0 PRIOVR

h’24 8 w/r priority bus ID register and control

bit [2:0] 0..7 priority ID, 0 highest

bit [4:3] 0..3 pad driver strength, 0 (strong) to 3 (weak)

bit [5] 0/1 output mode: DIGIT3000/LLC

bit [6] 0/1 source for prio request: AVO/active always

bit [7] 0/1 disable/enable priority interface, if disabled

data pins are tristate !

PRIOMODE

PID

PRIOSTR

OMODE

PIDSRC

PIDE

Sync Generat or

h’21 16 w/r L INE LENGTH:

bit[10:0] LINE LENGTH register

In LLC mode, this register defines the

cycle of the sync counter which generates

the SYNC pulses.

In LLC mode, the synccounter counts from

0 to LINE LENGTH, so this register has to

be set to “number of pixels per line –1”.

In DIGIT3000 mode, LINE LENGTH has to

be set to 1295 for correct adjustment of

vertical signals.

bit[15:11 ] reserved (set to 0)

1295 LINLEN

h’26 16 w/r HC START:

bit[10:0] HC START defines the beginning of the

HC signal in respect to the value of the

sync counter.

bit[15:11 ] reserved (set to 0)

50 HCSTRT

h’27 16 w/r HC STOP:

bit[10:0] HC STOP defines the end of the HC signal

in respect to the value of the sync counter.

bit[15:11 ] reserved (set to 0)

800 HCSTOP

I2C Sub-

address Number

of bits Mode Function Default Name

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20 Micronas

h’28 16 w/r AVO START:

bit[10:0] AVO STAR T defines the beginning of the

AVO signal

in respect to the value of the sync counter.

bit[11] reserved (set to 0)

bit[12] 0/1 vertical window disable/enable

bit[13] 0/1 vertical window 312/262 lines

bit[15:14]–2..1 vertical window interlace offset

60 AVSTRT

VERWIN

h’29 16 w/r AVO STOP:

bit[10:0] AVO STOP defines the end of the AVO

signal in respect to the value of the

sync counter.

bit[15:11] reserved for test picture generation

(set to 0 in normal operation)

bit[11] 0/1 disable/enable test pattern generator

bit[13:12] luma output mode:

00 Y = ramp (240 ... 17)

01 Y = 16

10 Y = 90

11 Y = 240

bit[14] 0/1 chroma output: 422/411 mode

bit[15] 0/1 chroma output: pseudo color bar/zero

if LMODE = 0

AVSTOP

COLBAREN

LMODE

M411

CMODE

h’22 16 w/r NEWLINE:

bit[10:0] NEWLINE defines the readout start of the

next line inrespect to the value of the sync

counter. The value of this register must be

greater than 31 for correct operation and

should be identical to AVOSTART (recom-

mended). In case of 1H-bypass mode for

scaler block, NEWLINE has no function.

bit[12:11] reserved (set to 0)

bit[13] vertical free run mode enabled, the vertical

frequency is selected via VERWIN (h’28)

bit[15:14] reserved (set to 0)

NEWLIN

FLW

I2C Sub-

address Number

of bits Mode Function Default Name

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 21

Table 3–2: Control Registers of the Fast Processor

– default v alues are initialized at reset

– * indicates: register is initializ ed according to the current standard when SDT register is changed.

FP Sub-

address Function Default Name

Standard Selection

h’20 S tan dar d se lec t:

bit[2:0] standard

0 PAL B,G,H,I (50 Hz) 4.433618

1 NTSC M (60 Hz) 3.579545

2 SECAM (50 Hz) 4.286

3 NTSC44 (60 Hz) 4.433618

4 PAL M (60 Hz) 3.5756 11

5 PAL N (50 Hz) 3.582056

6 PAL 60 (60 Hz) 4.4 336 18

7 NTSC COMB (60 Hz) 3.579545

bit[3] 0/1 MOD standard modifier

PAL modified to simple PAL

NTSC modified to compensated NTSC

SECAM modified to monochrome 625

NTSCC modified to monochrome 525

bit[4] 0/1 PAL+ mode off/on

bit[5] 0/1 4-H COMB mode

bit[6] 0/1 S-VHS mode:

The S-VHS/COMB bits allow the following modes:

00 composite input signal

01 comb filter active

10 S-VHS input signal

11 CVBS mode (composite input signal, no luma notch)

Option bits allow to suppress parts of the initialization; this can be

used for color standard search:

bit[7] no hpll setu p

bit[8] no ver t ic al setup

bit[9] no acc setu p

bit[10] 4-H comb filter setup only

bit[11] status bit, normally write 0. After the FP has switched to a

new standard, this bit is set to 1 to indicate operation

complete. Standard is automatically initialized when the

insel register is written.

SDT

PAL

NTSC

SECAM

NTSC44

PALM

PALN

PAL60

NTSCC

SDTMOD

PALPLUS

COMB

SVHS

SDTOPT

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

22 Micronas

h’21 Input select: writing to this register will also initialize the standard

bit[1:0] luma selector

00 VIN3

01 VIN2

10 VIN1

11 VIN4

bit[2 ] chroma selector

0/1 VIN1/CIN

bit[4:3] IF compensation

00 off

01 6 dB/Okt

10 12 dB/ Okt

11 10 dB/MHz only for SECAM

bit[6:5] chroma ban dwid th selec tor

00 narrow

01 normal

10 broad

11 wide

bit[7] 0/1 adaptive/fixed SECAM notch filter

bit[8] 0/1 enable luma lowpass filter

bit[10:9] hpll speed

00 no change

01 terrestrial

10 vcr

11 mixed

bit[11] status bit, write 0, this bit is set to 1 to indicate

operation complete.

INSEL

VIS

CIS

IFC

CBW

FNTCH

LOWP

HPLLMD

h’22 picture start position: This register sets the start point of active video

and can be used e.g. for panning. The setting is updated when ‘sdt’

ten.

0SFIF

h’23 luma/chroma delay adjust. The setting is updated when ‘sdt’ register

is updated.

bit[5:0] reserved, set to zero

bit[11:6] luma delay in clocks, allowed range is +1 ... –7

0LDLY

h’29 helper dela y register (PAL+ mode only)

bit[11:0] delay adjust for helper lines adjustable from

–96...96, 1 step corresponds to 1/32 clock

0 HLP_DLY

h’2f VGA mode select, pull-in range is limited to 2%

bit[1:0] 0 31.5 kHz

1 35.2 kHz

2/3 37.9 kHz

is set to 0 by FP if VGA = 0

bit[10] 0/1 disable/enable VGA mode

bit[11] status bit, write 0, this bit is set to 1 to indicate

operation complete.

VGA_C

VGAMODE

VGA

FP Sub-

address Function Default Name

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

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Comb Filter

h’28 comb filter control register

bit[1:0] not ch filt er sel ect

00 flat frequency characteristic

01 min. peaked

10 med. peaked

11 max. pea ked

bit[3:2] diagonal dot reduction

00 min. reduction ... 11 max. reduction

bit[4:5] horizontal difference gain

00 min. gain ... 11 max. gain

bit[7:6] vertical difference gain

00 max. gain ... 11 min. gain

bit[11:8] vertical peaking gain

0 no vertical peaking... 15 max. v ertical peaking

h’e7

COMB_UC

NOSEL

DDR

HDG

VDG

VPK

h’55 comb filter test register

bit[1:0] reserved, set ot 0

bit[2] 0/1 disable/enable vertical peaking DC rejection filter

bit[3] 0/1 disable/enable vertical peaking coring

bit[11:4] reserved, set to 0

CMB_TST

DCR

COR

Color Processing

h’34 ACC multiplier value for PAL+ Helper Signal

b[10:0] eeemmmmmmmm m * 2–e1280 ACCH

h’36 ACC PAL+ Helper gain adjust, gain is ref erenced to PAL b urst,

allowed values from 256..1023

a value of zero allows manual adjust of Helper amplitude via ACCh

787 HLPGAIN

h’39 amplitude killer level (0:killer disabled) 25 KILVL

h’3a amplit ude ki ll er hysteresis 5 KILHY

h’16c auto mati c hel per dis able for nonsta ndar d si gna ls

bit[11:0] 0 automatic function disabled

bit[1:0] 01 enable

bit[11:2] 1..50 number of fields to switch on helper signal

0HLPDIS

h’dc NTSC tint angle, ±512 = ±π/4 0 TINT

Horizontal PLL

h’aa

h’ab

h’ac

h-pll gain setting, these registers are used to set the h-pll speed, pll

speed selection is done via the input selection register

DVCO

h’f8 crystal oscillator center frequency adjust, –2048 ... 2047 –720 DVCO

h’f9 crystal oscillator center frequency adjustment value for line-lock

mode, true adjust value is DVCO – ADJUST.

For factory crystal alignment, using standard video signal: disable

autolock mode, set DVCO = 0, set lock mode, read crystal offset

from ADJUST register and use negative value for initial center fre-

quency adjustment via DVCO.

read only ADJUST

FP Sub-

address Function Default Name

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

24 Micronas

h’f7 crystal oscillator line-locked mode, lock command/status

write: 100 enab le lock

0 disable lock

read: 0 unlocked

>2047 locked

0XLCK

h’b5 crystal oscillator line-locked mode, autolock feature. If autolock is

enabled, crystal oscillator locking is started automatically.

bit[11:0] threshold, 0:autolock off

400 AUTOLCK

FP Status Register

h’12 general purpose control bits

bit[2:0] reserved, do not change

bit[3] vertical standard force

bit[8:4] reserved, do not change

bit[9] disable flywheel interlace

bit[11:10] reserved, do not change

to enable vertical free run mode set vfrc to 1 and dflw to 0

VFRC

DFLW

h’13 standard recognition status

bit[0] 1 vertical lock

bit[1] 1 horizontally lock ed

bit[2] 1 no si gna l detec ted

bit[3] 1 color amplitude killer active

bit[4] 1 disable amplitude killer

bit[5] 1 col or ident killer active

bit[6] 1 disable ident killer

bit[7] 1 interlace detected

bit[8] 1 no vertical sync detection

bit[9] 1 spurious vertical sync detection

bit[12:10] reserved

–ASR

h’14 input noise level, available only for VPC 3215C read only NOISE

h’cb number of lines per field, P/S: 312, N: 262 read only NLPF

h’15 vertical field counter, incremented per field read only VCNT

h’74 measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC) read only SAMPL

h’31 measured burst amplitude read only BAMPL

h’f0 firmware version number

bit[7:0] internal revision number

bit[11:8] firmware release

read only –

h’f1 hardware version number

bit[5:0] internal hardware revision number

bit[11:6] hardw are id, VPC 32x5C = 01

read only –

FP Sub-

address Function Default Name

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 25

Scaler Control Register

h’40 scaler mode register

bit[1:0] scaler mode

0 linear scaling mode

1 nonlinear scaling mode, ’panorama’

2 nonlinear scaling mode, ’waterglass’

3 reserved

bit[2] reserved, set to 0

bit[3] color mode select

0/1 4:2:2 mode / 4:1:1 mode

bit[4] scaler bypass

bit[5] reserved, set to 0

bit[6] luma output format

0 ITU-R luma output format (16–240)

1 CVBS output format

bit[7] chroma output format

0/1 ITU-R (offset binary) / signed

bit[10:8] reserved, set to 0

bit[11] 0 scaler update command, when the registers are

updated the bit is set to 1

0SCMODE

PANO

S411

BYE

YOF

COF

h’41 luma offset register

bit[6:0] luma offset 0..127

ITU-R output format: 57

CVBS output format: 4

this register is updated when the scaler mode register is written

57 YOFFS

h’42 active video length for 1H-FIFO

bit[11:0] length in pixels

D3000 mode (1296/h)1080

LLC mode (864/h)720

this register is updated when the scaler mode register is written

1080 FFLIM

h’43 scaler1 coefficient: This scaler compresses the signal.

For compression by a factor c, the value c*1024 is required.

bit[11:0] allowed values from 1024... 4095

This register is updated when the scaler mode register is written.

1024 SCINC1

h’44 scaler2 coefficient: This scaler expands the signal.

For expansion by a factor c, the value 1/c*1024 is required.

bit[11:0] allowed values from 256..1024

This register is updated when the scaler mode register is written.

1024 SCINC2

h’45 scaler1/2 nonlinear scaling coefficient

This register is updated when the scaler mode register is written. 0SCINC

h’47 –

h’4b scaler1 windo w controls, see table

5 12-bit registers for control of the nonlinear scaling

This register is updated when the scaler mode register is written.

0 SCW1_0 – 4

h’4c –

h’50 scaler2 windo w controls, see table

5 12-bit registers for control of the nonlinear scaling

This register is updated when the scaler mode register is written.

0 SCW2_0 – 4

FP Sub-

address Function Default Name

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

26 Micronas

LLC Control Register

h’60 horizontal offset

bit[11:0] offset between FSY and HS 0 LLC_OFFSET

h’65 vertical freeze start

freeze llc pll for llc_start < line number < llc_stop

bit[11:0] allowed values from –156...+156

–10 LLC_START

h’66 vertical freeze stop

freeze llc pll for llc_start < line number < llc_stop

bit[11:0] allowed values from –156...+156

4 LLC_STOP

h’69

h’6a 20 bit llc cloc k center frequency

13.5 MHz 174763 = h’02AAAB

16 MHz –135927 = h’FDED08

18 MHz 174763 = h’02AAAB

42 = h’02A

2731 = h’AABLLC_CLOCKH

LLC_CLOCKL

h’61 pll freque nc y li mit er, 8%

13.5 MHz 54

16 MHz 48

18 MHz 54

54 LLC_DFLIMIT

h’6d llc clock generator control word

bit[4:0] hardware registe r shadow

llc_clkc = 5→13.5 MHz

llc_clkc = 3→16 MHz

llc_clkc = 3→18 MHz

bit[10:5] reserved

bit[11] 0/1 enable/disable llc pll

2053 LLC_CLKC

FP Sub-

address Function Default Name

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 27

Table 3–3: Control Registers of the Fast Processor that are used for the control of DDP 3300A

– this function is only available in the 50 Hz version (VPC 320x)

– default v alues are initialized at reset

– * indicates: register is initializ ed according to the current standard when SDT register is changed

FP Sub-

address Function Default Name

FP Display Control Register

h’130 White Drive Red (0...1023) 700 WDR 1)

h’131 White Drive Green (0...1023) 700 WDG 1)

h’132 White Drive Blue (0...1023) 700 WDB 1)

h’139 Internal Brightness, Picture (0 ..511), the center value is 256, the r ange

allows for both increas e and re ducti on of br i ght ness. 256 IBR

h’13c Internal Brightness, measurement (0...511), the center value is 256,

the brightness for measurement can be set to measure at higher cutoff

current. The measurement brightness is independent of the drive val-

ues.

256 IBRM

h’13a Analog Brightness for external RGB (0...511), the center value is 256,

the range allows for both increase and reduction of brightness. 256 ABR

h’13b Analog Contrast for external RGB (0...511) 350 ACT

1) The white drive values will become active only after writing the blue value WDB, latching of new values is indi-

cated by setting the MSB of WDB.

FP Display Control Register, BCL

h’144 BCL threshold current, 0...2047 (max ADC output ~1152) 1000 BCLTHR

h’142 BCL time constant 0...15 →13 ... 1700 msec 15 BCLTM

h’143 BCL loop gain. 0..15 0 BCLG

h’145 BCL minimum contrast 0 ...1023 307 BCLMIN

h’105 Test register for BCL/EHT comp. function, register value:

0 normal operation

1 stop ADC offset compensation

x>1 use x in place of input from Measurement ADC

0BCLTST

FP Display Control Register, Deflection

h’103 interlace offset, –2048 ...2047

This value is added to the SAWTOOTH output during one field. 0INTLC

h’102 discharge sample count for deflection retrace,

SAWTOOTH DAC output impedance is reduced for DSCC lines after

vert ical retrace.

7DSCC

h’11f vertical discharge value,

SAWTOOTH output value during discharge operation, typically same

as A0 init value for sawtooth.

–1365 DSCV

h’10b EHT (electronic high tension) compensation coefficient, 0...511 0 EHT

h’10a EHT time constant. 0 ..15 → 3.2 ...410 msec 15 EHTTM

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

28 Micronas

Control registers, continued

FP Sub-

address Function Default Name

FP Display Control Register

FP Display Control Register, Vertical Sawtooth

h’110 DC offset of SAWTOOTH output

This offset is independent of EHT compensation. 0OFS

h’11b accu0 init value –1365 A0

h’11c accu1 init value 900 A1

h’11d accu2 init value 0 A2

h’11e accu3 init value 0 A3

FP Display Control Register, East-West Parabola

h’12b accu0 init value –1121 A0

h’12c accu1 init value 219 A1

h’12d accu2 init value 479 A2

h’12e accu3 init value –1416 A3

h’12f accu4 init value 1052 A4

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 29

3.2.1. Calculation of Vertical and East-West

Deflection Coefficients

In Table 3–4 the formula for the calculation of the

deflection initialization parameters from the polynomi-

nal coefficients a,b,c,d,e is given for the vertical and

East-West deflection. Let the polynomial be

The initialization values for the accumulators a0..a3 for

vertical deflection and a0..a4 for East-West deflection

are 12- bit values. The coe ffici ents that s hould be us ed

to calculate the initialization values for different field

frequencies are given below, the values must be

scaled b y 128, i.e. the value for a0 of the 50 Hz vertical

deflectio n is

3.2.2. Scaler Adjustment

In case of linear scaling, most of the scaler registers

need not be set. Only the scaler mode, active video

length, a nd th e fixed scaler inc rements (scinc 1/scin c2 )

must be written.

The adjustment of the scaler for nonlinear scaling

modes should use the parameters given in table 3–5.

An example for ‘panorama vi si on’ mode with 13.5 MHz

line-locked clock is depicted in Fig. 3–2. The figure

shows the scaling o f the input s ignal and th e var iation

of the scaling factor during the active video line. The

scaling factor starts below 1, i.e. for the borders the

video data is expanded by sca ler 2. The scaling fa ctor

becomes one and compression scaling is done by

scale r 1. When the pictu re center is re ached, the scal-

ing factor is held constant. At the second border the

scaler increment is inverted and the scaling factor

change s back symmetr ically. The pictur e indicates the

function of the scaler increments and the scaler win-

dow parameters. The correct adjustment requires that

pixel counts for the respective windows are always in

number of output samples of scaler 1 or 2.

Table 3–4: Tables for the Calculation of Initialization values for Vertical Sawtooth and East-West Parabola

P = a + b(x – 0.5) + c(x – 0.5) 2 + d(x – 0.5)3 + e(x – 0.5)4

a0 = (a · 128 – b · 1365.3 + c · 682.7 – d · 682.7) ÷ 128

Vertical Deflection 50 Hz

abcd

a0 128 –1365.3 +682.7 –682.7

a1 899.6 –904.3 +1363.4

a2 296.4 –898.4

a3 585.9

Vertical Deflection 60 Hz

abcd

a0 128 –1365.3 +682.7 –682.7

a1 1083.5 –1090.2 +1645.5

a2 429.9 –1305.8

a3 1023.5

East-West Deflection 50 Hz

ab c d e

a0 128 –341.3 1365.3 –85.3 341.3

a1 111.9 –899.6 84.8 –454.5

a2 586.8 –111.1 898.3

a3 72.1 –1171.7

a4 756.5

East-West Deflection 60 Hz

ab c d e

a0 128 –341.3 1365.3 –85.3 341.3

a1 134.6 –1083.5 102.2 –548.4

a2 849.3 –161.2 1305.5

a3 125.6 –2046.6

a4 1584.8

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

30 Micronas

Fig. 3–2: Scaler operation for ‘panorama’ mode at 13.5 MHz

border center border input signal

video signal

output signal

compression

ratio

expansion

(scaler2)

compression

(scaler1)

23401

scaler window

cutpoints

compression

(scaler1)

scinc2

scinc1

expansion

(scaler2)

scinc

Table 3–5: Set-up values for nonlinear scaler modes

Mode DIGIT3000 (20.25 MHz) LLC (13.5 MHz)

‘waterglass’

border 35% ‘panorama’

border 30% ‘waterglass’

border 35% ‘panorama’

border 30%

center 3/4 center 5/6 center 4/3 center 6/5 center 3/4 center 5/6 center 4/3 center 6/5

scinc1 1643 1427 1024 1024 2464 2125 1024 1024

scinc2 1024 1024 376 611 1024 1024 573 914

scinc 90 56 85 56 202 124 190 126

fflim 945 985 921 983 719 719 681 715

scw1 – 0 110 115 83 94 104 111 29 13

scw1 – 1 156 166 147 153 104 111 115 117

scw1 – 2 317 327 314 339 256 249 226 241

scw1 – 3 363 378 378 398 256 249 312 345

scw1 – 4 473 493 461 492 360 360 341 358

scw2 – 0 110 115 122 118 104 111 38 14

scw2 – 1 156 166 186 177 104 111 124 118

scw2 – 2 384 374 354 363 256 249 236 242

scw2 – 3 430 425 418 422 256 249 322 346

scw2 – 4 540 540 540 540 360 360 360 360

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 31

4. Specifications

4.1. Outline Dimensions

Fig. 4–1: 68-Pin Plastic Leaded Chip Carrier Package

(PLCC68)

Weight approximately 4.8 g

Dimensions in mm

4.2. Pin Connections and Short Descriptions

NC = not connected

LV = if not used, leave vacant

X = obligatory; connect as described in circuit diagram

x 45 °1.1

25.125 0.125±

0.22 0.07±

1.2 x 45°

16 x 1.27 = 20.32

0.1±0.1±

24.22 0.1±

4327

619

0.48

0.711

1.9

4.05 0.1

4.75±0.15

1.27 0.1±

16 x 1.27 = 20.32

0.1±0.1±

24.22 0.1±

0.9

23.4

SPGS7004-3/5E

25.125 0.125±

1.6

Pin No.

PLCC

68-pin

Pin Name Type Connection

(if not used)Sho rt Descri ption

1GND

FSUPPLY X Ground, Analog Front-End

2GND

FSUPPLY X Ground, Analog Front-End

3 CLK5 OUT LV CCU 5 MHz Clock Output

STBY SUPPLY X Standby Supply Voltage

5 XTAL2 OUT X Analog Crystal Out put

6 XTAL1 IN X Analog Cr y sta l Input

7GND

FSUPPLY X Ground, Analog Front-End

9GND

PSUPPLY X Ground, Output Pad Circuitry

10 INTLC OUT LV Interlace Output

12 VS OUT LV Vert ical Sy nc Puls e

13 FSY OUT LV Front Sync Pulse

14 MSY/HS IN/OUT LV Main Sync/Horizontal Sync Pulse

15 HELP ER OUT LV Helpe r Lin e Output

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

32 Micronas

16 HC IN/OUT LV Horizontal Clamp Pulse

17 AVO OUT LV Active Video Output

18 LLC2 OUT LV Double Output Clock

19 LLC1 IN/OUT LV Output Clock

20 Y7 OUT GNDPPicture Bus Luma (MSB)

21 Y6 OUT GNDPPicture Bus Luma

22 Y5 OUT GNDPPicture Bus Luma

23 Y4 OUT GNDPPicture Bus Luma

24 Y3 OUT GNDPPicture Bus Luma

25 Y2 OUT GNDPPicture Bus Luma

26 GNDPX Ground, Output Pad Circuitry

28 Y1 OUT GNDPPicture Bus Luma

29 Y0 OUT GNDPPicture Bus Luma (LSB)

30 CLK20 IN/OUT LV Main Clock Output 20.25 MHz

31 VSUPD SUPPLY X Supply Voltage, Digital Circuitry

34 GNDDSUPPLY X Ground, Digital Circuitry

35 GNDPSUPPLY X Ground, Output Pad Circuitry

36 VSUPP SUPPLY X Supply Voltage, Output Pad Supply

38 C7 OUT GNDPPicture Bus Chroma (MSB)

39 C6 OUT GNDPPicture Bus Chroma

40 C5 OUT GNDPPicture Bus Chroma

41 C4 OUT GNDPPicture Bus Chroma

42 C3 OUT GNDPPicture Bus Chroma

43 C2 OUT GNDPPicture Bus Chroma

46 C1 OUT GNDPPicture Bus Chroma

47 C0 OUT GNDPPicture Bus Chroma (LSB)

48 PR0 IN/OUT LV Picture Bus Priority (LSB)

49 PR1 IN/OUT LV Picture Bus Priority

50 PR2 IN/OUT LV Picture Bus Priority (MSB)

51 GNDPSUPPLY X Ground, Output Pad Circuitry

52 VGAV IN GNDPVGAV Input

Pin No.

PLCC

68-pin

Pin Name Type Connection

(if not used)Short Description

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 33

*) chroma selector must be set to 1 (CIN chroma select)

4.3. Pin Descriptions

(pin numbers for PLCC68 package)

Pin 1 – Ground, Analog Front-End GNDF

Pin 2 – Ground, Analog Front-End GNDF

Pin 3 – CCU 5 MHz Clock Output CLK5 (Fig. 4–11)

This pin provides a clock frequency for the TV micro-

controller, e.g. a CCU 3000 controller. It is also used

by the DDP 3300A display controller as a standby

clock.

Pin 4 – Standby Suppl y Vo lta ge VSTDBY

In standby mode, only the clock oscillator is active,

GNDF should be ground reference. Please activate

RESQ before powering-up other supplies

Pins 6 and 5 – XTAL1 Crystal Input and XTAL2 Crystal

Output (Fig. 4–8)

These pins are connected to an 20.25 MHz crystal

oscillator which is digitally tuned by integrated shunt

capac itances. The CLK20 and CLK5 clock signal s are

derived from this oscillator. An external clock can be

fed into XTAL1. In this case, clock frequency adjust-

ment must be switched off.

Pin 7 – Ground, Analog Front-End GNDF

Pin 9 – Ground, Output Pad Circuitry GNDP

Pin 10 – Interlace Output, INTLC (Fig. 4–4)

This pin supplies the interlace information, 0 indicates

first field, 1 indicates second field.

53 FPDAT IN/OUT LV Front-End/Back-End Data

54 RESQ IN X Reset Input, Active Low

55 SDA IN/OUT X I2C Bus Data

56 SCL IN/OUT X I2C Bus Clock

57 TEST IN GNDDTest Pin, connect to GNDD

58 VIN4 IN VRT Video 4 Analog Input

59 GNDFSUPPLY X Ground, Analog Front-End

60 VIN3 IN VRT Video 3 Analog Input

61 VIN2 IN VRT Video 2 Analog Input

62 VIN1 IN VRT* Video 1 Analog Input

63 CIN IN LV* Chroma/Video 4 Analog Input

64 VOUT OUT LV Analog Vi deo Outpu t

65 ASGF X Anal og Shi el d GNDF

66 VSUPF SUPPLY X Supply Voltage, Analog Front-End

67 ISGND SUPPLY X Signal Ground for Analog Input, connect to

GNDF

68 VRT OUTPUT X Reference Voltage Top, Analog

8, 11

27, 32

33, 37

44, 45

NC –LV OR GNDDNot connected

Pin No.

PLCC

68-pin

Pin Name Type Connection

(if not used)Sho rt Descri ption

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET
34 Micronas
Pin 12 – Vertical Sync Pulse, VS (Fig. 4–4)
This pin supplies the vertical sync signal. 
Pin 13 – Front Sync Pulse, FSY (Fig. 4–4)
This pin supplies the front sync information.
Pin 14 – Main Sync/Horizontal Sync Pulse MSY/HS
(Fig. 4–4)
This p in supp lies th e hor izontal s ync puls e infor matio n
in  li ne -l ock ed  mo de. In D IG I T3 0 00  mo de, thi s  pin is the
main sync  input .
Pin 15 – Helper Line Output, Helper (Fig. 4–4)
This signal indicates a helper line in PAL+ mode.
Pin 16 – Horizontal Clamp Pulse, HC (Fig. 4–4)
This signal can be used to clamp an external video sig-
nal, that  is synchronou s to the input signal . The timing
is programmable.
Pin 17 – Active Video Output, AVO (Fig. 4–4)
This pin indicates the active video output data. The
signal is clocked with the LLC1 clock.
Pin 18 – Double Output Clock, LLC2 (Fig. 4–6)
Pin 19 – Output Clock, LLC1 (Fig. 4–6)
This is the clock reference for the luma, chroma, and
status outputs.
Pin 26 – Ground, Output Pad Circuitry GNDP
Pins 20 to 25,28,29  – Luma   Outputs Y0 – Y7 (Fig. 4–4)
These output pins car ry the digital luminance data. The
data are clock ed with the LLC1 cloc k.
Pin 30 – Main Clock Output CLK20 (Fig. 4–5)
This is the 20.25 MHz main clock output.
Pin 31 – Supply Voltage, Digital Circuitry VSUPD 
Pin 34 – Ground, Digital Circuitry GNDD 
Pin 35 – Ground, Output Pad Circuitry GNDP
Pin 36 – Suppl y Vo lta ge, Out put Pad Supply VSUPP
Pins 38 to  43,46,47 – Chroma Outputs C0–C7 (Fig. 4–4)
These o utputs c arr y  the digi tal CrCb ch romin ance dat a.
The data are clocked with the LL1 clock. The data are
sampled at half the clock rate and multiplexed. The
CrCb multiplex is reset f or each TV line.
Pins 48 to 50 – Picture Bus Priority PR0–PR2 (Fig. 4–6)
The Picture Bus Priority lines carry the digital priority
selection signals. The priority interface allows digital
switching of up to 8 sources to the back-end processor.
Switching for different sources is prioritized and can be
on a per pixel basis.
Pin 51 – Ground, Output Pad Circuitry GNDP
Pin 52 – V GAV-Input. (Fig. 4–3)
This pin is connected to the v ertical sync signal of a V GA
signal.
Pin 53 – Front-End/Back-End Data FPDAT (Fig. 4–6)
This pin interfaces to the DDP 3300A back-end pro-
cessor. The information for the deflection drives and
for the white dri ve contr ol,  i. e. the beam  c urre nt l imiter,
is transmitted by this pin.
Pin 54 – Reset Input RESQ (Fig. 4–3)
A low lev el on this pin resets the VPC 32xx.
Pin 55 – I2C Bus Data SDA (Fig. 4–13)
This pin connects to the I2C bus data line.
Pin 56 – I2C Bus Clock SCL (Fig. 4–3)
This pin connects to the I2C bus clock line.
Pin 57 – Test Input TEST (Fig. 4–3)
This pin enables f actory test modes. For normal opera-
tion, it must be connected to ground.
Pin 59 – Ground, Analog Front-End GNDF 
Pins 62,61,60,58 – Video Input 1–4 (Fig. 4–12)
These  are the anal og vide o inputs. A CVBS  or S-VH S
luma signal is converted using the luma (Video 1) AD
conver ter. The  VIN1 input  can also  be sw itched to th e
chroma (Video 2) ADC. The input signal must be
AC-coupled.
Pin 63 – Chroma Input CIN (Fig. 4–10)
This pin is connected to the S-VHS chroma signal. A
resistive divider is used to bias the input signal to the
middle of the converter input range. CIN can only be
connec ted to the chr oma (Vide o 2) A/D conver ter. The
signal must be AC- coupled.
Pin 64 – Analog Video Output, VOUT (Fig. 4–7)
The analog video signal that is selected for the main
(luma,  CVBS) A DC is outp ut at thi s pin. A n emit ter fol-
lower is required at this pin.
Pin 65 – Ground, Analog Shield Front-End GNDF 
Pin 66 – Supply Voltage, Analog Front-End VSUPF 
(Fig. 4–9)
Pin 67 – Signal GND for Analog Input ISGND (Fig. 4–
11) This is the high quality ground reference for the
video input sign als. 
Pin 68  – Reference Voltage Top VRT (Fig. 4–9)
Via this pin, the reference v oltage f or the A/D conv erters
is d ecoup led . T he  pin  is c onn ect ed w ith  10 µF/4 7 nF  to
the Signal Ground Pin.

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 35

4.4. Pin Configuration

Fig. 4–2: 68-pin PLCC package

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

9 8 7 6 5 4 3 2 1 6867666564636261

26 44

VPC 32x5C

INTLC

FSY

MSY/HS

HELPER

AVO

LLC2

LLC1

VIN3

GNDF

VIN4

TEST

SCL

SDA

RESQ

FPDAT

VGAV

GNDP

PR2

PR1

PR0

GNDF

XTAL1

XTAL2

VSTBY

CLK5

GNDF

GNDP

VRT

ISGND

VSUPF

ASGF

VOUT

CIN

VIN1

VIN2

CLK20

VSUPD

GNDD

VSUPP

GNDP

GNDP NC

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

36 Micronas

4.5. Pin Circuits

Fig. 4–3: Input pins RESQ, TEST, VGAV

Fig. 4–4: Output pins C0–C7, Y0–Y7, FSY,

HC, AVO, HELPER, VS, INTLC, HS, LLC1, LLC2

Fig. 4–5: Output pin CLK20

Fig. 4–6: Input/Ou tput pins PR0–PR2, FPDAT

Fig. 4–7: Output pin VOUT

Fig. 4–8: Input/Output Pins XTAL1, XTAL2

Fig. 4–9: Pins VRT, ISGND

Fig. 4–10: Chroma input CIN

Fig. 4–11: Output pin CLK5

Fig. 4–12: Input pins VIN1–VIN4

Fig. 4–13: Pins SDA, SCL

VSUPD

GNDD

GNDP

VSUPP

VSUPD

GNDD

VSUPD

NGNDD

VSUPF

GNDF

VOUT

Vin’s

VREF

–

GNDF

VSTBY

NfECLK

0.5M

VSUPF

ISGND

VRT

Vref ADC Reference

–

GNDF

VSUPF

To ADC

GNDF

VSTBY

GNDF

VSUPF

To ADC

GNDD

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 37

4.6. Electrical Characteristics

4.6.1. Absolute Maximum Ratings

Stresses beyond those listed in the “Absolute Maximum Ratings” may c aus e permane nt dam age to the device. This

is a s tress rat ing only. Fu nctional operation o f th e device at these or any other cond itions b eyond th ose indi cated in

the “Recom mended Opera ting Conditions /Characteristi cs” of this spe cification is n ot implied. Exposure to absolute

maximum ratings conditions f or extended periods may affect device reliability.

4.6.2. Recommended Operating Conditions

Symbol Parameter Pin No. Min. Max. Unit

TAAmbient Operating Temperature –065°C

TSStorage Temperature ––40 125 °C

VSUP Supply Voltage, all Supply Inputs ––0.3 6 V

VIInput Voltage, all Inputs ––0.3 VSUP+0.3 V

VOOutput Voltage, all Outputs ––0.3 VSUP+0.3 V

Symbol Parameter Pin Name Min. Typ. Max. Unit

TAAmbient Operating Temperature –0–65 °C

VSUP Supply Voltages, all Supply Pins –4.75 5.0 5.25 V

VSUPP Supply Volt., Output Pad Supply VSUPP 3.15 –5.25 V

fXTAL Clock Frequency XTAL1/2 –20.25 –MHz

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

38 Micronas

4.6.3. Recommended Crystal Characteristics

Symbol Parameter Min. Typ. Max. Unit

TAOperating Ambient Temperature 0 –65 °C

fPParallel Resonance Frequency

with Load Capac ita nce CL = 13 pF –20.250000 –MHz

∆fP/fPAccuracy of Adjustment ––±20 ppm

∆fP/fPFrequency Temperature Drift ––±30 ppm

RRSeries Resistance ––25 Ω

C0Shunt Capacitance 3 –7pF

C1Motional Capacitance 20 –30 fF

Load Capacitance Recommendation

CLext External Load Capacitance 1) from

pins to Ground

(pin names: Xtal1 Xtal2)

–3.3 –pF

DCO Characteristics 2,3)

CICLoadmin Effective Load Capacitance @ min.

DCO–Position, Code 0,

package: 68PLCC

34.35.5pF

CICLoadrng Effective Load Capacitance Range,

DCO Codes from 0..255 11 12.7 15 pF

1) Remarks on defining the External Load Capacitance:

External c apacitors at each crystal pin to groun d are required . They are nece ssary to tune the e ffective lo ad capaci tance of th e

PCBs to the required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The

nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size

should be determined in the application. The suggested value is a figure based on experience with various PCB layouts.

Tuning condition: Code DVCO Register=–720

2) Remarks on Pulling Range of DCO:

The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard).

The resulting frequency fL with an effective load capacitance of CLeff = C ICLoad + CLoadBoard is :

1 + 0.5 * [ C1 / (C0 + CL) ]

fL = fP * _______________________

1 + 0.5 * [ C1 / (C0 + CLeff) ]

3) Remarks on DCO codes

The DCO hardware regi ster has 8 bits, the fp control register uses a range of –2048...2047

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 39

4.6.4. Characteristics

at TA = 0 to 65 °C, VSUPD/F = 4.75 to 5.25 V, VSUPP = 3.15 to 3.5V f = 20.25 MHz for min./max. values

at TC = 60 °C, VSUPD/F = 5 V, Vsupp = 3.15V f = 20.25 MHz for typical values

4.6.4.1. Characteristics, 5 MHz Clock Output

4.6.4.2. Characteristics, 20 MHz Clock Input/Output, External Cloc k Input (XTAL1)

4.6.4.3. Characteristics, Reset Input, Test Input

Symbol Parameter Pin N a me Min. Typ. Max. Unit

PTOT Total Power Dissipation ––1.15 1.5 W

IVSUPA Current Consumption VSUPF –40 –mA

IVSUPD Current Consumption VSUPD –160 –mA

IVSUPP Current Consumption VSUPP –40 –mA

IVSTDBY Current Consumption VSTDBY –1–mA

IL Input / Output Leakage Current All I/O Pins –1– 1 µA

Symbol Parameter Pi n N a m e Min. Typ. Max. Unit Test Conditions

VOL Output Low Voltage CLK5 ––0.4 V IOL = 0.4 mA

VOH Output High Voltage 4.0 –V–

STDBY V–IOL = 0.9 mA

tOT Output Transition Time –50 –ns CLOAD = 30 pF

Symbol Parameter Pi n N a m e Min. Typ. Max. Unit Test Conditions

VDCAV DC Average CLK20 VSUP/2

– 0.3 VSUP/2 VSUP/2

+ 0.3 VC

LOAD = 30 pF

VPP VOUT Peak to Peak 1.3 1.6 –VC

LOAD = 30 pF

tOT Output Transition Time ––18 ns CLOAD = 30 pF

VIT Input Trigger Level 2.1 2.5 2.9 V only for test purposes

VICloc k Input Voltage XTAL1 1.3 ––VPP capacitive coupling used,

XTAL2 open

Symbol Parameter Pi n N a m e Min. Typ. Max. Unit Test Conditions

VIL Input Low Voltage RESQ

TEST ––1.5 V

VIH Input High Voltage 3.0 ––V

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

40 Micronas

4.6.4.4. Characteristics, Priority, FPDAT Input/Output

Fig. 4–14: Priority, FPDAT input/output

4.6.4.5. Characteristics, VGAV Input

Symbol Parameter Pin Name Min. Typ. Max. Unit Tes t C o n ditions

VOL Output Low Voltage PR[2:0]

FPDAT ––0.5 V IOL = 14.4 mA, strength 0

IOL = 10.8 mA, strength 1

IOL = 7.2 mA, strength 2

IOL = 3.6 mA, strength 3

note: FPDAT strength = 2

VOH Output High Voltage 1.8 2.0 2.5 V –IOL = 10 µA

CLOAD = 70 pF

tOH Output Hold Time 6 ––ns

tODL Output Delay Time ––35 ns CLOAD = 70 pF

IL = 14.4 mA

strength = 3

IPL Output Pull-up Current PR[2:0]

FPDAT 1.2 1.5 1.5 mA VOL = 0 V

VIL Input Low Voltage ––0.8 V

VIH Input High Voltage 1.5 ––V

tIS Input Setup Time 7 ––ns

tIH Input Hold Time 5 ––ns

VIH

20.25 MHz Clock

VIL

VOHTRI

VOL

tODL

tOH

tIS tIH

Priority Bus

Output

Priority Bus

Input

Symbol Parameter Pin Name Min. Typ. Max. Unit Tes t C o n ditions

VIL Input Low Voltage VGAV ––0.8 V

VIH Input High Voltage 2.0 ––V

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 41

4.6.4.6. Characteristics, I2C Bus Interface

4.6.4.7. Characteristics, Analog Video Inputs

4.6.4.8. Characteristics, Analog Front-End and ADCs

Symbol Parameter Pi n N a m e Min. Typ. Max. Unit Test Conditions

VIL Input Low Voltage SDA, SCL ––1.5 V

VIH Input High Voltage 3.0 ––V

VOL Output Low Voltage ––0.4

0.6 V

VIl = 3 mA

Il = 6 mA

VIH Input Capacitance ––5pF

tFSignal Fall Time ––300 ns CL = 400 pF

tRSignal Rise Time ––300 ns CL = 400 pF

fSCL Clock Frequency SCL 0 –400 kHz

tLOW Low Period of SCL 1.3 ––µs

tHIGH High Period of SCL 0.6 ––µs

tSU Data Data Set Up Time to SCL high SDA 100 ––ns

tHD Data DATA Hold Time to SCL low 0 –0.9 µs

Symbol Parameter Pi n N a m e Min. Typ. Max. Unit Test Conditions

VVIN Analog Input Voltage VIN1, VIN2

VIN3, VI N 4

CIN

0–3.5 V

CCP Input Coupling Capacitor

Video Inputs VIN1, VIN2

VIN3, VI N 4 –680 –nF

CCP Input Coupling Capacitor

Chroma Input CIN –1–nF

Symbol Parameter Pi n N a m e Min. Typ. Max. Unit Test Conditions

VVRT Reference Voltage Top VR T 2.5 2.6 2.8 V 10 µF /10 nF, 1 GΩ Probe

Luma – Pa th

RVIN Input Resistance VIN1

VIN2

VIN3

VIN4

1––MΩCode Clamp–DAC=0

CVIN Input Capacitance –5–pF

VVIN Full Scale Input Voltage VIN1

VIN2

VIN3

VIN4

1.8 2.0 2.2 VPP min. AGC Gain

VVIN Full Scale Input Voltage 0.5 0.6 0.7 VPP max. AGC Gain

AGC AGC step width –0.166 –dB 6-B it Resolution= 64 Steps

fsig=1MHz,

– 2 dBr of max. AGC–Gain

DNLAGC AGC Differential Non-Linearity ––±0.5 LSB

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

42 Micronas

VVINCL Input Clamping Level, CVBS VIN1

VIN2

VIN3

VIN4

–1.0 –V Binary Level = 64 LSB

min. AGC Gain

QCL Clamping DAC Resolution –16 15 steps 5 Bit – I–DAC, bipolar

VVIN=1.5 V

ICL–LSB Input Clamping Current per step 0.7 1.0 1.3 µA

DNLICL Clamping DAC Differential Non-

Linearity ––±0.5 LSB

Chroma – Path

RCIN Input Resistance

SVHS Chroma CIN

VIN1 1.4 2.0 2.6 kΩ

VCIN Full Scale Input Vol tage,

Chroma 1.08 1.2 1.32 VPP

VCINDC Input Bias Level,

SVHS Chroma –1.5 –V

Binary Code for Open

Chroma Input –128 ––

Dynamic Characteristics for all Video-Paths (Luma + Chroma)

BW Bandwith VIN1

VIN2

VIN3

VIN4

810–MHz –2 dBr input signal level

XTALK Crosstalk, any Two Video Inputs ––56 –dB 1 MHz, –2 dBr signal level

THD Total Harmonic Distortion –50 –dB 1 MHz, 5 harmonics,

–2 dBr signal level

SINAD Signal to Noise and Distortion

Ratio –45 –dB 1 MHz, all outputs,

–2 dBr signal level

INL Integral Non-Linearity ––±1 LSB Code Density,

DC-ramp

DNL Differential Non-Linearity ––±0.8 LSB

DG Differential Gain ––±3% –12 dBr, 4.4 MHz signal on

DC-ramp

DP Differential Phase ––1.5 deg

Analog Video Output

VOUT Output Voltage Out:

VOUT

In:

VIN1

VIN2

VIN3

VIN4

1.7 2.0 2.3 VPP VIN = 1 VPP

, AGC= 0 dB

AGCVOUT AGC step width, VOUT –1.333 –dB 3 Bit Resolution=7 Steps

3 MSB’s of main AGC

DNLAGC AGC Diff erential Non-Linearity ––±0.5 LSB

VOUTDC DC-level –1–V clamped to Back porch

BW VOUT Bandwidth 8 10 –MHz Input: –2 dBr of main ADC

range, CL≤10 pF

THD VOUT Total Harmonic Distortion –––40 dB Input: –2 dBr of main ADC

range, CL≤10 pF

1 MHz, 5 Harmonics

CLVOUT Load Capacitance VOUT ––10 pF

ILVOUT Output Current ––±0.1 mA

Symbol Parameter Pin Name Min. Typ. Max. Unit Tes t C o n ditions

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 43

4.6.4.9. Characteristics, Output Pin Specification

Output Specification for SYNC, CONTROL, and DATA Pins:

Y[7:0], C[7:0], AVO, HS, HC, HELPER, INTLC, VS, FSY

NOTE 1: CLOAD depends on the selected driver strength which is I2C-programmable.

Fig. 4–15: Sync, control, and data outputs

Symbol Parameter Pi n N a m e Min. Typ. Max. Unit Test Conditions

VOL Output Low Voltage –––0.4 V see table below

VOH Output High Voltage –2.4 ––V see table below

tOH Output Hold Time –6––ns

tOD Output Delay Time –––35 ns NOTE 1

Table 4–1: Driver strength

Strength VSUPP = 5 V

Load VSUPP = 3.3 V

Load

000 < 100 pF < 50 pF

001 < 55 pF < 28 pF

010 < 37 pF < 20 pF

011 < 28 pF < 14 pF

100 < 23 pF < 12 pF

101 < 18 pF < 10 pF

110 < 14 pF < 8 pF

111 pins tristate

CLK20

20.25 MHz

in case of DIGIT3000 mode

LLC1

13.5 MHz

in case of LLC Mode

Output

2.0 V

tR, tF ≤ 5 ns

0.8 V

VOH

VOL

Data valid

tOD

tOH

Data valid

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

44 Micronas

4.6.4.10. Characterist ics, Input Pin Specification

Input Specification for SYNC, CONTROL, and DATA Pin: MSY (DIGIT3000 mode only)

Fig. 4–16: Sync, control, and data inputs

Symbol Parameter Pin Name Min. Typ. Max. Unit Tes t C o n ditions

VIL Input Low Voltage –––0.8 V

VIH Input High Voltage –1.5 ––V

tIS Input Setup Time –7––ns

tIH Input Hold Time –5––ns

CLK20

20.25 MHz

in case of DIGIT3000 Mode

LLC1

13.5 MHz

in case of LLC Mode

Input

Input Data valid

tIH

tIS

Data valid

tIH

tIS

VIH

VIL

2.0 V

tR, tF ≤ 5ns

0.8 V

VIH

VIL

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 45

4.6.4.11. Characteris tics, Clo ck Outp ut Specif icatio n

Line-Locked Clock Pins: LLC1, LLC2

Fig. 4–17: Line-locked clock output pins

Symbol Parameter Pi n N a m e Min. Typ. Max. Unit Test Conditions

CL Load capacitance –––50 pF

13.5 MHz Line Locked Clock

1/T13 LLC1 Clock Frequency –12.5 –14.5 MHz

tWL13 LLC1 Clock Low Time –26 ––ns CL = 30 pF

tWH13 LLC1 Clock High Time –26 ––ns CL = 30 pF

1/T27 LLC2 Clock Frequency –25 –29 MHz

tWL27 LLC2 Clock Low Time –10 ––ns CL = 30 pF

tWH27 LLC2 Clock High Time –10 ––ns CL = 30 pF

16 MHz Line Loc ked Clock

1/T13 LLC1 Clock Frequency –14.8 –17.2 MHz

18 MHz Line Loc ked Clock

1/T13 LLC1 Clock Frequency –16.6 –19.4 MHz

common ti mings – all modes

tSK Clock Skew –0–4ns

tR, tFCl ock Rise/Fall Time –––5nsC

L = 30 pF

VIL Input Low Voltage –––0.8 V

VIH Input High Voltage –2.0 ––V

VOL Output Low Voltage –––0.4 V IL = 2 mA

VOH Output High Voltage –2.4 ––VI

H = –2 mA

(13.5 MHz ±7%)

(27 MHz ±7%)

LLC2

LLC1

VIL

VIH

VIL

VIH

tSK

tWL13

tWH13

T13

tRtF

T27

tWL27

tWH27

tSK

tRtF

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

46 Micronas

5. Application Circuit

VPC 32x5C

PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Micronas 47

5.1. VGA mode with VPC3215C

In 100 Hz TV applications it can be desirab le to display

a VGA-signal on the TV. In this case a VGA-graphic

card de li vers the H, V a nd RGB si gna ls. Th es e sign al s

can be feed "directly" to the backend signal process-

ing. The VPC can generate a stable line locked clock

for the 100 Hz syst em in relation to the VG A sync sig-

nals.

While the V-sync is connected to the VGAV pin

direc tly, the H- sy nc ha s to be pulse -sha ped and ampli-

tude adjusted until it is connected to one of the video

input pins of the VPC. The recommended circuitry to

filter the H sync is given in the figure below.

Fig. 5–1: Application circuit for horizontal VGA-input

680 nF

Video Input VPC

H 31kHz 270 Ω

47pF

540 Ω

1N4148

BC848B

100 Ω

1kΩ

+5V analog

1N4148

2kΩ

GND analog GND analog

VPC 3205C, VPC 3215C PRELIMINARY DATA SH EET

48 Micronas

All information and data contained in this data sheet are without any

commitment, are not to be considered as an offer for conclusion of a

contract, nor shall they be constr ued as to create any liability. Any new

issue of this data sheet invalidates previous issues. Product availability

and delivery are exclusively subject to our respective order confirmation

form; the same applies to orders based on development samples deliv-

ered. By this publication, Micronas GmbH does not assume responsibil-

ity for patent infringements or other rights of third parties which may

result from its use.

Further, Micronas GmbH reserves the right to revise this publication and

to make c hanges to i ts conte nt, at any t ime, withou t obligati on to no tify

any person or entity of such revisions or changes.

No part of this publication may be reproduced, photocopied, stored on a

retrieval system, or transmitted without the express written consent of

Micr on as Gm bH .

Micronas GmbH

Hans-Bunte-Strasse 19

D-79108 Freiburg (Germany)

P.O. Box 840

D-79008 Freiburg (Germany)

Tel. +49-761-517-0

Fax +49-761-517-2174

E-mail: docservice@micronas.com

Internet: www.micronas.com

Printed in Germany

Order No. 6251-457-2PD

6. Data Sheet History

1. Preliminary data sheet: “VPC 3205C, VPC 3215C

Video Processor Family, Aug. 15, 1997

6251-457-1PD. First release of the preliminary data

sheet.

2. Preliminary data sheet: “VPC 3205C, VPC 3215C

Video Processor Family, Oct. 19, 1998,

6251-457-2PD. Second release of the preliminary data

sheet. Major changes:

–Fig. 4–1: Outline Dimensions for PLCC68 changed.

–Additional information contained in Supplement

No.3 / 6251-457-3PDS, Edition May 25 1998 has

been included.