Cover MVPG30x/MVPG31 Field Programmable DSP SwitcherTM 1 MHz, 3.0A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology Datasheet Doc. No. MV-S102808-00, Rev. G April 14, 2008 Marvell. Moving Forward Faster Document Classification: Proprietary MVPG30x/MVPG31 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: 2.00 Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 2008. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners. Doc. No. MV-S102808-00 Rev. G Page 2 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 MVPG30x/MVPG31 1 MHz, 3.0A Peak Current-Limit Step-Down Regulator with AnyVoltageTM Technology Datasheet PRODUCT OVERVIEW The Marvell(R) MVPG30x/MVPG31 is an intelligent digital synchronous step-down (Buck) switching regulator housed in a 4 mm x 3 mm DFN-12 package. The MVPG15x has an additional on-chip Low-Drop-Out (LDO) regulator controller. Internally self-compensated, the step-down regulator requires no external compensation and work with low-ESR output capacitors to simplify the design, minimize the board space, and reduce the amount of external components. The switching frequency for the step-down regulator is 1 MHz, allowing the use of low profile surface mount inductors and low value capacitors. The step-down regulator includes programmable output voltage to provide the user the ability to easily set the output voltage with external resistors, logic control, or serial data interface. The output voltage range is 0.72V to 3.63V. Features The LDO regulator controller with an external P-Channel MOSFET forms a low dropout regulator capable of driving 800 mA output current. The output voltage of the LDO regulator is fixed. The MVPG30x/MVPG31 operate from an input voltage range of 3.0V to 5.5V, making the device well-suited for portable applications. Tiny 4 mm x 3 mm DFN-12 package 1 MHz switching frequency Small and low profile inductors Stable with ceramic output capacitors No external compensation required Minimum amount of external components Over 95% efficiency High peak switch current limit: 3.0A Input voltage range: 3.0V to 5.5V Serial/Logic programmability AnyVoltageTM Technology provides 64 output voltage selections to provide flexibility Programmable output voltage range: 0.72V to 3.63V P-Channel LDO regulator controller with programmable current limit (MVPG30x) Lead-free packages Built-in under voltage lockout Over voltage protection Thermal shutdown protection Output voltage margining capability Application Other key features of the MVPG30x/MVPG31 include an internal current limit for the step-down regulator, an Under Voltage Lockout (UVLO), and thermal shutdown. Portable computing Point of load power supplies DSP power supplies Disk drive power supplies Figure 1: Typical High Efficiency 5.0V to 0.8V/2.0A Step-Down Regulator with 3.3V LDO Regulator R1 2 8 11 12 R3 11K 10 PVIN LDR 3 V OUT1 3.3V/up to 0.8A SVIN 1 LFB VSET MVPG30B 6 PSET SW SHDN SGND EP 4 Caution C3 10uF/6.3V U1 7 C1 0.1uF FDC642 P 47 mohm C2 10uF/6.3V ILIM R2 10 PGND VIN +3.0V to + 5.5V SFB L1 V OUT2 0.8V/2.0A 2.0uH 5 C4 22uF/6.3V This is a very high frequency device and proper PCB layout is required. Refer to Section 6, Applications Information, on page 49 for further information. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 3 MVPG30x/MVPG31 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102808-00 Rev. G Page 4 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Table of Contents Table of Contents Product Overview ....................................................................................................................................... 3 Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables ............................................................................................................................................ 11 1 Signal Description ....................................................................................................................... 13 1.1 Pin Configuration.............................................................................................................................................13 1.2 Pin Type Definitions .......................................................................................................................................15 1.3 Pin Description ................................................................................................................................................15 2 Electrical Specifications ............................................................................................................. 17 2.1 Absolute Maximum Ratings ............................................................................................................................17 2.2 Recommended Operating Conditions .............................................................................................................18 2.3 Electrical Characteristics ................................................................................................................................19 2.4 Switching Step-down Regulator ......................................................................................................................20 2.5 LDO Regulator Controller................................................................................................................................21 3 Functional Description................................................................................................................ 23 3.1 Regulation and Startup ...................................................................................................................................24 3.1.1 Digital Soft Start ................................................................................................................................24 3.2 Output Voltage--AnyVoltageTM Technology ...................................................................................................26 3.3 Programmable Current Limit for the LDO Regulator Controller ......................................................................28 3.3.1 Maximum LDO Output Current .........................................................................................................29 3.4 Under Voltage Lockout....................................................................................................................................29 3.5 Over Voltage Protection ..................................................................................................................................29 3.6 Thermal Shutdown ..........................................................................................................................................30 3.7 Adaptive Transient Response .........................................................................................................................31 4 Functional Characteristics ......................................................................................................... 33 4.1 Startup Waveforms .........................................................................................................................................33 4.2 Switching Waveforms......................................................................................................................................36 4.3 Load Transient Waveforms .............................................................................................................................37 4.3.1 Step-Down Regulator .......................................................................................................................37 4.3.2 LDO Regulator ..................................................................................................................................38 5 Typical Characteristics ............................................................................................................... 39 5.1 Efficiency Graphs ............................................................................................................................................39 5.2 Load Regulation ..............................................................................................................................................40 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 5 MVPG30x/MVPG31 Datasheet 5.3 Dropout Voltage ..............................................................................................................................................40 5.4 RDS (ON) Resistance .....................................................................................................................................41 5.5 IC Case and Inductor Temperature.................................................................................................................42 5.6 Input Voltage Graph ........................................................................................................................................43 5.6.1 Step-Down Regulator .......................................................................................................................43 5.6.2 LDO Regulator ..................................................................................................................................45 5.7 Temperature Graphs .......................................................................................................................................46 5.7.1 Step-Down Regulator .......................................................................................................................46 5.7.2 LDO Regulator ..................................................................................................................................48 6 Applications Information ............................................................................................................ 49 6.1 PC Board Layout Considerations and Guidelines ..........................................................................................49 6.1.1 PC Board Layout Examples for MVPG30x/MVPG31 .......................................................................51 6.2 Bill of Materials ................................................................................................................................................54 7 Mechanical Drawing .................................................................................................................... 57 7.1 Mechanical Drawing ........................................................................................................................................57 7.2 Dimensions .....................................................................................................................................................58 7.3 Typical Pad Layout Dimensions ......................................................................................................................59 7.3.1 Recommended Solder Pad Layout ...................................................................................................59 8 Part Order Numbering/Package Marking .................................................................................. 61 8.1 Part Order Numbering .....................................................................................................................................61 8.2 Package Marking ............................................................................................................................................62 A Revision History .......................................................................................................................... 65 Doc. No. MV-S102808-00 Rev. G Page 6 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 List of Figures List of Figures Product Overview ....................................................................................................................................... 3 Figure 1: 1 Typical High Efficiency 5.0V to 0.8V/2.0A Step-Down Regulator with 3.3V LDO Regulator ..............3 Signal Description ........................................................................................................................... 13 Figure 2: 12-Pin DFN Pin Diagram--MVPG30x Top View ..............................................................................13 Figure 3: 12-Pin DFN Pin Diagram--MVPG31 Top View ................................................................................14 2 Electrical Specifications ................................................................................................................. 17 3 Functional Description.................................................................................................................... 23 Figure 4: 4 MVPG30x/MVPG31 Block Diagram .................................................................................................23 Figure 5: Output Voltage Window ....................................................................................................................24 Figure 6: Inductor Current Steps at Startup .....................................................................................................25 Figure 7: Soft Startup (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) ......................................................................................25 Figure 8: Soft Startup.......................................................................................................................................25 Figure 9: Startup Sequence ............................................................................................................................27 Figure 10: VSET = 2.5V and PSET = -5% ............................................................................................................27 Figure 11: Maximum Output Current for the FDS642P P-Channel MOSFET....................................................29 Figure 12: UVLO and OVP Waveforms .............................................................................................................30 Figure 13: Adaptive Transient Response ..........................................................................................................31 Functional Characteristics.............................................................................................................. 33 Figure 14: Startup Using the Shutdown Pin ......................................................................................................33 Figure 15: Turn Off Using the Shutdown Pin .....................................................................................................33 Figure 16: Enable Threshold at VIN = 3.5V ........................................................................................................33 Figure 17: Enable Threshold at VIN = 5.0V ........................................................................................................33 Figure 18: Input Voltage Soft Start.....................................................................................................................34 Figure 19: Input Voltage Hot Plug ......................................................................................................................34 Figure 20: Step-Down Output Rise Time ...........................................................................................................34 Figure 21: Soft Start Current Limit Steps ...........................................................................................................34 Figure 22: UVLO and OVP Thresholds..............................................................................................................35 Figure 23: Switching Waveforms-- PWM Mode ...............................................................................................36 Figure 24: Switching Waveforms-- DCM Mode.................................................................................................36 Figure 25: PWM Output Ripple Voltage .............................................................................................................36 Figure 26: Switching Waveforms-- DCM Mode-Zoom ......................................................................................36 Figure 27: Load Transient Response ................................................................................................................37 Figure 28: Double-Pulsed Load Response ........................................................................................................37 Figure 29: Load Transient Response ................................................................................................................37 Figure 30: Double-Pulsed Load Response ........................................................................................................37 Figure 31: Load Transient Response ................................................................................................................38 Figure 32: Double-Pulsed Load Response ........................................................................................................38 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 7 MVPG30x/MVPG31 Datasheet Figure 33: 5 6 Typical Characteristics ................................................................................................................... 39 Figure 34: Efficiency Graphs..............................................................................................................................39 Figure 35: Load Regulation................................................................................................................................40 Figure 36: Dropout Voltage ................................................................................................................................40 Figure 37: RDS (ON) Resistance.......................................................................................................................41 Figure 38: IC Case and Inductor Temperature ..................................................................................................42 Figure 39: Supply Current vs. Input Voltage ......................................................................................................43 Figure 40: Output Voltage vs. Input Voltage ......................................................................................................43 Figure 41: Efficiency vs. Input Voltage...............................................................................................................43 Figure 42: Load Regulation vs. Input Voltage ....................................................................................................44 Figure 43: Frequency vs. Input Voltage .............................................................................................................44 Figure 44: Average Output Current Limit vs. Input Voltage ...............................................................................44 Figure 45: Output Voltage vs. Input Voltage ......................................................................................................45 Figure 46: LDO Load Regulation vs. Input Voltage ...........................................................................................45 Figure 47: Average Output Current Limit vs. Input Voltage ...............................................................................45 Figure 48: Supply Current vs. Temperature.......................................................................................................46 Figure 49: UVLO vs. Temperature .....................................................................................................................46 Figure 50: Output Voltage vs. Temperature.......................................................................................................46 Figure 51: Efficiency vs. Temperature ...............................................................................................................46 Figure 52: Load Regulation vs. Temperature ....................................................................................................47 Figure 53: Line Regulation vs. Temperature......................................................................................................47 Figure 54: Average Output Current Limit vs. Temperature ................................................................................47 Figure 55: Frequency vs. Temperature..............................................................................................................47 Figure 56: Output Voltage vs. Temperature.......................................................................................................48 Figure 57: Load Regulation vs. Temperature ....................................................................................................48 Figure 58: Line Regulation vs. Temperature......................................................................................................48 Figure 59: Average Output Current Limit vs. Temperature ................................................................................48 Applications Information ................................................................................................................ 49 Figure 60: 7 8 Load Transient Response ................................................................................................................38 MVPG30x PCB Layout Schematic ...................................................................................................50 Figure 61: MVPG31 PCB Layout Schematic .....................................................................................................50 Figure 62: Top Silk-Screen (Not to scale)--MVPG30x ......................................................................................51 Figure 63: Top Silk-Screen (Not to scale)--MVPG31........................................................................................51 Figure 64: Top Traces, Vias, and Copper (Not to scale)--MVPG30x................................................................52 Figure 65: Top Traces, Vias, and Copper (Not to scale)--MVPG31 .................................................................52 Figure 66: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale)--MVPG30x ...............53 Figure 67: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale)--MVPG31 .................53 Mechanical Drawing ........................................................................................................................ 57 Figure 68: Mechanical Drawing .........................................................................................................................57 Figure 69: Recommended Solder Pad Layout ...................................................................................................59 Part Order Numbering/Package Marking....................................................................................... 61 Doc. No. MV-S102808-00 Rev. G Page 8 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 List of Figures A Figure 70: Sample Part Order Number ..............................................................................................................61 Figure 71: MVPG30x Package Marking.............................................................................................................62 Figure 72: MVPG31 Package Marking ..............................................................................................................63 Revision History ............................................................................................................................... 65 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 9 MVPG30x/MVPG31 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102808-00 Rev. G Page 10 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 List of Tables List of Tables 1 2 3 Signal Description ............................................................................................................................ 13 Table 1: Pin Type Definitions ..........................................................................................................................15 Table 2: Pin Description..................................................................................................................................15 Electrical Specifications .................................................................................................................. 17 Table 3: Absolute Maximum Ratings ..............................................................................................................17 Table 4: Recommended Operating Conditions...............................................................................................18 Table 5: Electrical Characteristics ..................................................................................................................19 Table 6: Switching Step-down Regulator........................................................................................................20 Table 7: LDO Regulator Controller .................................................................................................................21 Functional Description..................................................................................................................... 23 Table 8: AnyVoltageTM Programming Table for 1% Resistors .......................................................................26 Table 9: Output Voltage Option Steps ............................................................................................................27 Table 10: P-Channel MOSFET Selection .........................................................................................................28 4 Functional Characteristics............................................................................................................... 33 5 Typical Characteristics .................................................................................................................... 39 6 Applications Information ................................................................................................................. 49 7 Table 11: MVPG30x BOM ................................................................................................................................54 Table 12: MVPG31 BOM ..................................................................................................................................55 Mechanical Drawing ......................................................................................................................... 57 Table 13: 8 Part Order Numbering/Package Marking........................................................................................ 61 Table 14: A Dimensions .......................................................................................................................................58 Part Order Options............................................................................................................................61 Revision History ............................................................................................................................... 65 Table 15: Revision History ................................................................................................................................65 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 11 MVPG30x/MVPG31 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102808-00 Rev. G Page 12 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Signal Description Pin Configuration 1 Signal Description 1.1 Pin Configuration Figure 2: 12-Pin DFN Pin Diagram--MVPG30x Top View LFB 1 12 PSET ILIM 2 11 VSET LDR 3 10 SHDN MVPG30x SGND 4 SFB 5 PGND SW 6 Copyright (c) 2008 Marvell April 14, 2008, 2.00 9 NC 8 SVIN 7 PVIN Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 13 MVPG30x/MVPG31 Datasheet Figure 3: 12-Pin DFN Pin Diagram--MVPG31 Top View NC 1 12 PSET NC 2 11 VSET NC 3 10 SHDN MVPG31 SGND 4 SFB 5 PGND SW 6 Doc. No. MV-S102808-00 Rev. G Page 14 9 NC 8 SVIN 7 PVIN Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Signal Description Pin Type Definitions 1.2 Table 1: Pin Type Definitions Pin Type Definitions Pi n Typ e Defi ni ti o ns I Input only O Output only S Supply NC Not Connected GND Ground 1.3 Pin Description Table 2 provides pin descriptions for the MVPG30x/MVPG31. Table 2: Pin Description MVPG30x Pi n # MVPG31 Pi n # P in N a m e P i n Ty p e Pi n F u nc t io n 1 -- LFB I LDO Regulator Controller Feedback Senses the output voltage of the LDO regulator. Connect to the drain of the P-channel MOSFET. When the LDO controller is not used, float the LDR pin. Connect the LFB to SGND, and connect ILIM to SVIN. 2 -- ILIM I Current-Limit Sense Pin for the LDO Regulator A built-in offset of 50 mV (typical) between VIN and ILIM in conjunction with the sense resistor is used to set the current-limit threshold for the LDO regulator controller. Connecting this pin to VIN disables the internal current limit circuitry. When the LDO controller is not used, float the LDR pin. Connect the LFB to SGND, and connect ILIM to SVIN. 3 -- LDR O LDO Regulator Controller Driver Connect to the gate of an external P-channel MOSFET. The external P-Channel MOSFET needs to have a threshold of -2.5V or lower and input capacitance (Ciss) of less than 1000 pF. When the LDO controller is not used, float the LDR pin. Connect the LFB to SGND, and connect ILIM to SVIN. 4 4 SGND O Signal Ground This pin must connect to the power ground. 5 5 SFB I Switching Regulator Feedback Senses the output voltage of the switching regulator. 6 6 SW O Switch Node Internal power MOSFET drain. This pin must connect to an external inductor. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 15 MVPG30x/MVPG31 Datasheet Table 2: Pin Description (Continued) MVPG30x Pi n # MVPG31 Pi n # P in N a m e P i n Ty p e Pi n F u nc t io n 7 7 PVIN I Power Input Voltage Internal power MOSFET source. Connect the decoupling 10 F capacitors between PVIN and PGND and position it as close as possible to the IC. 8 8 SVIN I Signal Input Voltage Input voltage is 3.0V to 5.5V for internal circuitry. Connect a 0.1 F decoupling capacitor between SVIN and SGND and position it as close as possible to the IC. 9 1, 2, 3, 9 NC O No Connect This pin is left floating. Do not connect this pin. 10 10 SHDN I Shutdown Logic low (0.8V) enables the step-down switching regulator and the LDO regulator controller. Logic high (2.0V) disables the step-down switching regulator and the LDO regulator controller. The high signal duration has to be at least 20 s to disable both regulators. 11 12 VSET I Voltage Set 1. Connect an external resistor to ground to set the output voltage of the step-down switching regulator. See Table 5, Electrical Characteristics, on page 19 for resistor values and output voltage options. 2. The total capacitance across this pin and SGND should not be greater than 25 pF. Shorting this pin to signal ground, floating this pin, or using 619 k< RVSET or RVSET<7.68 k disables the step-down switching regulator and sets the SFB pin to high impedance. Use resistor value with tolerance better than 2%. 12 12 PSET I Percent Set 1. Connect an external resistor to ground to set the output voltage of the step-down switching regulator. See Table 5, Electrical Characteristics, on page 19 for resistor values and output voltage options. 2. The total capacitance across this pin and SGND should not be greater than 25 pF. Shorting this pin to signal ground, floating this pin, or using 619 k< RPSET or RPSET<7.68 k does not affect the set voltage. Use resistor value with tolerance better than 2%. Although this pin can be left floating when it is not used, it is recommended to connect this pin to ground. Exposed Pad Exposed Pad PGND GND Power Ground The power ground must connect to the negative terminal of the input and output capacitors. Doc. No. MV-S102808-00 Rev. G Page 16 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Electrical Specifications Absolute Maximum Ratings 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings1 NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter Min Ty p Max U n i ts PVIN to PGND -0.3 -- 6.0 V PVIN to SVIN -0.3 -- +0.3 V PGND to SGND -0.3 -- +0.3 V VSW to PGND2 -0.3 -- (PVIN +0.3) V VSFB to SGND -0.3 -- (SVIN +0.3) V VVSET, VPSET to SGND -0.3 -- (SVIN +0.3) V VILIM, VLDR, VLFB to SGND -0.3 -- (SVIN +0.3) V VSHDN to SGND -0.3 -- (SVIN +0.3) V Operating Ambient Temperature Range3 -40 -- 85 C Maximum Junction Temperature -- -- 150 C Storage Temperature Range -65 -- 150 C Lead Temperature (soldering, 10s) -- 300 -- C ESD Rating4 -- 2.0 -- kV 1. Exceeding the absolute maximum rating may damage the device. 2. Capable of -1.0V for less than 50 ns. 3. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization and correlation with statistical process controls. 4. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5 k, in series with 100 pF. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 17 MVPG30x/MVPG31 Datasheet 2.2 Table 4: Recommended Operating Conditions Recommended Operating Conditions1 Sy m b o l P a r a m e te r Min Ty p Max U n i ts SVIN Signal Input Voltage 3.0 -- 5.5 V PVIN Power Input Voltage 3.0 -- 5.5 V JA Package Thermal Resistance2 -- 48.1 -- C/W -- 4.4 -- C/W -- -- 125 C JC TJMAX Maximum Operating Junction Temperature 1. This device is not guaranteed to function outside the specified operating range. 2. Tested on 4-layer (JESD51-7) and vias (JESD51-5) boards. Doc. No. MV-S102808-00 Rev. G Page 18 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Electrical Specifications Electrical Characteristics 2.3 Table 5: Electrical Characteristics Electrical Characteristics NOTE: The following applies unless otherwise noted: SVIN = PVIN = 5.0V, VSHDN = SGND = PGND, L(BUCK) = 2.0 H, COUT(BUCK) = 22 F (Ceramic), PFET = FDC642P, COUT(LDO) = 10 F (Ceramic), TA = 25C. Bold values indicate -40C < TA < 85C. Sy m b o l P a r a m e te r C o nd i ti on s Min Ty p e Max U n its SVIN Input Voltage Range SVIN = PVIN 3.0 -- 5.5 V Total Quiescent Current No load, VOUT = TBD -- 1.3 -- mA ISVIN Shutdown Supply Current VSHDN = SVIN = 5.5V -- 1.0 10 A VUVLO Under Voltage Lockout High threshold, SVIN increasing, ILOAD = 10mA -- 2.65 2.85 V Low threshold, SVIN decreasing, ILOAD = 10mA 2.35 2.50 -- V High threshold, SVIN increasing, ILOAD = 10mA -- 5.7 TBD V Low threshold, SVIN decreasing, ILOAD = 10mA TBD 5.6 -- V Enable regulators -- -- 0.8 V Disable regulators 2.0 -- -- VOVP VSHDN Over Voltage Protection Shutdown Input Voltage Logic ISHDN Shutdown Input Current VSHDN = SGND = PGND or 5.5V -- -- 1.0 A TOTS Over-temperature Thermal Shutdown TJ increasing (Disable regulators) -- 150 -- C TJ decreasing (Enable regulators) -- 120 -- C Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 19 MVPG30x/MVPG31 Datasheet 2.4 Table 6: Switching Step-down Regulator Switching Step-down Regulator NOTE: The following applies unless otherwise noted: SVIN = PVIN = 5.0V, VPSET = VSHDN = SGND = PGND, RVSET = 11 k, L = 2.0 H, COUT = 22 F (Ceramic), TA = 25 C. Bold values indicate -40C < TA < 85C. Sy m b o l P a r a m e te r Conditions M in Ty p Max U ni ts Output Voltage RVSET = 11K, PWM mode -- 0.8 -- V RVSET = 18.7K, PWM mode -- 1.0 -- RVSET = 31.6K, PWM mode -- 1.2 -- RVSET = 53.6K, PWM mode -- 1.5 -- RVSET = 97.6K, PWM mode -- 1.8 -- RVSET = 165K, PWM mode -- 2.5 -- RVSET = 280K, PWM mode -- 3.0 -- RVSET = 475K, PWM mode -- 3.3 -- RPSET = 11K -- -10 -- RPSET = 18.7K -- -7.5 -- RPSET = 31.6K -- -5.0 -- RPSET = 53.6K -- -2.5 -- RPSET = 97.6K -- 2.5 -- RPSET = 165K -- 5.0 -- RPSET = 280K -- 7.5 -- RPSET = 475K -- 10 -- Percentage Set % VLNREG Output Voltage Line Regulation SVIN = PVIN = 3.0V to 5.0V VOUT = 1.5V ILOAD = 500 mA -- 0.1 -- % VLDREG Output Voltage Load Regulation SVIN = PVIN = 5.0V VOUT = 1.5V ILOAD = 500 mA to 2.0A -- 0.2 -- % fSW Switching Frequency PWM mode -- 1.0 -- MHz RPFET RDS(ON) = of P-Channel FET SVIN = 3.0V, ISW = 100 mA -- 150 -- m SVIN = 5.0V, ISW = 100 mA -- 120 -- SVIN = 3.0V, ISW = 100 mA -- 90 -- SVIN = 5.0V, ISW = 100 mA -- 70 -- -- TBD -- RNFET ILIM RDS(ON) = of N-Channel FET Minimum Peak Switch Current Limit Doc. No. MV-S102808-00 Rev. G Page 20 m A Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Electrical Specifications LDO Regulator Controller Table 6: Switching Step-down Regulator (Continued) NOTE: The following applies unless otherwise noted: SVIN = PVIN = 5.0V, VPSET = VSHDN = SGND = PGND, RVSET = 11 k, L = 2.0 H, COUT = 22 F (Ceramic), TA = 25 C. Bold values indicate -40C < TA < 85C. Sy m b o l P a r a m e te r Conditions M in Ty p Max U ni ts ILSW Switch Leakage Current SVIN = PVIN = VSHDN = 5.5V VSW = PGND or 5.5V -- 1 50 A 2.5 Table 7: LDO Regulator Controller LDO Regulator Controller NOTE: The following applies unless otherwise noted: SVIN = PVIN = 5.0V, VSHDN = SGND = PGND, PFET= FDC642P, COUT = 10 F, TA = 25 C. Bold values indicate -40C < TA < 85C. Sy m b o l P a r a m e te r C o nd i ti on s M in Ty pe Max U ni ts Output Voltage Accuracy Room Temp, ILOAD = 10 mA -- 1 -- % Over Temp, ILOAD = 10 mA -- 2 -- VLNREG Line Regulation SVIN = PVIN = 3.5V to 5.0V, VOUT = 3.3V, ILOAD = 10 mA -- 0.08 -- % VLDREG Load Regulation SVIN = PVIN = 5.0V, VOUT = 3.3V, ILOAD = 10 mA to 800 mA -- 0.05 -- % VILTH Current-Limit Threshold SVIN-VILIM -- 50 -- mV Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 21 MVPG30x/MVPG31 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102808-00 Rev. G Page 22 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Functional Description 3 Functional Description Figure 4: MVPG30x/MVPG31 Block Diagram Q1 V +3.0V - 5.5V IN R1 C2 PVIN OSCILLATOR SVIN RSENSE C1 ILIM OUT1 V OUT2 LDR INTERNAL CIRCUITRY POWER SUPPLY CURRENT LIMIT V C3 LDO CONTROLLER LFB ENABLE_LDO ANALOGDIGITAL CONVERTER L1 PWM CONTROL DSP DRIVER SW PGND FAULT RESISTOR NETWORK ENABLE_LDO UVLO_LDO UNDERVOLTAGE LOCK-OUT C4 SFB BAND-GAPVOLTAGE REFERENCE FAULT RESISTOR SENSING CIRCUITRY THERMAL SHUT-DOWN SHDN SGND OFF VSET PSET R2 R3 ON Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 23 MVPG30x/MVPG31 Datasheet 3.1 Regulation and Startup The step-down switching regulator uses Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) modes to regulate the output voltage using digital control. The mode of operation depends on the level of output current and the output voltage. In steady states, the step-down switching regulator monitors the current flowing through the inductor to determine if the regulator is handling heavy or light load applications. For heavy load applications, the step-down regulator operates in the PWM mode (B and C) to minimize the ripple current for optimum efficiency and to minimize the ripple output voltage. The step-down regulator operates in the PFM and Discontinuous Conduction Mode (DCM) (A and D) to limit the switching actions for optimum efficiency in light load applications. In this mode, the average output voltage is slightly higher than the average output voltage for heavy transient load applications. Figure 5: Output Voltage Window A B C D Typical VOUT 3.1.1 PFM Mode PWM Mode PFM Mode Digital Soft Start During startup, the MVPG30x/MVPG31 provides a soft start function. Soft start reduces surge currents from the input voltage and provides well-controlled output voltage rise characteristics. The rate of the output voltage startup is limited by the value of the output capacitor and the internal current limit circuitry. This combination forces the output voltage to ramp up slowly, providing a soft start characteristic. During soft start, the MVPG30x/MVPG31 feeds a constant current to the output capacitor in several steps. Figure 6 shows the inductor current waveform during startup. The current limit is ramped up in seven steps beginning at approximately 40% of the current limit rating and ending at 100% at 25 s per step. The buck regulator behaves like a current source during this time as the output ramps up slowly. Figure 7 shows that the rise time for a MVPG30x/MVPG31 increases from 20 s at for a 0.8V output to 70 s for a 3.3V output with a 20 mA load. From Figure 8, the rise time can be estimated by assuming an average charging current of 0.75A. Rise time with a 3.3V output is calculated using the following equation. Cout * Vout RiseTime = -----------------------------I 22F * 3.3V = ------------------------------- = 96.8s 0.75A Doc. No. MV-S102808-00 Rev. G Page 24 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Functional Description Regulation and Startup Figure 6: Inductor Current Steps at Startup Figure 7: Soft Startup (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) 1V/DIV 500 mV/DIV VBUCK VBUCK IIND 500 mA/DIV 50 s/DIV 10 s/DIV COUT = 22 F ILOAD = 20 mA Figure 8: Soft Startup VOUT 1V/DIV IOUT 1A/DIV 50 s/DIV VOUT = 3.3V ILOAD = 1.65 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 25 MVPG30x/MVPG31 Datasheet 3.2 Output Voltage--AnyVoltageTM Technology The output voltage of the step-down switching regulator is programmed by using Table 8 to select resistor values for VSET and PSET pin. The VSET pin sets the output voltage and the PSET pin trims the set voltage to a percentage value. For example, to program 2.25V output, a 165 k resistor is selected for the VSET pin, and an 11 k resistor is selected for the PSET pin. The 165 k resistor sets the output voltage to 2.5V and the 11 k resistor trims the set voltage by -10%. Using the VSET resistor's value greater than 619 k or less than 7.68 k disables the step-down switching regulator and sets the SW pin to high impedance. If the VSET resistor's value is outside the 2% tolerance, the output can be either higher or lower than the set voltage. Using resistor values greater than 619 k or less than 7.68 k for the PSET pin does not affect the set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor, the percent value can be either higher or lower if the PSET resistor's value is outside the 2% tolerance. Table 8: AnyVoltageTM Programming Table for 1% Resistors VS E T P SE T - 1 0 .0 % - 7 .5 % -5.0% - 2 .5 % 0% 2.5% 5. 0 % 7 .5 % 1 0 . 0% 11 k 1 8 .7 k 31.6k 5 3 .6 k GND 97.6k 16 5 k 280k 475k GND Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 11 k 0.720 0.740 0.760 0.780 0.800 0.820 0.840 0.860 0.880 1 8 .7 k 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 3 1 .6 k 1.080 1.110 1.140 1.170 1.200 1.230 1.260 1.290 1.320 5 3 .6 k 1.350 1.388 1.425 1.463 1.500 1.538 1.575 1.613 1.650 9 7 .6 k 1.620 1.665 1.710 1.755 1.800 1.845 1.890 1.935 1.980 165k 2.250 2.313 2.375 2.438 2.500 2.563 2.625 2.688 2.750 280k 2.700 2.775 2.850 2.925 3.000 3.075 3.150 3.225 3.300 475k 2.970 3.053 3.135 3.218 3.300 3.383 3.465 3.548 3.630 Open Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z The VSET and PSET resistors are read once during startup before the output voltage is turned on. The output voltage cannot be changed on-the-fly. To configure the output to a different voltage, power has to recycle or the MVPG30x/MVPG31 has to turn OFF and back ON using the shutdown pin. Figure 9 shows the startup waveforms of the MVPG30x/MVPG31. Once the input voltage (VIN) is above the Under Voltage Lockout (UVLO) Upper Threshold (UTH), the VSET and PSET pin become active. Current is first sourced out of PSET pin and then the VSET pin, in exponentially increasing steps. After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V reference. If the VSET voltage is below internal reference voltage, the current source proceeds to the next step. Once the VSET voltage is above the internal reference voltage the sequence stops and the output voltage (VOUT) is allowed to turn on. Figure 10 shows the VSET waveform for VSET = 2.5V and PSET = -5% output. The MVPG30x/MVPG31 keeps track of how many steps are Doc. No. MV-S102808-00 Rev. G Page 26 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Functional Description Output Voltage--AnyVoltageTM Technology required to determine the appropriate output voltage. Table 9 provides the number of steps necessary for each output voltage option. Using a VSET resistor of 165 k requires the current source to step four times, and a PSET resistor of 31.6 k requires seven steps. Figure 9: Startup Sequence Figure 10: VSET = 2.5V and PSET = -5% VIN 2V/DIV VSET 500mV/DIV VOUT 1V/DIV VSET 1V/DIV 20m 500mV/DIV 500 PSET PSET 1V/DIV 200 s/DIV 2.0 ms/DIV Table 9: Output Voltage Option Steps Ste p VOUT (V ) R VSET (k ) St ep P SE T (%) R PSET (k ) 1 0 0 1 0 0 2 3.3 475 2 +10 475 3 3.0 280 3 +7.5 280 4 2.5 165 4 +5.0 165 5 1.8 97.6 5 +2.5 97.6 6 1.5 53.6 6 -2.5 53.6 7 1.2 31.6 7 -5.0 31.6 8 1.0 18.7 8 -7.5 18.7 9 0.8 11 9 -10 11 The MVPG30x/MVPG31 provides an innovative technique to set the output voltage. During startup it reads the value of external resistors, which are located outside the regulator's feedback loop to program the output voltage. By placing the output voltage programming resistor outside the regulator's feedback loop, its tolerance does not affect the accuracy of the output voltage. Normally, adjustable regulators use 1% resistors to set the output voltage. However, these resistors are located inside the feedback loop, introducing as much as 2% of initial accuracy error to the output voltage, resulting in an overall initial accuracy of 3%. Whereas, the MVPG30x/MVPG31 initial accuracy is 2% for any of the eight output voltages. The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The output voltage can potentially be programmed to the lower output voltage if there is contamination, which introduces excessive leakage current on the VSET and PSET pin, especially for the 3.3V output or +10%. The parasitic resistance on these nodes must be greater than 3 M and the stray capacitance must be less than 25 pF; otherwise, a 3.3V output can potentially end up at 3V. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 27 MVPG30x/MVPG31 Datasheet 3.3 Programmable Current Limit for the LDO Regulator Controller A sense resistor is placed between SVIN and ILIM pin to program the current limit of the LDO regulator controller. The following equation is used to determine the value of the sense resistor. 50mV ( Typical ) I LIM = ---------------------------------------R SENSE ( m ) When the LDO regulator controller is in current limit, the internal current-limit circuitry turns off the LDO regulator controller and holds the LDO regulator controller in the off state for 3 ms (typical hold time). After the hold-time is expired, the LDO regulator controller is enabled. The current-limit circuitry continues to disable and enable the regulator until the current limit is removed. The LDO regulator P-channel MOSFET can be selected from the following list based on the required current and ambient temperature. Table 10: P-Channel MOSFET Selection P ac k a g e Vi sh a y F a ir c h i ld Super SOT-6 FDC642P FDC634P Super SOT-3 / micro 3 FDN340P FDN302P SO-8 Si4433DY FDS9431A SC75-6 FLMP FDJ127P TO-263AB (D2-Pack) FDP4020P TSOP-6 Si3443DV SC70-6 FDG330P SOT-23 Si2333DS 1206-8 Chip FET Si5473DC SC-89 (6-lead) Si1039X SC75A/SC-89 (3-lead) Si1012R/X Doc. No. MV-S102808-00 Rev. G Page 28 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Functional Description Under Voltage Lockout 3.3.1 Maximum LDO Output Current The FDS642P is design to provide up to 800 mA of continuous output current. However, the tiny Super SOT-6 package can dissipate up to 0.7W. If the input and output voltage are close, then the full 800 mA is achieved (see Figure 11). As the input voltage increases, the IC dissipates more power, limiting the maximum output current. The output current has to decrease in order to keep the power dissipation under its 0.7W limit. Figure 11: Maximum Output Current for the FDS642P P-Channel MOSFET Load Current (A) Maximum LDO Output Current vs. Input Voltage 1.0 0.8 0.6 0.4 0.2 0.0 3 3.5 4 4.5 5 Input Voltage (V) 3.4 Under Voltage Lockout At startup, the MVPG30x/MVPG31 incorporates Under Voltage Lockout (UVLO) circuitry to enable the step-down switching regulator and the LDO controller when the input voltage is above 2.60V (typical). After the MVPG30x/MVPG31 is enabled and the input voltage is lowered, the highest value of the minimum input voltage for both regulators to remain enabled is 2.50V (typical). 3.5 Over Voltage Protection The MVPG30x/MVPG31 incorporates an Over Voltage Protection (OVP) circuitry to disable the step-down switching regulator and LDO controller when the input voltage is above 5.7V (typical). The step-down switching regulator and LDO controller are enabled when the input voltage is below 5.6V (typical). Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 29 MVPG30x/MVPG31 Datasheet Figure 12: UVLO and OVP Waveforms VOVP_HTH VOVP-LTH VUVLO-HTH VUVLO-LTH VIN BUCK Output Enable Undefined BUCK Output Disable LDO Output Enable Undefined LDO Output Disable 3.6 Thermal Shutdown When the junction temperature of the MVPG30x/MVPG31 exceeds 150C (typical), the thermal shutdown circuitry disables the step-down regulator. The step-down switching regulator is enabled when the junction temperature is decreased to 120C (typical). Doc. No. MV-S102808-00 Rev. G Page 30 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Functional Description Adaptive Transient Response 3.7 Adaptive Transient Response The MVPG30x/MVPG31 device's Smart Technology allows the step-down switching regulator to quickly respond to the multiple step loads and maintain stability over a wide range of applications. Figure 13shows an example of a second step-load applied while the output voltage of the step-down switching regulator increased due to the inductive kick from the first step-load. Condition: VIN = 5.0V, RSVIN = 10, CSVIN = 0.1 F, CPVIN = 10 F, L = 2.0 H, COUT(BUCK) = 22 F, ILOAD = 200 mA to 2.0A. Figure 13: Adaptive Transient Response 100mV/DIV VBUCK 2A/DIV ILOAD 20 s/DIV The overshoot (VSOAR) during a full-load to light-load transient due to stored inductor energy (Figure 13) can be calculated as: 2 V SOAR I LOAD ( MAX ) * L = --------------------------------------------2 * C OUT * V OUT Although the VSOAR cannot be eliminated, its amplitude can be controlled based on the COUT capacitor value. The appropriate COUT value can easily be calculated for the acceptable VSOAR level for each specific application. 2 C OUT I LOAD ( MAX ) * L = --------------------------------------------2 * V SOAR * V OUT Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 31 MVPG30x/MVPG31 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102808-00 Rev. G Page 32 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Functional Characteristics Startup Waveforms 4 Functional Characteristics The following applies unless otherwise noted: TA = 25C, RSVIN = 10, CSVIN = 0.1 F, CPVIN = 10 F, L = 2.0 H, COUT (BUCK) = 10 F, PFET = FDC642P, COUT (LDO) = 10 F. 4.1 Startup Waveforms NOTE: There is a delay (3.5 ms typ.) before the output voltage turns on. Figure 14: Startup Using the Shutdown Pin Figure 15: Turn Off Using the Shutdown Pin VLDO 2V/DIV VLDO 2V/DIV VBUCK VBUCK 500 mV/DIV VSHDN 500 mV/DIV VSHDN 2V/DIV 2V/DIV 1.0 ms/DIV 1.0 ms/DIV VIN = 5.0V ILOAD = No Load VIN = 5.0V VLDO= 3.3V tDLY~ 3.5 ms VLDO= 3.3V VBUCK= 1.2V ILOAD = No Load VBUCK= 1.2V Figure 16: Enable Threshold at VIN = 3.5V Figure 17: Enable Threshold at VIN = 5.0V 2V/DIV 2V/DIV VLDO VLDO 1V/DIV VBUCK VSHDN 1V/DIV VBUCK VSHDN 1V/DIV 1V/DIV 100 ms/DIV 100 ms/DIV VIN = 5.0V ILOAD = 10 mA VIN = 5.0V ILOAD = 10 mA VLDO= 3.3V VTH = 0.96V (Note) VLDO= 3.3V VTH = 1.12V (Note) VBUCK= 1.2V VBUCK= 1.2V Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 33 MVPG30x/MVPG31 Datasheet Figure 18: Input Voltage Soft Start VIN Figure 19: Input Voltage Hot Plug 5V/DIV VLDO VIN 5V/DIV VLDO 2V/DIV 1V/DIV VBUCK 2V/DIV 1V/DIV VBUCK 2.0 ms/DIV 1.0 ms/DIV VIN = 5.0V VBUCK= 1.2V VIN = 5.0V VBUCK= 1.2V VLDO= 3.3V ILOAD = No Load VLDO= 3.3V ILOAD = No Load Figure 20: Step-Down Output Rise Time VOUT Figure 21: Soft Start Current Limit Steps 500 mV/DIV IIND 1A/DIV 1A/DIV IIND 5.0 s/DIV VIN = 5.0V VBUCK= 1.2V ILOAD = 500 mA 50 s/DIV VIN = 5.0V VBUCK= 3.3V Doc. No. MV-S102808-00 Rev. G Page 34 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Functional Characteristics Startup Waveforms Figure 22: UVLO and OVP Thresholds 2V/DIV VIN VLDO 2V/DIV VBUCK 2V/DIV 100 ms/DIV VIN = 0 to 6.0V VUVLO(HTH) = 2.60V VLDO = 3.3V VUVLO(LTH) = 2.50V VBUCK = 1.5V VOVP(HTH) = 5.8V ILOAD(BUCK) = 50 VOVP(LTH) = 5.7V Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 35 MVPG30x/MVPG31 Datasheet 4.2 Switching Waveforms NOTE: For repeatability of measuring output ripple (VBUCK (P-P)) for the BUCK regulator, the standard test procedure limits the scope bandwidth to 20 MHz and uses a coax cable with very short leads terminated into 50. The coax leads must be routed away from the switching node as much as possible. Figure 23: Switching Waveforms-- PWM Mode Figure 24: Switching Waveforms-- DCM Mode VSW 5V/DIV 5V/DIV VSW IIND 500 mA/DIV VBUCK VBUCK 20 mV/DIV 5 mV/DIV IIND VIN 100 mV/DIV 500 mA/DIV 500 ns/DIV 5.0 s/DIV VIN = 5.0V VIN(P-P) = 200.2 mV VIN = 5.0V IIND(PK) = 670.4 mA VBUCK= 1.2V IOUT = 2.0A IIND(P-P) = 601.5 mA VBUCK= 1.2V Freq = 185 kHz IIND(PK) = 2.3A IOUT = 50 mA VOUT(P-P) = 6.3 mV (Note) Freq = 1 MHz VOUT(P-P) = 31.4 mV (Note) Figure 25: PWM Output Ripple Voltage Figure 26: Switching Waveforms-- DCM Mode-Zoom VSW VBUCK 5V/DIV 20 mV/DIV 20 mV/DIV VBUCK 500 mA/DIV IIND 100 ms/DIV 500 ns/DIV VIN = 5.0V IOUT = 2.0A VIN = 5.0V IOUT = 50 mA VBUCK= 1.2V VOUT(P-P) = 15.7 mV (Note) VBUCK= 1.2V Ringing Freq = 10 MHz Doc. No. MV-S102808-00 Rev. G Page 36 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Functional Characteristics Load Transient Waveforms 4.3 Load Transient Waveforms 4.3.1 Step-Down Regulator Figure 27: Load Transient Response Figure 28: Double-Pulsed Load Response VBUCK 100 mV/DIV 2A/DIV ILOAD VBUCK 100 mV/DIV 2A/DIV ILOAD 20 s/DIV 20 s/DIV VIN = 5.0V ILOAD = 200 mA to 2.0A VBUCK= 1.2V COUT = 22 F VIN = 5.0V ILOAD = 200 mA to 2.0A tRISE = 6.0A/s VBUCK= 1.2V tRISE = 6.0A/s tFALL = 129A/s COUT = 22 F tFALL = 129A/s Figure 29: Load Transient Response Figure 30: Double-Pulsed Load Response VBUCK 100 mV/DIV VBUCK 100 mV/DIV 2A/DIV ILOAD 2A/DIV ILOAD 20 s/DIV 20 s/DIV VIN = 5.0V IOUT = 200 mA to 2.0A VIN = 5.0V IOUT = 200 mA to 2.0A VBUCK= 1.2V tRISE = 6.0A/s VBUCK= 1.2V tRISE = 6.0A/s COUT = 2x22 F tFALL = 129A/s COUT = 2x22 F tFALL = 129A/s Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 37 MVPG30x/MVPG31 Datasheet Figure 31: Load Transient Response Figure 32: Double-Pulsed Load Response VBUCK 100 mV/DIV VBUCK 100 mV/DIV 2A/DIV ILOAD 2A/DIV ILOAD 20 s/DIV 20 s/DIV VIN = 5.0V ILOAD = 200 mA to 2.0A VIN = 5.0V ILOAD = 200 mA to 2.0A VBUCK= 1.2V tRISE = 6.0A/s VBUCK= 1.2V tRISE = 6.0A/s COUT = 4x22 F tFALL = 129A/s COUT = 4x22 F tFALL = 129A/s 4.3.2 LDO Regulator Figure 33: Load Transient Response VLDO 50 mV/DIV ILOAD 1A/DIV 20 s/DIV VIN = 5.0V COUT = 10 F VLDO= 3.3V ILOAD = 0.2A to 0.8 mA Doc. No. MV-S102808-00 Rev. G Page 38 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Typical Characteristics Efficiency Graphs 5 Typical Characteristics 5.1 Efficiency Graphs Figure 34: Efficiency Graphs Efficiency vs. Output Current Vin = 5.0V Efficiency vs. Output Current Vin = 3.3V 90 90 80 Efficiency (%) 100 Efficiency (%) 100 3.3V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 70 60 3.3V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 80 70 60 50 50 0 0.5 1 Output Current (A) 1.5 0 2 2 3.3V 90 90 3.3V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 80 70 60 0.1 1 Output Current (A) Efficiency (%) Efficiency (%) 1.5 100 100 2.5V 1.8V 80 1.5V 1.2V 70 1.0V 60 10 50 0.01 Copyright (c) 2008 Marvell April 14, 2008, 2.00 1 Output Current (A) Efficiency vs. Output Current Vin = 3.3V Efficiency vs. Output Current Vin = 5.0V 50 0.01 0.5 0.8V 0.1 1 Output Current (A) 10 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 39 MVPG30x/MVPG31 Datasheet 5.2 Load Regulation Figure 35: Load Regulation Step-Down Regulator Output Voltage vs. Output Current Vout = 1.5V Output Voltage (V) 1.60 1.55 1.50 1.45 3.3V 5.0V 1.40 0 5.3 0.5 1 Output Current (A) 1.5 2 Dropout Voltage Figure 36: Dropout Voltage LDO Regulator Dropout vs. Load Current Vin = 3.3V, Vout = 3.3V Step-Down Regulator Dropout vs. Load Current Vin = 3.2V, Vout = 3.3V 0.20 TA=85C TA=25C TA=-40C 0.2 TA=85C TA=25C TA=-40C 0.15 Dropout (V) Dropout (V) 0.3 0.1 0.10 0.05 0.00 0.0 0 0.2 0.4 0.6 Output Current (A) 0.8 1 0 0.2 Doc. No. MV-S102808-00 Rev. G Page 40 0.4 Output Current (A) 0.6 0.8 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Typical Characteristics RDS (ON) Resistance 5.4 RDS (ON) Resistance Figure 37: RDS (ON) Resistance Bottom FET Rds_On vs. Temperature 0.20 0.12 0.15 0.10 Rds_On () Rds_On () Top FET Rds_On vs. Temperature 0.10 3V 4V 5V 0.05 0.08 3V 4V 5V 0.06 0.00 0.04 -40 -20 0 20 40 60 -40 80 -20 0 Temperature (C) Top FET Rds_On vs. Input Voltage 40 60 0.20 0.12 0.15 0.10 0.10 0.05 0.08 0.06 TA = 25C TA = 25C 0.00 0.04 3.0 3.5 4.0 4.5 5.0 3.0 Input Voltage (V) 3.5 4.0 4.5 5.0 Input Voltage(V) Copyright (c) 2008 Marvell April 14, 2008, 2.00 80 Bottom FET Rds_On vs. Input Voltage Rds_On () Rds_On () 20 Temperature (C) Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 41 MVPG30x/MVPG31 Datasheet 5.5 IC Case and Inductor Temperature The following data was taken using a 0.625 square inch and L = 2.0 H. Actual results depend upon the size of the PCB proximity to other heat emitting components. Figure 38: IC Case and Inductor Temperature Input Current vs. Output Current VIN = 3.3V, TA = 25C Input Current vs. Output Current VIN = 5V, TA = 25C 2.0 2.0 Input Current (A) 1.5 1.0 Input Current (A) 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 0.5 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 1.5 1.0 0.5 0.0 0.0 0.0 0.5 1.0 Output Current (A) 1.5 0.0 2.0 0.5 IC Case Temperature vs. Output Current VIN = 5V, TA = 25C 70 55 40 IC Temperature (C) IC Temperature (C) 2.0 85 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 70 55 40 25 25 0 0.5 1 Output Current (A) 1.5 0.0 2 L Temperature (C) 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 40 1.0 Output Current (A) 1.5 2.0 60 60 50 0.5 Inductor Temperature vs. Output Current VIN = 3.3V, TA = 25C Inductor Temperature vs. Output Current VIN = 5V, TA = 25C L Temperature (C) 1.5 IC Case Temperature vs. Output Current VIN = 3.3V, TA = 25C 85 30 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 50 40 30 20 20 0.0 0.5 1.0 Output Current (A) 1.5 2.0 0.0 Doc. No. MV-S102808-00 Rev. G Page 42 1.0 Output Current (A) 0.5 1.0 Output Current (A) 1.5 2.0 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Typical Characteristics Input Voltage Graph 5.6 Input Voltage Graph Figure 39: Supply Current vs. Input Voltage Supply Current vs. Input Voltage Supply Current (mA) 4.0 3.0 2.0 1.0 0.0 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 Load = No Load 5.6.1 Step-Down Regulator Figure 40: Output Voltage vs. Input Voltage Figure 41: Efficiency vs. Input Voltage Efficiency vs. Input Voltage 100% 1.55 95% Efficiency (%) Output Voltage (V) Output Voltage vs. Input Voltage 1.60 1.50 1.45 90% 85% 1.40 80% 3.0 3.5 IOUT(BUCK) = 500 mA 4.0 4.5 Input Voltage (V) 5.0 5.5 3.0 3.5 VIN = 5.0V 4.0 4.5 Input Voltage (V) 5.0 5.5 IOUT(BUCK) = 1.0A VOUT(BUCK) = 1.5V Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 43 MVPG30x/MVPG31 Datasheet Figure 42: Load Regulation vs. Input Voltage Figure 43: Frequency vs. Input Voltage Frequency vs. Input Voltage 2000 0.50% 1500 Frequency (kHz) Load Regulation (%) Load Regulation vs. Input Voltage 0.70% 0.30% 0.10% -0.10% 1000 500 0 3.0 3.5 4.0 4.5 Input Voltage (V) VIN = 5.0V 5.0 5.5 IOUT(BUCK) = 500 mA to 2.0A 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 IOUT(BUCK) = 1.0A VOUT(BUCK) = 1.5V Figure 44: Average Output Current Limit vs. Input Voltage Average Output Current Limit vs. Input Voltage Current Limit (A) 4.0 3.0 2.0 1.0 0.0 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 Doc. No. MV-S102808-00 Rev. G Page 44 5.5 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Typical Characteristics Input Voltage Graph 5.6.2 LDO Regulator Figure 45: Output Voltage vs. Input Voltage Figure 46: LDO Load Regulation vs. Input Voltage Output Voltage vs. Input Voltage LDO Load Regulation vs. Input Voltage 3.60 3.40 Load Regulation (%) Output Voltage (V) 0.40% 3.20 3.00 0.30% 0.20% 0.10% 2.80 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 0.00% 4.0 IOUT(LDO) = 10 mA 4.5 VOUT(LDO) = 3.3V 5.0 Input Voltage (V) 5.5 IOUT(LDO) = 10 mA to 800 mA Figure 47: Average Output Current Limit vs. Input Voltage Average Output Current Limit vs. Input Voltage Current Limit (A) 2.0 1.5 1.0 0.5 0.0 3.5 4.0 4.5 Input Voltage (V) 5.0 Copyright (c) 2008 Marvell April 14, 2008, 2.00 5.5 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 45 MVPG30x/MVPG31 Datasheet 5.7 Temperature Graphs Figure 48: Supply Current vs. Temperature Figure 49: UVLO vs. Temperature UVLO vs. Temperature 3.0 3.0 2.9 UVLO (V) Supply Current (mA) Supply Current vs. Temperature 4.0 2.0 2.8 2.7 1.0 2.6 0.0 -40 -20 0 20 40 Temperature (C) IOUT(BUCK) = No Load 5.7.1 60 -40 80 IOUT(LDO) = No Load -20 0 40 60 80 IOUT(BUCK) = 10 mA Step-Down Regulator Figure 50: Output Voltage vs. Temperature Figure 51: Efficiency vs. Temperature Output Voltage vs. Temperature Efficiency vs. Temperature 1.60 100% 1.55 95% Efficiency (%) Output Voltage (V) 20 Temperature (C) 1.50 90% 85% 1.45 80% 1.40 -40 -20 0 20 40 Temperature (C) VIN = 5.0V 60 80 IOUT(BUCK) = 500 mA -40 -20 VIN = 5.0V 0 20 40 Temperature (C) 60 80 IOUT(BUCK) = 1.0A VOUT(BUCK) = 1.5V Doc. No. MV-S102808-00 Rev. G Page 46 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Typical Characteristics Temperature Graphs Figure 52: Load Regulation vs. Temperature Figure 53: Line Regulation vs. Temperature Line Regulation vs. Temperature See Test Conditions Load Regulation vs. Temperature See Test Conditions 0.20% 0.60% 0.50% 0.10% 0.40% 0.30% 0.00% 0.20% -0.10% 0.10% 0.00% -40 -20 0 20 40 60 -0.20% -40 80 -20 0 Temperature (C) VIN = 5.0V 20 40 60 80 Temperature (C) IOUT(BUCK) = 500 mA to 2.0A VIN = 3.0V to 5.0V VOUT(BUCK) = 1.5V IOUT(BUCK) = 500 mA VOUT(BUCK) = 1.5V Figure 54: Average Output Current Limit vs. Temperature Figure 55: Frequency vs. Temperature Frequency vs. Temperature Average Output Current Limit vs. Temperature 2000 5.0 Frequency (kHz) Current Limit (A) 1500 4.0 1000 3.0 500 2.0 0 -40 1.0 -40 -20 0 VIN = 5.0V 20 40 Temperature (C) 60 -20 0 20 40 Temperature (C) 60 80 80 VIN = 5.0V IOUT(BUCK) = 1.0A VOUT(BUCK) = 1.5V Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 47 MVPG30x/MVPG31 Datasheet 5.7.2 LDO Regulator Figure 56: Output Voltage vs. Temperature Figure 57: Load Regulation vs. Temperature Load Regulation vs. Temperature Output Voltage vs. Temperature 0.20% Load Regulation (%) Output Voltage (V) 3.40 3.35 3.30 3.25 3.20 0.15% 0.10% 0.05% 0.00% -40 -20 0 20 40 Temperature (C) VIN = 5.0V 60 80 -40 IOUT(LDO) = 10 mA -20 0 VIN = 5.0V 20 40 Temperature (C) 60 80 IOUT(LDO) = 10 mA to 800 mA VOUT(LDO) = 3.3V Figure 58: Line Regulation vs. Temperature Figure 59: Average Output Current Limit vs. Temperature Line Regulation vs. Temperature See Test Conditions Average Ouput Current Limit vs. Temperature 2.0 0.20% Current Limit (A) 0.10% 0.00% -0.10% -0.20% -40 -20 0 20 40 60 1.5 1.0 0.5 80 Temperature (C) 0.0 -40 VIN = 3.5V to 5.0V IOUT(LDO) = 10 mA -20 0 20 40 Temperature (C) 60 80 VIN = 5.0V VOUT(LDO) = 3.3V Doc. No. MV-S102808-00 Rev. G Page 48 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines 6 Applications Information 6.1 PC Board Layout Considerations and Guidelines To avoid noise and abnormal operating behavior, follow these layout recommendations. Warning 1. 2. This is a 2-layer board with one ground plane and one routing layer. Copy the routing layer in Figure 64 or Figure 65 as much as possible and place it on the top layer. The ground plane in Figure 66 or Figure 67 can be placed on any other layer. Use the recommend BOM in Table 11 or Table 12. Contact the factory where substitutions are made. 3. Review the recommended solder pad layout and notes in Section 7.3, Typical Pad Layout Dimensions, on page 59. 4. Do not replace the Ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic input capacitor in placed next to the IC. If Tantalum input capacitor is used, it must be rated for switching regulator applications and the operating voltage be derated by 50%. 5. Use either X7R or X5R type ceramic capacitors. If Y5V or Z5U type capacitor are used, then you must double the recommended capacitance value. 6. Any type of capacitor can be placed in parallel with the output capacitor. 7. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide the lowest noise and smallest foot print solution. 8. Use planes for the ground, input and outputs power to maintain good voltage filtering and to keep power losses low. 9. If there is not enough space for a power plane for the input supply, then the input supply trace must be at least 3/8 inch wide. 10. If there is not enough space for a power plane for the output supplies, then place the output as close to the load as possible with a trace of at least 3/8 inch wide. 11. Do not lay out the inductor first. The input capacitor placement is the most critical for proper operation. The AC current circulating through the input capacitor and loop 1 (LP1) are square wave with rise and fall times of 8 ns and slew rates as high as 300 A/s (see Figure 60). At these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3.0V per inch of PCB trace, VIND = L * di/dt. Therefore, the Ceramic input capacitor must be place as close as possible to the PVIN and PGND pins with as short and wide trace as possible. Also, the PVIN and PGND traces must be placed on the top layer. This will isolate the fast AC currents from interfering with the analog ground plane. 12. The MVPG30x/MVPG31 has two internal grounds, analog (SGND) and power (PGND). The analog ground ties to all the noise sensitive signals (PSET, VSET, and SVIN) while the power ground ties to the higher current power paths. Noise on an analog ground can cause problems with the IC's internal control and bias signals. For this reason, separate analog and power ground traces are recommended. The signal ground is connected to the power ground at one point, which is the (-) terminal of the output capacitor. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 49 MVPG30x/MVPG31 Datasheet 13. Keep loop 2 (LP2) as small as possible and connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as shown in Figure 60 or Figure 61, is recommended for best results. 14. Keep the switching node (SW) away from the SFB pin and all sensitive signal nodes, minimizing capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle. 15. Try not to route analog or digital lines in close proximity to the power supply especially the VSW node. If this can't be avoided, shield these lines with a power plane placed between the VSW node and the signal lines. 16. The type of solder paste recommended for QFN packages is "No clean", due to the difficulty of cleaning flux residues from beneath the QFN package. Figure 60: MVPG30x PCB Layout Schematic VIN R1 47mohm MVPG30 1 LFB 2 ILIM 3 LDR 4 5 6 1 6 SW U1 L1 2.0uH U2 NC SFB PGND 2 SHDN SGND 3 5 VSET MVPG30 SVIN PVIN R2 12 R4 11 10 9 C4 0.1uF 8 7 R3 10ohm EP FDC642P 4 PSET LP1 C2 10uF/6.3V C1 22uF/6.3V 10uF/6.3V VIN BUCK_OUT LDO_O UT C3 Figure 61: MVPG31 PCB Layout Schematic U1 2 3 4 5 6 PSET NC VSET NC MVPG31 SHDN SGND NC SFB SW SVIN PVIN LP1 C2 11 R3 10 9 C3 0.1uF 8 7 R1 10 ohm 22uF/6.3V C1 10uF/6.3V Doc. No. MV-S102808-00 Rev. G Page 50 R2 VIN B UCK __OUT 12 EP L1 2.0uH MVPG31 NC P GND 1 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines 6.1.1 PC Board Layout Examples for MVPG30x/MVPG31 For the MVPG30x: Actual board size = 565 mil x 945 mil; Area = 0.534 Sq. Inches. Total copper layers = 2 (Top and Bottom) All the components are on the top layer For the MVPG31: Actual board size = 420 mil x 725 mil; Area = 0.305 Sq. Inches. Total copper layers = 2 (Top and Bottom) All the components are on the top layer Figure 62: Top Silk-Screen (Not to scale)--MVPG30x Figure 63: Top Silk-Screen (Not to scale)--MVPG31 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 51 MVPG30x/MVPG31 Datasheet Figure 64: Top Traces, Vias, and Copper (Not to scale)--MVPG30x Connect the input voltage plane to this point. Connect the LDO regulator output voltage at this point. Connect the ground plane of the board to this point. Connect the Buck regulator output voltage at this point. Connect the ground plane of the board to this point. Figure 65: Top Traces, Vias, and Copper (Not to scale)--MVPG31 Do not connect this signal ground to the board ground on the top layer. Do not connect this signal ground to the board ground on the top layer. Connect BUCK_OUT trace at this point. Connect the ground plane of the board to this point. Connect VIN trace at this point. Doc. No. MV-S102808-00 Rev. G Page 52 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines Figure 66: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale)--MVPG30x Connect to the ground plane of the board. Connect to the ground plane of the board. Connect to the ground plane of the board. Connect to the ground plane of the board. Figure 67: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to scale)--MVPG31 Connect to the ground plane of the board. Connect to the ground plane of the board. Connect to the ground plane of the board. Connect to the ground plane of the board. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 53 MVPG30x/MVPG31 Datasheet 6.2 Bill of Materials The following tables list the components used with the MVPG30x/MVPG31. Table 11: MVPG30x BOM It e m Qty Ref Manufacturer Part No. Manufacturer D e s c r ip t i o n 1 1 U1 MVPG30B Marvell Semiconductor 1 MHz, 3.0A Peak Current-Limit Step-Down Regulator with LDO regulator controller 2 1 U2 FDC642P Fairchild P-FET, 2.5V, SuperSOT-6 package 3 1 C1 CE JMK212 BJ106MG-T Taiyo-Yuden 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic C2012X5R0J106MT TDK 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic CE JMK212 BJ226MG-T Taiyo-Yuden 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic C2012X5R0J226MT TDK 22 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic CE JMK212 BJ106MG-T Taiyo-Yuden 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic C2012X5R0J106MT TDK 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic RM LMK105 BJ104KV-F Taiyo-Yuden 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic C1005X5R1A104K TDK 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic 4 5 1 C2 6 7 1 C3 8 9 1 C4 10 11 1 L1 A918CY-2R0M=P3 Toko 2.0 H, 2.47A (typ.), 24 m (typ.), H = 2mm, L = 6.2 mm, W = 6.3 mm 12 1 R1 RL1220T-R047-J Susumu Co. Ltd. 0.047, 1/4W, 5%, 0805 Case Size 13 1 R2 14 1 R3 15 1 R4 See Section 3.2, Output Voltage--AnyVoltageTM Technology, on page 26. ERJ-2RKF10R0X Panasonic-ECG See Section 3.2, Output Voltage--AnyVoltageTM Technology, on page 26. Doc. No. MV-S102808-00 Rev. G Page 54 10, 1/16W, 1%, 0402 Case Size Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Applications Information Bill of Materials Table 12: MVPG31 BOM It e m Qty Ref Manufacturer Part No. Manufacturer D e s c r ip t i o n 1 1 U1 MVPG31 Marvell Semiconductor 1 MHz, 3.0A Peak Current-Limit Step-Down Regulator 2 1 C1 CE JMK212 BJ106MG-T Taiyo-Yuden 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic C2012X5R0J106MT TDK 10 F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic CE JMK212BJ226MG-T Taiyo-Yuden 22 F 20%, X5R, 6.3V, 0805 Case Size, Ceramic C2012X5R0J226MT TDK 22 F 20%, X5R, 6.3V, 0805 Case Size, Ceramic RM LMK105 BJ104KV-F Taiyo-Yuden 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic C1005X5R1A104K TDK 0.1 F, 10%, X5R, 10V, 0402 Case Size, Ceramic 3 4 1 C2 5 6 1 C4 7 8 1 L1 A918CY-2R0M=P3 Toko 2.0 H, 2.47A (typ.), 24 m (typ.), H = 2mm, L = 6.2 mm, W = 6.3 mm 9 1 R1 ERJ-2RKF10R0X Panasonic-ECG 10, 1/16W, 1%, 0402 Case Size 10 1 R2 See Section 3.2, Output Voltage--AnyVoltageTM Technology, on page 26 11 1 R3 See Section 3.2, Output Voltage--AnyVoltageTM Technology, on page 26 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 55 MVPG30x/MVPG31 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102808-00 Rev. G Page 56 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Mechanical Drawing Mechanical Drawing 7 Mechanical Drawing 7.1 Mechanical Drawing Figure 68: Mechanical Drawing Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 57 MVPG30x/MVPG31 Datasheet 7.2 Dimensions Table 13: Dimensions Sy m b o l D i m e n s io ns i n m m D i m e n s io n s i n in c h MIN NOM MAX MIN NOM MAX A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0.00 0.02 0.05 0.000 0.001 0.002 A2 0.20 REF 0.008 REF b1 0.18 0.23 0.28 0.007 0.009 0.011 b2 0.51 0.56 0.61 0.020 0.022 0.024 D 2.90 3.00 3.10 0.114 0.118 0.122 D1 1.60 1.70 1.80 0.063 0.067 0.071 E 3.90 4.00 4.10 0.153 0.157 0.161 E1 3.40 3.50 3.60 0.134 0.138 0.142 e 0.50 BSC 0.020 BSC L 0.30 0.40 0.50 0.012 0.016 0.020 aaa -- -- 0.15 -- -- 0.006 bbb -- -- 0.10 -- -- 0.004 ccc -- -- 0.10 -- -- 0.004 Doc. No. MV-S102808-00 Rev. G Page 58 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Mechanical Drawing Typical Pad Layout Dimensions 7.3 Typical Pad Layout Dimensions 7.3.1 Recommended Solder Pad Layout Figure 69: Recommended Solder Pad Layout Package Outline 0.55 0.23 0.50 0.67 0.075 4.00 0.83 3.50 0.56 1.75 1.60 2.20 3.30 4x3 DFN-12 Land Pattern (mm) 0.50 mm 0.23 mm 0.27 mm Pad SM Pad SM 0.051 mm Pad 0.168 mm DFN Lead with Non-Solder Mask Defined Terminal Note Top view Drawing not to scale Dimensions are in millimeters Exposed pad shall be copper plated Oversize solder mask by 0.102 mm (4 mils) over pad size (0.051 mm annular ring) 0.168 mm solder mask (sm) between pads Tolerance 0.05 mm Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 59 MVPG30x/MVPG31 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102808-00 Rev. G Page 60 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Part Order Numbering/Package Marking Part Order Numbering 8 Part Order Numbering/Package Marking 8.1 Part Order Numbering Figure 70 shows the part order numbering scheme for the MVPG30x/MVPG31. Refer to Marvell Field Applications Engineers (FAEs) or representatives for further information when ordering parts. Figure 70: Sample Part Order Number MVPG3x x-xx-xxx1C000-xxxx Part Numbers MVPG30 MVPG31 Custom Code (optional) Custom Code LDO Output Voltage Options B = 3.3V E = 2.5V Temperature Code C = Commercial I = Industrial Custom Code Environmental Code + = RoHS 0/6 - = RoHS 5/6 1 = RoHS 6/6 Package Code NAE = 12-pin DFN Table 14: Part Order Options P a c k a g e Ty p e M a r k in g LDO Ambient Te m p e r a t u r e Range Part Order Number 4 mm x 3 mm 12-pin DFN B0 3.3V -40C to 85C MVPG30B-xx-NAE1C000 4 mm x 3 mm 12-pin DFN E0 2.5V -40C to 85C MVPG30E-xx-NAE1C000 4 mm x 3 mm 12-pin DFN 00 -- -40C to 85C MVPG31-xx-NAE1C000 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 61 MVPG30x/MVPG31 Datasheet 8.2 Package Marking This section show the sample package markings and pin 1 location. Figure 71: MVPG30x Package Marking Marvell logo G30 B0A3R YWWAA Pin 1 Part number, LDO options, custom code, assembly house code G30 = Part number B0 = LDO output voltage options (B or E) A3 = Custom code R = Assembly house code Date code, traceability lot code YWW = Date code (Y = year, WW = Work Week) AA = Traceability lot code Note: The above drawing is not drawn to scale. Location of markings is approximate. Doc. No. MV-S102808-00 Rev. G Page 62 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 Part Order Numbering/Package Marking Package Marking Figure 72: MVPG31 Package Marking Marvell logo G31 00A3R YWWAA Pin 1 Part number, LDO option, custom code, assembly house code G31 = Part number 00 = No LDO output voltage option A3 = Custom code R = Assembly house code Date code, traceability lot code YWW = Date code (Y = year, WW = Work Week) AA = Traceability lot code Note: The above drawing is not drawn to scale. Location of markings is approximate. Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 63 MVPG30x/MVPG31 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102808-00 Rev. G Page 64 Copyright (c) 2008 Marvell Document Classification: Proprietary April 14, 2008, 2.00 A Revision History Table 15: Revision History D o c um en t Ty p e D o c u m e n t R e v i s io n Release Rev.G Electrical Specifications Updated VUVLO values in Table 5, Electrical Characteristics, on page 19 Copyright (c) 2008 Marvell April 14, 2008, 2.00 Doc. No. MV-S102808-00 Rev. G Document Classification: Proprietary Page 65 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster