3.3 V, 3.2 Gbps,
Limiting Amplifier
ADN2891
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
FEATURES GENERAL DESCRIPTION
Input sensitivity: 4 mV p-p The ADN2891 is a 3.2 Gbps limiting amplifier with integrated
loss-of-signal (LOS) detection circuitry and a received signal
strength indicator (RSSI). This part is optimized for SONET,
Gigabit Ethernet (GbE), and Fibre Channel optoelectronic
conversion applications. The ADN2891 has a differential input
sensitivity of 4 mV p-p and accepts up to a 2.0 V p-p differential
input overload voltage. The ADN2891 supports current mode
logic (CML) outputs with controlled rise and fall times.
80 ps rise/fall times
CML outputs: 700 mV p-p differential
Programmable LOS detector: 3.5 mV to 35 mV
Rx signal strength indicator (RSSI)
SFF-8472-compliant average power measurement
Single-supply operation: 3.3 V
Low power dissipation: 145 mW
Available in space-saving 3 mm × 3 mm, 16-lead LFCSP
By monitoring the bias current through a photodiode, the on-
chip RSSI detector measures the average power received with
2% typical linearity over the entire valid input range of the
photodiode. The on-chip RSSI detector facilitates SFF-8472-
compliant optical transceivers by eliminating the need for
external RSSI detector circuitry.
Extended temperature range: −40°C to +95°C
SFP reference design available
APPLICATIONS
SFP/SFF/GBIC optical transceivers
OC-3/OC-12/OC-48, GbE, Fibre Channel (FC) receivers
Additional features include a programmable loss-of-signal
(LOS) detector and output squelch.
10GBASE-LX4 transceivers
WDM transponders
The ADN2891 is available in a 3 mm × 3 mm, 16-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
05244-001
ADN2880
V
REF
DRVCC
50Ω50Ω
50Ω50Ω
3kΩ
PIN
NIN
PD_VCC
PD_CATHODE
ADN2891
RSSI/LOS
DETECTOR
0.01
μ
F
CAZ1 CAZ2 SQUELCH
AVCC AVEE DRVCC DRVEE
THRADJ
OUTP
LOS 10k
Ω
+V
ADuC7020
RSSI_OUT
OUTN
Figure 1.
ADN2891
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Limiting Amplifier ..................................................................... 10
Loss of Signal (LOS) Detector .................................................. 10
Received Signal Strength Indicator (RSSI) ............................. 10
Squelch Mode ............................................................................. 10
Applications..................................................................................... 11
PCB Design Guidelines ............................................................. 11
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
7/05—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to Ordering Guide .......................................................... 13
3/05—Revision 0: Initial Version
ADN2891
Rev. A | Page 3 of 16
SPECIFICATIONS
Test Conditions: VCC = 2.9 V to 3.6 V, VEE = 0 V, TA = −40°C to +95°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
QUANTIZER DC CHARACTERISTICS
Input Voltage Range 1.8 2.8 V p-p At PIN or NIN, dc-coupled
Input Common Mode 2.1 2.7 V DC-coupled
Differential Input Range 2.0 V p-p AC-coupled
Differential Input Sensitivity 5.2 3.5 mV p-p 3.2 Gbps, PRBS 223 − 1, BER ≤ 10−10
Input Offset Voltage 100 μV
Input RMS Noise 235 μV rms
Input Resistance 50 Ω Single-ended
Input Capacitance 0.65 pF
QUANTIZER AC CHARACTERISTICS
Input Data Rate 155 3200 Mb/s
Small Signal Gain 50 dB Differential
S11 −10 dB Differential, f < 3.2 GHz
S22 −10 dB Differential, f < 3.2 GHz
Random Jitter 4.0 6.4 ps rms Input ≥ 10 mV p-p, OC-48, PRBS 223 − 1
Deterministic Jitter 9.0 34 ps p-p Input ≥ 10 mV p-p, OC-48, PRBS 223 − 1
Low Frequency Cutoff 30 kHz CAZ = Open
1.0 kHz CAZ = 0.0 1 μF
Power Supply Rejection Ratio 45 dB f < 10 MHz
LOSS OF SIGNAL DETECTOR (LOS)
LOS Assert Level 1.9 3.5 5.6 mV p-p RTHRADJ = 100 kΩ
19 35 53 mV p-p RTHRADJ = 1 kΩ
Electrical Hysteresis 2.4 5.0 dB OC-3, PRBS 223 − 1
2.75 5.0 dB OC-48, PRBS 223 − 1
LOS Assert Time 950 ns DC-coupled
LOS De-Assert Time 62 ns DC-coupled
RSSI
Input Current Range 5 1000 μA
RSSI Output Linearity 2 % 5 μA < IIN ≤ 1000 μA
Gain 1.0 mA/mA IRSSI/IPD
Offset 145 nA
Difference between measured RSSI output
and PD_CATHODE (input) current of 5 μA
Compliance Voltage VCC − 0.9 VCC − 0.4 V Measured at PD_CATHODE, with I = 5 μA
or I = 1 mA
POWER SUPPLIES
VCC 2.9 3.3 3.6 V
ICC 45 49 mA
OPERATING TEMPERATURE RANGE −40 +25 +95 °C TMIN to TMAX
CML OUTPUT CHARACTERISTICS
Output Impedance 50 Ω Single-ended
Output Voltage Swing 600 660 850 mV p-p Differential
Output Rise and Fall Time 80 130 ps 20% to 80%
ADN2891
Rev. A | Page 4 of 16
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS (SQUELCH)
VIH, Input High Voltage 2.0 V
VIL, Input Low Voltage 0.8 V
Input Current 40 μA IINH, VIN = 2.4 V, 100 kΩ pull-down resistor on-chip
6 μA IINL, VIN = 0.4 V, 100 kΩ pull-down resistor on-chip
LOGIC OUTPUTS (LOS)
VOH, Output High Voltage 2.4 V Open drain output, 4.7 kΩ to 10 kΩ
pull-up resistor to VCC
VOL, Output Low Voltage 0.4 V Open drain output, 4.7 kΩ to 10 kΩ
pull-up resistor to VCC
ADN2891
Rev. A | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Power Supply Voltage 4.2 V
VEE − 0.4 V
Minimum Voltage
(All Inputs and Outputs)
VCC + 0.4 V
Maximum Voltage
(All Inputs and Outputs)
Storage Temperature −65°C to +150°C
Operating Temperature Range −40°C to +95°C THERMAL RESISTANCE
Production Soldering Temperature J-STD-20 θJA is specified for 4-layer PCB with exposed paddle soldered
to GND.
Junction Temperature 125°C
Table 3.
Package Type θ Unit
JA
3 mm × 3 mm, 16-lead LFCSP 28 °C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADN2891
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05244-002
AVCC
1
THRADJ
5
CAZ1
6
CAZ2
7
LOS
8
PD_CATHOD
E
16
PD_VCC
15
RSSI_OUT
14
SQUELCH
13
PIN
2
TOP VIEW
(Not to Scale)
NIN
3
AVEE
4
DRVCC
12
OUTN
10
DRVEE
9
OUTP
11
ADN2891
Figure 2. Pin Configuration
Note that the LFCSP has an exposed pad on the bottom. To improve heat dissipation, the exposed pad must be soldered to the GND plane
with filled vias.
Table 4. Pin Function Descriptions
Pin No. Mnemonic I/O Type Descriptions
1
1 AVCC P Analog Power Supply.
2 PIN AI Differential Data Input, Positive Port, 50 Ω On-Chip Termination.
3 NIN AI Differential Data Input, Negative Port, 50 Ω On-Chip Termination.
4 AVEE P Analog Ground.
5 THRADJ AO LOS Threshold Adjust Resistor.
6 CAZ1 AI If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for
input offset correction.
7 CAZ2 AI If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for
input offset correction.
8 LOS DO LOS Detector Output, Open Collector.
9 DRVEE P Output Buffer Ground.
10 OUTN DO Differential Data Output, CML, Negative Port, 50 Ω On-Chip Termination.
11 OUTP DO Differential Data Output, CML, Positive Port, 50 Ω On-Chip Termination.
12 DRVCC P Output Buffer Power Supply.
13 SQUELCH DI Disable Outputs, 100 kΩ On-Chip Pull-Down Resistor.
14 RSSI_OUT AO Average Current Output.
15 PD_VCC P Power Input for RSSI Measurement.
16 PD_CATHODE AO Photodiode Bias Voltage.
Pad P Connect to Ground.
Exposed
Pad
1 P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.
ADN2891
Rev. A | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
05244-015
50ps/DIV
100mV/DIV
05244-020
50ps/DIV
100mV/DIV
Figure 3. Eye of ADN2891 @ 25°C, 3.2 Gbps, and 10 mV Input Figure 6. Eye of ADN2891 @ 95°C, 3.2 Gbps, and 500 mV Input
05244-019
50ps/DIV
100mV/DIV
1ns/DIV
100mV/DIV
05244-017
Figure 4. Eye of ADN2891 @ 25°C, 3.2 Gbps, and 500 mV Input Figure 7. Eye of ADN2891 @ 25°C, 155 Mbps, and 10 mV Input
05244-027
50ps/DIV
100mV/DIV
Figure 5. Eye of ADN2891 @ 95°C, 3.2 Gbps, and 10 mV Input
ADN2891
Rev. A | Page 8 of 16
70
01k 100k
05244-011
R
TH
(Ω)
LOS TRIP AND RELEASE (mV)
60
50
40
30
20
10
10k
+95°C
+25°C
–40°C
+95°C
+25°C
–40°C
DEASSERTION
ASSERTION
5.0
003.5
05244-010
DATA RATE (Gbps)
RANDOM JITTER (ps)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.5 1.0 1.5 2.0 2.5 3.0
Figure 8. LOS Trip and Release vs. RTH at OC48
Figure 11. Random Jitter vs. Data Rate
8
01k 100k
05244-012
R
TH
(Ω)
LOS ELECTRICAL HYSTERESIS (dB)
6
4
2
10k
OC48
OC3
14
003.5
05244-013
DATA RATE (Gbps)
DETERMINISTIC JITTER (ps)
12
10
8
6
4
2
0.5 1.0 1.5 2.0 2.5 3.0
Figure 12. Deterministic Jitter vs. Data Rate
Figure 9. LOS Electrical Hysteresis vs. RTH at 25°C
70
0
100k
05244-005
SUPPLY-NOISE FREQUENCY (Hz)
POWER SUPPLY-NOISE REJECTION (dB)
10M
60
50
40
30
20
10
1M
18
0
05244-022
ELECTRICAL HYSTERESIS (dB)
SAMPLE
16
14
12
10
8
6
4
2
6.0 6.3 6.6 6.9 7.2 7.5 7.8 8.1 8.4 8.7 9.0
Figure 13. PSRR vs. Supply-Noise Frequency
Figure 10. Sample Lot Distribution—Worst-Case Condition:
Conditions = 155 Mbps, 100 kΩ @ 95°C, 3.6 V
ADN2891
Rev. A | Page 9 of 16
1200
00
05244-018
PD_CATHODE CURRENT (PHOTODIODE CURRENT) (μA)
RSSI OUTPUT CURRENT (μA)
1200
1000
800
600
400
200
200 400 600 800 1000
0
05244-025
TEMPERATURE (°C)
5μA REFERRED OFFSET (nA)
–40 100
900
800
700
600
500
400
300
200
100
–20 0 20 40 60 80
Figure 17. RSSI Offset is the Difference Between Measured RSSI
Output and PD_CATHODE (Input) Current of 5 μA
Figure 14. RSSI Output vs. Average Photodiode Current
5.0
0
05244-029
PD_CATHODE CURRENT (μA)
RSSI LINEARITY (%)
0 1000
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
200 400 600 800
+100°C+30°C
–40°C
60
00
05244-028
PD_CATHODE CURRENT (PHOTODIODE CURRENT) (μA)
RSSI OUTPUT CURRENT (μA)
60
50
40
30
20
10
10 20 30 40 50
Figure 18. RSSI Linearity % vs. PD_CATHODE Current
Figure 15. RSSI Output vs. Average Photodiode Current (Zoomed)
44.5
41.0
05244-024
TEMPERATURE (°C)
I
CC
(mA)
–60 120
44.0
43.5
43.0
42.5
42.0
41.5
–40 –20 0 20 40 60 80 100
–0.15
–0.70
05244-023
INPUT CURRENT (μA)
COMPLIANCE VOLTAGE REFERRED TO VCC (V)
0 1000
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
100 200 300 400 500 600 700 800 900
Current vs. Temperature
Figure 19. ADN2891 I
Figure 16. PD_CATHODE Compliance Voltage vs.
Input Current RSSI (Refer to VCC)
CC
ADN2891
Rev. A | Page 10 of 16
THEORY OF OPERATION
LIMITING AMPLIFIER
Input Buffer
The ADN2891 limiting amplifier provides differential inputs
(PIN/NIN), each having single-ended, on-chip, 50 Ω termina-
tion. The amplifier can accept either dc-coupled or ac-coupled
signals; however, an ac-coupled signal is recommended. Using a
dc-coupled signal, the amplifier needs a correct input common-
mode voltage and enough headroom to handle the dynamic
input signal strength. Additionally, TIA output offset drifts may
degrade receiver performance.
The ADN2891 limiting amplifier is a high gain device. It is
susceptible to dc offsets in the signal path. The pulse width
distortion presented in the NRZ data or a distortion generated
by the TIA may appear as dc offset or a corrupted signal to the
ADN2891 inputs. An internal offset correction loop can
compensate for certain levels of offset. To compensate for more
offset, an external capacitor connected between the CAZ1 and
CAZ2 pins maybe necessary. For GbE and FC applications, no
external capacitor is necessary; however, for SONET appli-
cations, a 0.01 μF capacitor helps the input signal offset
compensation and provides a 3 dB cutoff frequency at 1 kHz.
CML Output Buffer
The ADN2891 provides differential CML outputs, OUTP and
OUTN. Each output has an internal 50 Ω termination to VCC.
LOSS OF SIGNAL (LOS) DETECTOR
The on-chip LOS circuit drives LOS to logic high when the
input signal level falls below a user-programmable threshold.
The threshold level can be set to anywhere from 3.5 mV p-p to
35 mV p-p, typical, and is set by a resistor connected between
the THRADJ pin and VEE. See Figure 8 and Figure 9 for the
LOS threshold vs. THRADJ. The ADN2891 LOS circuit has an
electrical hysteresis greater than 2.5 dB to prevent chatter at the
LOS signal. The LOS output is an open-collector output that
must be pulled up externally with a 4.7 kΩ to 10 kΩ resistor.
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
The ADN2891 has an on-chip, RSSI circuit. By monitoring the
current supplied to the photodiode, the RSSI circuit provides an
accurate, average power measurement. The output of the RSSI is
a current that is directly proportional to the average amount of
PIN photodiode current. Placing a resistor between the
RSSI_OUT pin and GND converts the current to a GND
referenced voltage. This function eliminates the need for
external RSSI circuitry for SFF-8472-compliant optical
receivers. For more information, see Figure 14 to Figure 18.
SQUELCH MODE
Driving the SQUELCH input to logic high disables the limiting
amplifier outputs. Using LOS output to drive the SQUELCH
input, the limiting amplifier outputs stop toggling anytime a
signal input level to the limiting amplifier drops below the
programmed LOS threshold.
The SQUELCH pin has a 100 kΩ, internal, pull-down resistor.
ADN2891
Rev. A | Page 11 of 16
APPLICATIONS
PCB DESIGN GUIDELINES The exposed pad should connect to the GND plane using filled
vias so that solder does not leak through the vias during reflow.
Using filled vias in parallel under the package greatly reduces
the thermal resistance and enhances the reliability of the
connectivity of the exposed pad to the GND plane during
reflow.
Proper RF PCB design techniques must be used to ensure
optimal performance.
Output Buffer Power Supply and Ground Planes
Pin 9 (DRVEE) and Pin 12 (DRVCC) are the power supply and
ground pins that provide current to the differential output
buffer. To reduce possible series inductance, Pin 9, which is the
ground return of the output buffer, should connect to ground
directly. If the ground plane is an internal plane and
connections to the ground plane are vias, multiple vias in
parallel to ground can reduce series inductance.
To reduce power noise, a 10 μF electrolytic decoupling capacitor
between power and ground should be close to where the 3.3 V
supply enters the PCB. The other 0.1 μF and 1 nF ceramic chip
decoupling capacitors should be close to the VCC and VEE pins
to provide better decouple filtering and a shorter current return
loop.
Similarly, to reduce the possible series inductance, Pin 12,
which supplies power to the high speed differential
OUTP/OUTN output buffer, should connect to the power plane
directly. If the power plane is an internal plane and connections
to the power plane are vias, multiple vias in parallel can reduce
the series inductance, especially on Pin 12. See Figure 20 for the
recommended connections.
05244-008
CONNECT
EXPOSED
PAD TO
GND
AVCC 1
THRADJ
5
CAZ1
6
CAZ2
7
LOS
8
PD_CATHODE
16
PD_VCC
15
RSSI_OUT
14
SQUELCH
13
PIN 2
NIN 3
AVEE 4
DRVCC
12
OUTN
10
DRVEE
9
OUTP
C4
C3
11
C2
C1 TO HOST
BOARD
C7 C8
VCC
C5 C6
VCC
C11
C12 R2
VCC
R3
4.7kΩ TO 10kΩ
ON HOST BOARD
VCC
ADN2880
0.1μF
VCC
C9
RSSI MEASUREMENT
TO ADC
R1 C10
C1–C4, C11: 0.01μF X5R/X7R DIELECTRIC, 0201 CASE
C5, C7, C9, C10, C12: 0.1μF X5R/X7R DIELECTRIC, 0402 CASE
C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE
ADN2891
Figure 20. Typical Applications Circuit (Example of Using PIN PD and On-Chip RSSI Detector)
ADN2891
Rev. A | Page 12 of 16
PCB Layout As with any high speed, mixed-signal design, keep all high
speed digital traces away from sensitive analog nodes.
Figure 21 shows the recommended PCB layout. The 50 Ω
transmission lines are the traces that bring the high frequency
input and output signals (PIN, NIN, OUTP, and OUTN) to the
SMA connectors with minimum reflection. To avoid a signal
skew between the differential traces, each differential PIN/NIN
and OUTP/OUTN pair should have matched trace lengths from
the signal pins to the corresponding SMA connectors. C1, C2,
C3, and C4 are ac coupling capacitors in series with the high
speed, signal input/output paths. To minimize the possible
mismatch, the ac coupling capacitor pads should be the same
width as the 50 Ω transmission line trace width. To reduce
supply noise, a 1 nF decoupling capacitor should be placed on
the same layer as close as possible to the VCC pins. A 0.1 μF
decoupling capacitor can be placed on the bottom of the PCB
directly underneath the 1 nF capacitor. All high speed, CML
outputs have internal 50 Ω resistor termination between the
output pin and VCC. The high speed inputs, PIN and NIN, also
have the internal 50 Ω termination to an internal reference
voltage.
Soldering Guidelines for the LFCSP
The lands on the 16-lead LFCSP are rectangular. The PCB pad
for these should be 0.1 mm longer than the package land length
and 0.05 mm wider than the package land width. The land
should be centered on the pad. This ensures that the solder joint
size is maximized. The bottom of the LFCSP has a central
exposed pad. The pad on the printed circuit board should be at
least as large as the exposed pad. Users must connect the
exposed pad to VEE using filled vias so that solder does not
leak through the vias during reflow. This ensures a solid
connection from the exposed pad to VEE.
05244-009
1
VIAS TO
GND
EXPOSED PAD
PIN
NIN
VIA TO C12, R2
ON BOTTOM
C11 VIA TO BOTTOM
C3
C8
C4
C1 C6
C2
OUTP
DOUBLE-VIAS TO REDUCE
INDUCTANCE TO SUPPLY
AND GND
R1, C9, C10 ON BOTTOM
TO ROSA
PLACE C7 ON
BOTTOM OF BOARD
UNDERNEATH C8
OUTN
PLACE C5 ON
BOTTOM OF BOARD
UNDERNEATH C6
∼
4mm
DOUBLE-VIA TO GND
TO REDUCE INDUCTANCE
Figure 21. Recommended PCB Layout (Top View)
ADN2891
Rev. A | Page 13 of 16
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1
INDICATO
R
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATO
R
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
(BOTTOM VIEW )
*COMPLIANT
TO
JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 22. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADN2891ACPZ-500RL7 –40°C to +95°C 16-Lead VQ_LFCSP, 500 pieces CP-16-3 F04
1
ADN2891ACPZ-RL7 –40°C to +95°C 16-Lead VQ_LFCSP, 1,500 pieces CP-16-3 F04
1
ADN2891ACPZ-RL –40°C to +95°C 16-Lead VQ_LFCSP, 5,000 pieces CP-16-3 F04
1
EVAL-ADN2891EB Evaluation Board
1 Z = Pb-free part.
ADN2891
Rev. A | Page 14 of 16
NOTES
ADN2891
Rev. A | Page 15 of 16
NOTES
ADN2891
Rev. A | Page 16 of 16
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05244–0–7/05(A)
