ICS8745BY - INTEGRATED DEVICE TECHNOLOGY

DATA SHEET

1:5 Differential-to-LVDS Zero Delay

Clock Generator

ICS8745B

General Description

The ICS8745B is a highly versatile 1:5 LVDS Clock

Generator and a member of the HiPerClockS™ family

of High Performance Clock Solutions from IDT. The

ICS8745B has a fully integrated PLL and can be

configured as zero delay buffer, multiplier or divider,

and has an output frequency range of 31.25MHz to 700MHz. The

Reference Divider, Feedback Divider and Output Divider are each

programmable, thereby allowing for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external

feedback allows the device to achieve “zero delay” between the input

clock and the output clocks. The PLL_SEL pin can be used to

bypass the PLL for system test and debug purposes. In bypass

mode, the reference clock is routed around the PLL and into the

internal output dividers.

Features

•Five differential LVDS outputs designed to meet

or exceed the requirements of ANSI TIA/EIA-644

•Selectable differential clock inputs

•CLKx, nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

•Output frequency range: 31.25MHz to 700MHz

•Input frequency range: 31.25MHz to 700MHz

•VCO range: 250MHz to 700MHz

•External feedback for “zero delay” clock regeneration

with configurable frequencies

•Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

•Cycle-to-cycle jitter: 30ps (maximum)

•Output skew: 35ps (maximum)

•Static phase offset: 25ps ± 125ps

•Full 3.3V supply voltage

•0°C to 70°C ambient operating temperature

•Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

HiPerClockS™

ICS

ICS8745B

32-Lead LQFP 7mm x 7mm x 1.4mm

package body

Top View

Block Diagram

PLL_SEL

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

FB_IN

nFB_IN

SEL0

SEL1

SEL2

SEL3

nQ0

nQ1

nQ2

nQ3

nQ4

PLL

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

÷1, ÷2, ÷4, ÷8,

÷16, ÷32, ÷64

Pullup

Pulldown

Pullup

Pulldown

Pullup

Pulldown

Pullup

Pulldown

Pin Assignment

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

SEL0

SEL1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

nQ3

VDDO

nQ2

GND

nQ1

VDD

nFB_IN

FB_IN

SEL2

GND

nQ0

VDDO

PLL_SEL

VDDA

SEL3

VDDO

nQ4

GND

VDD

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 2,

12, 29

SEL0, SEL1,

SEL2 SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.

3 CLK0 Input Pulldown Non-inverting differential clock input.

4 nCLK0 Input Pullup Inverting differential clock input.

5 CLK1 Input Pulldown Non-inverting differential clock input.

6 nCLK1 Input Pullup Inverting differential clock input.

7 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK1,nCLK1. When LOW, selects CLK0,

nCLK0. LVCMOS / LVTTL interface levels.

8 MR Input Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Qx to go low and the inverted outputs nQx to go high.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS / LVTTL interface levels.

9, 32 VDD Power Core supply pins.

10 FBIN Input Pullup Inverting differential feedback input to phase detector for regenerating clocks with

“Zero Delay.”

11 FBIN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating clocks

with “Zero Delay.”

13, 19, 25 GND Power Power supply ground.

14, 15 nQ0/Q0 Output Differential output pair. LVDS interface levels.

16, 22, 28 VDDO Power Output supply pins.

17, 18 nQ1/Q1 Output Differential output pair. LVDS interface levels.

20, 21 nQ2/Q2 Output Differential output pair. LVDS interface levels.

23, 24 nQ3/Q3 Output Differential output pair. LVDS interface levels.

26, 27 nQ4/Q4 Output Differential output pair. LVDS interface levels.

30 VDDA Power Analog supply pin.

31 PLL_SEL Input Pullup PLL select. Selects between the PLL and reference clock as the input to the

dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Function Tables

Table 3A. Control Input Function Table

*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.

Inputs Outputs

PLL_SEL = 1

PLL Enable Mode

SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q[0:4], nQ[0:4]

0z 0 0 0 250 - 700 ÷1

0001 125 - 350 ÷1

0010 62.5 - 175 ÷1

0011 31.25 - 87.5 ÷1

0100 250 - 700 ÷2

0101 125 - 350 ÷2

0110 62.5 - 175 ÷2

0111 250 - 700 ÷4

1000 125 - 350 ÷4

1001 250 - 700 ÷8

1010 125 - 350 x2

1011 62.5 - 175 x2

1100 31.25 - 87.5 x2

1101 62.5 - 175 x4

1110 31.25 - 87.5 x4

1111 31.25 - 87.5 x8

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Table 3B. PLL Bypass Function Table

Inputs Outputs

PLL_SEL = 0

PLL Bypass Mode

SEL3 SEL2 SEL1 SEL0 Q[0:4], nQ[0:4]

0z000 ÷4

0001 ÷4

0010 ÷4

0011 ÷8

0100 ÷8

0101 ÷8

0110 ÷16

0111 ÷16

1000 ÷32

1001 ÷64

1010 ÷2

1011 ÷2

1100 ÷4

1101 ÷1

1110 ÷2

1111 ÷1

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -0°C to 70°C

Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI-0.5V to VDD + 0.5V

Outputs, IO

Continuos Current

Surge Current

10mA

15mA

Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)

Storage Temperature, TSTG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Core Supply Voltage 3.135 3.3 3.465 V

VDDA Analog Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage 3.135 3.3 3.465 V

IDD Power Supply Current 125 mA

IDDA Analog Supply Current 17 mA

IDDO Output Supply Current 59 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2 VDD + 0.3 V

VIL Input Low Voltage -0.3 0.8 V

IIH Input High Current

CLK_SEL,

SEL[0:3], MR VDD = VIN = 3.465V 150 µA

PLL_SEL VDD = VIN = 3.465V 5 µA

IIL Input Low Current

CLK_SEL,

SEL[0:3], MR VDD = 3.465V, VIN = 0V -5 µA

PLL_SEL VDD = 3.465V, VIN = 0V -150 µA

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C

NOTE 1: VIL should not be less than -0.3V

NOTE 2: For single-ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.

Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C

Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current

CLK0, CLK1,

FB_IN VDD = VIN = 3.465V 150 µA

nCLK0, nCLK1,

nFB_IN VDD = VIN = 3.465V 5 µA

IIL Input Low Current

CLK0, CLK1,

FB_IN

VDD = 3.465V,

VIN = 0V -5 µA

nCLK0, nCLK1,

nFB_IN

VDD = 3.465V,

VIN = 0V -150 µA

VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V

VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD – 0.85 V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOD Differential Output Voltage 320 440 550 mV

∆VOD VOD Magnitude Change 0 50 mV

VOS Offset Voltage 1.05 1.2 1.35 V

∆VOS VOS Magnitude Change 25 mV

Symbol Parameter Test Conditions Minimum Typical Maximum Units

FIN Input Frequency CLK0/nCLK0,

CLK1/nCLK1

PLL_SEL = 1 31.25 700 µA

PLL_SEL = 0 700 V

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

AC Electrical Characteristics

Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when

the PLL is locked and the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 4: Phase jitter is dependent on the input source used.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 6: Characterized at VCO frequency of 622MHz.

NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 700 MHz

tPD Propagation Delay; NOTE 1 PLL_SEL = 0V, f ≤ 700MHz 3.1 3.4 4.0 ns

tsk(Ø) Static Phase Offset; NOTE 2, 5 PLL_SEL = 3.3V -100 25 150 ps

tsk(o) Output Skew; NOTE 3, 5 35 ps

tjit(cc) Cycle-to-Cycle Jitter; NOTE 5, 6 30 ps

tjit(θ) Phase Jitter; NOTE 4, 5, 6 ±52 ps

tLPLL Lock Time 1ms

tR / tFOutput Rise/Fall Time; NOTE 7 20% to 80% 200 700 ps

odc Output Duty Cycle 45 50 54 %

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Parameter Measurement Information

3.3V LVDS Output Load AC Test Circuit

Phase Jitter and Static Phase Offset

Cycle-to-Cycle Jitter

Differential Input Level

Output Skew

Output Rise/Fall Time

SCOPE

nQx

3.3V±5%

POWER SUPPLY

+–

Float GND LVDS

VDDA,

VDDO

VDD,

nCLK[0:1]

CLK[0:1]

nFB_IN

FB_IN

➤

t(Ø)

VOH

VOL

VOH

VOL

➤

tcycle n tcycle n+1

tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q[0:4]

nQ[0:4]

VDD

nCLK[0:1]

CLK[0:1]

GND

VCMR

Cross Points

VPP

tsk(o)

nQx

nQy

20%

80% 80%

20%

tRtF

VOD

Q[0:4]

nQ[0:4]

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Parameter Measurement Information, continued

Output Duty Cycle

Offset Voltage Setup

Propagation Delay

Differential Output Voltage Setup

tPW

tPERIOD

tPW

tPERIOD

odc = x 100%

Q[0:4]

nQ[0:4]

out

LVDS

DC Input

➤

VOS/∆ VOS

VDD

nQ[0:4]

Q[0:4]

nCLK[0:1]

CLK[0:1]

tPD

➤

100

out

LVDS

DC Input VOD/∆ VOD

VDD

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Application Information

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The ICS8745B provides separate

power supplies to isolate any high switching noise from the outputs

to the internal PLL. VDD, VDDA and VDDO should be individually

connected to the power supply plane through vias, and 0.01µF

bypass capacitors should be used for each pin. Figure 1 illustrates

this for a generic VDD pin and also shows that VDDA requires that an

additional 10Ω resistor along with a 10µF bypass capacitor be

connected to the VDDA pin.

Figure 1. Power Supply Filtering

Wiring the Differential Input to Accept Single Ended Levels

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock swing

is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =

0.609.

Figure 2. Single-Ended Signal Driving Differential Input

VDD

VDDA

3.3V

10Ω

10µF.01µF

.01µF

V_REF

Single Ended Clock Input

VDD

CLKx

nCLKx

0.1u R2

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both signals must meet the VPP and VCMR

input requirements. Figures 3A to 3F show interface examples for the

HiPerClockS CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 3A, the input

termination applies for IDT HiPerClockS open emitter LVHSTL

drivers. If you are using an LVHSTL driver from another vendor, use

their termination recommendation.

3A. HiPerClockS CLK/nCLK Input Driven by an IDT

Open Emitter HiPerClockS LVHSTL Driver

Figure 3C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 3E. HiPerClockS CLK/nCLK Input

Driven by a 3.3V HCSL Driver

Figure 3B. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 3D. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVDS Driver

Figure 3F. HiPerClockS CLK/nCLK Input

Driven by a 2.5V SSTL Driver

1.8V

Zo = 50Ω

CLK

nCLK

3.3V

LVHSTL

IDT

HiPerClockS

LVHSTL Driver

HiPerClockS

Input

125

3.3V

Zo = 50Ω

CLK

nCLK

3.3V

LVPECL HiPerClockS

Input

HCSL

*R3 33

*R4 33

CLK

nCLK

2.5V 3.3V

Zo = 50Ω

HiPerClockS

Input

*Optional – R3 and R4 can be 0Ω

CLK

nCLK

HiPerClockS

Input

LVPECL

3.3V

Zo = 50Ω

3.3V

100

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50Ω

CLK

nCLK

HiPerClockS

SSTL

2.5V

Zo = 60Ω

2.5V

3.3V

120

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

CLK/nCLK Input

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from CLK to ground.

Outputs:

LVDS Outputs

All unused LVDS output pairs can be either left floating or terminated

with 100Ω across. If they are left floating, we recommend that there

is no trace attached.

3.3V LVDS Driver Termination

A general LVDS interface is shown in Figure 4. In a 100Ω differential

transmission line environment, LVDS drivers require a matched load

termination of 100Ω across near the receiver input. For a multiple

LVDS outputs buffer, if only partial outputs are used, it is

recommended to terminate the unused outputs.

Figure 4. Typical LVDS Driver Termination

3.3V

LVDS Driver

100Ω

–

3.3V 50Ω

50Ω

100Ω Differential Transmission Line

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Schematic Example

The schematic of the ICS8745B layout example is shown in Figure

5A. The ICS8745B recommended PCB board layout for this example

is shown in Figure 5B. This layout example is used as a general

guideline. The layout in the actual system will depend on the selected

component types, the density of the components, the density of the

traces, and the stack up of the P.C. board.

Figure 5A. ICS8745B LVDS Zero Delay Buffer Schematic Example

8745

SEL0

SEL1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

VDD

nFB_IN

FB_IN

SEL2

GND

nQ0

VDDO

nQ1

GND

nQ2

VDDO

nQ3

VDD

PLL_SEL

VDDA

SEL3

VDDO

nQ4

GND

SP = Space (i.e. not intstalled)

C16

10u

CLK_SEL

0.1uF

VDDO=3.3V

C11

0.01u

RD3

VDD

(U1-9)

VDD=3.3V

SEL[3:0] = 0101,

Divide by 2

RU3

Zo = 50 Ohm

(77.76 MHz)

RU4

RU5

SEL0

RD4

(155.5 MHz)

SEL2

RU6

0.1uF

RU7

3.3V PECL Driver

CLK_SEL

RD2

RD5

VDDO

SEL1

VDDO

(U1-28)

SEL3

R8A

Zo = 50 Ohm

100

Decoupling capacitor located near the power pins

R10

SEL3

RU2

RD6

100

VDD

SEL0

(U1-32)

SEL2

0.1uF

RD7

Zo = 50 Ohm

SEL1

3.3V

(U1-16)

PLL_SEL

VDD

VDDA

(U1-22)

0.1uF

PLL_SEL

Zo = 50 Ohm

LVDS_input

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

The following component footprints are used in this layout example.

All the resistors and capacitors are size 0603.

Power and Grounding

Place the decoupling capacitors as close as possible to the power

pins. If space allows, placement of the decoupling capacitor on the

component side is preferred. This can reduce unwanted inductance

between the decoupling capacitor and the power pin caused by the

via.

Maximize the power and ground pad sizes and number of vias

capacitors. This can reduce the inductance between the power and

ground planes and the component power and ground pins.

The RC filter consisting of R7, C11, and C16 should be placed as

close to the VDDA pin as possible.

Clock Traces and Termination

Poor signal integrity can degrade the system performance or cause

system failure. In synchronous high-speed digital systems, the clock

signal is less tolerant to poor signal integrity than other signals. Any

ringing on the rising or falling edge or excessive ring back can cause

system failure. The shape of the trace and the trace delay might be

restricted by the available space on the board and the component

location. While routing the traces, the clock signal traces should be

routed first and should be locked prior to routing other signal traces.

• The differential 50Ω output traces should have the same length.

• Avoid sharp angles on the clock trace. Sharp angle turns cause

the characteristic impedance to change on the transmission

lines.

• Keep the clock traces on the same layer. Whenever

possible, avoid placing vias on the clock traces.

Placement of vias on the traces can affect the trace

characteristic impedance and hence degrade signal

integrity.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow a separation of at least three trace

widths between the differential clock trace and the other

signal trace.

• Make sure no other signal traces are routed between the clock

trace pair.

• The matching termination resistors should be located as close

to the receiver input pins as possible.

Figure 5B. PCB Board Layout for ICS8745B

C16

GND

50 Ohm

Traces

VDDA

VDDO

VIA

Pin 1

R7 C11

VDD

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS8745B.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8745B is the sum of the core power plus the analog power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (125mA + 17mA) = 492mW

• Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 59mA = 2045mW

Total Power_MAX = 492mW + 204mW = 696mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air

flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.696W * 42.1°C/W = 99.3°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resitance θJA for 32 Lead LQFP, Forced Convection

θJA vs. Air Flow

Linear Feet per Minute 0200500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Reliability Information

Table 8. θJA vs. Air Flow Table for a 32 Lead LQFP

Transistor Count

The transistor count for ICS8745B is: 2772

θJA vs. Air Flow

Linear Feet per Minute 0200500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Package Outline and Package Dimensions

Package Outline - Y Suffix for 32 Lead LQFP

Table 9. Package Dimensions for 32 Lead LQFP

Reference Document: JEDEC Publication 95, MS-026

JEDEC Variation: BBC - HD

All Dimensions in Millimeters

Symbol Minimum Nominal Maximum

N32

A1.60

A1 0.05 0.10 0.15

A2 1.35 1.40 1.45

b0.30 0.37 0.45

c0.09 0.20

D & E 9.00 Basic

D1 & E1 7.00 Basic

D2 & E2 5.60 Ref.

e0.80 Basic

L0.45 0.60 0.75

θ0° 7°

ccc 0.10

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Ordering Information

Table 10. Ordering Information

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature

8745BY ICS8745BY 32 Lead LQFP Tray 0°C to 70°C

8745BYT ICS8745BY 32 Lead LQFP 1000 Tape & Reel -40°C to 70°C

8745BYLF ICS8745BYLF “Lead-Free” 32 Lead LQFP Tray -40°C to 70°C

8745BYLFT ICS8745BYLF “Lead-Free” 32 Lead LQFP 1000 Tape & Reel -40°C to 70°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not

recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product

for use in life support devices or critical medical instruments.

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Revision History Sheet

Rev Table Page Description of Change Date

BT4D 5 LVDS DC Characteristics Table - modified VOS 0.90V min. to 1.05V min,

1.15V typical to 1.2V typical, and 1.4V max. to 1.35V max. 3/17/04

BT9

Added Lead-Free bullet.

Ordering Information Table - added Lead-Free part. 12/2/04

BT9 1

Features Section - delete bullet, ""Industrial temperature available upon request.""

Ordering Information Table - added Lead-Free note. 3/18/05

T6 7

AC Characteristics Table - changed tPD max limit from 3.7ns to 4.0ns.

Added Power Considerations section.

Updated format throughout the datasheet.

4/16/07

T4C

T10

Pin Assignment - corrected pin 14 from Q0 to nQ0. Missed error when converted to new

format on April 16, 2007 from December 4, 2004.

Differential DC Characteristics Table - replaced NOTE 1 with new note.

AC Characteristics Table - added thermal note.

Updated Differential Clock Input Interface section.

Ordering Information Table - Part/Order Number - deleted “ICS” prefix.

Updated Header/Footer throughout the document and contact page.

4/29/09

ICS8745B Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT

product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third

party owners.

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