8Data Sheet - Rev 2.1
03/2004
ARA1400
0.025 BSC 0.089 0.014 TYP
0.025 MIN.
0.099
0.197
0.163
BODY OUTLINE
(NOMINAL)
0.070 0.150
0.060 TYP.
0.400
(12X)0.020 TO 0.060 DIA.P
PLATED THRU HOLES.
DIMENSIONS IN INCHES
APPLICA TION INFORMA TION
Amplifier Enable / Disable
The ARA1400 includes two amplification stages that
each can be shut down through external control pins
VREF1 and VREF2 (pins 5 and 18, respectively). By
applying a typical bias of 1.75 Volts to these pins,
the amplifiers are enabled. In order to fully disable
an amplifier, its control pin requires a negative bias
of -1.5 to -2.0 Volts.
Output Switch Control
A switch located at the output of Amplifier A2 in the
ARA1400 provides isolation without having to
disable the amplifiers. The switch is controled by
the Tx logic input (pin 25).
Amplifier Bias Current
The ISET pins (11 and 27) set the bias current for the
amplification stages. Grounding these pins results
in the maximum possible current. By placing a
resistor from the pin to ground, the current can be
reduced. The recommended bias conditions use
the configuration shown in the test circuit schematic
in Figure 4.
Thermal Layout Considerations
The device package for the ARA1400 features a heat
slug on the bottom of the package body. Use of the
heat slug is an integral part of the device design.
Soldering it to the ground plane of the PC board will
ensure the lowest possible thermal resistance for
the device, and will result in the longest MTF (mean
time to failure.)
A PC board layout that optimizes the benefits of the
heat slug is shown in Figure 5. The via holes located
under the body of the device must be plated through
to a ground plane layer of metal, in order to provide
sufficient thermal conductivity. The recommended
solder mask outline is shown in Figure 6.
ESD Sensitivity
Electrostatic discharges can cause permanent
damage to these devices. Electrostatic charges
accumulate on test equipment and the human body,
and can discharge without detection. Proper
precautions and handling are strongly
recommended. Refer to the ANADIGICS application
note on ESD precautions.
Figure 5: PC Board Layout