1996, 2003
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD78P0308, 78P0308Y
8-BIT SINGLE-CHIP MICROCONTROLLERS
Document No. U11776EJ2V1DS00 (2nd edition)
Date Published August 2005 N CP(K)
Printed in Japan
DESCRIPTION
The
µ
PD78P0308 and 78P0308Y are members of the
µ
PD780308 and 780308Y Subseries of the 78K/0 Series,
in which the on-chip mask ROM of the
µ
PD780308 and 780308Y is replaced with a one-time PROM.
Because this device can be programmed by users, it is ideally suited for system evaluation, small-scale and
multiple-device production, and early development and time-to-market.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µ
PD780308, 780308Y Subseries User’s Manual: U11377E
78K/0 Series Instructions User’s Manual: U12326E
FEATURES
•Pin-compatible with mask ROM version (except VPP pin)
•Program memory (one-time PROM): 60 KBNote
•Internal high-speed RAM: 1024 bytes
•Internal expansion RAM: 1024 bytes
•LCD display RAM: 40 x 4 bits
•Supply voltage: VDD = 2.0 to 5.5 V
Note The internal PROM capacity can be changed by setting the internal memory size switching register (IMS).
Remark Refer to 1. DIFFERENCES BETWEEN
µ
PD78P0308, 78P0308Y AND MASK ROM VERSIONS for the
difference between the one-time PROM and mask ROM versions.
The mark shows major revised points.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
µ
PD78P0308, 78P0308Y
2Data Sheet U11776EJ2V1DS
ORDERING INFORMATION
Part Number Package Internal ROM
µ
PD78P0308GC-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) One-time PROM
µ
PD78P0308GC-8EU-A 100-pin plastic LQFP (fine pitch) (14 × 14) One-time PROM
µ
PD78P0308YGC-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) One-time PROM
µ
PD78P0308YGC-8EU-A 100-pin plastic LQFP (fine pitch) (14 × 14) One-time PROM
µ
PD78P0308GF-3BA 100-pin plastic QFP (14 × 20) One-time PROM
µ
PD78P0308GF-3BA-A 100-pin plastic QFP (14 × 20) One-time PROM
µ
PD78P0308YGF-3BA 100-pin plastic QFP (14 × 20) One-time PROM
µ
PD78P0308YGF-3BA-A 100-pin plastic QFP (14 × 20) One-time PROM
Remark Products that have the part numbers suffixed by “-A” are lead-free products.
3
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name.
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
PD78083
PD78018F PD78018FY
PD78014H EMI-noise reduced version of the PD78018F
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
µ
µ
µ
µ
42/44-pin
64-pin
64-pin
52-pin 52-pin version of the PD780024A
µ
µ
PD780024AS
µ
52-pin 52-pin version of the PD780034A
PD780034AS
PD78054 with IEBus
TM
controller
PD78054 with enhanced serial I/O
PD78078Y with enhanced serial I/O and limited functions
PD78054 with timer and enhanced external interface
64-pin
64-pin
80-pin
80-pin
80-pin EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O
PD780034A
PD780988
PD780034AY
µ
µ
µ
64-pin
PD780024A with expanded RAM
PD780024A with enhanced A/D converter
µ
µ
µ
µ
On-chip inverter controller and UART. EMI-noise reduced.
PD78064
PD78064B
PD780308
100-pin
100-pin
100-pin PD780308Y
PD78064Y
80-pin
78K/0
Series
LCD drive
PD78064 with enhanced SIO, and expanded ROM and RAM
EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported
µ
µµ
µ
µ
µ
µ
µ
µ
PD78018F with enhanced serial I/O
µ
µ
80-pin
100-pin
100-pin
Products in mass production Products under development
Y subseries products are compatible with I
2
C bus.
ROMless version of the PD78078
µ
100-pin
µ
µ
100-pin EMI-noise reduced version of the PD78078
µ
Inverter control
PD780208100-pin
VFD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
µ
µ
PD78098B
µ
100-pin
PD780024A PD780024AY
µµ
µ
80-pin
80-pin PD780852
PD780828B
µ
µ
For automobile meter driver. On-chip CAN controller
100-pin PD780958
µ
For industrial meter control
On-chip automobile meter controller/driver
Meter control
80-pin On-chip IEBus controller
80-pin
On-chip controller compliant with J1850 (Class 2)
PD780833Y
µ
PD780948 On-chip CAN controller
µ
64-pin PD780078 PD780078Y
µµ
PD780034A with timer and enhanced serial I/O
PD78054 PD78054Y
PD78058F PD78058FY
µ
µ
µ
µ
PD780058 PD780058Y
µµ
PD78070A PD78070AY
PD78078 PD78078Y
PD780018AY
µ
µ
µ
µ
µ
Control
PD78075B
µ
PD780065
µ
µ
PD78044H
PD780232
80-pin
80-pin For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
µ
µ
PD78044F
80-pin Basic subseries for driving VFD. Display output total: 34
µ
µ
120-pin
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
PD780318
PD780328
120-pin
120-pin
PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
µ
µ
PD780338
µ
µ
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µ
µ
µ
On-chip CAN controller
Specialized for CAN controller function
80-pin
PD780703AY
µ
PD780702Y
µ
64-pin PD780816
µ
PD780344 with enhanced A/D converter
100-pin
100-pin
µ
PD780344 PD780344Y
PD780354 PD780354Y
µ
µ
µ
µ
µ
PD78P0308, 78P0308Y
4Data Sheet U11776EJ2V1DS
The major functional differences between the subseries are shown below.
•Subseries without the suffix Y
Function ROM Timer 8-Bit 10-Bit 8-Bit Serial Interface I/O
External
Subseries Name Capacity 8-Bit 16-Bit Watch WDT A/D A/D D/A
Expansion
Control
µ
PD78075B
32 KB to 40 KB
4 ch 1 ch 1 ch 1 ch 8 ch – 2 ch 3 ch (UART: 1 ch) 88 1.8 V Yes
µ
PD78078
48 KB to 60 KB
µ
PD78070A – 61 2.7 V
µ
PD780058
24 KB to 60 KB
2 ch
3 ch (time-division UART: 1 ch)
68 1.8 V
µ
PD78058F
48 KB to 60 KB
3 ch (UART: 1 ch) 69 2.7 V
µ
PD78054
16 KB to 60 KB
2.0 V
µ
PD780065
40 KB to 48 KB
–4 ch (UART: 1 ch) 60 2.7 V
µ
PD780078
48 KB to 60 KB
2 ch – 8 ch 3 ch (UART: 2 ch) 52 1.8 V
µ
PD780034A
8 KB to 32 KB
1 ch 3 ch (UART: 1 ch) 51
µ
PD780024A
8 ch –
µ
PD780034AS
–4 ch 39 –
µ
PD780024AS
4 ch –
µ
PD78014H 8 ch 2 ch 53 Yes
µ
PD78018F
8 KB to 60 KB
µ
PD78083
8 KB to 16 KB
–– 1 ch (UART: 1 ch) 33 –
Inverter
µ
PD780988
16 KB to 60 KB
3 ch Note –1 ch – 8 ch – 3 ch (UART: 2 ch) 47 4.0 V Yes
control
VFD
µ
PD780208
32 KB to 60 KB
2 ch 1 ch 1 ch 1 ch 8 ch – – 2 ch 74 2.7 V –
drive
µ
PD780232
16 KB to 24 KB
3 ch – – 4 ch 40 4.5 V
µ
PD78044H
32 KB to 48 KB
2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 V
µ
PD78044F
16 KB to 40 KB
2 ch
LCD
µ
PD780354
24 KB to 32 KB
4 ch 1 ch 1 ch 1 ch – 8 ch – 3 ch (UART: 1 ch) 66 1.8 V –
drive
µ
PD780344 8 ch –
µ
PD780338
48 KB to 60 KB
3 ch 2 ch – 10 ch 1 ch 2 ch (UART: 1 ch) 54
µ
PD780328 62
µ
PD780318 70
µ
PD780308
48 KB to 60 KB
2 ch 1 ch 8 ch – –
3 ch (time-division UART: 1 ch)
57 2.0 V
µ
PD78064B 32 KB 2 ch (UART: 1 ch)
µ
PD78064
16 KB to 32 KB
Bus
µ
PD780948 60 KB 2 ch 2 ch 1 ch 1 ch 8 ch – – 3 ch (UART: 1 ch) 79 4.0 V Yes
interface
µ
PD78098B
40 KB to 60 KB
1 ch 2 ch 69 2.7 V –
supported
µ
PD780816
32 KB to 60 KB
2 ch 12 ch – 2 ch (UART: 1 ch) 46 4.0 V
Meter control
µ
PD780958
48 KB to 60 KB
4 ch 2 ch – 1 ch – – – 2 ch (UART: 1 ch) 69 2.2 V –
Dashboard
µ
PD780852
32 KB to 40 KB
3 ch 1 ch 1 ch 1 ch 5 ch – – 3 ch (UART: 1 ch) 56 4.0 V –
control
µ
PD780828B
32 KB to 60 KB
59
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
VDD
MIN.
Value
5
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
•Subseries with the suffix Y
Function ROM Timer 8-Bit 10-Bit 8-Bit Serial Interface I/O VDD
External
Subseries Name Capacity 8-Bit 16-Bit
Watch
WDT A/D A/D D/A
MIN. Value Expansion
Control
µ
PD78078Y
48 KB to 60 KB
4 ch 1 ch 1 ch 1 ch 8 ch −2 ch 3 ch (UART: 1 ch, 88 1.8 V Yes
µ
PD78070AY −I2C: 1 ch) 61 2.7 V
µ
PD780018AY
48 KB to 60 KB
−3 ch (I2C: 1 ch) 88
µ
PD780058Y
24 KB to 60 KB
2 ch 2 ch 3 ch (time-division 68 1.8 V
UART: 1 ch, I
2
C: 1 ch)
µ
PD78058FY
48 KB to 60 KB
3 ch (UART: 1 ch, 69 2.7 V
µ
PD78054Y
16 KB to 60 KB
I2C: 1 ch) 2.0 V
µ
PD780078Y
48 KB to 60 KB
2 ch −8 ch −4 ch (UART: 2 ch, 52 1.8 V
I2C: 1 ch)
µ
PD780034AY
8 KB to 32 KB
1 ch 3 ch (UART: 1 ch, 51
µ
PD780024AY 8 ch −I2C: 1 ch)
µ
PD78018FY
8 KB to 60 KB
2 ch (I2C: 1 ch) 53
LCD
µ
PD780354Y
24 KB to 32 KB
4 ch 1 ch 1 ch 1 ch −8 ch −4 ch (UART: 1 ch, 66 1.8 V −
drive
µ
PD780344Y 8 ch −I2C: 1 ch)
µ
PD780308Y
48 KB to 60 KB
2 ch 3 ch (time-division 57 2.0 V
UART: 1 ch, I
2
C: 1 ch)
µ
PD78064Y
16 KB to 32 KB
2 ch (UART: 1 ch,
I2C: 1 ch)
Bus
µ
PD780702Y 60 KB 3 ch 2 ch 1 ch 1 ch 16 ch −−4 ch (UART: 1 ch, 67 3.5 V −
interface
µ
PD780703AY 59.5 KB I2C: 1 ch)
supported
µ
PD780833Y 60 KB 65 4.5 V
Remark The functions of the subseries without the suffix Y and the subseries with the suffix Y are the same, except
for the serial interface (if a subseries without the suffix Y is available).
µ
PD78P0308, 78P0308Y
6Data Sheet U11776EJ2V1DS
Item
µ
PD78P0308
µ
PD78P0308Y
Internal memory One-time PROM 60 KBNote
High-speed RAM 1024 bytes
Expansion RAM 1024 bytes
LCD display RAM 40 x 4 bits
General-purpose registers 8 bits x 32 registers (8 bits x 8 registers x 4 banks)
Minimum instruction execution time On-chip minimum instruction execution time variable function
When main system 0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s/6.4
µ
s/12.8
µ
s (@ 5.0 MHz operation)
clock is selected
When subsystem 122
µ
s (@ 32.768 kHz operation)
clock is selected
Instruction set • 16-bit operation
•Multiply/divide (8 bits x 8 bits, 16 bits ÷ 8 bits)
•Bit manipulation (set, reset, test, Boolean operation)
•BCD adjustment, etc.
I/O ports Total: 57
(Segment signal output pins included) • CMOS input: 2
•CMOS I/O: 55
A/D converter 8-bit resolution x 8 channels
LCD controller/driver • Segment signal output: 40 pins maximum
•Common signal output: 4 pins maximum
•Bias: 1/2,1/3 bias convertible
Serial interface • 3-wire serial I/O/SBI/2-wire serial I/O • 3-wire serial I/O/2-wire serial I/O/I2C
mode selectable: 1 channel bus mode selectable: 1 channel
•3-wire serial I/O/UART mode selectable: 1 channel
•3-wire serial I/O mode: 1 channel
Timer • 16-bit timer/event counter: 1 channel
•8-bit timer/event counter: 2 channels
•Watch timer: 1 channel
•Watchdog timer: 1 channel
Timer output 3 pins (14-bit PWM output enable: 1 pin)
Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,
and 5.0 MHz (@ 5.0 MHz operation with main system clock)
32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz
(@ 5.0 MHz operation with main system clock)
OVERVIEW OF FUNCTIONS
Note The internal PROM capacity can be changed by setting the internal memory size switching register (IMS).
7
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Item
µ
PD78P0308
µ
PD78P0308Y
Vectored Maskable Internal: 13, External: 6
interrupt sources Non-maskable Internal: 1
Software 1
Test input Internal: 1, External: 1
Supply voltage VDD = 2.0 to 5.5 V
Package • 100-pin plastic LQFP (fine pitch) (14 × 14)
•100-pin plastic QFP (14 × 20)
µ
PD78P0308, 78P0308Y
8Data Sheet U11776EJ2V1DS
PIN CONFIGURATIONS (TOP VIEW)
(1) Normal operating mode
•100-pin plastic LQFP (fine pitch) (14 × 14)
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remarks 1. [ ]:
µ
PD78P0308Y only
2. When the device is used in applications where the noise generated inside the microcontroller needs to
be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and
VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
26
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AV
REF
P100
P101
P102
P103
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
COM2
V
LC1
V
LC2
V
SS0
S0
S1
S2
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
P70/SI2/RxD
P27/SCK0[/SCL]
P26/SO0/SB1[/SDA1]
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
S21
S20
S19
P10/ANI0
AV
SS
P117
P116
P114/R
X
D
P00/INTP0/TI00
XT2
XT1/P07
V
DD1
P113/T
X
D
P110/S13
P05/INTP5
P04/INTP4
P71/SO2/T
X
D
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P11/ANI1
V
SS1
P37
COM0
COM1
S4
S3
V
LC0
BIAS
COM3
S22
S23
P86/S33
P85/S34
P84/S35
P83/S36
P82/S37
P81/S38
P80/S39
P25/SI0/SB0[/SDA0]
P96/S25
P97/S24
P03/INTP3
P02/INTP2
P01/INTP1/TI01
X1
X2
V
PP
V
DD0
P115
P112/SCK3
P72/SCK2/ASCK
RESET
P111/SO3
9
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
•100-pin plastic QFP (14 × 20)
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remarks 1. [ ]:
µ
PD78P0308Y only
2. When the device is used in applications where the noise generated inside the microcontroller needs to
be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and
VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
P13/ANI3
P14/ANI4
P16/ANI6
P17/ANI7
P101
P102
P103
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
V
LC1
V
LC2
V
SS0
S0
S1
S2
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
P70/SI2/R
X
D
P27/SCK0[/SCL]
P26/SO0/SB1[/SDA1]
P87/S32
P90/S31
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
S21
S20
S19
P10/ANI0
AV
SS
P117
P116
XT2
XT1/P07
P113/T
X
D
P112/SCK3
P111/SO3
P110/SI3
P05/INTP5
P72/SCK2/ASCK
P71/SO2/T
X
D
V
SS1
P37
S4
S3
V
LC0
BIAS
COM3
S22
S23
P86/S33
P85/S34
P84/S35
P83/S36
P82/S37
P81/S38
P80/S39
P25/SI0/SB0[/SDA0]
P96/S25
P97/S24
P01/INTP1/TI01
P00/INTP0/TI00
RESET
X1
X2
V
PP
P11/ANI1
P12/ANI2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
79
78
77
26
27
28
29
30
76
COM2
COM1
COM0
P115
P114/R
X
D
V
DD1
P02/INTP2
P03/INTP3
P04/INTP4
P15/ANI5
P100
AV
REF
V
DD0
µ
PD78P0308, 78P0308Y
10 Data Sheet U11776EJ2V1DS
ANI0 to ANI7: Analog input RxD: Receive data
ASCK: Asynchronous serial clock S0 to S39: Segment output
AVREF:Analog reference voltage SB0, SB1: Serial bus
AVSS:Analog ground SCK0, SCK2, SCK3: Serial clock
BIAS: LCD power supply bias control SCL: Serial clock
BUZ: Buzzer clock SDA0, SDA1: Serial data
COM0 to COM3: Common output SI0, SI2, SI3: Serial input
INTP0 to INTP5: External interrupt input SO0, SO2, SO3: Serial output
P00 to P05, P07: Port 0 TI00, TI01: Timer input
P10 to P17: Port 1 TI1, TI2: Timer input
P25 to P27: Port 2 TO0 to TO2: Timer output
P30 to P37: Port 3 TxD: Transmit data
P70 to P72: Port 7 VDD0, VDD1:Power supply
P80 to P87: Port 8 VLC0 to VLC2:LCD power supply
P90 to P97: Port 9 VPP:Programming power supply
P100 to P103: Port 10 VSS0, VSS1:Ground
P110 to P117: Port 11 X1, X2: Crystal (main system clock)
PCL: Programmable clock XT1, XT2: Crystal (subsystem clock)
RESET: Reset
11
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
(2) PROM programming mode
•100-pin plastic LQFP (fine pitch) (14 × 14)
Cautions 1. (L): Independently connect to VSS via a pull-down resistor.
2. VSS:Connect to GND.
3. RESET: Set to low level.
4. Open: Leave open.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
26
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
RESET
V
DD
V
DD
(L)
Open
V
PP
(L)
PGM
A9
(L)
(L)
(L)
(L)
(L)
(L)
V
SS
(L)
Open
(L)
(L)
OE
CE
V
DD
(L)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
(L)
µ
PD78P0308, 78P0308Y
12 Data Sheet U11776EJ2V1DS
•100-pin plastic QFP (14 × 20)
Cautions 1. (L): Independently connect to VSS via a pull-down resistor.
2. VSS:Connect to GND.
3. RESET: Set to low level.
4. Open: Leave open.
A0 to A16: Address bus RESET: Reset
CE: Chip enable VDD:Power supply
D0 to D7: Data bus VPP:Programming power supply
OE: Output enable VSS:Ground
PGM: Program
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
79
78
26
27
28
29
30
76
RESET
V
DD
OE
V
DD
(L)
Open
V
PP
(L)
PGM
A9
(L)
(L)
(L)
(L)
(L)
V
SS
(L)
Open
(L)
CE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
(L)
(L)
V
DD
(L)
D0
D1
D2
D3
D4
D5
D6
D7
77
13
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
BLOCK DIAGRAM
Remark [ ]:
µ
PD78P0308Y only
TO0/P30
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
SI0/SB0[/SDA0]/P25
SO0/SB1[/SDA1]/P26
SCK0[/SCL]/P27
INTP0/P00 to
INTP5/P05
TI00/INTP0/P00
SCK2/ASCK/P72
ANI0/P10 to
ANI7/P17
AVREF
AVSS
SI2/RxD/P70
SO2/TxD/P71
RxD/P114
TxD/P113
BUZ/P36
PCL/P35
16-bit timer/
event counter
8-bit timer/event
counter 1
8-bit timer/event
counter 2
Watchdog timer
Watch timer
Serial interface 0
Serial interface 3
Interrupt control
Buzzer output
Clock output
control
A/D converter
Serial interface 2
P01 to P05
P10 to P17
P25 to P27
P30 to P37
P70 to P72
P110 to P117
P80 to P87
P90 to P97
P100 to P103
S24/P97 to
S31/P90
COM0 to COM3
VLC0 to VLC2
fLCD
RESET
X1
X2
XT1/P07
XT2
VDD0, VDD1 VSS0, VSS1 VPP
S32/P87 to
S39/P80
Port 0
Port 1
Port 2
Port 3
Port 7
LCD
controller/driver
Port 8
Port 9
Port 11
Port 10
System control
RAM
(2048 bytes)
78K/0
CPU
core
PROM
(60 KB)
P00
P07
S0 to S23
BIAS
SI3/P110
SO3/P111
SCK3/P112
µ
PD78P0308, 78P0308Y
14 Data Sheet U11776EJ2V1DS
CONTENTS
1. DIFFERENCES BETWEEN
µ
PD78P0308, 78P0308Y AND MASK ROM VERSIONS ................. 15
2. PIN FUNCTIONS ............................................................................................................................ 16
2.1 Pins in Normal Operating Mode ......................................................................................... 16
2.2 Pins in PROM Programming Mode ..................................................................................... 19
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ................................... 20
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ......................................................... 24
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ........................................... 25
5. PROM PROGRAMMING ................................................................................................................ 26
5.1 Operating Modes .................................................................................................................. 26
5.2 PROM Write Procedure........................................................................................................ 28
5.3 PROM Read Procedure ........................................................................................................ 32
6. ONE-TIME PROM VERSION SCREENING ................................................................................... 32
7. ELECTRICAL SPECIFICATIONS .................................................................................................. 33
8. PACKAGE DRAWINGS ................................................................................................................. 61
9. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 63
APPENDIX A. DEVELOPMENT TOOLS............................................................................................. 65
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 71
15
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
1. DIFFERENCES BETWEEN
µ
PD78P0308, 78P0308Y AND MASK ROM VERSIONS
The
µ
PD78P0308 and 78P0308Y are single-chip microcontrollers with an on-chip one-time PROM to which a
program can be written only once.
It is possible to make all the functions except for the PROM specifications and the mask option of LCD drive power
supply dividing resistor the same as those of mask ROM versions by setting the internal memory size switching register
(IMS).
Differences between the one-time PROM versions (
µ
PD78P0308, 78P0308Y) and mask ROM versions (
µ
PD780306,
780308, 780306Y, 780308Y) are shown in Table 1-1.
Table 1-1. Differences Between
µ
PD78P0308, 78P0308Y and Mask ROM Versions
Item
µ
PD78P0308
µ
PD78P0308Y Mask ROM Versions
µ
PD780308 Subseries
µ
PD780308Y Subseries
Internal ROM configuration One-time PROM Mask ROM
Internal ROM capacity 60 KB
µ
PD780306, 780306Y: 48 KB
µ
PD780308, 780308Y: 60 KB
Internal ROM capacity change PossibleNote Impossible
by the internal memory size
switching register (IMS)
IC pin No Yes
VPP pin Yes No
Mask options of LCD drive None Available
power supply dividing resistor
Serial interface (SBI) Provided Not provided Provided Not provided
Serial interface (I2C) Not provided Provided Not provided Provided
Electrical specifications, Refer to the data sheet of the individual product.
recommended soldering conditions
Note The internal PROM capacity is set to 60 KB by RESET input.
Caution There are differences in noise immunity and noise radiation between the one-time PROM and mask
ROM versions. When pre-producing an application set with a one-time PROM version and then
mass-producing it with a mask ROM version, be sure to conduct sufficient evaluations on the
commercial samples (CS) (not engineering samples (ES)) of the mask ROM version.
µ
PD78P0308, 78P0308Y
16 Data Sheet U11776EJ2V1DS
Pin Name I/O Function After Reset Alternate Function
P00 Input Port 0 Input only Input INTP0/TI00
P01 I/O 7-bit I/O port Input/output can be specified Input INTP1/TI01
P02 in 1-bit units. When used as INTP2
P03 the input port, on-chip pull-up INTP3
P04 resistor connection can be INTP4
P05 specified by software settings. INTP5
P07Note 1 Input Input only Input XT1
P10 to P17 I/O Port 1 Input ANI0 to ANI7
8-bit I/O port
Input/output can be specified in 1-bit units.
When used as the input port, on-chip pull-up resistor
connection can be specified by software settings.Note 2
P25 I/O Port 2 Input SI0/SB0[/SDA0]
3-bit I/O port
Input/output can be specified in 1-bit units.
When used as the input port, on-chip pull-up resistor
connection can be specified by software settings.
P30 I/O Port 3 Input TO0
P31 8-bit I/O port TO1
P32 Input/output can be specified in 1-bit units. TO2
P33 When used as the input port, on-chip pull-up resistor TI1
P34 connection can be specified by software settings. TI2
P35 PCL
P36 BUZ
P37 —
2. PIN FUNCTIONS
2.1 Pins in Normal Operating Mode
(1) Port pins (1/2)
Notes 1. When the P07/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register (PCC)
to 1, and be sure not to use the feedback resistor of the subsystem clock oscillator.
2. When the P10/ANI0 to P17/ANI7 pins are used as the analog inputs for the A/D converter, shift port 1 to
input mode. The on-chip pull-up resistors are automatically disabled.
Remark [ ]:
µ
PD78P0308Y only
P26
P27
SO0/SB1[/SDA1]
SCK0[/SCL]
17
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Pin Name I/O Function After Reset Alternate Function
P70 I/O Port 7 Input SI2/RXD
3-bit I/O port
Input/output can be specified in 1-bit units.
When used as the input port, on-chip pull-up resistor
connection can be specified by software settings.
P80 to P87 I/O Port 8 Input S39 to S32
8-bit I/O port
Input/output can be specified in 1-bit units.
When used as the input port, on-chip pull-up resistor
connection can be specified by software settings.
The I/O port/segment signal output function is
specifiable in 2-bit units by the LCD display control
register (LCDC).
P90 to P97 I/O Port 9 Input S31 to S24
8-bit I/O port
Input/output can be specified in 1-bit units.
When used as the input port, on-chip pull-up resistor
connection can be specified by software settings.
The I/O port/segment signal output function is
specifiable in 2-bit units by the LCD display control
register (LCDC).
P100 to P103 I/O Port 10 Input —
4-bit I/O port
Input/output can be specified in 1-bit units.
When used as the input port, on-chip pull-up resistor
connection can be specified by software settings.
It is possible to directly drive LEDs.
P110 I/O Port 11 Input SI3
P111 8-bit I/O port SO3
P112 Input/output can be specified in 1-bit units. SCK3
P113 When used as the input port, on-chip pull-up resistor TXD
P114 connection can be specified by software settings. RXD
P115 to P117 Falling edge detection is possible. —
(1) Port pins (2/2)
P71
P72
SO2/TXD
SCK2/ASCK
µ
PD78P0308, 78P0308Y
18 Data Sheet U11776EJ2V1DS
Pin Name I/O Function After Reset Alternate Function
INTP0 Input External interrupt request input for which the valid edge Input P00/TI00
INTP1 (rising edge, falling edge, or both rising and falling edges) P01/TI01
INTP2 can be specified. P02
INTP3 P03
INTP4 P04
INTP5 P05
SI0 Input Serial interface serial data input. Input P25/SB0[/SDA0]
SI2 P70/RxD
SI3 P110
SO0 Output Serial interface serial data output. Input P26/SB1[/SDA1]
SO2 P71/TxD
SO3 P111
SB0 I/O Serial interface serial data input/output. Input P25/SI0[/SDA0]
SB1 P26/SO0[/SDA1]
SDA0
µ
PD78P0308Y only P25/SI0/SB0
SDA1 P26/SO0/SB1
SCK0 I/O Serial interface serial clock input/output. Input P27[/SCL]
SCK2 P72/ASCK
SCK3 P112
SCL
µ
PD78P0308Y only P27/SCK0
RxD Input Asynchronous serial interface serial data input. Input P70/SI2, P114
TxD Output Asynchronous serial interface serial data output. Input P71/SO2, P113
ASCK Input Asynchronous serial interface serial clock input. Input P72/SCK2
TI00 Input External count clock input to 16-bit timer (TM0). Input P00/INTP0
TI01 Capture trigger signal input to capture register (CR00). P01/INTP1
TI1 External count clock input to 8-bit timer (TM1). P33
TI2 External count clock input to 8-bit timer (TM2). P34
TO0 Output
16-bit timer (TM0) output (also used for 14-bit PWM output).
Input P30
TO1 8-bit timer (TM1) output. P31
TO2 8-bit timer (TM2) output. P32
PCL Output Clock output (for main system clock, subsystem clock Input P35
trimming).
BUZ Output Buzzer output. Input P36
S0 to S23 Output LCD controller/driver segment signal output. Output —
S24 to S31 Input P97 to P90
S32 to S39 P87 to P80
COM0 to COM3 Output LCD controller/driver common signal output. Output —
VLC0 to VLC2 —LCD drive voltage. — —
BIAS — LCD drive power supply. — —
(2) Non-port pins (1/2)
Remark [ ]:
µ
PD78P0308Y only
19
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Pin Name I/O Function
RESET Input PROM programming mode setting.
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET
pin, this chip is set in the PROM programming mode.
VPP Input PROM programming mode setting and high voltage application during program write/verification.
A0 to A16 Input Address bus.
D0 to D7 I/O Data bus.
CE Input PROM enable input/program pulse input.
OE Input Read strobe input to PROM.
PGM Input Program/program inhibit input in PROM programming mode.
VDD —Positive power supply.
VSS —Ground potential.
Pin Name I/O Function After Reset Alternate Function
ANI0 to ANI7 Input A/D converter analog input. Input P10 to P17
AVREF Input A/D converter reference voltage input — —
(also used for analog power supply).
AVSS —
A/D converter ground potential. Set to the same potential as VSS0.
——
RESET Input System reset input. — —
X1 Input Crystal resonator connection for main system clock — —
X2 — oscillation. — —
XT1 Input Crystal resonator connection for subsystem clock Input P07
XT2 — oscillation. — —
VDD0 —Positive power supply for ports. — —
VSS0 —Ground potential for ports. — —
VDD1 —Positive power supply (except for ports and analog). — —
VSS1 —Ground potential (except for ports and analog). — —
VPP —
High voltage application in program write/verify mode.
——
Connect directly to VSS0 or VSS1 in normal operating mode.
(2) Non-port pins (2/2)
2.2 Pins in PROM Programming Mode
µ
PD78P0308, 78P0308Y
20 Data Sheet U11776EJ2V1DS
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/INTP0/TI00 2 Input Connect to VSS0.
P01/INTP1/TI01 8-C I/O Input: Independently connect to VSS0 via a resistor.
P02/INTP2 Output: Leave open.
P03/INTP3
P04/INTP4
P05/INTP5
P07/XT1 16 Input Connect to VDD0.
P10/ANI0 to P17/ANI7 11-B I/O Input: Independently connect to VDD0 or VSS0 via a resistor.
P25/SI0/SB0[/SDA0] 10-B Output: Leave open.
P26/SO0/SB1[/SDA1]
P27/SCK0[/SCL]
P30/TO0 5-H
P31/TO1
P32/TO2
P33/TI1 8-C
P34/TI2
P35/PCL 5-H
P36/BUZ
P37
P70/SI2/RXD8-C
P71/SO2/TXD5-H
P72/SCK2/ASCK 8-C
P80/S39 to P87/S32 17-C
P90/S31 to P97/S24
P100 to P103 5-H
P110/SI3 8-C Input: Independently connect to VDD0 via a resistor.
P111/SO3 Output: Leave open.
P112/SCK3
P113/TXD
P114/RXD
P115 to P117
S0 to S23 17-B Output Leave open.
COM0 to COM3 18-A
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The types of pin I/O circuits and the recommended connection of unused pins are shown in Table 2-1.
For the configuration of each type of I/O circuit, see Figure 2-1.
Table 2-1. Type of I/O Circuit of Each Pin (1/2)
Remark [ ]:
µ
PD78P0308Y only
21
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
VLC0 to VLC2 ——Leave open.
BIAS
RESET 2 Input —
XT2 16 — Leave open.
AVREF ——Connect to VSS0.
AVSS
VPP Connect directly to VSS0 or VSS1.
Table 2-1. Type of I/O Circuit of Each Pin (2/2)
µ
PD78P0308, 78P0308Y
22 Data Sheet U11776EJ2V1DS
Figure 2-1. List of Pin I/O Circuits (1/2)
Type 2
IN
Type 10-B
Pull-up
enable
Data
Output
disable
V
DD0
P-ch
N-ch
P-ch
IN/OUT
V
DD0
Type 11-B
Type 16
Pull-up
enable
Data
Output
disable
V
DD0
P-ch
N-ch
P-ch
IN/OUT
V
DD0
Type 5-H
Input
enable
Type 8-C
Schmitt-triggered input with hysteresis characteristics
Pull-up
enable
Data
Output
disable
Input
enable
N-ch
V
DD0
P-ch
IN/OUT
V
DD0
P-ch
P-ch
N-ch
V
REF
(threshold voltage)
Comparator +
–
Pull-up
enable
Data
Open drain
Output disable
N-ch
P-ch
V
DD0
V
DD0
P-ch
IN/OUT
XT1 XT2
P-ch
Feedback
cut-off
V
SS0
V
SS0
V
SS0
AV
SS
V
SS0
23
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Figure 2-1. List of Pin I/O Circuits (2/2)
Type 17-B Type 17-C
Pull-up
enable
Data
Output
disable
VDD0
P-ch
N-ch
P-ch
IN/OUT
VDD0
Input
enable
Type 18-A
SEG
data
VLC0
OUT
VLC1
VLC2
VSS1
COM
data
VLC0
OUT
VLC1
VLC2
VSS1
P-ch
P-ch N-ch
N-ch P-ch
P-ch
N-ch
N-ch
SEG
data
VLC0
VLC1
VLC2
VSS1
P-ch
P-ch
P-ch
N-ch
N-ch
N-ch
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
VSS0
µ
PD78P0308, 78P0308Y
24 Data Sheet U11776EJ2V1DS
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This is a register used to disable use of part of the internal memory by software. By setting the internal memory
size switching register (IMS), it is possible to get the same memory map as that of the mask ROM versions with a
different internal memory (ROM) capacity.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to CFH.
Figure 3-1. Format of Internal Memory Size Switching Register
RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0
7654321 0
Symbol
IMS
Address R/W
FFF0H CFH
After reset
R/W
Table 3-1 shows the setting values of IMS that make the memory mapping the same as that of the mask ROM
versions.
Table 3-1. Internal Memory Size Switching Register Setting Values
RAM2 RAM1 RAM0 Internal high-speed
RAM capacity selection
1101024 bytes
Other than above Setting prohibited
Target Mask ROM Versions IMS Setting Value
µ
PD780306, 780306Y CCH
µ
PD780308, 780308Y CFH
ROM3 ROM2 ROM1 ROM0
Internal
ROM
capacity
selection
11 0048 KB
11 1160 KB
Other than above Setting prohibited
25
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
IXRAM3 IXRAM2 IXRAM1 IXRAM0 Internal expansion RAM
capacity selection
10101024 bytes
Other than above Setting prohibited
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
IXS 0 0 0 0 IXRAM3 IXRAM2 IXRAM1 IXRAM0 FFF4H 0AH W
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS)
This register is used to set the internal expansion RAM capacity by software. By setting the internal expansion RAM
size switching register (IXS), it is possible to get the same memory map as that of the mask ROM versions with a
different internal expansion RAM capacity.
IXS is set with an 8-bit memory manipulation instruction.
RESET input sets IXS to 0AH.
Figure 4-1. Format of Internal Expansion RAM Size Switching Register
Table 4-1 shows the setting values of IXS that make the memory mapping the same as that of the mask ROM
versions.
Table 4-1. Internal Expansion RAM Size Switching Register Setting Values
Target Mask ROM Versions IXS Setting Value
µ
PD780306, 780306Y 0AH
µ
PD780308, 780308Y
µ
PD78P0308, 78P0308Y
26 Data Sheet U11776EJ2V1DS
5. PROM PROGRAMMING
The
µ
PD78P0308 and 78P0308Y have an on-chip 60 KB PROM as a program memory. For programming, set
the PROM programming mode with the VPP and RESET pins. For the connection of unused pins, refer to PIN
CONFIGURATIONS (2) PROM programming mode.
Caution Programs must be written in addresses 0000H to EFFFH (the last address EFFFH must be specified).
They cannot be written by a PROM programmer that cannot specify the write address.
5.1 Operating Modes
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM
programming mode is set. This mode will become the operating mode as shown in Table 5-1 when the CE, OE, and
PGM pins are set as shown.
Further, when the read mode is set, it is possible to read the contents of the PROM.
Table 5-1. Operating Modes of PROM Programming
Pin RESET VPP VDD CE OE PGM D0 to D7
Operating Mode
Page data latch L +12.5 V +6.5 V H L H Data input
Page write H H L High-impedance
Byte write L H L Data input
Program verify L L H Data output
Program inhibit ×HHHigh-impedance
×LL
Read +5 V +5 V L L H Data output
Output disable L H ×High-impedance
Standby H ××High-impedance
×: L or H
27
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
(1) Read mode
Read mode is set if CE = L, OE = L is set.
(2) Output disable mode
Data output becomes high-impedance, and is in the output disable mode, if OE = H is set.
Therefore, data can be read from any device by controlling the OE pin, if multiple
µ
PD78P0308 and 78P0308Ys
are connected to the data bus.
(3) Standby mode
Standby mode is set if CE = H is set.
In this mode, data outputs become high-impedance irrespective of the OE status.
(4) Page data latch mode
Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode.
In this mode, 1-page 4-byte data is latched in an internal address/data latch circuit.
(5) Page write mode
After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed
by applying a 0.1 ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification
can be performed, if CE = L, OE = L are set.
If programming is not performed by a one-time program pulse, write and verification operations should be
executed X times (X ≤ 10) repeatedly.
(6) Byte write mode
Byte write is executed when a 0.1 ms program pulse (active low) is applied to the PGM pin with CE = L, OE =
H. Then, program verification can be performed if OE = L is set.
If programming is not performed by a one-time program pulse, write and verification operations should be
executed X times (X ≤ 10) repeatedly.
(7) Program verify mode
Program verify mode is set if CE = L, PGM = H, OE = L are set.
In this mode, check if the write operation was performed correctly after the write.
(8) Program inhibit mode
Program inhibit mode is used when the OE pin, VPP pin, and D0 to D7 pins of multiple
µ
PD78P0308 and
78P0308Ys are connected in parallel and a write is performed to one of those devices.
When a write operation is performed, the page write mode or byte write mode described above is used. At this
time, a write is not performed to a device whose PGM pin is driven high.
µ
PD78P0308, 78P0308Y
28 Data Sheet U11776EJ2V1DS
5.2 PROM Write Procedure
Figure 5-1. Page Program Mode Flow Chart
G = Start address
N = Program last address
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X = 0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
X = X + 1
X = 10 ?
Address = N ?
V
DD
= 4.5 to 5.5 V, V
PP
= V
DD
Yes
No
Fail
Fail
All pass
Pass
No
Yes
Pass
Address = Address + 1
0.1 ms program pulse
Verify 4 bytes
Verify all bytes
Write end Defective product
29
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Figure 5-2. Page Program Mode Timing
A2 to A16
A0, A1
D0 to D7
VPP
VPP
VDD
VDD
VDD + 1.5
VDD
CE
VIH
VIL
PGM
VIH
VIL
OE
VIH
VIL
Page data latch Page program Program verify
Data outputData input
Hi-Z
µ
PD78P0308, 78P0308Y
30 Data Sheet U11776EJ2V1DS
Figure 5-3. Byte Program Mode Flow Chart
G = Start address
N = Program last address
Start
Address = G
V
DD
= 6.5 V, V
PP
= 12.5 V
X = 0
X = X + 1
Address = N ?
V
DD
= 4.5 to 5.5 V, V
PP
= V
DD
Yes
No
Fail
Fail
All pass
Pass
No
Yes
Pass
Address = Address + 1
X = 10 ?
0.1 ms program pulse
Verify
Verify all bytes
Write end Defective product
31
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Figure 5-4. Byte Program Mode Timing
Cautions 1. VDD should be applied before VPP, and cut after VPP.
2. VPP should not exceed +13.5 V, including overshoot.
3. Disconnection during application of +12.5 V to VPP may have an adverse effect on reliability.
Program
Data input Data output
Program verify
A0 to A16
D0 to D7
V
PP
V
PP
V
DD
V
DD
+ 1.5
V
DD
V
IH
V
IL
V
DD
CE
V
IH
V
IL
PGM
V
IH
V
IL
OE
Hi-Z
µ
PD78P0308, 78P0308Y
32 Data Sheet U11776EJ2V1DS
5.3 PROM Read Procedure
The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown
below.
(1) Fix the RESET pin to low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in
PIN CONFIGURATIONS (2) PROM programming mode.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input the address of the data to be read to the A0 to A16 pins.
(4) Read mode
(5) Output data to the D0 to D7 pins.
The timing of steps (2) to (5) above is shown in Figure 5-5.
Figure 5-5. PROM Read Timing
6. ONE-TIME PROM VERSION SCREENING
The one-time PROM versions cannot be tested completely by NEC Electronics before they are shipped, because
of their structure. It is recommended to perform screening to verify PROM after writing the necessary data and
performing high-temperature storage under the conditions below.
Storage Temperature Storage Time
125°C24 hours
A0 to A16
CE (input)
OE (input)
D0 to D7 Hi-Z
Address input
Data output Hi-Z
33
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD –0.3 to +7.0 V
VPP –0.3 to +13.5 V
AVREF –0.3 to VDD + 0.3 V
AVSS –0.3 to +0.3 V
Input voltage VI1 P00 to P05, P07, P10 to P17, P25 to P27, –0.3 to VDD + 0.3 V
P30 to P37, P70 to P72, P80 to P87, P90 to P97,
P100 to P103, P110 to P117, X1, X2, XT2, RESET
VI2 A9 PROM programming mode –0.3 to +13.5 V
Output voltage VO–0.3 to VDD + 0.3 V
Analog input voltage VAN P10 to P17 Analog input pin AVSS – 0.3 to AVREF + 0.3 V
Output current, high IOH Per pin –10 mA
Total for P01 to P05, P10 to P17, P25 to P27, –15 mA
P70 to P72, P110 to P117
Total for P30 to P37, P80 to P87, P90 to P97, –15 mA
P100 to P103
Output current, low IOL Per pin Peak value 30 mA
r.m.s. value 15Note mA
Total for P01 to P05, P10 to P17, Peak value 60 mA
P110 to P117 r.m.s. value 40Note mA
Total for P30 to P37, Peak value 140 mA
P100 to P103 r.m.s. value 100Note mA
Total for P25 to P27, P70 to P72, Peak value 50 mA
P80 to P87, P90 to P97 r.m.s. value 20Note mA
Operating ambient temperature
TA–40 to +85 °C
Storage temperature Tstg –65 to +150 °C
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input capacitance CIN f = 1 MHz 15 pF
Output capacitance COUT Unmeasured pins returned 15 pF
I/O capacitance CIO
to 0 V. 15 pF
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Note The root mean square (r.m.s.) value should be calculated as follows: [r.m.s. value] = [Peak value] × Duty
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
√
µ
PD78P0308, 78P0308Y
34 Data Sheet U11776EJ2V1DS
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.0Note 4 to 5.5 V)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
3. After VDD reaches oscillation voltage range MIN.
4. However, oscillation start voltage or higher and VDD = 2.0 V or higher (for external clock, VDD = 2.0 V or
higher).
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
•Keep the wiring length as short as possible.
•Do not cross the wiring with the other signal lines.
•Do not route the wiring near a signal line through which a high fluctuating current flows.
•Always make the ground point of the oscillator capacitor the same potential as VSS1.
•Do not ground the capacitor to a ground pattern through which a high current flows.
•Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit
Circuit
Ceramic Oscillation VDD = Oscillation 1.0 5.0 MHz
resonator frequency (fX)Note 1 voltage range
Oscillation After VDD reaches 4 ms
stabilization timeNote 2 oscillation voltage range MIN.
Crystal Oscillation VDD = Oscillation 1 5 MHz
resonator frequency (fX)Note 1 voltage range
Oscillation 4.5 V ≤ VDD ≤ 5.5 VNote 3 10 ms
stabilization timeNote 2 2.0 V ≤ VDD < 4.5 VNote 3 30
External clock X1 input 1.0 5.0 MHz
frequency (fX)Note 1
X1 input high-/low- 85 500 ns
level width (tXH, tXL)
X1
X2
X1
X2
VPP
C1
C2
R1
X1
X2
VPP
C1
C2
R1
35
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
XT1 XT2
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.0Note 4 to 5.5 V)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
3. After VDD reaches oscillation voltage range MIN.
4. However, oscillation start voltage or higher and VDD = 2.0 V or higher (for external clock, VDD = 2.0 V or
higher).
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figure to avoid an adverse effect from wiring capacitance.
•Keep the wiring length as short as possible.
•Do not cross the wiring with the other signal lines.
•Do not route the wiring near a signal line through which a high fluctuating current flows.
•Always make the ground point of the oscillator capacitor the same potential as VSS1.
•Do not ground the capacitor to a ground pattern through which a high current flows.
•Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
R2
XT2
XT1
V
PP
C4
C3
Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit
Circuit
Crystal Oscillation VDD = Oscillation 32 32.768 35 kHz
resonator frequency (fXT)Note 1 voltage range
Oscillation 4.5 V ≤ VDD ≤ 5.5 VÑote 3 1.2 2 s
stabilization timeNote 2
2.0 V ≤ VDD < 4.5 VNote 3 10
External clock XT1 input 32 100 kHz
frequency (fXT)Note 1
XT1 input high-/low- 5 15
µ
s
level width (tXTH, tXTL)
µ
PD78P0308, 78P0308Y
36 Data Sheet U11776EJ2V1DS
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, VIH1 P10 to P17, P30 to P32, 2.7 V ≤ VDD ≤ 5.5 V 0.7VDD VDD V
high P35 to P37, P80 to P87,
P90 to P97, P100 to P103 2.0 V ≤ VDD < 2.7 V 0.8VDD VDD V
VIH2 P00 to P05, P25 to P27, 2.7 V ≤ VDD ≤ 5.5 V 0.8VDD VDD V
P33, P34, P70 to P72,
P110 to P117, RESET 2.0 V ≤ VDD < 2.7 V 0.85VDD VDD V
VIH3 X1, X2 2.7 V ≤ VDD ≤ 5.5 V VDD – 0.5 VDD V
2.0 V ≤ VDD < 2.7 V VDD – 0.2 VDD V
VIH4 XT1/P07, XT2 4.5 V ≤ VDD ≤ 5.5 V 0.8VDD VDD V
2.7 V ≤ VDD < 4.5 V 0.9VDD VDD V
2.0 V ≤ VDD < 2.7 VNote 0.9VDD VDD V
Input voltage, VIL1 P10 to P17, P30 to P32, 2.7 V ≤ VDD ≤ 5.5 V 0 0.3VDD V
low P35 to P37, P80 to P87,
P90 to P97, P100 to P103 2.0 V ≤ VDD < 2.7 V 0 0.2VDD V
VIL2 P00 to P05, P25 to P27, 2.7 V ≤ VDD ≤ 5.5 V 0 0.2VDD V
P33, P34, P70 to P72,
P110 to P117, RESET 2.0 V ≤ VDD < 2.7 V 0 0.15VDD V
VIL3 X1, X2 2.7 V ≤ VDD ≤ 5.5 V 0 0.4 V
2.0 V ≤ VDD < 2.7 V 0 0.2 V
VIL4 XT1/P07, XT2 4.5 V ≤ VDD ≤ 5.5 V 0 0.2VDD V
2.7 V ≤ VDD < 4.5 V 0 0.1VDD V
2.0 V ≤ VDD < 2.7 VNote 00.1VDD V
Output voltage, VOH VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 VDD V
high IOH = –100
µ
AVDD – 0.5 VDD V
Output voltage, VOL1 P100 to P103 VDD = 4.5 to 5.5 V, 0.6 2.0 V
low IOL = 15 mA
P01 to P05, P10 to P17, VDD = 4.5 to 5.5 V, 0.4 V
P25 to P27, P30 to P37, IOL = 1.6 mA
P70 to P72, P80 to P87,
P90 to P97, P110 to P117
VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, 0.2VDD V
open-drain,
pulled up (R = 1 kΩ)
VOL3 IOL = 400
µ
A0.5 V
Note When the XT1/P07 pin is used as P07, input the inverse phase of P07 to the XT2 pin.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
37
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input leakage ILIH1 VIN = VDD P00 to P05, P10 to P17, P25 to P27, 3
µ
A
current, high P30 to P37, P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
P110 to P117, RESET
ILIH2 X1, X2, XT1/P07, XT2 20
µ
A
Input leakage ILIL1 VIN = 0 V P00 to P05, P10 to P17, P25 to P27, –3
µ
A
current, low P30 to P37, P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
P110 to P117, RESET
ILIL2 X1, X2, XT1/P07, XT2 –20
µ
A
Output leakage ILOH VOUT = VDD 3
µ
A
current, high
Output leakage ILOL VOUT = 0 V –3
µ
A
current, low
Software R VIN = 0 V P01 to P05, P10 to P17, 15 45 90 kΩ
pull-up resistor P25 to P27, P30 to P37,
P70 to P72, P80 to P87,
P90 to P97, P100 to
P103, P110 to P117
Supply IDD1 5.00 MHz crystal oscillation VDD = 5.0 V ±10%Note 5 515mA
currentNote 1 (fXX = 2.5 MHz)Note 2 VDD = 3.0 V ±10%Note 6 0.7 2.1 mA
operating mode VDD = 2.2 V ±10%Note 6 0.4 1.2 mA
5.00 MHz crystal oscillation VDD = 5.0 V ±10%Note 5 927mA
(fXX = 5.0 MHz)
Note 3
operating mode
VDD = 3.0 V ±10%Note 6 13mA
IDD2 5.00 MHz crystal oscillation VDD = 5.0 V ±10% 1.4 4.2 mA
(fXX = 2.5 MHz)Note 2 VDD = 3.0 V ±10% 500 1500
µ
A
HALT mode VDD = 2.2 V ±10% 280 840
µ
A
5.00 MHz crystal oscillation VDD = 5.0 V ±10% 1.6 4.8 mA
(fXX = 5.0 MHz)Note 3 HALT mode VDD = 3.0 V ±10% 650 1950
µ
A
IDD3 32.768 kHz crystal oscillation VDD = 5.0 V ±10% 135 270
µ
A
operating modeNote 4 VDD = 3.0 V ±10% 95 190
µ
A
VDD = 2.2 V ±10% 70 140
µ
A
IDD4 32.768 kHz crystal oscillation VDD = 5.0 V ±10% 25 55
µ
A
HALT modeNote 4 VDD = 3.0 V ±10% 5 15
µ
A
VDD = 2.2 V ±10% 2.5 12.5
µ
A
IDD5 XT1 = VDD VDD = 5.0 V ±10% 1 30
µ
A
STOP mode VDD = 3.0 V ±10% 0.5 10
µ
A
When feedback resistor is connected
VDD = 2.2 V ±10% 0.3 10
µ
A
IDD6 XT1 = VDD VDD = 5.0 V ±10% 0.1 30
µ
A
STOP mode VDD = 3.0 V ±10% 0.05 10
µ
A
When feedback resistor is disconnected
VDD = 2.2 V ±10% 0.05 10
µ
A
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 5.5 V)
Notes 1. Current flowing to the VDD pin. Not including the current flowing to the A/D converter, on-chip pull-up
resistors, or LCD dividing resistors.
2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
3. Main system clock fXX = fX operation (when OSMS is set to 01H)
4. When the main system clock is stopped.
5. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
6. Low-speed mode operation (when PCC is set to 04H)
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
µ
PD78P0308, 78P0308Y
38 Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.5 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviationNote (common) VLCD1 = VLCD × 2/3
LCD output voltage VODS IO = ±1
µ
AVLCD2 = VLCD × 1/3 0 ±0.2 V
deviationNote (segment) 2.5 V ≤ VLCD ≤ VDD
LCD Controller/Driver Characteristics (at Normal Operation)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.0 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) 2.0 V ≤ VLCD ≤ VDD
LCD output voltage VODS IO = ±1
µ
A0±0.2 V
deviation
Note
(segment)
(1) Static display mode (TA = –10 to +85°C, VDD = 2.0 to 5.5 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
(2) 1/3 bias method (TA = –10 to +85°C, VDD = 2.5 to 5.5 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.7 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) VLCD1 = VLCD × 1/2
LCD output voltage VODS IO = ±1
µ
AVLCD2 = VLCD1 0±0.2 V
deviationNote (segment) 2.7 V ≤ VLCD ≤ VDD
(3) 1/2 bias method (TA = –10 to +85°C, VDD = 2.7 to 5.5 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
39
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.0 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) VLCD1 = VLCD × 2/3
LCD output voltage VODS IO = ±1
µ
AVLCD2 = VLCD × 1/3 0 ±0.2 V
deviation
Note
(segment) 2.0 V ≤ VLCD ≤ VDD
LCD Controller/Driver Characteristics (at Low-Voltage Operation)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.0 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) 2.0 V ≤ VLCD ≤ VDD
LCD output voltage VODS IO = ±1
µ
A0±0.2 V
deviation
Note
(segment)
(1) Static display mode (TA = –10 to +85°C, 2.0 V ≤ VDD < 3.4 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
(2) 1/3 bias method (TA = –10 to +85°C, 2.0 V ≤ VDD < 3.4 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.0 VDD V
LCD dividing resistor RLCD 60 100 150 kΩ
LCD output voltage VODC IO = ±5
µ
AVLCD0 = VLCD 0±0.2 V
deviation
Note
(common) VLCD1 = VLCD × 1/2
LCD output voltage VODS IO = ±1
µ
AVLCD2 = VLCD1 0±0.2 V
deviation
Note
(segment) 2.0 V ≤ VLCD ≤ VDD
(3) 1/2 bias method (TA = –10 to +85°C, 2.0 V ≤ VDD < 3.4 V)
Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the
segment or common output (VLCDn; n = 0, 1, 2).
µ
PD78P0308, 78P0308Y
40 Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Cycle time TCY Operating on main system clock 2.7 V ≤ VDD ≤ 5.5 V 0.8 64
µ
s
(Min. instruction (fXX = 2.5 MHz)Note 1 2.0 V ≤ VDD < 2.7 V 2.0 64
µ
s
execution time) Operating on main system clock 3.5 V ≤ VDD ≤ 5.5 V 0.4 32
µ
s
(fXX = 5.0 MHz)Note 2 2.7 V ≤ VDD < 3.5 V 0.8 32
µ
s
Operating on subsystem clock 40Note 3 122 125
µ
s
TI00 input fTI00 tTI00 = tTIH00 + tTIL00 01/tTI00 MHz
frequency
TI00 input high-/ tTIH00,3.5 V ≤ VDD ≤ 5.5 V
2/f
sam
+ 0.1
Note 4
µ
s
low-level width tTIL00 2.7 V ≤ VDD < 3.5 V
2/f
sam
+ 0.2
Note 4
µ
s
2.0 V ≤ VDD < 2.7 V
2/f
sam
+ 0.5
Note 4
µ
s
TI01 input fTI01 2.7 V ≤ VDD ≤ 5.5 V 0 100 kHz
frequency 2.0 V ≤ VDD < 2.7 V 0 50 kHz
TI01 input high-/ tTIH01,2.7 V ≤ VDD ≤ 5.5 V 10
µ
s
low-level width tTIL01 2.0 V ≤ VDD < 2.7 V 20
µ
s
TI1, TI2 input fTI1 4.5 V ≤ VDD ≤ 5.5 V 0 4 MHz
frequency 2.0 V ≤ VDD < 4.5 V 0 275 kHz
TI1, TI2 input high-/
tTIH1,4.5 V ≤ VDD ≤ 5.5 V 100 ns
low-level width
tTIL1 2.0 V ≤ VDD < 4.5 V 1.8
µ
s
Interrupt request tINTH,INTP0 3.5 V ≤ VDD ≤ 5.5 V
2/f
sam
+ 0.1
Note 4
µ
s
input high-/low- tINTL 2.7 V ≤ VDD < 3.5 V
2/f
sam
+ 0.2
Note 4
µ
s
level width 2.0 V ≤ VDD < 2.7 V
2/f
sam
+ 0.5
Note 4
µ
s
INTP1 to INTP5, P110 to P117 2.7 V ≤ VDD ≤ 5.5 V 10
µ
s
2.0 V ≤ VDD < 2.7 V 20
µ
s
RESET low-level tRSL 2.7 V ≤ VDD ≤ 5.5 V 10
µ
s
width 2.0 V ≤ VDD < 2.7 V 20
µ
s
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 2.0 to 5.5 V)
Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
2. Main system clock fXX = fX operation (when OSMS is set to 01H)
3. This is the value when the external clock is used. The value is 114
µ
s (min.) when the crystal resonator
is used.
4. In combination with bits 0 (SCS0) and 1 (SCS1) of the sampling clock select register (SCS), selection of
fsam is possible between fXX/2N, fXX/32, fXX/64, and fXX/128 (when N = 0 to 4).
41
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
TCY vs. VDD (at main system clock fXX = fX/2 operation) TCY vs. VDD (at main system clock fXX = fX operation)
60
10
2.0
1.0
1023456
0.8
0.4
60
10
2.0
1.0
1023456
0.8
0.4
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
µ
Guaranteed
operation range
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
µ
Guaranteed
operation range
32
2.7 3.5
µ
PD78P0308, 78P0308Y
42 Data Sheet U11776EJ2V1DS
(2) Serial interface (TA = –40 to +85°C, VDD = 2.0 to 5.5 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY1 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK0 high-/low-level width tKH1,4.5 V ≤ VDD ≤ 5.5 V tKCY1/2 – 50 ns
tKL1 2.0 V ≤ VDD < 4.5 V tKCY1/2 – 100 ns
SI0 setup time (to SCK0↑) tSIK1 4.5 V ≤ VDD ≤ 5.5 V 100 ns
2.7 V ≤ VDD < 4.5 V 150 ns
2.0 V ≤ VDD < 2.7 V 300 ns
SI0 hold time (from SCK0↑)tKSI1 400 ns
SO0 output delay time tKSO1 C = 100 pFNote 300 ns
from SCK0↓
Note C is the load capacitance of SCK0 and SO0 output lines.
Note C is the load capacitance of SO0 output line.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY2 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK0 high-/low-level width tKH2,4.5 V ≤ VDD ≤ 5.5 V 400 ns
tKL2 2.7 V ≤ VDD < 4.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
SI0 setup time (to SCK0↑)tSIK2 100 ns
SI0 hold time (from SCK0↑)tKSI2 400 ns
SO0 output delay time tKSO2 C = 100 pFNote 300 ns
from SCK0↓
SCK0 rise, fall time tR2,1000 ns
tF2
(ii) 3-wire serial I/O mode (SCK0...external clock input)
43
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
(iii) SBI mode (SCK0...internal clock output):
µ
PD78P0308 only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY3 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.0 V ≤ VDD < 4.5 V 3200 ns
SCK0 high-/low-level tKH3,4.5 V ≤ VDD ≤ 5.5 V tKCY3/2 – 50 ns
width tKL3 2.0 V ≤ VDD < 4.5 V
tKCY3/2 – 150
ns
SB0, SB1 setup time tSIK3 4.5 V ≤ VDD ≤ 5.5 V 100 ns
(to SCK0↑)2.0 V ≤ VDD < 4.5 V 300 ns
SB0, SB1 hold time tKSI3 tKCY3/2 ns
(from SCK0↑)
SB0, SB1 output delay tKSO3 R = 1 kΩ,4.5 V ≤ VDD ≤ 5.5 V 0 250 ns
time from SCK0↓C = 100 pFNote 2.0 V ≤ VDD < 4.5 V 0 1000 ns
SB0, SB1↓ from SCK0↑tKSB tKCY3 ns
SCK0↓ from SB0, SB1↓tSBK tKCY3 ns
SB0, SB1 high-level tSBH tKCY3 ns
width
SB0, SB1 low-level tSBL tKCY3 ns
width
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(iv) SBI mode (SCK0...external clock input):
µ
PD78P0308 only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY4 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.0 V ≤ VDD < 4.5 V 3200 ns
SCK0 high-/low-level tKH4,4.5 V ≤ VDD ≤ 5.5 V 400 ns
width tKL4 2.0 V ≤ VDD < 4.5 V 1600 ns
SB0, SB1 setup time tSIK4 4.5 V ≤ VDD ≤ 5.5 V 100 ns
(to SCK0↑)2.0 V ≤ VDD < 4.5 V 300 ns
SB0, SB1 hold time tKSI4 tKCY4/2 ns
(from SCK0↑)
SB0, SB1 output delay tKSO4 R = 1 kΩ,4.5 V ≤ VDD ≤ 5.5 V 0 300 ns
time from SCK0↓C = 100 pFNote 2.0 V ≤ VDD < 4.5 V 0 1000 ns
SB0, SB1↓ from SCK0↑tKSB tKCY4 ns
SCK0↓ from SB0, SB1↓tSBK tKCY4 ns
SB0, SB1 high-level tSBH tKCY4 ns
width
SB0, SB1 low-level tSBL tKCY4 ns
width
SCK0 rise, fall time tR4,1000 ns
tF4
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
µ
PD78P0308, 78P0308Y
44 Data Sheet U11776EJ2V1DS
(v) 2-wire serial I/O mode (SCK0...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY5 R = 1 kΩ,2.7 V ≤ VDD ≤ 5.5 V 1600 ns
C = 100 pFNote 2.0 V ≤ VDD < 2.7 V 3200 ns
SCK0 high-level width tKH5 2.7 V ≤ VDD ≤ 5.5 V tKCY5/2 – 160 ns
2.0 V ≤ VDD < 2.7 V tKCY5/2 – 190 ns
SCK0 low-level width tKL5 4.5 V ≤ VDD ≤ 5.5 V tKCY5/2 – 50 ns
2.0 V ≤ VDD < 4.5 V tKCY5/2 – 100 ns
SB0, SB1 setup time tSIK5 4.5 V ≤ VDD ≤ 5.5 V 300 ns
(to SCK0↑)2.7 V ≤ VDD < 4.5 V 350 ns
2.0 V ≤ VDD < 2.7 V 400 ns
SB0, SB1 hold time tKSI5 600 ns
(from SCK0↑)
SB0, SB1 output delay tKSO5 300 ns
time from SCK0↓
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(vi) 2-wire serial I/O mode (SCK0...external clock input)
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY6 2.7 V ≤ VDD ≤ 5.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK0 high-level width tKH6 2.7 V ≤ VDD ≤ 5.5 V 650 ns
2.0 V ≤ VDD < 2.7 V 1300 ns
SCK0 low-level width tKL6 2.7 V ≤ VDD ≤ 5.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
SB0, SB1 setup time tSIK6 100 ns
(to SCK0↑)
SB0, SB1 hold time tKSI6 tKCY6/2 ns
(from SCK0↑)
SB0, SB1 output delay tKSO6 R = 1 kΩ,4.5 V ≤ VDD ≤ 5.5 V 0 300 ns
time from SCK0↓C = 100 pFNote 2.0 V ≤ VDD < 4.5 V 0 500 ns
SCK0 rise, fall time tR6,1000 ns
tF6
45
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
(vii) I2C bus mode (SCL...internal clock output):
µ
PD78P0308Y only
Note R and C are the load resistance and load capacitance of SCL, SDA0, and SDA1 output lines.
(viii) I2C bus mode (SCL...external clock input):
µ
PD78P0308Y only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCL cycle time tKCY8 1000 ns
SCL high-/low-level width tKH8, tKL8 400 ns
SDA0, SDA1 setup time tSIK8 200 ns
(to SCL↑)
SDA0, SDA1 hold time tKSI8 0ns
(from SCL↓)
SDA0, SDA1 output delay tKSO8 R = 1 kΩ,4.5 V ≤ VDD ≤ 5.5 V 0 300 ns
time from SCL↓C = 100 pFNote 2.0 V ≤ VDD < 4.5 V 0 500 ns
SDA0, SDA1↓ from SCL↑tKSB 200 ns
or SDA0, SDA1↑ from
SCL↑
SCL↓ from SDA0, SDA1↓tSBK 400 ns
SDA0, SDA1 high-level tSBH 500 ns
width
SCL rise, fall time tR8, tF8 1000 ns
Note R and C are the load resistance and load capacitance of SDA0 and SDA1 output lines.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCL cycle time tKCY7 R = 1 kΩ,2.7 V ≤ VDD ≤ 5.5 V 10
µ
s
C = 100 pFNote 2.0 V ≤ VDD < 2.7 V 20
µ
s
SCL high-level width tKH7 2.7 V ≤ VDD ≤ 5.5 V tKCY7 – 160 ns
2.0 V ≤ VDD < 2.7 V tKCY7 – 190 ns
SCL low-level width tKL7 4.5 V ≤ VDD ≤ 5.5 V tKCY7 – 50 ns
2.0 V ≤ VDD < 4.5 V tKCY7 – 100 ns
SDA0, SDA1 setup time tSIK7 2.7 V ≤ VDD ≤ 5.5 V 200 ns
(to SCL↑)2.0 V ≤ VDD < 2.7 V 300 ns
SDA0, SDA1 hold time tKSI7 0ns
(from SCL↓)
SDA0, SDA1 output tKSO7 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns
delay time from SCL↓2.0 V ≤ VDD < 4.5 V 0 500 ns
SDA0, SDA1↓ from tKSB 200 ns
SCL↑ or SDA0, SDA1↑
from SCL↑
SCL↓ from SDA0, SDA1↓tSBK 400 ns
SDA0, SDA1 high-level tSBH 500 ns
width
µ
PD78P0308, 78P0308Y
46 Data Sheet U11776EJ2V1DS
(b) Serial interface channel 2
(i) 3-wire serial I/O mode (SCK2...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK2 cycle time tKCY9 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK2 high-/low-level width tKH9,4.5 V ≤ VDD ≤ 5.5 V tKCY9/2 – 50 ns
tKL9 2.0 V ≤ VDD < 4.5 V tKCY9/2 – 100 ns
SI2 setup time (to SCK2↑) tSIK9 4.5 V ≤ VDD ≤ 5.5 V 100 ns
2.7 V ≤ VDD < 4.5 V 150 ns
2.0 V ≤ VDD < 2.7 V 300 ns
SI2 hold time (from SCK2↑)tKSI9 400 ns
SO2 output delay time tKSO9 C = 100 pFNote 300 ns
from SCK2↓
Note C is the load capacitance of SCK2 and SO2 output lines.
Note C is the load capacitance of SO2 output line.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK2 cycle time tKCY10 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK2 high-/low-level width tKH10,4.5 V ≤ VDD ≤ 5.5 V 400 ns
tKL10 2.7 V ≤ VDD < 4.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
SI2 setup time (to SCK2↑)tSIK10 100 ns
SI2 hold time (from SCK2↑)tKSI10 400 ns
SO2 output delay time tKSO10 C = 100 pFNote 300 ns
from SCK2↓
SCK2 rise, fall time tR10,1000 ns
tF10
(ii) 3-wire serial I/O mode (SCK2...external clock input)
47
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ASCK cycle time tKCY11 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
ASCK high-/low-level tKH11,4.5 V ≤ VDD ≤ 5.5 V 400 ns
width tKL11 2.7 V ≤ VDD < 4.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
Transfer rate 4.5 V ≤ VDD ≤ 5.5 V 39063 bps
2.7 V ≤ VDD < 4.5 V 19531 bps
2.0 V ≤ VDD < 2.7 V 9766 bps
ASCK rise, fall time tR11,1000 ns
tF11
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 4.5 V ≤ VDD ≤ 5.5 V 78125 bps
2.7 V ≤ VDD < 4.5 V 39063 bps
2.0 V ≤ VDD < 2.7 V 19531 bps
(iii) UART mode (dedicated baud rate generator output)
(iv) UART mode (external clock input)
µ
PD78P0308, 78P0308Y
48 Data Sheet U11776EJ2V1DS
(c) Serial interface channel 3
(i) 3-wire serial I/O mode (SCK3...internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK3 cycle time tKCY12 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK3 high-/low-level width tKH12,4.5 V ≤ VDD ≤ 5.5 V tKCY12/2 – 50 ns
tKL12 2.0 V ≤ VDD < 4.5 V
t
KCY12
/2 – 100
ns
SI3 setup time (to SCK3↑)tSIK12 4.5 V ≤ VDD ≤ 5.5 V 100 ns
2.7 V ≤ VDD < 4.5 V 150 ns
2.0 V ≤ VDD < 2.7 V 300 ns
SI3 hold time (from SCK3↑)tKSI12 400 ns
SO3 output delay time tKSO12 C = 100 pFNote 300 ns
from SCK3↓
Note C is the load capacitance of SCK3 and SO3 output lines.
Note C is the load capacitance of SO3 output line.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK3 cycle time tKCY13 4.5 V ≤ VDD ≤ 5.5 V 800 ns
2.7 V ≤ VDD < 4.5 V 1600 ns
2.0 V ≤ VDD < 2.7 V 3200 ns
SCK3 high-/low-level width tKH13,4.5 V ≤ VDD ≤ 5.5 V 400 ns
tKL13 2.7 V ≤ VDD < 4.5 V 800 ns
2.0 V ≤ VDD < 2.7 V 1600 ns
SI3 setup time (to SCK3↑)tSIK13 100 ns
SI3 hold time (from SCK3↑)tKSI13 400 ns
SO3 output delay time tKSO13 C = 100 pFNote 300 ns
from SCK3↓
SCK3 rise, fall time tR13,1000 ns
tF13
(ii) 3-wire serial I/O mode (SCK3...external clock input)
49
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
AC Timing Test Points (Excluding X1, XT1 Inputs)
Clock Timing
TI Timing
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
TI00, TI01
tTIL00, tTIL01 tTIH00, tTIH01
tTIL1 tTIH1
1/fTI1
TI1, TI2
t
XL
t
XH
1/f
X
V
DD
– 0.5 V
0.4 V
t
XTL
t
XTH
1/f
XT
V
IH4
(MIN.)
V
IL4
(MAX.)
X1 input
XT1 input
µ
PD78P0308, 78P0308Y
50 Data Sheet U11776EJ2V1DS
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm tKHm
SCK0, SCK2,
SCK3
SI0, SI2, SI3
SO0, SO2, SO3
tSIKm tKSIm
tKSOm
Input data
Output data
tRn tFn
m = 1, 2, 9, 10, 12, 13
n = 2, 10, 13
SBI mode (bus release signal transfer,
µ
PD78P0308 only):
SBI mode (command signal transfer,
µ
PD78P0308 only):
tSIK3, 4
tKCY3, 4
tKL3, 4 tKH3, 4
SCK0
tSBL tSBH
tKSB tSBK tKSI3, 4
tKSO3, 4
SB0, SB1
tR4 tF4
tSIK3, 4
tKCY3, 4
tKL3, 4 tKH3, 4
SCK0
tKSB tSBK tKSI3, 4
tKSO3, 4
SB0, SB1
tR4 tF4
51
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
2-wire serial I/O mode:
I2C bus mode (
µ
PD78P0308Y only):
tKSO5, 6
tSIK5, 6
tKCY5, 6
tKL5, 6 tKH5, 6
SCK0
tKSI5, 6
SB0, SB1
tR6 tF6
t
KL7, 8
t
SBH
t
SBK
t
KH7, 8
t
KSO7, 8
t
KSI7, 8
t
SBK
t
SIK7, 8
t
KSB
t
KSB
t
F8
t
R8
t
KCY7, 8
SCL
SDA0, SDA1
UART mode:
ASCK
tKCY11
tKL11 tKH11
tR11 tF11
µ
PD78P0308, 78P0308Y
52 Data Sheet U11776EJ2V1DS
A/D Converter Characteristics (TA = –40 to +85°C, VDD = 2.2 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 888bit
Overall errorNote 1 2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR
2.2 V ≤ AVREF < 2.7 V ±1.4 %FSR
Conversion time tCONV 2.7 V ≤ AVREF ≤ 5.5 V 19.1 200
µ
s
2.2 V ≤ AVREF < 2.7 V 38.2 200
µ
s
Sampling time tSAMP 24/fXX
µ
s
Analog input voltage VIAN AVSS AVREF V
Reference voltage AVREF 2.2 VDD V
AVREF-AVSS resistance RAIREF When A/D conversion not operating 4 14 kΩ
AVREF current AIREF When A/D conversion operatingNote 2 2.5 5.0 mA
When A/D conversion not operatingNote 3 0.5 1.5 mA
Notes 1. Quantization error (±1/2 LSB) is not included. This is expressed as a percentage (%FSR) to the full-scale
value.
2. Indicates current flowing to AVREF pin when the CS bit of the A/D converter mode register (ADM) is 1.
3. Indicates current flowing to AVREF pin when the CS bit of ADM is 0.
53
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply VDDDR 1.6 5.5 V
voltage
Data retention supply IDDDR VDDDR = 1.6 V 0.1 10
µ
A
current Subsystem clock stop and feedback
resistor disconnected.
Release signal set time tSREL 0
µ
s
Oscillation stabilization tWAIT Release by RESET 217/fx s
wait time Release by interrupt request Note s
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS),
selection of 212/fXX and 214/fXX to 217/fXX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
t
SREL
t
WAIT
V
DD
RESET
STOP mode
Data retention mode
Internal reset operation
HALT mode
Operating mode
V
DDDR
STOP instruction execution
tSREL
tWAIT
VDD
STOP instruction execution
STOP mode
Data retention mode
HALT mode
Operating mode
Standby release signal
(interrupt request)
VDDDR
µ
PD78P0308, 78P0308Y
54 Data Sheet U11776EJ2V1DS
Interrupt Request Input Timing
RESET Input Timing
t
INTL
t
INTH
INTP0 to INTP5
t
RSL
RESET
55
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH 0.7VDD VDD V
Input voltage, low VIL 00.3VDD V
Output voltage, high VOH1 IOH = –1 mA VDD – 1.0 V
VOH2 IOH = –100
µ
AVDD – 0.5 V
Output voltage, low VOL IOL = 1.6 mA 0.4 V
Input leakage current ILI 0 ≤ VIN ≤ VDD –10 +10
µ
A
Output leakage current ILO 0 ≤ VOUT ≤ VDD, OE = VIH –10 +10
µ
A
VPP supply voltage VPP VDD – 0.6 VDD VDD + 0.6 V
VDD supply voltage VDD 4.5 5.0 5.5 V
VPP supply current IPP VPP = VDD 100
µ
A
VDD supply current IDD CE = VIL, VIN = VIH 50 mA
PROM Programming Characteristics
DC Characteristics
(1) PROM write mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
(2) PROM read mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH 0.7VDD VDD V
Input voltage, low VIL 00.3VDD V
Output voltage, high VOH IOH = –1 mA VDD – 1.0 V
Output voltage, low VOL IOL = 1.6 mA 0.4 V
Input leakage current ILI 0 ≤ VIN ≤ VDD –10 +10
µ
A
VPP supply voltage VPP 12.2 12.5 12.8 V
VDD supply voltage VDD 6.25 6.5 6.75 V
VPP supply current IPP PGM = VIL 50 mA
VDD supply current IDD 50 mA
µ
PD78P0308, 78P0308Y
56 Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Address setup time (to PGM↓) tAS 2
µ
s
OE setup time tOES 2
µ
s
CE setup time (to PGM↓) tCES 2
µ
s
Input data setup time (to PGM↓) tDS 2
µ
s
Address hold time (from OE↑) tAH 2
µ
s
Input data hold time (from PGM↑) tDH 2
µ
s
Data output float delay time from OE↑tDF 0250 ns
VPP setup time (to PGM↓) tVPS 1.0 ms
VDD setup time (to PGM↓) tVDS 1.0 ms
Program pulse width tPW 0.095 0.105 ms
Valid data delay time from OE↓tOE 1
µ
s
OE hold time tOEH 2
µ
s
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Address setup time (to OE↓) tAS 2
µ
s
OE setup time tOES 2
µ
s
CE setup time (to OE↓) tCES 2
µ
s
Input data setup time (to OE↓) tDS 2
µ
s
Address hold time (from OE↑) tAH 2
µ
s
tAHL 2
µ
s
tAHV 0
µ
s
Input data hold time (from OE↑) tDH 2
µ
s
Data output float delay time from OE↑tDF 0250 ns
VPP setup time (to OE↓) tVPS 1.0 ms
VDD setup time (to OE↓) tVDS 1.0 250 ms
Program pulse width tPW 0.095 0.105 ms
Valid data delay time from OE↓tOE 1
µ
s
OE pulse width during data latching tLW 1
µ
s
PGM setup time tPGMS 2
µ
s
CE hold time tCEH 2
µ
s
OE hold time tOEH 2
µ
s
AC Characteristics
(1) PROM write mode
(a) Page program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
(b) Byte program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
57
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data output delay time from address tACC CE = OE = VIL 800 ns
Data output delay time from CE↓tCE OE = VIL 800 ns
Data output delay time from OE↓tOE CE = VIL 200 ns
Data output float delay time from OE↑tDF CE = VIL 060ns
Data hold time from address tOH CE = OE = VIL 0ns
(2) PROM read mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
PROM programming mode setup time tSMA 10
µ
s
(3) PROM programming mode setting (TA = 25°C, VSS = 0 V)
µ
PD78P0308, 78P0308Y
58 Data Sheet U11776EJ2V1DS
PROM Write Mode Timing (Page Program Mode)
A2 to A16
A0, A1
D0 to D7
V
DD
V
PP
V
PP
V
DD
V
DD
+ 1.5
V
DD
V
IL
V
IH
CE
V
IL
V
IH
PGM
V
IL
V
IH
OE
t
AS
Page data latch Page program Program verify
Data
output
Data input
t
AHL
t
DS
t
DH
t
VPS
Hi-Z Hi-Z
t
PGMS
t
AHV
t
DF
t
AH
t
OE
t
OEH
t
CES
t
OES
t
CEH
t
PW
t
VDS
t
LW
Hi-Z
59
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
PROM Write Mode Timing (Byte Program Mode)
Notes 1. If you want to read within the tACC range, make the OE input delay time from the fall of CE the maximum
of tACC – tOE.
2. tDF is the time from when either OE or CE first reaches VIH.
Cautions 1. VDD should be applied before VPP, and cut after VPP.
2. VPP should not exceed +13.5 V, including overshoot.
3. Disconnection during application of 12.5 V to VPP may have an adverse effect on reliability.
PROM Read Mode Timing
A0 to A16
D0 to D7
V
PP
V
PP
V
DD
V
DD
V
DD
+ 1.5
V
DD
CE
V
IH
V
IL
PGM
V
IH
V
IL
OE
V
IH
V
IL
Program Program verify
Data input Data output
Hi-Z Hi-Z Hi-Z
t
DF
t
AH
t
AS
t
DS
t
DH
t
VPS
t
VDS
t
CES
t
PW
t
OEH
t
OES
t
OE
CE
V
IH
V
IL
OE
V
IH
V
IL
D0 to D7
A0 to A16 Valid address
t
CE
Hi-Z Data output Hi-Z
t
ACCNote 1
t
OENote 1
t
OH
t
DFNote 2
µ
PD78P0308, 78P0308Y
60 Data Sheet U11776EJ2V1DS
PROM Programming Mode Setting Timing
RESET
0
VDD
VDD
0
VDD
VPP
A0 to A16 Valid address
tSMA
61
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
8. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
16.00±0.20
14.00±0.20
0.50 (T.P.)
1.00
J
16.00±0.20
K
C14.00±0.20
I0.08
1.00±0.20
L0.50±0.20
F1.00
N
P
Q
0.08
1.40±0.05
0.10±0.05
S100GC-50-8EU, 8EA-2
S1.60 MAX.
H0.22+0.05
−0.04
M0.17+0.03
−0.07
R3°+7°
−3°
125
26
50
100
76
75 51
S
SN
J
detail of lead end
C D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
µ
PD78P0308, 78P0308Y
62 Data Sheet U11776EJ2V1DS
80
81 50
100
131
30
51
100-PIN PLASTIC QFP (14x20)
HI
J
detail of lead end
M
QR
K
M
L
P
S
SN
G
F
NOTE
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
23.6±0.4
20.0±0.2
0.30±0.10
0.6
H
17.6±0.4
I
C14.0±0.2
0.15
J0.65 (T.P.)
K1.8±0.2
L0.8±0.2
F0.8
P100GF-65-3BA1-4
N
P
Q
0.10
2.7±0.1
0.1±0.1
R5°±5°
S3.0 MAX.
M0.15+0.10
−0.05
C D
A
B
S
63
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
9. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 9-1. Surface Mounting Type Soldering Conditions (1/2)
(1) 100-pin plastic QFP (14 × 20)
µ
PD78P0308GF-3BA, 78P0308YGF-3BA
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-00-3
(at 210°C or higher), Count: Three times or less
VPS Package peak temperature: 215°C, Time: 40 seconds max. VP15-00-3
(at 200°C or higher), Count: Three times or less
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., WS60-00-1
Count: Once, Preheating temperature: 120°C max. (package surface
temperature)
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Caution Do not use different soldering methods together (except for partial heating).
(2) 100-pin plastic LQFP (fine pitch) (14 × 14)
µ
PD78P0308GC-8EU, 78P0308YGC-8EU
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-107-2
(at 210°C or higher), Count: Twice or less,
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
VPS Package peak temperature: 215°C, Time: 40 seconds max. VP15-107-2
(at 200°C or higher), Count: Twice or less,
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
µ
PD78P0308, 78P0308Y
64 Data Sheet U11776EJ2V1DS
Table 9-1. Surface Mounting Type Soldering Conditions (2/2)
(3) 100-pin plastic QFP (14 × 20)
µ
PD78P0308GF-3BA-A, 78P0308YGF-3BA-A
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. IR60-203-3
(at 220°C or higher), Count: Three times or less, Exposure limit: 3 daysNote
(after that, prebake at 125°C for 20 to 72 hours)
Wave soldering For details, contact an NEC Electronics sales representative. −
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products that have the part numbers suffixed by “-A” are lead-free products.
(4) 100-pin plastic LQFP (fine pitch) (14 × 14)
µ
PD78P0308GC-8EU-A, 78P0308YGC-8EU-A
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. IR60-207-3
(at 220°C or higher), Count: Three times or less, Exposure limit: 7 daysNote
(after that, prebake at 125°C for 20 to 72 hours)
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Remark Products that have the part numbers suffixed by “-A” are lead-free products.
65
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are provided for system development using the
µ
PD78P0308 and 78P0308Y.
Also refer to (6) Precautions When Using Development Tools.
(1) Software Package
SP78K0 CD-ROM in which development tools (software) common to 78K/0 Series products are
integrated in one package
(2) Language Processing Software
RA78K0 Assembler package common to 78K/0 Series products
CC78K0 C compiler package common to 78K/0 Series products
DF780308 Device file for
µ
PD780308 and 780308Y Subseries products (part number:
µ
S××××DF78064)
CC78K0-L C compiler library source file common to 78K/0 Series products
(3) PROM Write Tools
PG-1500 PROM programmer
PA-78P0308GC Programmer adapter connected to the PG-1500
PA-78P0308GF
PG-1500 controller Control program for the PG-1500
(4) Debugging Tools
•When using IE-78K0-NS or IE-78K0-NS-A as in-circuit emulator
IE-78K0-NS In-circuit emulator common to 78K/0 Series products
IE-78K0-NS-PA Performance board to enhance/expand functions of IE-78K0-NS
IE-78K0-NS-A Combination of IE-78K0-NS and IE-78K0-NS-PA
IE-70000-MC-PS-B Power supply unit for IE-78K0-NS
IE-70000-98-IF-C Adapter required when using a PC-9800 series (excluding notebook-type PCs) as the host
machine (C bus supported)
IE-70000-CD-IF-A PC card and interface cable required when using a notebook type PC as the host machine
(PCMCIA socket supported)
IE-70000-PC-IF-C Adapter required when using an IBM PC/ATTM compatible as the host machine (ISA bus
supported)
IE-70000-PCI-IF-A Adapter required when using a PC with an on-chip PCI bus as the host machine
IE-780308-NS-EM1 Emulation board to emulate
µ
PD780308 and 780308Y Subseries products
NP-100GC Emulation probe for a 100-pin plastic LQFP (GC-8EU type)
NP-H100GC-TQ
NP-100GF Emulation probe for a 100-pin plastic QFP (GF-3BA type)
NP-100GF-TQ
NP-H100GF-TQ
TGC-100SDW Conversion adapter to connect the NP-100GC or NP-H100GC-TQ and a target system
board made to be mounted on a 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100 Conversion socket to connect the NP-100GF and a target system board made to be
mounted on a 100-pin plastic QFP (GF-3BA type)
TGF-100RBP Conversion socket to connect the NP-100GF-TQ or NP-H100GF-TQ and a target system
board made to be mounted on a 100-pin plastic QFP (GF-3BA type)
ID78K0-NS Integrated debugger for the IE-78K0-NS and IE-78K0-NS-A
SM78K0 System simulator common to 78K/0 Series products
DF780308 Device file for
µ
PD780308 and 780308Y Subseries products (part number:
µ
S××××DF78064)
µ
PD78P0308, 78P0308Y
66 Data Sheet U11776EJ2V1DS
•When using IE-78001-R-A as in-circuit emulator
IE-78001-R-ANote In-circuit emulator common to 78K/0 Series products
IE-70000-98-IF-C Adapter required when using a PC-9800 series (excluding notebook-type PCs) as the host
machine (C bus supported)
IE-70000-PC-IF-C Adapter required when using an IBM PC/AT compatible as the host machine (ISA bus
supported)
IE-70000-PCI-IF-A Adapter required when using a PC with an on-chip PCI bus as the host machine
IE-780308-R-EMNote Emulation board to emulate
µ
PD780308 and 780308Y Subseries products
EP-78064GC-R Emulation probe for a 100-pin plastic LQFP (GC-8EU type)
EP-78064GF-R Emulation probe for a 100-pin plastic QFP (GF-3BA type)
TGC-100SDW Conversion adapter to connect the EP-78064GC-R and a target system board made to be
mounted on a 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100 Conversion socket to connect the EP-78064GF-R and a target system board made to be
mounted on a 100-pin plastic QFP (GF-3BA type)
ID78K0 Integrated debugger for the IE-78001-R-A
SM78K0 System simulator common to 78K/0 Series products
DF780308 Device file for
µ
PD780308 and 780308Y Subseries products (part number:
µ
S××××DF78064)
Note Maintenance product
(5) Real-Time OS
RX78K0 Real-time OS for 78K/0 Series products
67
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
(6) Precautions When Using Development Tools
•The package name of the DF780308 is DF78064.
•Use the ID78K0-NS, ID78K0, and SM78K0 in combination with the DF780308.
•Use the CC78K0 and RX78K0 in combination with the RA78K0 and DF780308.
•The NP-100GC, NP-H100GC-TQ, NP-100GF, NP-100GF-TQ, and NP-H100GF-TQ are products of Naito
Densei Machida Mfg. Co., Ltd. (tel: +81-45-475-4191).
•The TGC-100SDW and TGF-100RBP are products of TOKYO ELETECH CORPORATION.
Contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (tel: +81-3-3820-7112)
Osaka Electronics Department (tel: +81-6-6244-6672)
•Please refer to Single-Chip Microcontroller Development Tools Selection Guide (U11069E) for information
on the third party development tools.
•The following table shows the software supported by each host machine and OS.
Host machine PC EWS
[OS] PC-9800 series [Japanese WindowsTM]HP9000 series 700TM [HP-UXTM]
Software IBM PC/AT compatibles [Japanese/English Windows] SPARCstationTM [SunOSTM, SolarisTM]
RA78K0 √Note √
CC78K0 √Note √
PG-1500 controller √Note
ID78K0-NS √
ID78K0 √
SM78K0 √
RX78K0 √Note √
Note DOS-based software
µ
PD78P0308, 78P0308Y
68 Data Sheet U11776EJ2V1DS
Drawing of Conversion Adapter (TGC-100SDW)
Figure A-1. Drawing of TGC-100SDW (for Reference Only)
ITEM MILLIMETERS INCHES
b1.85±0.25 0.073±0.010
c3.5 0.138
a14.45 0.569
d2.0 0.079
h16.0 0.630
i1.125±0.3 0.044±0.012
j0~5°0.000~0.197°
e3.9 0.154
f0.25
g 4.5 0.177
TGC-100SDW-G1E
0.010
k5.9 0.232
l0.8 0.031
m2.4 0.094
n2.7 0.106
ITEM MILLIMETERS INCHES
B
0.5x24=12 0.020x0.945=0.472
C0.5 0.020
A21.55 0.848
D
0.5x24=12 0.020x0.945=0.472
H10.9 0.429
I13.3 0.524
J15.7 0.618
E15.0 0.591
F21.55
G 3.55 0.140
0.848
K18.1 0.713
L13.75 0.541
M
0.5x24=12.0 0.020x0.945=0.472
Q10.0 0.394
R11.3 0.445
S18.1 0.713
N1.125±0.3 0.044±0.012
O1.125±0.2
P7.5 0.295
0.044±0.008
W1.8 0.071
XC 2.0 C 0.079
Y 0.9 0.035
T 5.0 0.197
U5.0
V4- 1.3 4- 0.051
0.197
Z 0.3 0.012
φ
φφ
φ
φ
φ
φ
φ
φ
φ
φφ
H
A
B
C
I J K
G
F E D
N OL
MX
P Q R S
U
Protrusion height
W
V
k
I
m
n
Z
j
g
i
h
a
e
d
c
b
Y
f
X
T
note: Product of TOKYO ELETECH CORPORATION.
69
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
Drawings of Conversion Socket (EV-9200GF-100) and Recommended Footprints
Figure A-2. Drawing of EV-9200GF-100 (for Reference Only)
EV-9200GF-100
A
D
EB
F
1
No.1 pin index
M
N O
L
K
S
RQ
I
H
G
P
C
J
EV-9200GF-100-G0E
ITEM MILLIMETERS INCHES
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
24.6
21
15
18.6
4-C 2
0.8
12.0
22.6
25.3
6.0
16.6
19.3
8.2
8.0
2.5
2.0
0.35
2.3
1.5
0.969
0.827
0.591
0.732
4-C 0.079
0.031
0.472
0.89
0.996
0.236
0.654
0.76
0.323
0.315
0.098
0.079
0.014
0.091
0.059
φ
φ
φ
φ
µ
PD78P0308, 78P0308Y
70 Data Sheet U11776EJ2V1DS
Figure A-3. Recommended Footprints of EV-9200GF-100 (for Reference Only)
F
H
E
D
A
B
C
I
J
K
L
0.026 × 1.142=0.742
0.026 × 0.748=0.486
EV-9200GF-100-P1E
ITEM MILLIMETERS INCHES
A
B
C
D
E
F
G
H
I
J
K
L
26.3
21.6
15.6
20.3
12±0.05
6±0.05
0.35±0.02
2.36±0.03
2.3
1.57±0.03
1.035
0.85
0.614
0.799
0.472
0.236
0.014
0.093
0.091
0.062
0.65±0.02 × 29=18.85±0.05
0.65±0.02 × 19=12.35±0.05
φ
+0.001
–0.002 +0.002
–0.002
+0.001
–0.002 +0.003
–0.002
+0.003
–0.002
+0.003
–0.002
+0.001
–0.001
+0.001
–0.002
φ
+0.001
–0.002
φ
φ
G
φ
φ
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNT MANUAL" website
(http://www.necel.com/pkg/en/mount/index.html).
Caution
71
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name Document No.
µ
PD780308, 780308Y Subseries User’s Manual U11377E
µ
PD780306, 780308 Data Sheet U11105E
µ
PD780306Y, 780308Y Data Sheet U12251E
µ
PD78P0308, 78P0308Y Data Sheet This document
78K/0 Series Instructions User’s Manual U12326E
78K/0 Series Application Note Basic (III) U10182E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
RA78K0 Assembler Package Operation U14445E
Language U14446E
Structured Assembly Language U11789E
CC78K0 C Compiler Operation U14297E
Language U14298E
SM78K Series System Simulator Ver.2.30 or Later Operation (Windows Based) U15373E
External Part User Open Interface Specifications U15802E
ID78K Series Integrated Debugger Ver.2.30 or Later Operation (Windows Based) U15185E
RX78K0 Real-Time OS Fundamentals U11537E
Installation U11536E
Project Manager Ver.3.12 or Later (Windows Based) U14610E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name Document No.
IE-78K0-NS In-Circuit Emulator U13731E
IE-78K0-NS-A In-Circuit Emulator U14889E
IE-78K0-NS-PA Performance Board To be prepared
IE-780308-NS-EM1 Emulation Board U13304E
IE-78001-R-A In-Circuit Emulator U14142E
IE-780308-R-EM Emulation Board U11362E
Documents Related to PROM Programming (User’s Manuals)
Document Name Document No.
PG-1500 PROM Programmer U11940E
PG-1500 Controller PC-9800 series (MS-DOSTM) Based EEU-1291
IBM PC series (PC DOSTM) Based U10540E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
µ
PD78P0308, 78P0308Y
72 Data Sheet U11776EJ2V1DS
Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages −X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
73
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between V
IL
(MAX)
and V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
µ
PD78P0308, 78P0308Y
74 Data Sheet U11776EJ2V1DS
Regional Information
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
J05.6
N
EC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
•
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
•
Succursale Française
•
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
•
Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-265 40 10
•
Tyskland Filial
Taeby, Sweden
Tel: 08-63 87 200
•
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
75
µ
PD78P0308, 78P0308Y
Data Sheet U11776EJ2V1DS
FIP and IEBus are trademarks of NEC Electronics Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries.
PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
µ
PD78P0308, 78P0308Y
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
