August 2010 Doc ID 14494 Rev 5 1/20
20
L6392
High-voltage high and low side driver
Features
■High voltage rail up to 600 V
■dV/dt immunity ± 50 V/nsec in full temperature
range
■Driver current capability:
– 290 mA source
– 430 mA sink
■Switching times 75/35 nsec rise/fall with 1 nF
load
■3.3 V, 5 V TTL/CMOS inputs with hysteresis
■Integrated bootstrap diode
■Operational amplifier for advanced current
sensing
■Adjustable dead-time
■Interlocking function
■Compact and simplified layout
■Bill of material reduction
■Flexible, easy and fast design
Applications
■Motor driver for home appliances, factory
automation, industrial drives.
■HID ballasts, power supply units.
Description
The L6392 is a high-voltage device manufactured
with the BCD “OFF-LINE” technology. It is a single
chip half-bridge gate driver for N-channel Power
MOSFET or IGBT.
The high side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing microcontroller/DSP
The IC embeds an operational amplifier suitable
for advanced current sensing in applications such
as field oriented motor control.
DIP-14
SO-14
Table 1. Device summary
Order codes Package Packaging
L6392N DIP-14 Tube
L6392D SO-14 Tube
L6392DTR SO-14 Tape and reel
www.st.com
Contents L6392
2/20 Doc ID 14494 Rev 5
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
L6392 Block diagram
Doc ID 14494 Rev 5 3/20
1 Block diagram
Figure 1. Block diagram
UV
DETECTION
LEVEL
SHIFTER
BOOTSTRAP DRIVER
S
V
CC
LVG
DRIVER
V
CC
HIN
LIN
HVG
DRIVER
HVG
OUT
LVG
BOOT
UV
DETECTION
OP+
OP-
GND
OPOUT
SD
DT
OPAMP
DEAD
TIME
R
LOGIC
SHOOT
THROUGH
PREVENTION
FLOATING STRUCTURE
+
-
V
CC
3
2
13
14
7
5
6
1
4
12
8
10
9
from LVG
5V
Pin connection L6392
4/20 Doc ID 14494 Rev 5
2 Pin connection
Figure 2. Pins connection (top view)
Table 2. Pin description
Pin N# Pin name Type Function
1LIN I Low side driver logic input (active low)
2SD
(1) I Shut down logic input (active low)
3 HIN I High side driver logic input (active high)
4 VCC P Lower section supply voltage
5 DT I Dead time setting
6 OPOUT O Opamp output
7 GND P Ground
8 OP+ I Opamp non inverting input
9 OP- I Opamp inverting input
10 LVG (1)
1. The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows
to omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
O Low side driver output
11 NC Not connected
12 OUT P High side (floating) common voltage
13 HVG (1) O High side driver output
14 BOOT P Bootstrapped supply voltage
VCC
HIN
LIN
SD
1
3
2
4NC
OUT
HVG
BOO
T
14
13
GND
DT
OPOUT
LVG
OP-
12
11
10
9
5
7
6
8OP+
L6392 Truth table
Doc ID 14494 Rev 5 5/20
3 Truth table
Note: X: don’t care
Table 3. Truth table
Inputs Outputs
SD LIN HIN LVG HVG
LXXLL
HLLHL
HLHL L
HHL L L
HHH L H
Electrical data L6392
6/20 Doc ID 14494 Rev 5
4 Electrical data
4.1 Absolute maximum ratings
Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to 1 kV (Human body model)
4.2 Thermal data
Table 4. Absolute maximum rating
Symbol Parameter
Value
Unit
Min Max
V
CC
Supply voltage - 0.3 + 21 V
V
out
Output voltage V
boot
-21 V
boot
+0.3 V
V
boot
Bootstrap voltage - 0.3 620 V
V
hvg
High side gate output voltage V
out
- 0.3 V
boot
+ 0.3 V
V
Ivg
Low side gate output voltage -0.3 V
CC
+ 0.3 V
Vop+ Opamp non-inverting input -0.3 V
CC
+ 0.3 V
Vop- Opamp inverting input -0.3 VCC + 0.3 V
V
i
Logic input voltage -0.3 15 V
dV
out
/dt Allowed output slew rate 50 V/ns
P
tot
Total power dissipation (TA = 25 °C) 800 mW
T
J
Junction temperature 150 °C
T
stg
Storage temperature -50 150 °C
Table 5. Thermal data
Symbol Parameter SO-14 DIP-14 Unit
R
th(JA)
Thermal resistance junction to ambient 165 100 °C/W
L6392 Electrical data
Doc ID 14494 Rev 5 7/20
4.3 Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Pin Parameter Test condition Min Max Unit
V
CC
4 Supply voltage 12.5 20 V
V
BO
(1)
1. VBO = Vboot -Vout
14-12 Floating supply voltage 12.4 20 V
V
out
12 DC output voltage -9 (2)
2. LVG off. VCC = 12.5 V.
Logic is operational if Vboot > 5 V.
580 V
f
sw
Switching frequency HVG, LVG load C
L
= 1nF 800 kHz
TJJunction temperature -40 125 °C
Electrical characteristics L6392
8/20 Doc ID 14494 Rev 5
5 Electrical characteristics
5.1 AC operation
Table 7. AC operation electrical characteristics (VCC = 15 V; TJ =+25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
t
on
1 vs 10
3 vs 13
High/low side driver turn-
on propagation delay V
out
= 0 V
Vboot = V
cc
C
L
= 1 nF
Vi = 0 to 3.3 V
See Figure 3
50 125 200 ns
t
off
High/low side driver turn-
off propagation delay 50 125 200 ns
t
sd
2 vs
10, 13
Shut down to high/low
side propagation delay 50 125 200 ns
MT Delay matching, HS and
LS turn-on/off 30 ns
DT 5 Dead time setting range
(1)
RDT = 0; C
L
= 1 nF; C
DT
= 100 nF 0.1 0.18 0.25
μs
RDT = 37 kΩ;C
L
= 1 nF; C
DT
=100 nF 0.48 0.6 0.72
RDT = 136 kΩ;C
L
=1 nF; C
DT
=100 nF 1.35 1.6 1.85
RDT = 260 kΩ;C
L
=1 nF; C
DT
=100 nF 2.6 3.0 3.4
MDT Matching dead time (2)
RDT = 0 Ω; C
L
=1 nF; C
DT
=100 nF 80
ns
RDT = 37 kΩ;C
L
=1 nF; C
DT
=100 nF 120
RDT = 136 kΩ;C
L
=1 nF; C
DT
=100 nF 250
RDT = 260 kΩ;C
L
=1 nF; C
DT
=100 nF 400
t
r
10, 13 Rise time C
L
= 1 nF 75 120 ns
t
f
Fall time C
L
= 1 nF 35 70 ns
1. See Figure 4 on page 9
2. MDT = | DTLH - DTHL | see Figure 5 on page 13
L6392 Electrical characteristics
Doc ID 14494 Rev 5 9/20
Figure 3. Timing characteristics
Figure 4. Typical dead time vs. DT resistor value
HIN
HVG
50%
10%
90%
50%
trtf
ton toff
90%
10%
LIN
LVG
50%
10%
90%
50%
trtf
ton toff
90%
10%
LVG/HVG
SD
90%
50%
tf
tsd
10%
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Electrical characteristics L6392
10/20 Doc ID 14494 Rev 5
5.2 DC operation
Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
Low supply voltage section
Vcc_hys
4
Vcc UV hysteresis 1200 1500 1800 mV
Vcc_thON
Vcc UV turn ON
threshold 11.5 12 12.5 V
Vcc_thOFF
Vcc UV turn OFF
threshold 10 10.5 11 V
I
qccu
Undervoltage quiescent
supply current
VCC = 10 V
SD = 5 V; LIN = 5 V;
HIN = GND;
RDT = 0 Ω;
OP + = GND; OP - = 5 V
120 150 μA
I
qcc
Quiescent current
VCC = 15 V
SD = 5 V; LIN = 5 V;
HIN = GND;
RDT = 0 Ω;
OP + = GND; OP - = 5 V
680 1000 μA
Bootstrapped supply voltage section (1)
VBO_hys
14
VBO UV hysteresis 1200 1500 1800 mV
VBO_thON VBO UV turn ON
threshold 10.6 11.5 12.4 V
VBO_thOFF VBO UV turn OFF
threshold 9.1 10 10.9 V
I
QBOU
Undervoltage VBO
quiescent current
VBO = 9 V
SD = 5 V; LIN and HIN = 5 V;
RDT = 0 Ω;
OP + = GND; OP - = 5 V
70 110 μA
I
QBO
VBO quiescent current
VBO = 15 V
SD = 5 V; LIN and HIN = 5 V;
RDT = 0 Ω;
OP + = GND; OP - = 5 V
150 210 μA
ILK
High voltage leakage
current Vhvg = Vout = Vboot = 600 V 10 μA
R
DS(on)
Bootstrap driver on
resistance (2) LVG ON 120 Ω
L6392 Electrical characteristics
Doc ID 14494 Rev 5 11/20
Symbol Pin Parameter Test condition Min Typ Max Unit
Driving buffers section
I
so
10, 13
High/low side source
short circuit current V
i
= V
ih
(t
p
< 10 ms) 200 290 mA
I
si
High/low side sink short
circuit current V
i
= V
il
(tp < 10 ms) 250 430 mA
Logic inputs
V
il
1, 2, 3 Low logic level voltage 0.8 V
V
ih
High logic level voltage 2.25 V
Vil_S
1, 3 Single input voltage LIN and HIN connected together
and floating 0.8 V
I
HINh
3
HIN logic “1” input bias
current HIN = 15 V 110 175 260 μA
I
HINl
HIN logic “0” input bias
current HIN = 0 V 1 μA
I
LINI
1
LIN logic “0” input bias
current LIN = 0 V 3 6 20 μA
I
LINh
LIN logic “1” input bias
current LIN = 15 V 1 μA
I
SDh
2
SD logic “1” input bias
current SD = 15 V 10 30 100 μA
I
SDl
SD logic “0” input bias
current SD = 0 V 1 μA
1. VBO = Vboot - Vout
2. RDSon is tested in the following way:
RDSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 14 current when
VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2
Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = +25 °C) (continued)
Electrical characteristics L6392
12/20 Doc ID 14494 Rev 5
Table 9. OPAMP characteristics (VCC = 15 V, TJ = +25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
V
io
8, 9
Input offset voltage Vic = 0 V, Vo = 7.5 V 6 mV
I
io
Input offset current Vic = 0 V, Vo = 7.5 V 440nA
Iib Input bias current (1) 100 200 nA
V
icm
Input common mode voltage
range 0V
CC-4 V
V
OL
6
Low level output voltage RL = 10 kΩ to VCC 75 150 mV
V
OH
High level output voltage RL = 10 kΩ to GND 14 14.7 V
I
o
Output short circuit current
Source,
Vid = + 1 V; Vo = 0 V 16 30 mA
Sink
Vid = -1 V; Vo = VCC
50 80 mA
SR Slew rate Vi = 1÷4;
CL = 100 pF; unity gain 2.5 3.8 V/μs
GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz
Avd Large signal voltage gain RL = 2 kΩ70 85 dB
SRV Power supply rejection ratio vs Vcc 60 75 dB
CMRR Common mode rejection
ratio 55 70 dB
1. The direction of input current is out of the IC.
L6392 Waveforms definitions
Doc ID 14494 Rev 5 13/20
6 Waveforms definitions
Figure 5. Dead time - timing waveforms
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
DTLH DTHL
DTLH DTHL
DTLH DTHL
DTLH DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
INTERLOCKING
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
(*) HIN and LIN can be connected togheter and driven by just one control signal
INTERLOCKING
INTERLOCKING
G
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
Typical application diagram L6392
14/20 Doc ID 14494 Rev 5
7 Typical application diagram
Figure 6. Application diagram
UV
DETECTION
LEVEL
SHIFTER
BOOTSTRAP DRIVER
S
V
CC
LVG
DRIVER
V
CC
HIN
LIN
HVG
DRIVER
HVG
H.V.
TO LOAD
OUT
LVG
BOOT
Cboot
UV
DETECTION
OP+
OP-
GND
OPOUT
SD
DT
OPAMP
DEAD
TIME
R
LOGIC
SHOOT
THROUGH
PREVENTION
FLOATING STRUCTURE
+
-
SD
LATCH
3
2
13
14
7
5
6
1
4
12
8
10
9
from LVG
5V
L6392 Bootstrap driver
Doc ID 14494 Rev 5 15/20
8 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 7 a). In the L6392 a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with diode in series, as shown in
Figure 7 b.
An internal charge pump (Figure 7 b) provides the DMOS driving voltage.
8.1 CBOOT selection and charging
To choose the proper C
BOOT
value the external MOS can be seen as an equivalent
capacitor. This capacitor C
EXT
is related to the MOS total gate charge:
The ratio between the capacitors C
EXT
and C
BOOT
is proportional to the cyclical voltage loss.
It has to be:
CBOOT >>> CEXT
e.g.: if Q
gate
is 30 nC and V
gate
is 10 V, C
EXT
is 3 nF. With C
BOOT
= 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the C
BOOT
selection has to take into account also
the leakage and quiescent losses.
e.g.: HVG steady state consumption is lower than 200 μA, so if HVG T
ON
is 5 ms, C
BOOT
has
to supply 1 μC to C
EXT
. This charge on a 1μF capacitor means a voltage drop of 1 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if V
OUT
is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (T
charge
) of the C
BOOT
is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS R
DSON
(typical value:
120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
where Q
gate
is the gate charge of the external power MOS, R
dson
is the on resistance of the
bootstrap DMOS, and T
charge
is the charging time of the bootstrap capacitor.
CEXT
Qgate
Vgate
--------------=
Vdrop Ich earg Rdson Vdrop
→Qgate
Tch earg
------------------ Rdson
==
Bootstrap driver L6392
16/20 Doc ID 14494 Rev 5
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the T
charge
is 5 μs. In fact:
V
drop
has to be taken into account when the voltage drop on C
BOOT
is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 7. Bootstrap driver
Vdrop
30nC
5μs
---------------120Ω0.7V∼⋅=
TO LOAD
D99IN1067
H.V.
HVG
ab
LVG
HVG
LVG
C
BOOT
TO LOA
D
H.V.
C
BOOT
DBOOT
BOOTVSVS
VOUT
BOOT
VOUT
L6392 Package mechanical data
Doc ID 14494 Rev 5 17/20
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 8. DIP-14 mechanical data and package dimensions
DIP14
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 1.39 1.65 0.055 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 15.24 0.600
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 2.54 0.050 0.100
OUTLINE AND
MECHANICAL DATA
Package mechanical data L6392
18/20 Doc ID 14494 Rev 5
Figure 9. SO-14 mechanical data and package dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.35 1.75 0.053 0.069
A1 0.10 0.30 0.004 0.012
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.01
D (1) 8.55 8.75 0.337 0.344
E 3.80 4.0 0.150 0.157
e 1.27 0.050
H 5.8 6.20 0.228 0.244
h 0.25 0.50 0.01 0.02
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO14
0016019 D
L6392 Revision history
Doc ID 14494 Rev 5 19/20
10 Revision history
Table 10. Document revision history
Date Revision Changes
29-Feb-2008 1 Initial release
18-Mar-2008 2 Cover page updated
17-Sep-2008 3 Updated Table 4 on page 6, Table 4 on page 6, Table 9 on page 12
17-Feb-2009 4 Updated Table 7 on page 8, Table 8 on page 10, Table 9 on page 12
Added Table 4 on page 9
11-Aug-2010 5 Updated cover page, Table 1 on page 1, Table 7 on page 8, Ta bl e 9
on page 12
L6392
20/20 Doc ID 14494 Rev 5
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