LP38859T-0.8 - National Semiconductor

LP38859

LP38859 3A Fast-Response High-Accuracy LDO Linear Regulator with Soft-Start

Literature Number: SNVS337D

LP38859

October 25, 2011

3A Fast-Response High-Accuracy LDO Linear Regulator

with Soft-Start

General Description

The LP38859 is a high current, fast response regulator which

can maintain output voltage regulation with extremely low in-

put to output voltage drop. Fabricated on a CMOS process,

the device operates from two input voltages: VBIAS provides

voltage to drive the gate of the N-MOS power transistor, while

VIN is the input voltage which supplies power to the load. The

use of an external bias rail allows the part to operate from ultra

low VIN voltages. Unlike bipolar regulators, the CMOS archi-

tecture consumes extremely low quiescent current at any

output load current. The use of an N-MOS power transistor

results in wide bandwidth, yet minimum external capacitance

is required to maintain loop stability.

The fast transient response of this device makes it suitable

for use in powering DSP, Microcontroller Core voltages and

Switch Mode Power Supply post regulators. The LP38859 is

available in TO-220 and TO-263 5-Lead packages.

Dropout Voltage: 240 mV (typical) at 3A load current.

Low Ground Pin Current: 10 mA (typical) at 3A load current.

Soft-Start: Programmable Soft-Start time.

Precision Output Voltage: ±1.0% for TJ = 25°C and ±2.0%

for 0°C ≤ TJ ≤ +125°C, across all line and load conditions

Features

■Standard VOUT values of 0.8V and 1.2V

■Wide VBIAS Supply operating range of 3.0V to 5.5V

■Stable with 10µF Ceramic capacitors

■Dropout voltage of 240 mV (typical) at 3A load current

■Precision Output Voltage across all line and load

conditions:

—±1.0% VOUT for TJ = 25°C

—±2.0% VOUT for 0°C ≤ TJ ≤ +125°C

—±3.0% VOUT for -40°C ≤ TJ ≤ +125°C

■Over-Temperature and Over-Current protection

■Available in 5 lead TO-220 and TO-263 packages

■Custom VOUT values between 0.8V and 1.2V are available

■−40°C to +125°C Operating Temperature Range

Applications

■ASIC Power Supplies In:

- Desktops, Notebooks, and Graphics Cards, Servers

- Gaming Set Top Boxes, Printers and Copiers

■Server Core and I/O Supplies

■DSP and FPGA Power Supplies

■SMPS Post-Regulator

Typical Application Circuit

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LP38859 3A Fast-Response High-Accuracy LDO Linear Regulator with Soft-Start

Ordering Information

VOUT * Order Number Package Type Package Drawing Supplied As

0.8V

LP38859S-0.8 TO263-5 TS5B Rail of 45

LP38859SX-0.8 TO263-5 TS5B Tape and Reel of 500

LP38859T-0.8 TO220-5 T05D Rail of 45

1.2V

LP38859S-1.2 TO263-5 TS5B Rail of 45

LP38859SX-1.2 TO263-5 TS5B Tape and Reel of 500

LP38859T-1.2 TO220-5 T05D Rail of 45

* For custom VOUT values between 0.8V and 1.2V please contact the National Semiconductor Sales Office.

Connection Diagrams

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TO263–5, Top View

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TO220–5, Top View

Pin Descriptions

TO220–5 and TO263–5 Packages

Pin # Pin Symbol Pin Description

1 SS Soft-Start capacitor connection. Used to slow the rise time of VOUT at turn-on.

2 IN The unregulated voltage input pin.

3 GND Ground

4 OUT The regulated output voltage pin.

5 BIAS The supply for the internal control and reference circuitry.

TAB TAB

The TAB is a thermal connection that is physically attached to the backside of

the die, and used as a thermal heat-sink connection. See the Application

Information section for details.

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LP38859

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C

Lead Temperature

Soldering, 5 seconds 260°C

ESD Rating

Human Body Model (Note 2) ±2 kV

Power Dissipation (Note 3) Internally Limited

VIN Supply Voltage (Survival) −0.3V to +6.0V

VBIAS Supply Voltage (Survival) −0.3V to +6.0V

VSS SoftStart Voltage (Survival) −0.3V to +6.0V

VOUT Voltage (Survival) −0.3V to +6.0V

IOUT Current (Survival) Internally Limited

Junction Temperature −40°C to +150°C

Operating Ratings (Note 1)

VIN Supply Voltage (VOUT + VDO) to VBIAS

VBIAS Supply Voltage 3.0V to 5.5V

IOUT 0 mA to 3.0A

Junction Temperature Range

(Note 3)

−40°C to +125°C

Electrical Characteristics Unless otherwise specified: VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN =

COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the

junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical

correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.

Symbol Parameter Conditions MIN TYP MAX Units

VOUT VOUT Accuracy

VOUT(NOM) + 1V ≤ VIN ≤ VBIAS,

3.0V ≤ VBIAS ≤ 5.5V,

10 mA ≤ IOUT ≤ 3A

-1.0

-3.0 0.0 1.0

3.0

VOUT(NOM) + 1V ≤ VIN ≤ VBIAS,

3.0V ≤ VBIAS ≤ 5.5V,

10 mA ≤ IOUT ≤ 3.0A,

0°C ≤ TJ ≤ +125°C

-2.0 0.0 2.0

ΔVOUT/ΔVIN

Line Regulation, VIN

(Note 4)VOUT(NOM) + 1V ≤ VIN ≤ VBIAS - 0.04 - %/V

ΔVOUT/ΔVBIAS

Line Regulation, VBIAS

(Note 4)3.0V ≤ VBIAS ≤ 5.5V - 0.10 - %/V

ΔVOUT/ΔIOUT

Output Voltage Load Regulation

(Note 5)10 mA ≤ IOUT ≤ 3.0A - 0.2 - %/A

VDO Dropout Voltage (Note 6)IOUT = 3.0A - 240 300

450 mV

IGND(IN)

Quiescent Current Drawn from

VIN Supply

LP38859-0.8

10 mA ≤ IOUT ≤ 3.0A - 7.0 8.5

9.0 mA

LP38859-1.2

10 mA ≤ IOUT ≤ 3.0A 11 12

IGND(BIAS)

Quiescent Current Drawn from

VBIAS Supply 10 mA ≤ IOUT ≤ 3.0A - 3.0 3.8

4.5 mA

UVLO Under-Voltage Lock-Out

Threshold

VBIAS rising until device is

functional

2.20

2.00 2.45 2.70

2.90 V

UVLO(HYS)

Under-Voltage Lock-Out

Hysteresis

VBIAS falling from UVLO threshold

until device is non-functional

50 150 300

350 mV

ISC Output Short-Circuit Current VIN = VOUT(NOM) + 1V,

VBIAS = 3.0V, VOUT = 0.0V - 6.2 - A

Soft-Start

rSS Soft-Start internal resistance LP38859-0.8 11.0 13.5 16.0 kΩ

LP38859-1.2 13.5 16.0 18.5

tSS

Soft-Start time

tSS = CSS × rSS × 5

LP38859-0.8, CSS = 10 nF - 675 - μs

LP38859-1.2, CSS = 10 nF - 800 -

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LP38859

Symbol Parameter Conditions MIN TYP MAX Units

AC Parameters

PSRR

(VIN)

Ripple Rejection for VIN Input

Voltage

VIN = VOUT(NOM) + 1V,

f = 120 Hz - 80 -

VIN = VOUT(NOM) + 1V,

f = 1 kHz - 65 -

PSRR

(VBIAS)Ripple Rejection for VBIAS Voltage

VBIAS = VOUT(NOM) + 3V,

f = 120 Hz - 58 -

VBIAS = VOUT(NOM) + 3V,

f = 1 kHz - 58 -

Output Noise Density f = 120 Hz - 1 - µV/√Hz

Output Noise Voltage

VOUT = 1.8V

BW = 10 Hz − 100 kHz - 150 - µV (rms)

BW = 300 Hz − 300 kHz - 90 -

Thermal Parameters

TSD

Thermal Shutdown Junction

Temperature - 160 - °C

TSD(HYS) Thermal Shutdown Hysteresis - 10 -

θJ-A

Thermal Resistance, Junction to

Ambient(Note 3)

TO220-5 - 60 -

°C/W

TO263-5 - 60 -

θJ-C

Thermal Resistance, Junction to

Case(Note 3)

TO220-5 - 3 -

TO263-5 - 3 -

Note 1: Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the

device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical

Characteristics.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22-A114. The HBM rating for

device pin 1 (SS) is ±1.5 kV.

Note 3: Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to ambient thermal

resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See

the Application Information section for details.

Note 4: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 5: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load.

Note 6: Dropout voltage is defined the as input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to

drop no more than 2% from the nominal value.

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LP38859

Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V,

VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = open.

VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS

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VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature

20131261

VIN Ground Pin Current vs Temperature

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Load Regulation vs Temperature

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Dropout Voltage (VDO) vs Temperature

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Output Current Limit (ISC) vs Temperature

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LP38859

VOUT vs Temperature

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UVLO Thresholds vs Temperature

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Soft-Start Resistor (rSS) vs Temperature

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Soft-Start rSS Variation vs Temperature

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VOUT vs CSS, 10 nF to 47 nF

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VIN Line Transient Response

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LP38859

VIN Line Transient Response

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VBIAS Line Transient Response

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VBIAS Line Transient Response

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Load Transient Response, COUT = 10 µF Ceramic

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Load Transient Response, COUT = 10 µF Ceramic

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Load Transient Response, COUT = 100 µF Ceramic

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LP38859

Load Transient Response, COUT = 100 µF Ceramic

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Load Transient Response, COUT = 100 µF Tantalum

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Load Transient Response, COUT = 100 µF Tantalum

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VBIAS PSRR

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VIN PSRR

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Output Noise

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LP38859

Block Diagram

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LP38859

Application Information

EXTERNAL CAPACITORS

To assure regulator stability, input and output capacitors are

required as shown in the Typical Application Circuit.

Output Capacitor

A minimum output capacitance of 10 µF, ceramic, is required

for stability. The amount of output capacitance can be in-

creased without limit. The output capacitor must be located

less than 1 cm from the output pin of the IC and returned to

the device ground pin with a clean analog ground.

Only high quality ceramic types such as X5R or X7R should

be used, as the Z5U and Y5F types do not provide sufficient

capacitance over temperature.

Tantalum capacitors will also provide stable operation across

the entire operating temperature range. However, the effects

of ESR may provide variations in the output voltage during

fast load transients. Using the minimum recommended 10 µF

ceramic capacitor at the output will allow unlimited capaci-

tance, Tantalum and/or Aluminum, to be added in parallel.

Input Capacitor

The input capacitor must be at least 10 µF, but can be in-

creased without limit. It's purpose is to provide a low source

impedance for the regulator input. A ceramic capacitor, X5R

or X7R, is recommended.

Tantalum capacitors may also be used at the input pin. There

is no specific ESR limitation on the input capacitor (the lower,

the better).

Aluminum electrolytic capacitors can be used, but are not

recommended as their ESR increases very quickly at cold

temperatures. They are not recommended for any application

where the ambient temperature falls below 0°C.

Bias Capacitor

The capacitor on the bias pin must be at least 1 µF, and can

be any good quality capacitor (ceramic is recommended).

INPUT VOLTAGE

The input voltage (VIN) is the high current external voltage rail

that will be regulated down to a lower voltage, which is applied

to the load. The input voltage must be at least VOUT + VDO,

and no higher than whatever values is used for VBIAS.

BIAS VOLTAGE

The bias voltage (VBIAS) is a low current external voltage rail

required to bias the control circuitry and provide gate drive for

the N-FET pass transistor. The bias voltage must be in the

range of 3.0V to 5.5V to ensure proper operation of the device.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the

device from functioning when the bias voltage is below the

Under-Voltage Lock-Out (UVLO) threshold of approximately

2.45V.

As the bias voltage rises above the UVLO threshold the de-

vice control circuitry becomes active. There is approximately

150 mV of hysteresis built into the UVLO threshold to provide

noise immunity.

When the bias voltage is between the UVLO threshold and

the Minimum Operating Rating value of 3.0V the device will

be functional, but the operating parameters will not be within

the guaranteed limits.

SUPPLY SEQUENCING

There is no requirement for the order that VIN or VBIAS are

applied or removed.

One practical limitation is that the Soft-Start circuit starts

charging CSS when VBIAS rises above the UVLO threshold. If

the application of VIN is delayed beyond this point the benefits

of Soft-Start will be compromised.

In any case, the output voltage cannot be guaranteed until

both VIN and VBIAS are within the range of guaranteed oper-

ating values.

If used in a dual-supply system where the regulator output

load is returned to a negative supply, the output pin must be

diode clamped to ground. A Schottky diode is recommended

for this diode clamp.

REVERSE VOLTAGE

A reverse voltage condition will exist when the voltage at the

output pin is higher than the voltage at the input pin. Typically

this will happen when VIN is abruptly taken low and COUT con-

tinues to hold a sufficient charge such that the input to output

voltage becomes reversed.

The NMOS pass element, by design, contains no body diode.

This means that, as long as the gate of the pass element is

not driven, there will not be any reverse current flow through

the pass element during a reverse voltage event. The gate of

the pass element is not driven when VBIAS is below the UVLO

threshold.

When VBIAS is above the UVLO threshold the control circuitry

is active and will attempt to regulate the output voltage. Since

the input voltage is less than the output voltage the control

circuit will drive the gate of the pass element to the full VBIAS

potential when the output voltage begins to fall. In this condi-

tion, reverse current will flow from the output pin to the input

pin , limited only by the RDS(ON) of the pass element and the

output to input voltage differential. This condition is outside

the guaranteed operating range and should be avoided.

SOFT-START

The LP38859 incorporates a Soft-Start function that reduces

the start-up current surge into the output capacitor (COUT) by

allowing VOUT to rise slowly to the final value. This is accom-

plished by controlling VREF at the SS pin. The soft-start timing

capacitor (CSS) is internally held to ground until VBIAS rises

above the Under-Voltage Lock-Out threshold (ULVO).

VREF will rise at an RC rate defined by the internal resistance

of the SS pin (rSS), and the external capacitor connected to

the SS pin. This allows the output voltage to rise in a con-

trolled manner until steady-state regulation is achieved. Typ-

ically, five time constants are recommended to assure that the

output voltage is sufficiently close to the final steady-state

value. During the soft-start time the output current can rise to

the built-in current limit.

Soft-Start Time = CSS × rSS × 5 (1)

Since the VOUT rise will be exponential, not linear, the in-rush

current will peak during the first time constant (τ), and VOUT

will require four additional time constants (4τ) to reach the final

value (5τ) .

After achieving normal operation, should VBIAS fall below the

ULVO threshold the device output will be disabled and the

Soft-Start capacitor (CSS) discharge circuit will become ac-

tive. The CSS discharge circuit will remain active until VBIAS

falls to 500 mV (typical). When VBIAS falls below 500 mV (typ-

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LP38859

ical), the CSS discharge circuit will cease to function due to a

lack of sufficient biasing to the control circuitry.

Since VREF appears on the SS pin, any leakage through CSS

will cause VREF to fall, and thus affect VOUT. A leakage of 50

nA (about 10 MΩ) through CSS will cause VOUT to be approx-

imately 0.1% lower than nominal, while a leakage of 500 nA

(about 1 MΩ) will cause VOUT to be approximately 1% lower

than nominal. Typical ceramic capacitors will have a factor of

10X difference in leakage between 25°C and 85°C, so the

maximum ambient temperature must be included in the ca-

pacitor selection process.

Typical CSS values will be in the range of 1 nF to 100 nF,

providing typical Soft-Start times in the range of 70 μs to 7 ms

(5τ). Values less than 1 nF can be used, but the Soft-Start

effect will be minimal. Values larger than 100 nF will provide

soft-start, but may not be fully discharged if VBIAS falls from

the UVLO threshold to less than 500 mV in less than 100 µs.

Figure 1 shows the relationship between the COUT value and

a typical CSS value.

20131223

FIGURE 1. Typical CSS vs COUT Values

The CSS capacitor must be connected to a clean ground path

back to the device ground pin. No components, other than

CSS, should be connected to the SS pin, as there could be

adverse effects to VOUT.

If the Soft-Start function is not needed the SS pin should be

left open, although some minimal capacitance value is always

recommended.

POWER DISSIPATION AND HEAT-SINKING

Additional copper area for heat-sinking may be required de-

pending on the maximum device dissipation (PD) and the

maximum anticipated ambient temperature (TA) for the de-

vice. Under all possible conditions, the junction temperature

must be within the range specified under operating condi-

tions.

The total power dissipation of the device is the sum of three

different points of dissipation in the device.

The first part is the power that is dissipated in the NMOS pass

element, and can be determined with the formula:

PD(PASS) = (VIN - VOUT) × IOUT (2)

The second part is the power that is dissipated in the bias and

control circuitry, and can be determined with the formula:

PD(BIAS) = VBIAS × IGND(BIAS) (3)

where IGND(BIAS) is the portion of the operating ground current

of the device that is related to VBIAS.

The third part is the power that is dissipated in portions of the

output stage circuitry, and can be determined with the formu-

la:

PD(IN) = VIN × IGND(IN) (4)

where IGND(IN) is the portion of the operating ground current

of the device that is related to VIN.

The total power dissipation is then:

PD = PD(PASS) + PD(BIAS) + PD(IN) (5)

The maximum allowable junction temperature rise (ΔTJ) de-

pends on the maximum anticipated ambient temperature

(TA) for the application, and the maximum allowable operating

junction temperature (TJ(MAX)) .

(6)

The maximum allowable value for junction to ambient Ther-

mal Resistance, θJA, can be calculated using the formula:

(7)

Heat-Sinking The TO-220 Package

The TO220-5 package has a θJA rating of 60°C/W and a θJC

rating of 3°C/W. These ratings are for the package only, no

additional heat-sinking, and with no airflow. If the needed

θJA, as calculated above, is greater than or equal to 60°C/W

then no additional heat-sinking is required since the package

can safely dissipate the heat and not exceed the operating

TJ(MAX). If the needed θJA is less than 60°C/W then additional

heat-sinking is needed.

The thermal resistance of a TO-220 package can be reduced

by attaching it to a heat sink or a copper plane on a PC board.

If a copper plane is to be used, the values of θJA will be same

as shown in next section for TO-263 package.

The heat-sink to be used in the application should have a

heat-sink to ambient thermal resistance, θHA:

(8)

where θJA is the required total thermal resistance from the

junction to the ambient air, θCH is the thermal resistance from

the case to the surface of the heart-sink, and θJC is the thermal

resistance from the junction to the surface of the case.

For this equation, θJC is about 3°C/W for a TO-220 package.

The value for θCH depends on method of attachment, insula-

tor, etc. θCH varies between 1.5°C/W to 2.5°C/W. Consult the

heat-sink manufacturer datasheet for details and recommen-

dations.

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LP38859

Heat-Sinking The TO-263 Package

The TO-263 package has a θJA rating of 60°C/W, and a θJC

rating of 3°C/W. These ratings are for the package only, no

additional heat-sinking, and with no airflow.

The TO-263 package uses the copper plane on the PCB as

a heat-sink. The tab of this package is soldered to the copper

plane for heat sinking. shows a curve for the θJA of TO-263

package for different copper area sizes, using a typical PCB

with 1 ounce copper and no solder mask over the copper area

for heat-sinking.

20131225

FIGURE 2. θJA vs Copper (1 Ounce) Area for the TO-263

package

Figure 2 shows that increasing the copper area beyond 1

square inch produces very little improvement. The minimum

value for θJA for the TO-263 package mounted to a PCB is

32°C/W.

Figure 3 shows the maximum allowable power dissipation for

TO-263 packages for different ambient temperatures, assum-

ing θJA is 35°C/W and the maximum junction temperature is

125°C.

20131226

FIGURE 3. Maximum power dissipation vs ambient

temperature for the TO-263 package

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LP38859

Physical Dimensions inches (millimeters) unless otherwise noted

TO-220 5-Lead, Stagger Bend Package (TO220-5)

NS Package Number TO5D

TO-263 5-Lead, Molded, Surface Mount Package (TO263-5)

NS Package Number TS5B

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LP38859

Notes

LP38859 3A Fast-Response High-Accuracy LDO Linear Regulator with Soft-Start

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Audio www.ti.com/audio Communications and Telecom www.ti.com/communications

Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers

Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps

DLP®Products www.dlp.com Energy and Lighting www.ti.com/energy

DSP dsp.ti.com Industrial www.ti.com/industrial

Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical

Interface interface.ti.com Security www.ti.com/security

Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265