KVR667D2D8F5/1GI - KINGSTON TECHNOLOGY

Memory Module Specifications

VALUERAM0522-001.A00 09/29/06 Page 1

This document describes ValueRAM's 1GB (128M x 72-bit) PC2-5300 CL5 SDRAM (Synchronous DRAM) "fully

buffered," ECC, dual rank, Intel® Validated memory module. This module is based on eighteen 64M x 8-bit 667MHz

DDR2 FBGA components. The module also includes an AMB device (Advanced Memory Buffer). The electrical

and mechanical specifications are as follows:

Description:

KVR667D2D8F5/1GI

1GB 128M x 72-Bit PC2-5300

CL5 ECC 240-Pin FBDIMM

·FBDIMM Module: 240-pin

·JEDEC Standard: R/C B

·Memory Organization: 2 rank of x8 devices

·DDR2 DRAM Interface: SSTL_18

·DDR2 Speed Grade: 667 Mbps

·CAS Latency: 5-5-5

·Module Bandwidth: 5.3 GB/s

·DRAM: VDD = VDDQ = 1.8V

·AMB: VCC = VCCFBD = 1.5V

·EEPROM: VDDSPD = 3.3V (typical)

·Heat Spreader: Full DIMM Heat Spreader (FDHS)

·PCB Height: 30.35mm, double-side

·RoHS Compliant

Feature:

DDR2 240-pin FBDIMM Pinout:

Front

Side

Back

Side

Front

Side

Back

Side

Front

Side

Back

Side

Front

Side

Back

Side

1VDD 121 VDD 31 PN3 151 SN3 61 PN9 181 SN9 91 PS9 211 SS9

2VDD 122 VDD 32 PN3 152 SN3 62 VSS 182 VSS 92 VSS 212 VSS

3VDD 123 VDD 33 VSS 153 VSS 63 PN10 183 SN10 93 PS5 213 SS5

4VSS 124 VSS 34 PN4 154 SN4 64 PN10 184 SN10 94 PS5 214 SS5

5VDD 125 VDD 35 PN4 155 SN4 65 VSS 185 VSS 95 VSS 215 VSS

6VDD 126 VDD 36 VSS 156 VSS 66 PN11 186 SN11 96 PS6 216 SS6

7VDD 127 VDD 37 PN5 157 SN5 67 PN11 187 SN11 97 PS6 217 SS6

8VSS 128 VSS 38 PN5 158 SN5 68 VSS 188 VSS 98 VSS 218 VSS

9VCC 129 VCC 39 VSS 159 VSS KEY 99 PS7 219 SS7

10 VCC 130 VCC 40 PN13 160 SN13 69 VSS 189 VSS 100 PS7 220 SS7

11 VSS 131 VSS 41 PN13 161 SN13 70 PS0 190 SS0 101 VSS 221 VSS

12 VCC 132 VCC 42 VSS 162 VSS 71 PS0 191 SS0 102 PS8 222 SS8

13 VCC 133 VCC 43 VSS 163 VSS 72 VSS 192 VSS 103 PS8 223 SS8

14 VSS 134 VSS 44 RFU* 164 RFU* 73 PS1 193 SS1 104 VSS 224 VSS

15 VTT 135 VTT 45 RFU* 165 RFU* 74 PS1 194 SS1 105 RFU** 225 RFU**

16 VID1 136 VID0 46 VSS 166 VSS 75 VSS 195 VSS 106 RFU** 226 RFU**

17 RESET 137 DNU/M_Test 47 VSS 167 VSS 76 PS2 196 SS2 107 VSS 227 VSS

18 VSS 138 VSS 48 PN12 168 SN12 77 PS2 197 SS2 108 VDD 228 SCK

19 RFU** 139 RFU** 49 PN12 169 SN12 78 VSS 198 VSS 109 VDD 229 SCK

20 RFU** 140 RFU** 50 VSS 170 VSS 79 PS3 199 SS3 110 VSS 230 VSS

21 VSS 141 VSS 51 PN6 171 SN6 80 PS3 200 SS3 111 VDD 231 VDD

22 PN0 142 SN0 52 PN6 172 SN6 81 VSS 201 VSS 112 VDD 232 VDD

23 PN0 143 SN0 53 VSS 173 VSS 82 PS4 202 SS4 113 VDD 233 VDD

24 VSS 144 VSS 54 PN7 174 SN7 83 PS4 203 SS4 114 VSS 234 VSS

25 PN1 145 SN1 55 PN7 175 SN7 84 VSS 204 VSS 115 VDD 235 VDD

26 PN1 146 SN1 56 VSS 176 VSS 85 VSS 205 VSS 116 VDD 236 VDD

27 VSS 147 VSS 57 PN8 177 SN8 86 RFU* 206 RFU* 117 VTT 237 VTT

28 PN2 148 SN2 58 PN8 178 SN8 87 RFU* 207 RFU* 118 SA2 238 VDDSPD

29 PN2 149 SN2 59 VSS 179 VSS 88 VSS 208 VSS 119 SDA 239 SA0

30 VSS 150 VSS 60 PN9 180 SN9 89 VSS 209 VSS 120 SCL 240 SA1

90 PS9 210 SS9

RFU = Reserved Future Use.

* These pin positions are reserved for forwarded clocks to be used in future module implementations

** These pin positions are reserved for future architecture flexibility

1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN13,

PS9/PS9, SS9/SS9

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DIMM Connector Pin Description:

Pin Name Pin Description Count

SCK System Clock Input, positive line11

SCK System Clock Input, negative line11

PN[13:0] Primary Northbound Data, positive lines 14

PN[13:0] Primary Northbound Data, negative lines 14

PS[9:0] Primary Southbound Data, positive lines 10

PS[9:0] Primary Southbound Data, negative lines 10

SN[13:0] Secondary Northbound Data, positive lines 14

SN[13:0] Secondary Northbound Data, negative lines 14

SS[9:0] Secondary Southbound Data, positive lines 10

SS[9:0] Secondary Southbound Data, negative lines 10

SCL Serial Presence Detect (SPD) Clock Input 1

SDA SPD Data Input / Output 1

SA[2:0] SPD Address Inputs, also used to select the DIMM number in the AMB 3

VID[1:0] Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs

VID[0] is VDD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is V CC value: OPEN = 1.5 V, GND = 1.2 V 2

RESET AMB reset signal 1

RFU Reserved for Future Use216

VCC AMB Core Power and AMB Channel Interface Power (1.5 Volt) 8

VDD DRAM Power and AMB DRAM I/O Power (1.8 Volt) 24

VTT DRAM Address/Command/Clock Termination Power (V DD/2) 4

VDDSPD SPD Power 1

VSS Ground 80

DNU/M_Test

The DNU/M_Test pin provides an exter nal connection on R/Cs A-D for testing

the margin of Vref which is produced by a voltage divider on the module. It

is not intended to be used in normal system operation and must not be

connected (DNU) in a system. This test pin may have other features on future card designs

and if it does, will be included in this specification at that time.

Total 240

1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency

2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility

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Absolute Maximum Ratings

095°C

AMB device operating temperature (Ambient) 0110°C

Symbol Parameter MIN MAX Units

IN, VOUT

Voltage on any pin relative to V

-0.3 1.75 V

Voltage on V

pin relative to V

-0.3 1.75 V

Voltage V

pin relative to Vss -0.5 2.3 V

Voltage on V

pin relative to V

-0.5 2.3 V

STG

Storage temperature -55 100 °C

CASE

DDR2 SDRAM device operating temperature (Ambient)

Note: (1) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.

(1)

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Functional Block Diagram:

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DM/

DQS0

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Serial PD

A1 A2

SA0 SA1 SA2

SDA

SCL

DQS

RDQS NU/ DM/

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS0

RDQS RDQS

DQ12

DQ13

DQ14

DQ15

DQ8

DQ9

DQ10

DQ11

DM/

DQS1

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/ DM/

D10

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS1

RDQS RDQS

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DM/

DQS2

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/ DM/

D11

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS2

RDQS RDQS

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DM/

DQS3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/ DM/

D12

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS3

RDQS RDQS

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

DM/

DQS8

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/ DM/

D17

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS8

RDQS RDQS

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DM/

DQS4

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/ DM/

D13

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS4

RDQS RDQS

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DM/

DQS5

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/ DM/

D14

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS5

RDQS RDQS

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DM/

DQS6

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/ DM/

D15

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS6

RDQS RDQS

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DM/

DQS7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/ DM/

D16

CS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

RDQS NU/

DQS7

RDQS RDQS

Notes:

1. DQ-to-I/O wiring may be changed within a byte.

2. There are two physical copies of each

address/command/control/clock

VSS

D0-D17, AMB

D0-D17, SPD, AMB

D0-D17VREF

SPD, AMB

VDD

VDDSPD

AMB

VCC

VTT

All address/command/control/clock

VTT Terminators

DQS9

DQS10

DQS11

DQS12

DQS13

DQS14

DQS15

DQS16

DQS17

PN0-PN13

PS0-PS9

SS0-SS9

WE (all SDRAMs)

CK/CK (all SDRAMs)

BA0-BA2 (all SDRAMs)

A0-A15 (all SDRAMs)

RAS (all SDRAMs)

CAS (all SDRAMs)

SCL

SDA

SA1-SA2

ODT -> ODT (all SDRAMs)

RESET

SN0-SN13

CKE0 -> CKE (D0-D8)

S0 -> CS (D0-D8)

CKE1 -> CKE (D9-D17)

S1 -> CS (D9-D17)

SCK/SCK

SA0

825 22

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Architecture:

Advanced Memory Buffer Pin Description:

Pin Name Pin Description Count

FB-DIMM Channel Signals 99

SCK System Clock Input, positive line 1

SCK System Clock Input, negative line 1

PN[13:0] Primary Northbound Data, positive lines 14

PN[13:0] Primary Northbound Data, negative lines 14

PS[9:0] Primary Southbound Data, positive lines 10

PS[9:0] Primary Southbound Data, negative lines 10

SN[13:0] Secondary Northbound Data, positive lines 14

SN[13:0] Secondary Northbound Data, negative lines 14

SS[9:0] Secondary Southbound Data, positive lines 10

SS[9:0] Secondary Southbound Data, negative lines 10

FBDRES To an external precision calibration resistor connected to Vcc 1

DDR2 Interface Signals 175

DQS[8:0] Data Strobes, positive lines 9

DQS[8:0] Data Strobes, negative lines 9

DQS[17:9]/DM[8:0] Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes. 9

DQS[17:9] Data Strobes (x4 DRAM only), negative lines 9

DQ[63:0] Data 64

CB[7:0] Checkbits 8

A[15:0]A, A[15:0]B Addresses. A10 is part of the pre-charge command 32

BA[2:0]A, BA[2:0]B Bank Addresses 6

RASA, RASB Part of command, with CAS, WE, and CS[1:0]. 2

CASA, CASB Part of command, with RAS, WE, and CS[1:0]. 2

WEA, WEB Part of command, with RAS, CAS, and CS[1:0]. 2

ODTA, ODTB On-die Termination Enable 2

CKE[1:0]A, CKE[1:0]B Clock Enable (one per rank) 4

CS[1:0]A, CS[1:0]B Chip Select (one per rank) 4

CLK[3:0] CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be out-

put disabled when not in use. 4

CLK[3:0] Negative lines for CLK[3:0] 4

DDRC_C14 DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18. 1

DDRC_B18 DDR Compensation: Resistor connected to common return pin DDRC_C14 1

DDRC_C18 DDR Compensation: Resistor connected to common return pin DDRC_C14 1

DDRC_B12 DDR Compensation: Resistor connected to VSS 1

DDRC_C12 DDR Compensation: Resistor connected to VDD 1

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SPD Bus Interface Signals 5

SCL Serial Presence Detect (SPD) Clock Input 1

SDA SPD Data Input / Output 1

SA[2:0] SPD Address Inputs, also used to select the DIMM number in the AMB 3

Miscellaneous Signals 163

PLLTSTO PLL Clock Observability Output 1

VCCAPLL Analog VCC for the PLL. Tied with low pass filter to VCC. 1

VSSAPLL Analog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM. 1

TEST_pin# Leave floating on the DIMM 6

TESTLO_pin# Tie to ground on the DIMM25

BFUNC Tie to ground to set functionality as buffer on DIMM. 1

RESET AMB reset signal 1

NC No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power

islands. 129

RFU Reserved for Future Use 18

Power/Ground Signals 213

VCC AMB Core Power (1.5 Volt) 24

VCCFBD AMB Channel I/O Power (1.5 Volt) 8

VDD AMB DRAM I/O Power (1.8 Volt) 24

VDDSPD SPD Power (3.3 Volt) 1

VSS Ground 156

Total 655

1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency.

2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs: each pin should have a zero

ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production

DIMMs with a direct connection to ground.

Advanced Memory Buffer Pin Description:

VALUERAM0522-001.A00 Page 7

TECHNOLOGY

Package Dimensions:

TECHNOLOGY

AMB

Advanced Memory Buffer

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

FBGA DDR2

SDRAM

(Units = millimeters)

Units: inches (millimeters)

0.054 (1.37)

0.046 (1.17)

0.346 (8.8)

MAX with heat sink

Detail A

0.047 (1.19)

0.042 (1.06)

45°x 0.0071(0.18)