5 kV RMS/3.75 kV RMS, 600 Mbps,
Dual-Channel LVDS Isolators
Data Sheet
ADN4650/ADN4651/ADN4652
Rev. D Document Feedback
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FEATURES
5 kV rms/3.75 kV rms LVDS isolator
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Up to 600 Mbps switching with low jitter
4.5 ns maximum propagation delay
151 ps maximum peak-to-peak total jitter at 600 Mbps
100 ps maximum pulse skew
600 ps maximum part to part skew
2.5 V or 3.3 V supplies
−75 dBc power supply ripple rejection and glitch immunity
±8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN55022 Class B radiated emissions limits with
600 Mbps PRBS
Safety and regulatory approvals (20-lead SOIC package)
UL (pending): 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 424 V peak
Fail-safe output high for open, short, and terminated input
conditions (ADN4651/ADN4652)
Operating temperature range: −40°C to +125°C
Choice of package and isolation options
3.75 kV rms in highly integrated 20-lead SSOP
5 kV rms in 20-lead SOIC with 7.8 mm creepage/clearance
APPLICATIONS
Analog front-end (AFE) isolation
Data plane isolation
Isolated high speed clock and data links
Isolated serial peripheral interface (SPI) over LVDS
GENERAL DESCRIPTION
The ADN4650/ADN4651/ADN46521 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 600 Mbps with very low jitter.
The devices integrate Analog Devices, Inc., iCoupler® technology,
enhanced for high speed operation, to provide galvanic isolation of
the TIA/EIA-644-A compliant LVDS drivers and receivers. This
technology allows drop-in isolation of an LVDS signal chain.
Multiple channel configurations are offered, and the LVDS receivers
on the ADN4651/ADN4652 include a fail-safe mechanism to
FUNCTIONAL BLOCK DIAGRAMS
LVDS LVDS
GND1GND2
VDD1
VIN1 VIN2
DIN1+
DIN1–
DIN2–
DIN2+
VDD2
DOUT2+
DOUT2–
DOUT1–
DOUT1+
ADN4650
LDO LDO
DIGITAL ISOLATOR
ISOLATION
BARRIER
13677-101
Figure 1.
LVDS LVDS
GND
1
GND
2
V
DD1
V
IN1
V
IN2
D
IN1+
D
IN1–
D
OUT2–
D
OUT2+
V
DD2
D
IN2+
D
IN2–
D
OUT1–
D
OUT1+
ADN4651 LDO LDO
DIGITAL ISOLATOR
ISOLATION
BARRIER
13677-001
Figure 2.
LVDS LVDS
GND
1
GND
2
V
DD1
V
IN1
V
IN2
D
IN1+
D
IN1–
D
OUT2–
D
OUT2+
V
DD2
D
IN2+
D
IN2–
D
OUT1–
D
OUT1+
ADN4652
LDO LDO
DIGITAL ISOLATOR
ISOLATION
BARRIER
13677-103
Figure 3.
ensure a Logic 1 on the corresponding LVDS driver output
when the inputs are floating, shorted, or terminated, but not driven.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
regulator (LDO) can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and are available in a 20-lead, wide
body SOIC package with 5 kV rms isolation or a 20-lead SSOP
package with 3.75 kV rms isolation.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 2 of 25
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Receiver Input Threshold Test Voltages .................................... 4
Timing Specifications .................................................................. 4
Insulation and Safety Related Specifications ............................ 5
Package Characteristics ............................................................... 6
Regulatory Information ............................................................... 6
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics (Pending) ............................................................ 6
Recommended Operating Conditions ...................................... 7
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance .......................................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions ............................9
Typical Performance Characteristics ........................................... 12
Test Circuits and Switching Characteristics................................ 17
Theory of Operation ...................................................................... 18
Truth Table and Fail-Safe Receiver .......................................... 18
Isolation ....................................................................................... 19
PCB Layout ................................................................................. 19
Magnetic Field Immunity.......................................................... 19
Insulation Lifetime ..................................................................... 20
Applications Information .............................................................. 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
1/2017—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 24
9/2016—Rev. B to Rev. C
Added 20-Lead SSOP .................................................... Throughout
Changes to Title, Features Section, and General Description .... 1
Added Table 5; Renumbered Sequentially .................................... 5
Change to Figure 5 ........................................................................... 7
Changes to PCB Layout Section ................................................... 19
Changes to Surface Tracking Section ........................................... 20
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
4/2016—Rev. A to Rev. B
Added ADN4652 ................................................................ Universal
Changes to Features Section and General Description Section ...... 1
Added Figure 3; Renumbered Sequentially .................................. 1
Changes to Supply Current Parameter, Table 1 ............................ 3
Changes to Skew Parameter and Fail-Safe Delay Parameter,
Table 3 ................................................................................................ 4
Changes to Table 12 .......................................................................... 9
Moved Figure 7 ............................................................................... 10
Added Table 13 ................................................................................ 10
Added Figure 8 and Table 14, Renumbered Sequentially ......... 11
Changes to PCB Layout Section ................................................... 19
Changes to Ordering Guide .......................................................... 24
2/2016—Rev. 0 to Rev. A
Added ADN4650 ................................................................ Universal
Changes to Features Section and General Description Section ........ 1
Added Figure 1; Renumbered Sequentially ................................... 1
Changes to Supply Current Parameter, Table 1 ............................. 3
Changes to Skew Parameter and Fail-Safe Delay Parameter,
Table 3 ................................................................................................. 4
Added Figure 5................................................................................... 9
Changes to Table 12 ........................................................................... 9
Changes to Figure 30 Caption and Figure 31 Caption .............. 14
Change to Figure 34 ....................................................................... 15
Changes to Truth Table and Fail-Safe Receiver Section ............ 16
Added Table 13; Renumbered Sequentially ................................ 16
Change to Applications Information Section ............................. 20
Added Figure 41 ............................................................................. 20
Changes to Ordering Guide .......................................................... 22
11/2015—Revision 0: Initial Ver sion
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 3 of 25
SPECIFICATIONS
For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. For all typical
specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUTS (RECEIVERS)
Input Threshold See Figure 36 and Table 2
High VTH 100 mV
Low
VTL −100
mV
Differential Input Voltage |VID| 100 mV See Figure 36 and Table 2
Input Common-Mode Voltage VIC 0.5|VID| 2.4 − 0.5|VID| V See Figure 36 and Table 2
Input Current IIH, IIL −5 +5 µA DINx± = VDD or 0 V, other input = 1.2 V, VDD = 2.5 V or 0 V
Differential Input Capacitance1 CINx± 2 pF DINx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input = 1.2 V
OUTPUTS (DRIVERS)
Differential Output Voltage |VOD| 250 310 450 mV See Figure 34 and Figure 35, RL = 100 Ω
VOD Magnitude Change |ΔVOD| 50 mV See Figure 34 and Figure 35, RL = 100 Ω
Offset Voltage VOS 1.125 1.17 1.375 V See Figure 34, RL = 100 Ω
VOS Magnitude Change ΔVOS 50 mV See Figure 34, RL = 100 Ω
V
OS
Peak-to-Peak
1
V
OS(PP)
150
mV
See Figure 34, R
L
= 100 Ω
Output Short-Circuit Current IOS −20 mA DOUTx± = 0 V
12 mA |VOD| = 0 V
Differential Output
Capacitance1
COUTx± 5 pF DOUTx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V, VDD1 or VDD2 = 0 V
POWER SUPPLY
Supply Current IDD1, IIN1,
IDD2, or IIN2
ADN4651/ADN4652 Only
55
mA
No output load, inputs with 100 Ω, no applied |V
ID
|
58 80 mA All outputs loaded, RL = 100 Ω, f = 300 MHz
ADN4650 Only 50 65 mA No output load, inputs with 100 Ω, |VID| = 200 mV
60 72 mA All outputs loaded, RL = 100 Ω, f = 300 MHz
LDO Input Range VIN1 or
VIN2
3.0 3.3 3.6 V No external supply on VDD1 or VDD2
LDO Output Range VDD1 or
VDD2
2.375 2.5 2.625 V
Power Supply Ripple Rejection,
Phase Spur Level
PSRR −75 dBc Phase spur level on DOUTx± with 300 MHz clock on
DINx± and applied ripple of 100 kHz, 100 mV p-p on
a 2.5 V supply to VDD1 or VDD2
COMMON-MODE TRANSIENT
IMMUNITY2
|CM| 25 50 kV/µs VCM = 1000 V, transient magnitude = 800 V
1 These specifications are guaranteed by design and characterization.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx− pin in the same state as the corresponding DINx+/DINx−
pin (no change on output), or producing the expected transition on any DOUTx+/DOUTx− pin if the applied common-mode transient edge is coincident with a data
transition on the corresponding DINx+/DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 4 of 25
RECEIVER INPUT THRESHOLD TEST VOLTAGES
Table 2. Test Voltages for Receiver Operation
Applied Voltages
Input Voltage, Differential (VID) (V) Input Voltage, Common-Mode (VIC) (V) Driver Output (VOD) (mV) DINx+ (V) DINx− (V)
1.25 1.15 +0.1 1.2 >+250
1.15
1.25
−0.1
1.2
<−250
2.4 2.3 +0.1 2.35 >+250
2.3 2.4 −0.1 2.35 <−250
0.1
0
+0.1
0.05
>+250
0 0.1 −0.1 0.05 <−250
1.5
0.9
+0.6
1.2
>+250
0.9 1.5 −0.6 1.2 <−250
2.4 1.8 +0.6 2.1 >+250
1.8 2.4 −0.6 2.1 <−250
0.6 0 +0.6 0.3 >+250
0 0.6 −0.6 0.3 <−250
TIMING SPECIFICATIONS
For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. All typical specifications,
VDD1 = VDD2 = 2.5 V, T A = 25°C.
Table 3.
Parameter Symbol Min Typ Max1 Unit Test Conditions/Comments
PROPAGATION DELAY tPLH, tPHL 4 4.5 ns See Figure 37, from any DINx+/DINx− to DOUTx+/DOUTx−
SKEW See Figure 37, across all DOUTx+/DOUTx−
Duty Cycle
2
t
SK(D)
100
ps
Channel to Channel
3
t
SK(CH)
200
500
ps
150
300
ps
ADN4650 only
Part to Part
4
t
SK(PP)
600
ps
ADN4650, ADN4651, ADN4652, or combinations
500
ps
ADN4650 to ADN4650 only
JITTER5 See Figure 37, for any DOUTx+/DOUTx−
Random Jitter, RMS6 (1σ) tRJ(RMS) 2.6 4.8 ps rms 300 MHz clock input
Deterministic Jitter7, 8 tDJ(PP) 30 96 ps 600 Mbps, 223 − 1 PRBS
With Crosstalk tDJC(PP) 30 ps 600 Mbps, 223 − 1 PRBS
Total Jitter at BER 1 × 10−12 tTJ(PP) 70 151 ps 300 MHz/600 Mbps, 223 − 1 PRBS9
Additive Phase Jitter tADDJ 387 fs rms 100 Hz to 100 kHz, fOUT = 10 MHz10
376 fs rms 12 kHz to 20 MHz, fOUT = 300 MHz11
RISE/FALL TIME
t
R
, t
F
350
ps
See Figure 37, any D
OUTx+
/D
OUTx−
, 20% to 80%, R
L
= 100 Ω, C
L
= 5 pF
FAIL-SAFE DELAY12 tFSH, tFSL 1 1.2 µs ADN4651/ADN4652 only; see Figure 37 and Figure 4,
any DOUTx+/DOUTx−, RL = 100 Ω
MAXIMUM DATA RATE 600 Mbps
1 These specifications are guaranteed by design and characterization.
2 Duty cycle or pulse skew is the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, |tPHLx – tPHLx|.
3 Channel to channel or output skew is the difference between the largest and smallest values of tPLHx within a device or the difference between the largest and smallest
values of tPHLx within a device, whichever of the two is greater.
4 Part to part output skew is the difference between the largest and smallest values of tPLHx across multiple devices or the difference between the largest and smallest
values of tPHLx across multiple devices, whichever of the two is greater.
5 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. VID = 400 mV p-p, tR = tF = 0.3 ns (20% to 80%).
6 This specification is measured over a population of ~7,000,000 edges.
7 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK(D)).
8 This specification is measured over a population of ~3,000,000 edges.
9 Using the formula tTJ(PP) = 14 × tRJ(RMS) + tDJ(PP).
10 With input phase jitter of 250 fs rms subtracted.
11 With input phase jitter of 100 fs rms subtracted.
12 The fail-safe delay is the delay before DOUTx± is switched high to reflect idle input to DINx± (|VID| < 100 mV, open or short/terminated input condition).
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 5 of 25
Timing Diagram
>1.3V
1.2V
0V
0V
~1.3V
~1.0V
~ +0. 3V
~ –0.3V
<1.1V
(D
INx–
= 1.2V )
D
INx+
V
ID
D
OUTx+
D
OUTx–
V
OD
t
FSH
t
FSL
+0.1V
+0.1V +0.1V
–0.1V
13677-034
Figure 4. Fail-Safe Timing Diagram
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 4. 20-Lead SOIC Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage
5000
V rms
1-minute duration
Minimum External Air Gap (Clearance) L (I01) 7.8 mm min Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L (I02) 7.8 mm min Measured from input terminals to output terminals,
shortest distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB) 8.1 mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance) 17 µm min Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
Table 5. 20-Lead SSOP Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 3750 V rms 1-minute duration
Minimum External Air Gap (Clearance) L (I01) 5.3 mm min Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L (I02) 5.3 mm min Measured from input terminals to output terminals,
shortest distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB) 5.6 mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance) 22 µm min Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group
II
Material Group (DIN VDE 0110, 1/89, Table 1)
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 6 of 25
PACKAGE CHARACTERISTICS
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1 RI-O 1013 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance
2
C
I
3.7
pF
IC Junction to Ambient Thermal Resistance θJA Thermal simulation with 4-layer standard JEDEC PCB
20-Lead SOIC 45.7 °C/W
20-Lead SSOP 69.6 °C/W
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 12 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-
isolation waveforms and insulation levels.
Table 7.
UL (Pending) CSA (Pending) VDE (Pending)
To Be Recognized Under UL 1577
Component Recognition
Program1
To be approved under CSA
Component Acceptance Notice 5A
To be certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Single Protection, Isolation Voltage Reinforced insulation, VIORM = 424 V peak, VIOSM = 6000 V peak
20-lead SOIC, 5000 V rms
20-lead SSOP, 3750 V rms Basic insulation, VIORM = 424 V peak, VIOSM = 10,000 V peak
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage ≥ 6000 V rms (20-lead SOIC) or ≥4500 V rms (20-lead SSOP)
for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage ≥ 795 V peak for 1 sec (partial discharge
detection limit = 5 pC).
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of
the safety data.
Table 8.
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 600 V rms I to III
Climatic Classification 40/125/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum Working Insulation Voltage VIORM 424 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd (m) 795 V peak
Input to Output Test Voltage, Method A Vpd (m)
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
636 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
509 V peak
Highest Allowable Overvoltage VIOTM 5000 V peak
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 7 of 25
Description
Test Conditions/Comments
Symbol
Characteristic
Unit
Surge Isolation Voltage
Basic VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 10,000 V peak
Reinforced VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 6000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 5)
Maximum Junction Temperature TS 150 °C
Total Power Dissipation at 25°C
P
S
20-Lead SOIC 2.78 W
20-Lead SSOP 1.8 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
3.0
2.5
2.0
1.5
0.5
1.0
0
13677-002
020015010050
SAFE LIMITING POWER (W)
AMBI E NT TE M P E RATURE ( °C)
20-L E AD S SOP
20-L E AD S O IC
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 9.
Parameter Symbol Rating
Operating Temperature TA −40°C to +125°C
Supply Voltages
Supply to LDO VIN1, VIN2 3.0 V to 3.6 V
LDO Bypass, V
INx
Shorted to V
DDx
V
DD1
, V
DD2
2.375 V to 2.625 V
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 8 of 25
ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter Rating
VIN1 to GND1/VIN2 to GND2 −0.3 V to +6.5 V
V
DD1
to GND
1
/V
DD2
to GND
2
−0.3 V to +2.8 V
Input Voltage (DINx+, DINx−) to GNDx on
the Same Side
−0.3 V to VDD + 0.3 V
Output Voltage (DOUTx+, DOUTx−) to
GNDx on the Same Side
−0.3 V to VDD + 0.3 V
Short-Circuit Duration (DOUTx+, DOUTx−)
to GNDx on the Same Side
Continuous
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ Maximum) 150°C
Power Dissipation (TJ maximum − TA)/θJA
ESD
Human Body Model (All Pins to
Respective GNDx, 1.5 kΩ, 100 pF)
±4 kV
IEC 61000-4-2 (LVDS Pins to Isolated
GNDx Across Isolation Barrier)
20-Lead SOIC ±8 kV
20-Lead SSOP ±7 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 11. Thermal Resistance
Package Type θJA Unit
20-Lead SOIC 45.7 °C/W
20-lead SSOP 69.6 °C/W
ESD CAUTION
Table 12. Maximum Continuous Working Voltage1
Rating
Parameter 20-Lead SOIC 20-Lead SSOP Constraint
AC Voltage
Bipolar Waveform
Basic Insulation 495 V peak 424 V peak 50-year minimum insulation lifetime for 1% failure
Reinforced Insulation 495 V peak 424 V peak 50-year minimum insulation lifetime for 1% failure
Unipolar Waveform
Basic Insulation
990 V peak
848 V peak
50-year minimum insulation lifetime for 1% failure
Reinforced Insulation 875 V peak 620 V peak Lifetime limited by package creepage, maximum approved working voltage
DC Voltage
Basic Insulation 1079 V peak 754 V peak Lifetime limited by package creepage, maximum approved working voltage
Reinforced Insulation 536 V peak 380 V peak Lifetime limited by package creepage, maximum approved working voltage
1 The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for
more details.
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 9 of 25
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
IN1 1
GND
12
V
DD1 3
GND
14
20
19
18
17
D
IN1+ 5
D
IN1– 6
D
IN2+ 7
D
IN2– 8
V
DD1 912
GND
1
V
IN2
GND
2
V
DD2
GND
2
D
OUT1+
D
OUT1–
D
OUT2+
D
OUT2–
V
DD2
GND
2
10 11
16
15
14
13
ADN4650
TOP VIEW
(No t t o Scal e)
13677-104
Figure 6. ADN4650 Pin Configuration
Table 13. ADN4650 Pin Function Descriptions
Pin No. Mnemonic Description
1
V
IN1
Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass V
IN1
to GND
1
using a 1 μF capacitor. Alternatively, if using a
2.5 V supply, connect VIN1 directly to VDD1.
2, 4, 10 GND1 Ground, Side 1.
3, 9 VDD1 2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO.
5 DIN1+ Noninverted Differential Input 1.
6 DIN1− Inverted Differential Input 1.
7 DIN2+ Noninverted Differential Input 2.
8 DIN2− Inverted Differential Input 2.
11, 17, 19 GND2 Ground, Side 2.
12, 18
V
DD2
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND
2
with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 µF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO.
13 DOUT2− Inverted Differential Output 2.
14 DOUT2+ Noninverted Differential Output 2.
15 DOUT1− Inverted Differential Output 1.
16 DOUT1+ Noninverted Differential Output 1.
20 VIN2 Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using a
2.5 V supply, connect VIN2 directly to VDD2.
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 10 of 25
V
IN1 1
GND
12
V
DD1 3
GND
14
20
19
18
17
D
IN1+ 5
D
IN1– 6
D
OUT2+ 7
D
OUT2– 8
V
DD1 912
GND
1
V
IN2
GND
2
V
DD2
GND
2
D
OUT1+
D
OUT1–
D
IN2+
D
IN2–
V
DD2
GND
2
10 11
16
15
14
13
ADN4651
TOP VIEW
(No t t o Scal e)
13677-003
Figure 7. ADN4651 Pin Configuration
Table 14. ADN4651 Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN1 Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if using a
2.5 V supply, connect VIN1 directly to VDD1.
2, 4, 10 GND1 Ground, Side 1.
3, 9 VDD1 2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO.
5 DIN1+ Noninverted Differential Input 1.
6 DIN1− Inverted Differential Input 1.
7 DOUT2+ Noninverted Differential Output 2.
8 DOUT2− Inverted Differential Output 2.
11, 17, 19 GND2 Ground, Side 2.
12, 18 VDD2 2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO.
13 DIN2− Inverted Differential Input 2.
14 DIN2+ Noninverted Differential Input 2.
15 DOUT1− Inverted Differential Output 1.
16 DOUT1+ Noninverted Differential Output 1.
20 VIN2 Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using a 2.5
V supply, connect VIN2 directly to VDD2.
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 11 of 25
V
IN1 1
GND
12
V
DD1 3
GND
14
20
19
18
17
D
IN1+
5
D
IN1–
6
D
OUT2+
7
D
OUT2–
8
V
DD1 912
GND
1
V
IN2
GND
2
V
DD2
GND
2
D
OUT1+
D
OUT1–
D
IN2+
D
IN2–
V
DD2
GND
2
10 11
16
15
14
13
ADN4652
TOP VIEW
(No t t o Scal e)
13677-108
Figure 8. ADN4652 Pin Configuration
Table 15. ADN4652 Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN1 Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if using a 2.5
V supply, connect VIN1 directly to VDD1.
2, 4, 10 GND1 Ground, Side 1.
3, 9 VDD1 2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO.
5 DOUT1+ Noninverted Differential Output 1.
6 DOUT1− Inverted Differential Output 1.
7 DIN2+ Noninverted Differential Input 2.
8 DIN2− Inverted Differential Input 2.
11, 17, 19 GND2 Ground, Side 2.
12, 18 VDD2 2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO.
13 DOUT2− Inverted Differential Output 2.
14 DOUT2+ Noninverted Differential Output 2.
15 DIN1− Inverted Differential Input 1.
16 DIN1+ Noninverted Differential Input 1.
20 VIN2 Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using a 2.5
V supply, connect VIN2 directly to VDD2.
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 12 of 25
TYPICAL PERFORMANCE CHARACTERISTICS
VDD1 = VDD2 = 2.5 V, T A = 25°C, RL = 100 Ω, 300 MHz input with |VID| = 200 mV, and VIC = 1.1 V, unless otherwise noted.
70
0
10
20
30
40
50
60
050 100 150 200 250 300
SUPPLY CURRE NT (mA)
INPUT CL OCK F RE QUENCY ( M Hz )
IDD1
IDD2
IIN1
IIN2
13677-004
Figure 9. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN1± Input Clock Frequency
(DIN2± Not Switching)
70
0
10
20
30
40
50
60
050 100 150 200 250 300
SUPPLY CURRE NT (mA)
INPUT CL OCK F RE QUENCY ( M Hz )
IDD1
IDD2
IIN1
IIN2
13677-005
Figure 10. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN2± Input Clock Frequency
(DIN1± Not Switching)
70
0
10
20
30
40
50
60
–50 –25 025 50 75 100 125
SUPPLY CURRE NT (mA)
AMBI ENT T E M P E RATURE ( °C)
IDD1
IDD2
IIN1
IIN2
13677-006
Figure 11. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA)
(DIN1± with 300 MHz Clock Input, DIN2± Not Switching)
70
0
10
20
30
40
50
60
–50 –25 025 50 75 100 125
SUPPLY CURRE NT (mA)
AMBI ENT T E M P E RATURE ( °C)
I
DD1
I
DD2
I
IN1
I
IN2
13677-007
Figure 12. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA)
(DIN2± with 300 MHz Clock Input, DIN1± Not Switching)
70
0
10
20
30
40
50
60
2.35 2.40 2.45 2.50 2.55 2.60 2.65
SUPPLY CURRE NT (mA)
SUPPLY VOLTAGE, V
DD1
/V
DD2
(V)
I
DD1
(D
IN2
ACTI V E )
I
DD2
(D
IN2
ACTI V E )
I
DD1
(D
IN1
ACTI V E )
I
DD2
(D
IN1
ACTI V E )
13677-008
Figure 13. IDD1/IDD2 Supply Current vs. Supply Voltage, VDD1/VDD2
70
0
10
20
30
40
50
60
3.00 3.15 3.30 3.45 3.60
SUPPLY CURRE NT (mA)
SUPPLY VOLTAGE, V
IN1
/V
IN2
(V)
I
IN1
(D
IN2
ACTI V E )
I
IN2
(D
IN2
ACTI V E )
I
IN
1 (D
IN1
ACTI V E )
I
IN2
(D
IN1
ACTI V E )
13677-009
Figure 14. IIN1/IIN2 Supply Current vs. Supply Voltage, VIN1/VIN2
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 13 of 25
2.65
2.35
2.40
2.45
2.50
2.55
2.60
3.0 3.1 3.2 3.3 3.4 3.5 3.6
LDO OUTPUT VOLTAGE, V
DD1
/V
DD2
(V)
LDO INPUT VOLTAGE, V
IN1
/V
IN2
(V)
V
DD1
V
DD2
13677-010
Figure 15. LDO Output Voltage, VDD1/VDD2 vs. LDO Input Voltage, VIN1/VIN2
350
250
260
270
280
290
300
310
320
330
340
050 100 150 200 300250 350
DRIVER DIFFERENTIAL OUTPUT VOLTAGE, V
OD
(mV)
INP UT CLOCK F RE QUENCY ( M Hz )
V
OD
CHANNEL 1
V
OD
CHANNEL 2
13677-011
Figure 16. Driver Differential Output Voltage, VOD vs. Input Clock Frequency
450
0
50
100
150
200
250
300
350
400
50 12510075 150
DRIVER DIFFERENTIAL OUTPUT VOLTAGE, V
OD
(mV)
OUTPUT LOAD, R
L
(Ω)
13677-012
V
OD
CHANNEL 1
V
OD
CHANNEL 2
Figure 17. Driver Differential Output Voltage, VOD vs. Output Load, RL
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
2.35 2.652.602.55
2.50
2.452.40
DRIVER OUTPUT HIGH VOLTAGE, VOH (V)
SUPPLY VOLTAGE, VDD1/VDD2 (V)
13677-013
VOH CHANNEL 1
VOH CHANNEL 2
Figure 18. Driver Output High Voltage, VOH vs. Supply Voltage, VDD1/VDD2
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
2.35 2.652.602.55
2.502.452.40
DRIVER OUTPUT LOW VOLTAGE, VOL (V)
SUPPLY VOLTAGE, VDD1/VDD2 (V)
13677-014
VOL CHANNEL 1
VOL CHANNEL 2
Figure 19. Driver Output Low Voltage, VOL vs. Supply Voltage, VDD1/VDD2
1.375
1.325
1.275
1.225
1.175
1.125
2.35 2.652.602.552.502.45
2.40
DRIVER OUTPUT OFFSET VOLTAGE, VOS (V)
SUPPLY VOLTAGE, VDD1/VDD2 (V)
13677-015
VOS CHANNEL 1
VOS CHANNEL 2
Figure 20. Driver Output Offset Voltage, VOS vs. Supply Voltage, VDD1/VDD2
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 14 of 25
3.60
3.55
3.50
3.45
3.40
3.35
3.30
2.35 2.652.602.552.502.452.40
DIFFERENTIAL PROPAGATION DELAY (ns)
SUPPLY VOLTAGE, V
DD1
AND V
DD2
(V)
t
PHL
CHANNEL 2
t
PLH
CHANNEL 2
t
PHL
CHANNEL 1
t
PLH
CHANNEL 1
13677-017
Figure 21. Differential Propagation Delay vs. Supply Voltage, VDD1 and VDD2
4.0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
–50 125
75 100
5025
0–25
DIFFERENTIAL PROPAGATION DELAY (ns)
AMBI ENT T E M P E RATURE ( °C)
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
13677-018
Figure 22. Differential Propagation Delay vs. Ambient Temperature (TA)
3.60
3.55
3.50
3.45
3.40
3.35
3.30 01.4
1.0 1.20.80.60.40.2
DIFFERENTIAL PROPAGATION DELAY (ns)
DIFFERENTIAL INPUT VOLTAGE, VID (V)
tPHL CHANNEL 2
tPLH CHANNE L 2
tPHL CHANNEL 1
tPLH CHANNE L 1
13677-019
Figure 23. Differential Propagation Delay vs. Receiver Differential Input
Voltage, VID
3.60
3.55
3.50
3.45
3.40
3.35
3.30 02.52.01.51.00.5
DIFFERENTIAL PROPAGATION DELAY (ns)
RECEIVER INPUT OFFSET VOLTAGE, VIC (V)
tPHL CHANNEL 2
tPLH CHANNE L 2
tPHL CHANNEL 1
tPLH CHANNE L 1
13677-020
Figure 24. Differential Propagation Delay vs. Receiver Input Offset Voltage, VIC
240
220
200
180
160
140
120
2.35 2.652.602.552.502.452.40
DIFFERENTIAL OUTPUT TRANSITION TIME (ps)
SUPPLY VOLTAGE, V
DD1
/V
DD2
(V)
t
F
CHANNEL 2
t
R
CHANNEL 2
t
F
CHANNEL 1
t
R
CHANNEL 1
13677-021
Figure 25. Differential Output Transition Time vs. Supply Voltage, VDD1/VDD2
240
120
140
160
180
200
220
–50 12575 10050250–25
DIFFERENTIAL OUTPUT TRANSITION TIME (ps)
AMBI ENT T E M P E RATURE ( °C)
tF CHANNEL 2
tR CHANNEL 2
tF CHANNEL 1
tR CHANNEL 1
13677-022
Figure 26. Differential Output Transition Time vs. Ambient Temperature (TA)
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 15 of 25
30
0
5
10
15
20
25
2.35 2.652.60
2.55
2.502.452.40
DUTY CY CLE S KE W,
t
SK(D)
(p s)
SUPPLY VOLTAGE, V
DD1
AND V
DD2
(V)
t
SK(D)
CHANNEL 2
t
SK(D)
CHANNEL 1
13677-023
Figure 27. Duty Cycle Skew, tSK(D) vs. Supply Voltage, VDD1 and VDD2
30
0
5
10
15
20
25
–50 12575 1005025
0–25
DUTY CY CLE S KE W,
tSK(D)
(p s)
AMBI ENT T E M P E RATURE ( °C)
tSK(D)
CHANNEL 2
tSK(D)
CHANNEL 1
13677-024
Figure 28. Duty Cycle Skew, tSK(D) vs. Ambient Temperature (TA)
40
35
30
25
20
15
10
5
00600500400300200100
DETERMINISTIC JITTER,
tDJ(PP)
(p s)
DATA RATE (M bp s)
CHANNEL 1
CHANNEL 2
13677-025
Figure 29. Deterministic Jitter, tDJ(PP) vs. Data Rate
50
45
40
35
30
25
20
15
10
5
0
2.35 2.652.602.552.502.452.40
DETERMINISTIC JITTER,
t
DJ(PP)
(p s)
SUPPLY VOLTAGE, V
DD1
/V
DD2
(V)
CHANNEL 1
CHANNEL 2
13677-026
Figure 30. Deterministic Jitter, tDJ(PP) vs. Supply Voltage, VDD1/VDD2
60
50
40
30
20
10
0
–50 –25 025 50 75 100 125
DETERMINISTIC JITTER,
tDJ(PP)
(p s)
AMBI ENT T E M P E RATURE ( °C)
CHANNEL 1
CHANNEL 2
13677-027
Figure 31. Deterministic Jitter, tDJ(PP) vs. Ambient Temperature
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 17 of 25
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
RL/2
RL/2
DOUTx+
DOUTx–
VOS VOD
V
V
D
DINx+
DINx–
R
13677-030
Figure 34. Driver Test Circuit
3.75kΩ
3.75kΩ
NOTES
1. VTEST = 0V TO 2.4V
RL
DOUTx+
DOUTx–
VTEST
VOD
V
V
D
DINx+
DINx–
R
13677-031
Figure 35. Driver Test Circuit (Full Load Across Common-Mode Range)
NOTES
1. VID = VIN+ – VIN–
2. VIC = (VIN+ + VIN–)/2
3. VOD = VOUT+ – VOUT–
4. VOS = (VOUT+ + VOUT–)/2
DOUTx+
DOUTx–
DINx+
DINx–
DR VOD
VID
VOUT–
VIN–
VOUT+
VIN+
13677-032
Figure 36. Voltage Definitions
NOTES
1. C
L
INCL UDE S P ROBE AND JIG CAP ACITANCE .
R
L
C
L
C
L
D
OUTx+
DOUTx–
DINx+
DINx–
50Ω
SIGNAL
GENERATOR D
R
50Ω
13677-033
Figure 37. Timing Test Circuit
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 18 of 25
THEORY OF OPERATION
The ADN4650/ADN4651/ADN4652 are TIA/EIA-644-A LVDS
compliant isolated buffers. LVDS signals applied to the inputs are
transmitted on the outputs of the buffer, and galvanic isolation
is integrated between the two sides of the device. This integration
allows drop-in isolation of LVDS signal chains.
The LVDS receiver detects the differential voltage present
across a termination resistor on an LVDS input. An integrated
digital isolator transmits the input state across the isolation
barrier, and an LVDS driver outputs the same state as the input.
With a positive differential voltage of ≥100 mV across any DINx±
pin, the corresponding DOUTx+ pin sources current. This current
flows across the connected transmission line and termination at
the receiver at the far end of the bus, while DOUTx− sinks the
return current. With a negative differential voltage of ≤−100 mV
across any DINx± pin, the corresponding DOUTx+ pin sinks current,
with DOUTx− sourcing the current. Table 16 and Table 17 show
these input/output combinations.
The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.1 mA), developing between ±250 mV and ±450 mV
across a 100 Ω termination resistor (RT). The received voltage is
centered around 1.2 V. Note that because the differential voltage
(VID) reverses polarity, the peak-to-peak voltage swing across RT
is twice the differential voltage magnitude (|VID|).
TRUTH TABLE AND FAIL-SAFE RECEIVER
The LVDS standard, TIA/EIA-644-A, defines normal receiver
operation under two conditions: an input differential voltage
of ≥+100 mV corresponding to one logic state, and a voltage of
≤−100 mV for the other logic state. Between these thresholds,
standard LVDS receiver operation is undefined (it may detect
either state), as shown in Table 16 for the ADN4650. The
ADN4651/ADN4652 incorporate a fail-safe circuit to ensure
the LVDS outputs are in a known state (logic high) when the
input state is undefined (−100 mV < VID < +100 mV), as shown
in Table 17.
This input state can occur when the inputs are floating
(unconnected, no termination resistor), when the inputs are
shorted, and when there is no active driver connected to the
inputs (but with a termination resistor). Open-circuit, short-
circuit, and terminated/idle bus fail-safes, respectively, ensure a
known output state for these conditions, as implemented by the
ADN4651/ADN4652.
After the fail-safe circuit is triggered by these input states
(−100 mV < VID < +100 mV), there is a delay of up to 1.2 µs
before the output is guaranteed to be high (VOD ≥ 250 mV).
During this time, the output may transition to or stay in a logic
low state (VOD ≤ −250 mV).
The fail-safe circuit triggers as soon as the input differential
voltage remains between +100 mV and −100 mV for some
nanoseconds. This means that very slow rise and fall times on
the input signal, outside typical LVDS operation (350 ps maximum
tR/tF), can potentially trigger the fail-safe circuit on a high to low
crossover.
At the minimum |VID| of 100 mV for normal operation, the
rise/fall time must be ≤5 ns to avoid triggering a fail-safe state.
Increasing |VID| to 200 mV correspondingly allows an input
rise/fall time of up to 10 ns without triggering a fail-safe state.
For very low speed applications where slow high to low transitions
in excess of this limit are expected, using external biasing resistors
is an option to introduce a minimum |VID| of 100 mV (that is,
the fail-safe cannot trigger).
Table 16. ADN4650 Input/Output Operation
Input (DINx±) Output (DOUTx±)
Powered On VID (mV) Logic Powered On VOD (mV) Logic
Yes ≥100 High Yes ≥250 High
Yes ≤−100 Low Yes ≤−250 Low
Yes −100 < VID < +100 Indeterminate Yes Indeterminate Indeterminate
No Don’t care Don’t care Yes ≥250 High
Table 17. ADN4651/ADN4652 Input/Output Operation
Input (DINx±) Output (DOUTx±)
Powered On
V
ID
(mV)
Logic
Powered On
V
OD
(mV)
Logic
Yes ≥100 High Yes ≥250 High
Yes ≤−100 Low Yes ≤−250 Low
Yes −100 < VID < +100 Indeterminate Yes ≥250 High
No Don’t care Don’t care Yes ≥250 High
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 19 of 25
ISOLATION
In response to any change in the input state detected by the
integrated LVDS receiver, an encoder circuit sends narrow (~1 ns)
pulses to a decoder circuit using integrated transformer coils.
The decoder is bistable and is, therefore, either set or reset by
the pulses that indicate input transitions. The decoder state
determines the LVDS driver output state in normal operation,
and this in turn reflects the isolated LVDS buffer input state.
In the absence of input transitions for more than approximately
1 µs, a periodic set of refresh pulses, indicative of the correct input
state, ensures dc correctness at the output (including the fail-safe
output state, if applicable). These periodic refresh pulses also
correct the output state within 1 μs in the event of a fault condition
or set the ADN4651/ADN4652 output to the fail-safe state.
On power-up, the output state may initially be in the incorrect
dc state if there are no input transitions. The output state is
corrected within 1 µs by the refresh pulses.
If the decoder receives no internal pulses for more than
approximately 1 µs, the device assumes that the input side is
unpowered or nonfunctional, in which case, the output is set to
a positive differential voltage (logic high).
PCB LAYOUT
The ADN4650/ADN4651/ADN4652 can operate with high
speed LVDS signals up to 300 MHz clock, or 600 Mbps nonreturn
to zero (NRZ) data. With such high frequencies, it is particularly
important to apply best practices for the LVDS trace layout and
termination. Locate a 100 Ω termination resistor as close as
possible to the receiver, across the DINx+ and DINx− pins.
Controlled 50 Ω impedance traces are needed on LVDS signal
lines for full signal integrity, reduced system jitter, and minimizing
electromagnetic interference (EMI) from the PCB. Trace widths,
lateral distance within each pair, and distance to the ground plane
underneath all must be chosen appropriately. Via fencing to the
PCB ground between pairs is also a best practice to minimize
crosstalk between adjacent pairs.
The ADN4650/ADN4651/ADN4652 pass EN55022 Class B
emissions limits without extra considerations required for the
isolator when operating with up to 600 Mbps PRBS data. When
isolating high speed clocks (for example, 300 MHz), a reduced
PCB clearance (isolation gap) may be required with the 20-lead
SOIC models to reduce dipole antenna effects and provide
sufficient margin below Class B emissions limits. The 20-lead
SSOP models pass the Class B limits up to 150 MHz clock
frequencies with no extra PCB measures.
The best practice for high speed PCB design avoids any other emis-
sions from PCBs in applications that use the ADN4650/ADN4651/
ADN4652. Special care is recommended for off board connections,
where switching transients from high speed LVDS signals (and
clocks in particular) may conduct onto cabling, resulting in
radiated emissions. Use common-mode chokes, ferrites, or
other filters as appropriate at the LVDS connectors, as well as
cable shield or PCB ground connections to earth/chassis.
The ADN4650/ADN4651/ADN4652 require appropriate
decoupling of the VDDx pins with 100 nF capacitors. If the
integrated LDO is not used, and a 2.5 V supply is connected
directly, connect the appropriate VINx pin to the supply as well,
as shown in Figure 38, using the ADN4651 as an example.
1
2
3
4
20
19
18
17
516
615
714
813
9
V
DD2
12
10 11
100nF 100nF
100nF 100nF
V
DD1
V
IN2
V
DD2
V
DD1
100Ω
100Ω
GND
1
V
IN1
GND
1
GND
2
GND
1
GND
2
GND
2
D
IN1+
D
IN1–
D
IN2+
D
IN2–
D
OUT2–
D
OUT2+
D
OUT1–
D
OUT1+
ADN4651
TOP VI EW
(No t t o Scal e)
13677-035
Figure 38. Required PCB Layout When Not Using the LDO (2.5 V Supply)
1
2
3
4
20
19
18
17
516
615
714
813
9
V
DD2
12
10 11
100nF 100nF
100nF 100nF
V
DD1
V
IN2
V
DD2
V
DD1
100Ω
100Ω
GND
1
V
IN1
GND
1
GND
2
GND
1
GND
2
GND
2
D
IN1+
D
IN1–
D
IN2+
D
IN2–
D
OUT2–
D
OUT2+
D
OUT1–
D
OUT1+
ADN4651
TOP VI EW
(No t t o Scal e)
1µF1µF 1µF 1µF
13677-036
Figure 39. Required PCB Layout When Using the LDO (3.3 V Supply)
When the integrated LDO is used, bypass capacitors of 1 µF are
required on the VINx pins and on the nearest VDDx pins (LDO
output), as shown in Figure 39, using the ADN4651 as an
example.
MAGNETIC FIELD IMMUNITY
The limitation on the magnetic field immunity of the device
is set by the condition in which the induced voltage in the
transformer receiving coil is sufficiently large, either to falsely
set or reset the decoder. The following analysis defines such
conditions. The ADN4650/ADN4651/ADN4652 are examined
in a 2.375 V operating condition because it represents the most
susceptible mode of operation for this product.
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 20 of 25
The pulses at the transformer output have an amplitude greater
than 0.5 V. The decoder has a sensing threshold of about 0.25 V,
therefore establishing a 0.25 V margin in which induced voltages
are tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt)∑πrn2; n = 1, 2, …, N
where:
β is the magnetic flux density.
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADN4650/
ADN4651/ADN4652, and an imposed requirement that the
induced voltage be, at most, 50% of the 0.25 V margin at the
decoder, a maximum allowable magnetic field is calculated
as shown in Figure 40.
MAG NETI C FI E LD FRE QUENCY ( Hz )
1k
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSI TY ( kgau ss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
13677-037
Figure 40. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.92 kgauss induces a
voltage of 0.125 V at the receiving coil. This voltage is about
50% of the sensing threshold and does not cause a faulty output
transition. If such an event occurs with the worst case polarity
during a transmitted pulse, it reduces the received pulse from
>0.5 V to 0.375 V. This voltage is still higher than the 0.25 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADN4650/
ADN4651/ADN4652 transformers. Figure 41 expresses these
allowable current magnitudes as a function of frequency for
selected distances. The ADN4650/ADN4651/ADN4652 are
very insensitive to external fields. Only extremely large, high
frequency currents, very close to the component, can potentially
be a concern. For the 1 MHz example noted, a 2.29 kA current
must be placed 5 mm from the ADN4650/ADN4651/ADN4652
to affect component operation.
MAG NETI C FI E LD FRE QUENCY ( Hz )
10k
1k
100
MAXI MUM AL LO WABL E CURRE NT (kA)
0.01 1M
10
1k 10k 10M
0.1
1
100M
100k
DISTANCE = 1m
DISTANCE = 100mm
DISTANCE = 5mm
13677-038
Figure 41. Maximum Allowable Current for Various Current to
ADN4650/ADN4651/ADN4652 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Avoid PCB structures that form loops.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation as well as on
the materials and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation barrier, pollution degree, and material group. The
material group and creepage for ADN4650/ADN4651/ADN4652
are presented in Table 4 and Table 5.
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 21 of 25
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. It is the working voltage applicable
to tracking that is specified in most standards.
Testing and modeling show that the primary driver of long-term
degradation is displacement current in the polyimide insulation
causing incremental damage. The stress on the insulation can be
broken down into broad categories, such as dc stress, which causes
very little wear out because there is no displacement current,
and an ac component time varying voltage stress, which causes
wear out.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the isolation barrier, as shown in
Equation 1. Because only the ac portion of the stress causes
wear out, the equation can be rearranged to solve for the ac rms
voltage, as shown in Equation 2. For insulation wear out with the
polyimide materials used in this product, the ac rms voltage
determines the product lifetime.
22
DCRMSACRMS
VVV +=
(1)
or
22
DCRMSRMSAC
VVV −=
(2)
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance, and lifetime of a device, see Figure 42 and
the following equations.
The working voltage across the barrier from Equation 1 is
22
DCRMSACRMS
VVV +=
22 400
240 +=
RMS
V
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the creepage
required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
22
DCRMS
RMSAC
V
V
V−=
22 400466 −=
RMSAC
V
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for the working
voltage in Table 12 for the expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 50-year service life.
Note that the dc working voltage limit in Table 12 is set by the
creepage of the package as specified in IEC 60664-1. This value
can differ for specific system level standards.
ISOLATION VOLTAGE
TIME
V
AC RMS
V
RMS
V
DC
V
PEAK
13677-039
Figure 42. Critical Voltage Example
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 22 of 25
APPLICATIONS INFORMATION
High speed LVDS interfaces can be isolated using the ADN4650/
ADN4651/ADN4652 either between components, between boards,
or at a cable interface. The ADN4650/ADN4651/ADN4652 offer
full LVDS compliant inputs and outputs, allowing increased LVDS
output drive strength compared to built-in reduced specification
LVDS interfaces on other components. The LVDS compliant
receiver inputs on the ADN4650/ADN4651/ADN4652 also
ensure full compatibility with any LVDS source being isolated.
Isolated analog front-end applications provide an example of
the ADN4650/ADN4651 isolating an LVDS interface between
components. As shown in Figure 43, two ADN4650 components
isolate the LVDS interface of the AD7960 analog-to-digital
converter (ADC), including 600 Mbps data, a 300 MHz echoed
clock, and a 5 MHz sample clock. Isolation of the AD7960 using
two ADN4651 components is shown in Figure 44. The ADN4651
additive phase jitter is sufficiently low that it does not affect the
ADC performance even when isolating the sample clock. In
addition, implementing the galvanic isolation improves ADC
performance by removing digital and power supply noise from
the field-programmable gate array (FPGA) circuit.
Newer programmable logic controller (PLC) and input/output
modules communicate across an LVDS backplane, illustrating a
board to board LVDS interface, as shown in Figure 45. With a
daisy-chain type topology for transmit and receive to either
adjacent node, two ADN4651 (or ADN4652) devices on each
node can isolate four LVDS channels. The addition of galvanic
isolation allows a much more robust backplane interface port
on the PLC or input/output modules.
With galvanic isolation, even LVDS ports can be treated as full
external ports, and transmitted along cable runs (see Figure 46),
even in harsh environments where high common-mode
voltages may be induced on the cable. The low jitter of the
ADN4651/ADN4652 ensures that more of the jitter budget can
be used to account for the cable effects, allowing the cable to be
as long as possible. The ADN4651/ADN4652 offer a high drive
strength, fully LVDS compliant output, capable of driving short
cable runs of a few meters. This is in contrast to alternative
isolation methods that degrade the LVDS signal quality. The
data rate can be chosen as appropriate for the cable length; the
ADN4651/ADN4652 operate not only at 600 Mbps but also at
any arbitrary data rate down to dc.
ISOLATION
AD7960
ADN4650
ADN4650
CNV±
100Ω
DCO±
CLK±
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
D±
CNV±
DCO±
CLK±
D±
ISOLATION
FPGA/ASIC
13677-040
100Ω
Figure 43. Example Isolated Analog Front-End Implementation (Isolated AD7960 Using the ADN4650)
ISOLATION
AD7960
ADN4651
ADN4651
CNV±
100Ω
CLK±
DCO±
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
D±
CNV±
CLK±
DCO±
D±
ISOLATION
FPGA/ASIC
13677-040
Figure 44. Example Isolated Analog Front-End Implementation (Isolated AD7960 Using the ADN4651)
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 23 of 25
ADN4651
ISOLATION ISOLATION
ADN4651
ISOLATION
CONNECTOR
CONNECTOR
100Ω
100Ω 100Ω
100Ω 100Ω
100Ω 100Ω
100Ω 100Ω
100Ω 100Ω
100Ω
MCU 1 MCU 2 MCU 3
MO DULE 1 MO DULE 2 MO DULE 3
ADN4651
ISOLATION ISOLATION
ISOLATION
100Ω100Ω100Ω
100Ω100Ω100Ω
CONNECTOR
CONNECTOR
13677-041
Figure 45. Example Isolated Backplane Implementation for PLCs and Input/Output Modules Using the ADN4651
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
ADN4651 ADN4651
FPGA/
ASIC FPGA/
ASIC
ISOLATION
ISOLATION
CONNECTOR
CONNECTOR
SHIELDED
TWISTED PAIR
CABLE
13677-042
Figure 46. Example Isolated LVDS Cable Application Using the ADN4651
ADN4650/ADN4651/ADN4652 Data Sheet
Rev. D | Page 24 of 25
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
20 11
10
1
1.27
(0.0500)
BSC
06-07-2006-A
Figure 47. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDE C STANDARDS MO-150-AE
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
0.05 M I N
0.65 BSC
2.00 M AX
0.38
0.22
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
COPLANARITY
0.10
PKG-004600
06-01-2006-A
TOP VIEW
SIDE VIEW END VIEW
PIN 1
INDICATOR
SEATING
PLANE
Figure 48. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADN4650BRWZ −40°C to +125°C 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] RW-20
ADN4650BRWZ-RL7 −40°C to +125°C 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W]
RW-20
ADN4650BRSZ −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4650BRSZ-RL7
−40°C to +125°C
20-Lead Shrink Small Outline Package [SSOP]
RS-20
Data Sheet ADN4650/ADN4651/ADN4652
Rev. D | Page 25 of 25
Model
1
Temperature Range
Package Description
Package Option
ADN4651BRSZ −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4651BRSZ-RL7 −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4651BRWZ −40°C to +125°C 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] RW-20
ADN4651BRWZ-RL7 −40°C to +125°C 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] RW-20
ADN4652BRSZ −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4652BRSZ-RL7 −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADN4652BRWZ
−40°C to +125°C
20-Lead, Wide Body, Standard Small Outline Package [SOIC_W]
RW-20
ADN4652BRWZ-RL7 −40°C to +125°C 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] RW-20
EVAL-ADN4650EBZ ADN4650 SSOP Evaluation Board
EVAL-ADN4650EB1Z ADN4650 SOIC_W Evaluation Board
EVAL-ADN4651EBZ ADN4651 SSOP Evaluation Board
EVAL-ADN4651EB1Z ADN4651 SOIC_W Evaluation Board
EVAL-ADN4652EBZ ADN4651 SSOP Evaluation Board
EVAL-ADN4652EB1Z ADN4652 SOIC_W Evaluation Board
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D13677-0-1/17(D)
