5 kV RMS/3.75 kV RMS, 600 Mbps, Dual-Channel LVDS Isolators ADN4650/ADN4651/ADN4652 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS APPLICATIONS Analog front-end (AFE) isolation Data plane isolation Isolated high speed clock and data links Isolated serial peripheral interface (SPI) over LVDS VIN1 ADN4650 ISOLATION BARRIER LDO VDD2 DIN1+ DOUT1+ DIN1- DOUT1- LVDS DOUT2+ DIN2- DOUT2- Multiple channel configurations are offered, and the LVDS receivers on the ADN4651/ADN4652 include a fail-safe mechanism to 13677-101 DIN2+ GND2 GND1 Figure 1. VIN1 ADN4651 VIN2 ISOLATION BARRIER LDO LDO VDD1 VDD2 DIN1+ DOUT1+ DIN1- DOUT1- LVDS LVDS DIGITAL ISOLATOR DIN2+ DOUT2- DIN2- GND1 13677-001 DOUT2+ GND2 Figure 2. VIN1 ADN4652 LDO VIN2 ISOLATION BARRIER LDO VDD1 VDD2 DOUT1+ DIN1+ DIN1- DOUT1- LVDS DIGITAL ISOLATOR LVDS DIN2+ DOUT2+ DIN2- DOUT2- GND2 Figure 3. 1 The devices integrate Analog Devices, Inc., iCoupler(R) technology, enhanced for high speed operation, to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This technology allows drop-in isolation of an LVDS signal chain. LVDS DIGITAL ISOLATOR GND1 The ADN4650/ADN4651/ADN4652 are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 600 Mbps with very low jitter. LDO VDD1 GENERAL DESCRIPTION 1 VIN2 13677-103 5 kV rms/3.75 kV rms LVDS isolator Complies with TIA/EIA-644-A LVDS standard Multiple dual-channel configurations Up to 600 Mbps switching with low jitter 4.5 ns maximum propagation delay 151 ps maximum peak-to-peak total jitter at 600 Mbps 100 ps maximum pulse skew 600 ps maximum part to part skew 2.5 V or 3.3 V supplies -75 dBc power supply ripple rejection and glitch immunity 8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: >25 kV/s Passes EN55022 Class B radiated emissions limits with 600 Mbps PRBS Safety and regulatory approvals (20-lead SOIC package) UL (pending): 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 424 V peak Fail-safe output high for open, short, and terminated input conditions (ADN4651/ADN4652) Operating temperature range: -40C to +125C Choice of package and isolation options 3.75 kV rms in highly integrated 20-lead SSOP 5 kV rms in 20-lead SOIC with 7.8 mm creepage/clearance ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated, but not driven. For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout regulator (LDO) can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and are available in a 20-lead, wide body SOIC package with 5 kV rms isolation or a 20-lead SSOP package with 3.75 kV rms isolation. Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2015-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADN4650/ADN4651/ADN4652 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................8 Applications ....................................................................................... 1 ESD Caution...................................................................................8 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ............................9 Functional Block Diagrams ............................................................. 1 Typical Performance Characteristics ........................................... 12 Revision History ............................................................................... 2 Test Circuits and Switching Characteristics................................ 17 Specifications..................................................................................... 3 Theory of Operation ...................................................................... 18 Receiver Input Threshold Test Voltages .................................... 4 Truth Table and Fail-Safe Receiver .......................................... 18 Timing Specifications .................................................................. 4 Isolation ....................................................................................... 19 Insulation and Safety Related Specifications ............................ 5 PCB Layout ................................................................................. 19 Package Characteristics ............................................................... 6 Magnetic Field Immunity.......................................................... 19 Regulatory Information ............................................................... 6 Insulation Lifetime ..................................................................... 20 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics (Pending) ............................................................ 6 Applications Information .............................................................. 22 Recommended Operating Conditions ...................................... 7 Ordering Guide .......................................................................... 24 Absolute Maximum Ratings............................................................ 8 Outline Dimensions ....................................................................... 24 REVISION HISTORY 1/2017--Rev. C to Rev. D Changes to Ordering Guide .......................................................... 24 9/2016--Rev. B to Rev. C Added 20-Lead SSOP .................................................... Throughout Changes to Title, Features Section, and General Description .... 1 Added Table 5; Renumbered Sequentially .................................... 5 Change to Figure 5 ........................................................................... 7 Changes to PCB Layout Section ................................................... 19 Changes to Surface Tracking Section ........................................... 20 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 4/2016--Rev. A to Rev. B Added ADN4652 ................................................................ Universal Changes to Features Section and General Description Section ...... 1 Added Figure 3; Renumbered Sequentially .................................. 1 Changes to Supply Current Parameter, Table 1 ............................ 3 Changes to Skew Parameter and Fail-Safe Delay Parameter, Table 3 ................................................................................................ 4 Changes to Table 12 .......................................................................... 9 Moved Figure 7 ............................................................................... 10 Added Table 13................................................................................ 10 Added Figure 8 and Table 14, Renumbered Sequentially ......... 11 Changes to PCB Layout Section ................................................... 19 Changes to Ordering Guide .......................................................... 24 2/2016--Rev. 0 to Rev. A Added ADN4650 ................................................................ Universal Changes to Features Section and General Description Section........ 1 Added Figure 1; Renumbered Sequentially ...................................1 Changes to Supply Current Parameter, Table 1 .............................3 Changes to Skew Parameter and Fail-Safe Delay Parameter, Table 3 .................................................................................................4 Added Figure 5...................................................................................9 Changes to Table 12...........................................................................9 Changes to Figure 30 Caption and Figure 31 Caption .............. 14 Change to Figure 34 ....................................................................... 15 Changes to Truth Table and Fail-Safe Receiver Section ............ 16 Added Table 13; Renumbered Sequentially ................................ 16 Change to Applications Information Section ............................. 20 Added Figure 41 ............................................................................. 20 Changes to Ordering Guide .......................................................... 22 11/2015--Revision 0: Initial Version Rev. D | Page 2 of 25 Data Sheet ADN4650/ADN4651/ADN4652 SPECIFICATIONS For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. For all typical specifications, VDD1 = VDD2 = 2.5 V, TA = 25C. Table 1. Parameter INPUTS (RECEIVERS) Input Threshold High Low Symbol Min Typ 100 0.5|VID| -5 |VOD| |VOD| VOS VOS VOS(PP) IOS 250 310 1.125 1.17 Differential Output Capacitance1 POWER SUPPLY Supply Current COUTx 1 2 Test Conditions/Comments mV V A pF See Figure 36 and Table 2 See Figure 36 and Table 2 DINx = VDD or 0 V, other input = 1.2 V, VDD = 2.5 V or 0 V DINx = 0.4 sin(30 x 106t) V + 0.5 V, other input = 1.2 V 450 50 1.375 50 150 -20 12 mV mV V mV mV mA mA pF See Figure 34 and Figure 35, RL = 100 See Figure 34 and Figure 35, RL = 100 See Figure 34, RL = 100 See Figure 34, RL = 100 See Figure 34, RL = 100 DOUTx = 0 V |VOD| = 0 V DOUTx = 0.4 sin(30 x 106t) V + 0.5 V, other input = 1.2 V, VDD1 or VDD2 = 0 V 55 80 65 72 3.6 mA mA mA mA V No output load, inputs with 100 , no applied |VID| All outputs loaded, RL = 100 , f = 300 MHz No output load, inputs with 100 , |VID| = 200 mV All outputs loaded, RL = 100 , f = 300 MHz No external supply on VDD1 or VDD2 2.625 V 2 5 IDD1, IIN1, IDD2, or IIN2 VIN1 or VIN2 VDD1 or VDD2 PSRR 3.0 58 50 60 3.3 2.375 2.5 |CM| 25 ADN4650 Only COMMON-MODE TRANSIENT IMMUNITY 2 mV mV 2.4 - 0.5|VID| +5 ADN4651/ADN4652 Only Power Supply Ripple Rejection, Phase Spur Level 100 -100 |VID| VIC IIH, IIL CINx LDO Output Range Unit See Figure 36 and Table 2 VTH VTL Differential Input Voltage Input Common-Mode Voltage Input Current Differential Input Capacitance1 OUTPUTS (DRIVERS) Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change VOS Peak-to-Peak1 Output Short-Circuit Current LDO Input Range Max -75 dBc 50 kV/s Phase spur level on DOUTx with 300 MHz clock on DINx and applied ripple of 100 kHz, 100 mV p-p on a 2.5 V supply to VDD1 or VDD2 VCM = 1000 V, transient magnitude = 800 V These specifications are guaranteed by design and characterization. |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx- pin in the same state as the corresponding DINx+/DINx- pin (no change on output), or producing the expected transition on any DOUTx+/DOUTx- pin if the applied common-mode transient edge is coincident with a data transition on the corresponding DINx+/DINx- pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. D | Page 3 of 25 ADN4650/ADN4651/ADN4652 Data Sheet RECEIVER INPUT THRESHOLD TEST VOLTAGES Table 2. Test Voltages for Receiver Operation Applied Voltages DINx+ (V) DINx- (V) 1.25 1.15 1.15 1.25 2.4 2.3 2.3 2.4 0.1 0 0 0.1 1.5 0.9 0.9 1.5 2.4 1.8 1.8 2.4 0.6 0 0 0.6 Input Voltage, Differential (VID) (V) +0.1 -0.1 +0.1 -0.1 +0.1 -0.1 +0.6 -0.6 +0.6 -0.6 +0.6 -0.6 Input Voltage, Common-Mode (VIC) (V) 1.2 1.2 2.35 2.35 0.05 0.05 1.2 1.2 2.1 2.1 0.3 0.3 Driver Output (VOD) (mV) >+250 <-250 >+250 <-250 >+250 <-250 >+250 <-250 >+250 <-250 >+250 <-250 TIMING SPECIFICATIONS For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. All typical specifications, VDD1 = VDD2 = 2.5 V, TA = 25C. Table 3. Parameter PROPAGATION DELAY SKEW Duty Cycle 2 Channel to Channel 3 Part to Part 4 Symbol tPLH, tPHL tSK(D) tSK(CH) Typ 4 200 150 tSK(PP) JITTER 5 Random Jitter, RMS 6 (1) Deterministic Jitter 7, 8 With Crosstalk Total Jitter at BER 1 x 10-12 Additive Phase Jitter tRJ(RMS) tDJ(PP) tDJC(PP) tTJ(PP) tADDJ RISE/FALL TIME FAIL-SAFE DELAY 12 tR, tF tFSH, tFSL MAXIMUM DATA RATE Min 2.6 30 30 70 387 376 1 600 Max 1 4.5 Unit ns 100 500 300 600 500 ps ps ps ps ps 4.8 96 ps rms ps ps ps fs rms fs rms ps s 151 350 1.2 Test Conditions/Comments See Figure 37, from any DINx+/DINx- to DOUTx+/DOUTx- See Figure 37, across all DOUTx+/DOUTx- ADN4650 only ADN4650, ADN4651, ADN4652, or combinations ADN4650 to ADN4650 only See Figure 37, for any DOUTx+/DOUTx- 300 MHz clock input 600 Mbps, 223 - 1 PRBS 600 Mbps, 223 - 1 PRBS 300 MHz/600 Mbps, 223 - 1 PRBS9 100 Hz to 100 kHz, fOUT = 10 MHz 10 12 kHz to 20 MHz, fOUT = 300 MHz 11 See Figure 37, any DOUTx+/DOUTx-, 20% to 80%, RL = 100 , CL = 5 pF ADN4651/ADN4652 only; see Figure 37 and Figure 4, any DOUTx+/DOUTx-, RL = 100 Mbps These specifications are guaranteed by design and characterization. Duty cycle or pulse skew is the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, |tPHLx - tPHLx|. 3 Channel to channel or output skew is the difference between the largest and smallest values of tPLHx within a device or the difference between the largest and smallest values of tPHLx within a device, whichever of the two is greater. 4 Part to part output skew is the difference between the largest and smallest values of tPLHx across multiple devices or the difference between the largest and smallest values of tPHLx across multiple devices, whichever of the two is greater. 5 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. VID = 400 mV p-p, tR = tF = 0.3 ns (20% to 80%). 6 This specification is measured over a population of ~7,000,000 edges. 7 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK(D)). 8 This specification is measured over a population of ~3,000,000 edges. 9 Using the formula tTJ(PP) = 14 x tRJ(RMS) + tDJ(PP). 10 With input phase jitter of 250 fs rms subtracted. 11 With input phase jitter of 100 fs rms subtracted. 12 The fail-safe delay is the delay before DOUTx is switched high to reflect idle input to DINx (|VID| < 100 mV, open or short/terminated input condition). 1 2 Rev. D | Page 4 of 25 Data Sheet ADN4650/ADN4651/ADN4652 Timing Diagram >1.3V DINx+ 1.2V (DINx- = 1.2V) <1.1V +0.1V VID 0V -0.1V DOUTx+ ~1.3V DOUTx- ~1.0V ~ +0.3V +0.1V +0.1V VOD ~ -0.3V tFSH tFSL 13677-034 0V Figure 4. Fail-Safe Timing Diagram INSULATION AND SAFETY RELATED SPECIFICATIONS For additional information, see www.analog.com/icouplersafety. Table 4. 20-Lead SOIC Package Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L (I01) Value 5000 7.8 Unit V rms mm min Minimum External Tracking (Creepage) L (I02) 7.8 mm min Minimum Clearance in the Plane of the Printed Circuit Board (PCB Clearance) L (PCB) 8.1 mm min CTI 17 >400 II m min V Unit V rms mm min Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Table 5. 20-Lead SSOP Package Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L (I01) Value 3750 5.3 Minimum External Tracking (Creepage) L (I02) 5.3 mm min Minimum Clearance in the Plane of the Printed Circuit Board (PCB Clearance) L (PCB) 5.6 mm min CTI 22 >400 II m min V Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group Rev. D | Page 5 of 25 Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADN4650/ADN4651/ADN4652 Data Sheet PACKAGE CHARACTERISTICS Table 6. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 IC Junction to Ambient Thermal Resistance 20-Lead SOIC 20-Lead SSOP 1 2 Symbol RI-O CI-O CI JA Min Typ 1013 2.2 3.7 Max Unit pF pF Test Conditions/Comments f = 1 MHz Thermal simulation with 4-layer standard JEDEC PCB 45.7 69.6 C/W C/W The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION See Table 12 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels. Table 7. UL (Pending) To Be Recognized Under UL 1577 Component Recognition Program 1 Single Protection, Isolation Voltage 20-lead SOIC, 5000 V rms 20-lead SSOP, 3750 V rms File E214100 CSA (Pending) To be approved under CSA Component Acceptance Notice 5A VDE (Pending) To be certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, VIORM = 424 V peak, VIOSM = 6000 V peak Basic insulation, VIORM = 424 V peak, VIOSM = 10,000 V peak File 2471900-4880-0001 File 205078 In accordance with UL 1577, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage 6000 V rms (20-lead SOIC) or 4500 V rms (20-lead SSOP) for 1 sec. 2 In accordance with DIN V VDE V 0884-10, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage 795 V peak for 1 sec (partial discharge detection limit = 5 pC). 1 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS (PENDING) This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of the safety data. Table 8. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 600 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method B1 Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Test Conditions/Comments VIORM x 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC Symbol Characteristic Unit VIORM Vpd (m) I to IV I to IV I to III 40/125/21 2 424 795 V peak V peak 636 V peak 509 V peak 5000 V peak Vpd (m) VIORM x 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM x 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIOTM Rev. D | Page 6 of 25 Data Sheet ADN4650/ADN4651/ADN4652 Description Surge Isolation Voltage Basic Reinforced Safety Limiting Values Maximum Junction Temperature Total Power Dissipation at 25C 20-Lead SOIC 20-Lead SSOP Insulation Resistance at TS Test Conditions/Comments Symbol Characteristic Unit VPEAK = 12.8 kV, 1.2 s rise time, 50 s, 50% fall time VPEAK = 10 kV, 1.2 s rise time, 50 s, 50% fall time Maximum value allowed in the event of a failure (see Figure 5) VIOSM VIOSM 10,000 6000 V peak V peak TS PS 150 C 2.78 1.8 >109 W W VIO = 500 V RS RECOMMENDED OPERATING CONDITIONS 3.0 20-LEAD SOIC Table 9. SAFE LIMITING POWER (W) 2.5 2.0 Parameter Operating Temperature Supply Voltages Supply to LDO LDO Bypass, VINx Shorted to VDDx 20-LEAD SSOP 1.5 1.0 0 0 50 100 150 AMBIENT TEMPERATURE (C) 200 13677-002 0.5 Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 Rev. D | Page 7 of 25 Symbol TA Rating -40C to +125C VIN1, VIN2 VDD1, VDD2 3.0 V to 3.6 V 2.375 V to 2.625 V ADN4650/ADN4651/ADN4652 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 10. Parameter VIN1 to GND1/VIN2 to GND2 VDD1 to GND1/VDD2 to GND2 Input Voltage (DINx+, DINx-) to GNDx on the Same Side Output Voltage (DOUTx+, DOUTx-) to GNDx on the Same Side Short-Circuit Duration (DOUTx+, DOUTx-) to GNDx on the Same Side Operating Temperature Range Storage Temperature Range Junction Temperature (TJ Maximum) Power Dissipation ESD Human Body Model (All Pins to Respective GNDx, 1.5 k, 100 pF) IEC 61000-4-2 (LVDS Pins to Isolated GNDx Across Isolation Barrier) 20-Lead SOIC 20-Lead SSOP JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating -0.3 V to +6.5 V -0.3 V to +2.8 V -0.3 V to VDD + 0.3 V Table 11. Thermal Resistance Package Type 20-Lead SOIC 20-lead SSOP -0.3 V to VDD + 0.3 V JA 45.7 69.6 Unit C/W C/W Continuous -40C to +125C -65C to +150C 150C (TJ maximum - TA)/JA ESD CAUTION 4 kV 8 kV 7 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 12. Maximum Continuous Working Voltage1 Rating Parameter AC Voltage Bipolar Waveform Basic Insulation Reinforced Insulation Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation 1 20-Lead SOIC 20-Lead SSOP Constraint 495 V peak 495 V peak 424 V peak 424 V peak 50-year minimum insulation lifetime for 1% failure 50-year minimum insulation lifetime for 1% failure 990 V peak 875 V peak 848 V peak 620 V peak 50-year minimum insulation lifetime for 1% failure Lifetime limited by package creepage, maximum approved working voltage 1079 V peak 536 V peak 754 V peak 380 V peak Lifetime limited by package creepage, maximum approved working voltage Lifetime limited by package creepage, maximum approved working voltage The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Rev. D | Page 8 of 25 Data Sheet ADN4650/ADN4651/ADN4652 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VIN1 1 20 VIN2 GND1 2 19 GND2 VDD1 3 18 VDD2 GND1 4 17 GND2 ADN4650 DOUT1+ TOP VIEW (Not to Scale) 15 DOUT1- 14 DOUT2+ DIN1- 6 DIN2+ 7 16 DIN2- 8 13 DOUT2- VDD1 9 12 VDD2 GND1 10 11 GND2 13677-104 DIN1+ 5 Figure 6. ADN4650 Pin Configuration Table 13. ADN4650 Pin Function Descriptions Pin No. 1 Mnemonic VIN1 2, 4, 10 3, 9 GND1 VDD1 5 6 7 8 11, 17, 19 12, 18 DIN1+ DIN1- DIN2+ DIN2- GND2 VDD2 13 14 15 16 20 DOUT2- DOUT2+ DOUT1- DOUT1+ VIN2 Description Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 F capacitor. Alternatively, if using a 2.5 V supply, connect VIN1 directly to VDD1. Ground, Side 1. 2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 F capacitors. If supplying 3.3 V to VIN1, connect a 1 F capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the internal LDO. Noninverted Differential Input 1. Inverted Differential Input 1. Noninverted Differential Input 2. Inverted Differential Input 2. Ground, Side 2. 2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 F capacitors. If supplying 3.3 V to VIN2, connect a 1 F capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the internal LDO. Inverted Differential Output 2. Noninverted Differential Output 2. Inverted Differential Output 1. Noninverted Differential Output 1. Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 F capacitor. Alternatively, if using a 2.5 V supply, connect VIN2 directly to VDD2. Rev. D | Page 9 of 25 ADN4650/ADN4651/ADN4652 Data Sheet VIN1 1 20 VIN2 GND1 2 19 GND2 VDD1 3 18 VDD2 GND1 4 17 GND2 DIN1- 6 DOUT2+ 7 ADN4651 DOUT1+ TOP VIEW (Not to Scale) 15 DOUT1- 14 DIN2+ 16 DOUT2- 8 13 DIN2- VDD1 9 12 VDD2 GND1 10 11 GND2 13677-003 DIN1+ 5 Figure 7. ADN4651 Pin Configuration Table 14. ADN4651 Pin Function Descriptions Pin No. 1 Mnemonic VIN1 2, 4, 10 3, 9 GND1 VDD1 5 6 7 8 11, 17, 19 12, 18 DIN1+ DIN1- DOUT2+ DOUT2- GND2 VDD2 13 14 15 16 20 DIN2- DIN2+ DOUT1- DOUT1+ VIN2 Description Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 F capacitor. Alternatively, if using a 2.5 V supply, connect VIN1 directly to VDD1. Ground, Side 1. 2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 F capacitors. If supplying 3.3 V to VIN1, connect a 1 F capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the internal LDO. Noninverted Differential Input 1. Inverted Differential Input 1. Noninverted Differential Output 2. Inverted Differential Output 2. Ground, Side 2. 2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 F capacitors. If supplying 3.3 V to VIN2, connect a 1 F capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the internal LDO. Inverted Differential Input 2. Noninverted Differential Input 2. Inverted Differential Output 1. Noninverted Differential Output 1. Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 F capacitor. Alternatively, if using a 2.5 V supply, connect VIN2 directly to VDD2. Rev. D | Page 10 of 25 ADN4650/ADN4651/ADN4652 VIN1 1 20 VIN2 GND1 2 19 GND2 VDD1 3 18 VDD2 GND1 4 17 GND2 ADN4652 16 TOP VIEW (Not to Scale) DIN1+ 15 DIN1- DIN2+ 7 14 DOUT2+ DIN2- 8 13 DOUT2- VDD1 9 12 VDD2 GND1 10 11 GND2 DOUT1+ 5 DOUT1- 6 13677-108 Data Sheet Figure 8. ADN4652 Pin Configuration Table 15. ADN4652 Pin Function Descriptions Pin No. 1 Mnemonic VIN1 2, 4, 10 3, 9 GND1 VDD1 5 6 7 8 11, 17, 19 12, 18 DOUT1+ DOUT1- DIN2+ DIN2- GND2 VDD2 13 14 15 16 20 DOUT2- DOUT2+ DIN1- DIN1+ VIN2 Description Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 F capacitor. Alternatively, if using a 2.5 V supply, connect VIN1 directly to VDD1. Ground, Side 1. 2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 F capacitors. If supplying 3.3 V to VIN1, connect a 1 F capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the internal LDO. Noninverted Differential Output 1. Inverted Differential Output 1. Noninverted Differential Input 2. Inverted Differential Input 2. Ground, Side 2. 2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 F capacitors. If supplying 3.3 V to VIN2, connect a 1 F capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the internal LDO. Inverted Differential Output 2. Noninverted Differential Output 2. Inverted Differential Input 1. Noninverted Differential Input 1. Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 F capacitor. Alternatively, if using a 2.5 V supply, connect VIN2 directly to VDD2. Rev. D | Page 11 of 25 ADN4650/ADN4651/ADN4652 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 70 60 60 30 20 IDD1 IDD2 IIN1 IIN2 10 0 0 50 150 100 250 200 300 INPUT CLOCK FREQUENCY (MHz) 20 0 -50 60 60 SUPPLY CURRENT (mA) 70 50 40 30 20 IDD1 IDD2 IIN1 IIN2 0 0 50 100 150 200 250 300 INPUT CLOCK FREQUENCY (MHz) 0 2.35 30 20 75 AMBIENT TEMPERATURE (C) 100 125 2.40 2.45 2.50 (DIN2 ACTIVE) (DIN2 ACTIVE) (DIN1 ACTIVE) (DIN1 ACTIVE) 2.55 2.60 2.65 50 40 30 20 IIN1 (DIN2 ACTIVE) IIN2 (DIN2 ACTIVE) IIN1 (DIN1 ACTIVE) IIN2 (DIN1 ACTIVE) 10 13677-006 50 IDD1 IDD2 IDD1 IDD2 Figure 13. IDD1/IDD2 Supply Current vs. Supply Voltage, VDD1/VDD2 IDD1 IDD2 IIN1 IIN2 25 125 SUPPLY VOLTAGE, VDD1 /VDD2 (V) SUPPLY CURRENT (mA) 40 100 20 60 50 75 30 60 0 50 40 70 -25 25 50 70 0 -50 0 10 Figure 10. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN2 Input Clock Frequency (DIN1 Not Switching) 10 -25 Figure 12. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA) (DIN2 with 300 MHz Clock Input, DIN1 Not Switching) 70 10 IDD1 IDD2 IIN1 IIN2 AMBIENT TEMPERATURE (C) 13677-005 SUPPLY CURRENT (mA) 30 10 Figure 9. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN1 Input Clock Frequency (DIN2 Not Switching) SUPPLY CURRENT (mA) 40 13677-008 40 50 Figure 11. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA) (DIN1 with 300 MHz Clock Input, DIN2 Not Switching) Rev. D | Page 12 of 25 0 3.00 3.15 3.30 3.45 3.60 SUPPLY VOLTAGE, VIN1/VIN2 (V) Figure 14. IIN1/IIN2 Supply Current vs. Supply Voltage, VIN1/VIN2 13677-009 50 13677-007 SUPPLY CURRENT (mA) 70 13677-004 SUPPLY CURRENT (mA) VDD1 = VDD2 = 2.5 V, TA = 25C, RL = 100 , 300 MHz input with |VID| = 200 mV, and VIC = 1.1 V, unless otherwise noted. Data Sheet ADN4650/ADN4651/ADN4652 2.60 2.55 2.50 2.45 2.40 VDD1 VDD2 2.35 3.0 3.1 3.2 3.5 3.4 3.3 3.6 LDO INPUT VOLTAGE, VIN1/VIN2 (V) 1.45 1.40 1.35 1.30 VOH CHANNEL 1 VOH CHANNEL 2 2.40 2.45 2.50 2.55 2.60 2.65 SUPPLY VOLTAGE, VDD1 /VDD2 (V) Figure 18. Driver Output High Voltage, VOH vs. Supply Voltage, VDD1/VDD2 1.25 340 330 320 310 300 290 280 270 VOD CHANNEL 1 VOD CHANNEL 2 260 250 50 100 150 200 250 300 350 INPUT CLOCK FREQUENCY (MHz) 1.10 1.05 1.00 0.95 VOL CHANNEL 1 VOL CHANNEL 2 0.90 2.35 2.40 2.45 2.50 2.55 2.60 2.65 SUPPLY VOLTAGE, VDD1 /VDD2 (V) Figure 19. Driver Output Low Voltage, VOL vs. Supply Voltage, VDD1/VDD2 1.375 DRIVER OUTPUT OFFSET VOLTAGE, VOS (V) 450 400 350 300 250 200 150 100 50 VOD CHANNEL 1 VOD CHANNEL 2 75 100 OUTPUT LOAD, RL () 125 150 Figure 17. Driver Differential Output Voltage, VOD vs. Output Load, RL 1.325 1.275 1.225 1.175 VOS CHANNEL 1 VOS CHANNEL 2 1.125 2.35 13677-012 0 50 1.15 2.40 2.45 2.50 2.55 SUPPLY VOLTAGE, VDD1 /VDD2 (V) 2.60 2.65 13677-015 0 1.20 13677-014 DRIVER OUTPUT LOW VOLTAGE, VOL (V) 350 Figure 16. Driver Differential Output Voltage, VOD vs. Input Clock Frequency DRIVER DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV) 1.50 1.25 2.35 13677-011 DRIVER DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV) Figure 15. LDO Output Voltage, VDD1/VDD2 vs. LDO Input Voltage, VIN1/VIN2 1.55 13677-013 DRIVER OUTPUT HIGH VOLTAGE, VOH (V) 1.60 13677-010 LDO OUTPUT VOLTAGE, VDD1 /VDD2 (V) 2.65 Figure 20. Driver Output Offset Voltage, VOS vs. Supply Voltage, VDD1/VDD2 Rev. D | Page 13 of 25 ADN4650/ADN4651/ADN4652 Data Sheet 3.60 3.40 3.35 3.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 SUPPLY VOLTAGE, VDD1 AND VDD2 (V) Figure 21. Differential Propagation Delay vs. Supply Voltage, VDD1 and VDD2 3.8 3.7 3.6 3.5 3.4 3.3 tPHL CHANNEL 2 tPLH CHANNEL 2 tPHL CHANNEL 1 tPLH CHANNEL 1 3.2 3.1 3.0 -50 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE (C) Figure 22. Differential Propagation Delay vs. Ambient Temperature (TA) 3.50 3.45 3.40 tPHL CHANNEL 2 tPLH CHANNEL 2 tPHL CHANNEL 1 tPLH CHANNEL 1 3.35 3.30 0 0.2 0.4 0.6 0.8 1.0 DIFFERENTIAL INPUT VOLTAGE, VID (V) 1.2 1.4 Figure 23. Differential Propagation Delay vs. Receiver Differential Input Voltage, VID 0.5 1.0 1.5 2.0 2.5 Figure 24. Differential Propagation Delay vs. Receiver Input Offset Voltage, VIC 240 tF CHANNEL 2 tR CHANNEL 2 tF CHANNEL 1 tR CHANNEL 1 220 200 180 160 140 120 2.35 2.40 2.45 2.50 2.55 2.60 2.65 SUPPLY VOLTAGE, VDD1 /VDD2 (V) Figure 25. Differential Output Transition Time vs. Supply Voltage, VDD1/VDD2 DIFFERENTIAL OUTPUT TRANSITION TIME (ps) 3.55 3.35 RECEIVER INPUT OFFSET VOLTAGE, VIC (V) 240 220 200 180 160 tF CHANNEL 2 tR CHANNEL 2 tF CHANNEL 1 tR CHANNEL 1 140 120 -50 13677-019 DIFFERENTIAL PROPAGATION DELAY (ns) 3.60 3.40 0 DIFFERENTIAL OUTPUT TRANSITION TIME (ps) 3.9 3.45 3.30 13677-018 DIFFERENTIAL PROPAGATION DELAY (ns) 4.0 3.50 13677-020 3.45 3.55 13677-021 3.50 tPHL CHANNEL 2 tPLH CHANNEL 2 tPHL CHANNEL 1 tPLH CHANNEL 1 -25 0 25 50 75 AMBIENT TEMPERATURE (C) 100 125 13677-022 3.55 DIFFERENTIAL PROPAGATION DELAY (ns) tPHL CHANNEL 2 tPLH CHANNEL 2 tPHL CHANNEL 1 tPLH CHANNEL 1 13677-017 DIFFERENTIAL PROPAGATION DELAY (ns) 3.60 Figure 26. Differential Output Transition Time vs. Ambient Temperature (TA) Rev. D | Page 14 of 25 Data Sheet ADN4650/ADN4651/ADN4652 40 25 20 15 10 5 0 2.35 2.40 2.45 2.60 2.55 2.50 2.65 SUPPLY VOLTAGE, VDD1 AND VDD2 (V) 30 25 20 15 10 5 CHANNEL 1 CHANNEL 2 0 13677-023 tSK(D) CHANNEL 2 tSK(D) CHANNEL 1 35 0 100 200 300 400 500 600 DATA RATE (Mbps) Figure 27. Duty Cycle Skew, tSK(D) vs. Supply Voltage, VDD1 and VDD2 13677-025 DETERMINISTIC JITTER, tDJ(PP) (ps) DUTY CYCLE SKEW, tSK(D) (ps) 30 Figure 29. Deterministic Jitter, tDJ(PP) vs. Data Rate 30 50 15 10 5 tSK(D) CHANNEL 2 tSK(D) CHANNEL 1 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE (C) 35 30 25 20 15 10 CHANNEL 1 CHANNEL 2 5 0 2.35 2.40 2.45 2.50 2.55 2.60 2.65 SUPPLY VOLTAGE, VDD1 /VDD2 (V) Figure 28. Duty Cycle Skew, tSK(D) vs. Ambient Temperature (TA) Figure 30. Deterministic Jitter, tDJ(PP) vs. Supply Voltage, VDD1/VDD2 DETERMINISTIC JITTER, tDJ(PP) (ps) 60 50 40 30 20 10 CHANNEL 1 CHANNEL 2 0 -50 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE (C) Figure 31. Deterministic Jitter, tDJ(PP) vs. Ambient Temperature Rev. D | Page 15 of 25 13677-027 0 -50 40 13677-026 DETERMINISTIC JITTER, tDJ(PP) (ps) 20 13677-024 DUTY CYCLE SKEW, tSK(D) (ps) 45 25 CH2 50mV CH4 10mV 300ps/DIV DELAY 61.0828ns CH1 50mV CH3 10mV CH2 50mV CH4 10mV 300ps/DIV DELAY 61.0828ns Figure 33. ADN4651 Eye Diagram for DOUT2 Figure 32. ADN4651 Eye Diagram for DOUT1 Rev. D | Page 16 of 25 13677-029 CH1 50mV CH3 10mV Data Sheet 13677-028 ADN4650/ADN4651/ADN4652 Data Sheet ADN4650/ADN4651/ADN4652 TEST CIRCUITS AND SWITCHING CHARACTERISTICS DOUTx+ DINx+ RL/2 DOUTx- V VOS V VOD Figure 34. Driver Test Circuit R DINx- D DOUTx- NOTES 1. VTEST = 0V TO 2.4V 3.75k Figure 36. Voltage Definitions DINx+ VTEST SIGNAL GENERATOR V RL 3.75k V VOD 50 13677-031 DOUTx+ DINx+ VOUT+ VOUT- NOTES 1. VID = VIN+ - VIN- 2. VIC = (VIN+ + VIN-)/2 3. VOD = VOUT+ - VOUT- 4. VOS = (VOUT+ + VOUT-)/2 D 13677-030 DINx- RL/2 DOUTx- 13677-032 R VOD DOUTx+ R 50 DINx- Rev. D | Page 17 of 25 RL D DOUTx- NOTES 1. CL INCLUDES PROBE AND JIG CAPACITANCE. Figure 35. Driver Test Circuit (Full Load Across Common-Mode Range) CL Figure 37. Timing Test Circuit CL 13677-033 DOUTx+ D DINx- VIN- DINx+ R VID VIN+ ADN4650/ADN4651/ADN4652 Data Sheet THEORY OF OPERATION The ADN4650/ADN4651/ADN4652 are TIA/EIA-644-A LVDS compliant isolated buffers. LVDS signals applied to the inputs are transmitted on the outputs of the buffer, and galvanic isolation is integrated between the two sides of the device. This integration allows drop-in isolation of LVDS signal chains. The LVDS receiver detects the differential voltage present across a termination resistor on an LVDS input. An integrated digital isolator transmits the input state across the isolation barrier, and an LVDS driver outputs the same state as the input. With a positive differential voltage of 100 mV across any DINx pin, the corresponding DOUTx+ pin sources current. This current flows across the connected transmission line and termination at the receiver at the far end of the bus, while DOUTx- sinks the return current. With a negative differential voltage of -100 mV across any DINx pin, the corresponding DOUTx+ pin sinks current, with DOUTx- sourcing the current. Table 16 and Table 17 show these input/output combinations. The output drive current is between 2.5 mA and 4.5 mA (typically 3.1 mA), developing between 250 mV and 450 mV across a 100 termination resistor (RT). The received voltage is centered around 1.2 V. Note that because the differential voltage (VID) reverses polarity, the peak-to-peak voltage swing across RT is twice the differential voltage magnitude (|VID|). TRUTH TABLE AND FAIL-SAFE RECEIVER The LVDS standard, TIA/EIA-644-A, defines normal receiver operation under two conditions: an input differential voltage of +100 mV corresponding to one logic state, and a voltage of -100 mV for the other logic state. Between these thresholds, standard LVDS receiver operation is undefined (it may detect either state), as shown in Table 16 for the ADN4650. The ADN4651/ADN4652 incorporate a fail-safe circuit to ensure the LVDS outputs are in a known state (logic high) when the input state is undefined (-100 mV < VID < +100 mV), as shown in Table 17. This input state can occur when the inputs are floating (unconnected, no termination resistor), when the inputs are shorted, and when there is no active driver connected to the inputs (but with a termination resistor). Open-circuit, shortcircuit, and terminated/idle bus fail-safes, respectively, ensure a known output state for these conditions, as implemented by the ADN4651/ADN4652. After the fail-safe circuit is triggered by these input states (-100 mV < VID < +100 mV), there is a delay of up to 1.2 s before the output is guaranteed to be high (VOD 250 mV). During this time, the output may transition to or stay in a logic low state (VOD -250 mV). The fail-safe circuit triggers as soon as the input differential voltage remains between +100 mV and -100 mV for some nanoseconds. This means that very slow rise and fall times on the input signal, outside typical LVDS operation (350 ps maximum tR/tF), can potentially trigger the fail-safe circuit on a high to low crossover. At the minimum |VID| of 100 mV for normal operation, the rise/fall time must be 5 ns to avoid triggering a fail-safe state. Increasing |VID| to 200 mV correspondingly allows an input rise/fall time of up to 10 ns without triggering a fail-safe state. For very low speed applications where slow high to low transitions in excess of this limit are expected, using external biasing resistors is an option to introduce a minimum |VID| of 100 mV (that is, the fail-safe cannot trigger). Table 16. ADN4650 Input/Output Operation Input (DINx) Powered On Yes Yes Yes No VID (mV) 100 -100 -100 < VID < +100 Don't care Output (DOUTx) Logic High Low Indeterminate Don't care Powered On Yes Yes Yes Yes VOD (mV) 250 -250 Indeterminate 250 Logic High Low Indeterminate High Table 17. ADN4651/ADN4652 Input/Output Operation Input (DINx) Powered On Yes Yes Yes No VID (mV) 100 -100 -100 < VID < +100 Don't care Output (DOUTx) Logic High Low Indeterminate Don't care Rev. D | Page 18 of 25 Powered On Yes Yes Yes Yes VOD (mV) 250 -250 250 250 Logic High Low High High Data Sheet ADN4650/ADN4651/ADN4652 In the absence of input transitions for more than approximately 1 s, a periodic set of refresh pulses, indicative of the correct input state, ensures dc correctness at the output (including the fail-safe output state, if applicable). These periodic refresh pulses also correct the output state within 1 s in the event of a fault condition or set the ADN4651/ADN4652 output to the fail-safe state. The ADN4650/ADN4651/ADN4652 require appropriate decoupling of the VDDx pins with 100 nF capacitors. If the integrated LDO is not used, and a 2.5 V supply is connected directly, connect the appropriate VINx pin to the supply as well, as shown in Figure 38, using the ADN4651 as an example. 100nF VIN1 On power-up, the output state may initially be in the incorrect dc state if there are no input transitions. The output state is corrected within 1 s by the refresh pulses. If the decoder receives no internal pulses for more than approximately 1 s, the device assumes that the input side is unpowered or nonfunctional, in which case, the output is set to a positive differential voltage (logic high). GND1 VDD1 100 100nF 1 20 2 19 3 18 GND1 4 17 DIN1+ 5 DIN1- 6 TOP VIEW (Not to Scale) 15 ADN4651 The ADN4650/ADN4651/ADN4652 can operate with high speed LVDS signals up to 300 MHz clock, or 600 Mbps nonreturn to zero (NRZ) data. With such high frequencies, it is particularly important to apply best practices for the LVDS trace layout and termination. Locate a 100 termination resistor as close as possible to the receiver, across the DINx+ and DINx- pins. Controlled 50 impedance traces are needed on LVDS signal lines for full signal integrity, reduced system jitter, and minimizing electromagnetic interference (EMI) from the PCB. Trace widths, lateral distance within each pair, and distance to the ground plane underneath all must be chosen appropriately. Via fencing to the PCB ground between pairs is also a best practice to minimize crosstalk between adjacent pairs. The ADN4650/ADN4651/ADN4652 pass EN55022 Class B emissions limits without extra considerations required for the isolator when operating with up to 600 Mbps PRBS data. When isolating high speed clocks (for example, 300 MHz), a reduced PCB clearance (isolation gap) may be required with the 20-lead SOIC models to reduce dipole antenna effects and provide sufficient margin below Class B emissions limits. The 20-lead SSOP models pass the Class B limits up to 150 MHz clock frequencies with no extra PCB measures. VDD2 GND2 DOUT1+ 16 DOUT1- DOUT2+ 7 14 DIN2+ DOUT2- 8 13 DIN2- 9 12 GND1 10 11 VDD1 100nF PCB LAYOUT VIN2 GND2 100 VDD2 GND2 100nF 13677-035 In response to any change in the input state detected by the integrated LVDS receiver, an encoder circuit sends narrow (~1 ns) pulses to a decoder circuit using integrated transformer coils. The decoder is bistable and is, therefore, either set or reset by the pulses that indicate input transitions. The decoder state determines the LVDS driver output state in normal operation, and this in turn reflects the isolated LVDS buffer input state. The best practice for high speed PCB design avoids any other emissions from PCBs in applications that use the ADN4650/ADN4651/ ADN4652. Special care is recommended for off board connections, where switching transients from high speed LVDS signals (and clocks in particular) may conduct onto cabling, resulting in radiated emissions. Use common-mode chokes, ferrites, or other filters as appropriate at the LVDS connectors, as well as cable shield or PCB ground connections to earth/chassis. Figure 38. Required PCB Layout When Not Using the LDO (2.5 V Supply) 1F 100nF 1F VIN1 GND1 20 100nF 1F 1F VIN2 2 19 3 18 GND1 4 17 GND2 DIN1+ 5 16 6 TOP VIEW (Not to Scale) 15 DOUT1+ DIN1- DOUT2+ 7 14 DIN2+ DOUT2- 8 13 DIN2- 9 12 GND1 10 11 VDD1 100 1 VDD1 ADN4651 100nF GND2 VDD2 DOUT1- 100 VDD2 GND2 100nF 13677-036 ISOLATION Figure 39. Required PCB Layout When Using the LDO (3.3 V Supply) When the integrated LDO is used, bypass capacitors of 1 F are required on the VINx pins and on the nearest VDDx pins (LDO output), as shown in Figure 39, using the ADN4651 as an example. MAGNETIC FIELD IMMUNITY The limitation on the magnetic field immunity of the device is set by the condition in which the induced voltage in the transformer receiving coil is sufficiently large, either to falsely set or reset the decoder. The following analysis defines such conditions. The ADN4650/ADN4651/ADN4652 are examined in a 2.375 V operating condition because it represents the most susceptible mode of operation for this product. Rev. D | Page 19 of 25 ADN4650/ADN4651/ADN4652 Data Sheet where: is the magnetic flux density. rn is the radius of the nth turn in the receiving coil. N is the number of turns in the receiving coil. Given the geometry of the receiving coil in the ADN4650/ ADN4651/ADN4652, and an imposed requirement that the induced voltage be, at most, 50% of the 0.25 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 40. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 DISTANCE = 100mm 10 DISTANCE = 5mm 1 0.1 0.01 1k 100k 10k 10M 1M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 41. Maximum Allowable Current for Various Current to ADN4650/ADN4651/ADN4652 Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Avoid PCB structures that form loops. 1k 100 INSULATION LIFETIME 10 All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation as well as on the materials and material interfaces. 1 0.1 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 13677-037 0.01 0.001 1k DISTANCE = 1m 1k 13677-038 V = (-d/dt)rn2; n = 1, 2, ..., N 10k MAXIMUM ALLOWABLE CURRENT (kA) The pulses at the transformer output have an amplitude greater than 0.5 V. The decoder has a sensing threshold of about 0.25 V, therefore establishing a 0.25 V margin in which induced voltages are tolerated. The voltage induced across the receiving coil is given by Figure 40. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.92 kgauss induces a voltage of 0.125 V at the receiving coil. This voltage is about 50% of the sensing threshold and does not cause a faulty output transition. If such an event occurs with the worst case polarity during a transmitted pulse, it reduces the received pulse from >0.5 V to 0.375 V. This voltage is still higher than the 0.25 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADN4650/ ADN4651/ADN4652 transformers. Figure 41 expresses these allowable current magnitudes as a function of frequency for selected distances. The ADN4650/ADN4651/ADN4652 are very insensitive to external fields. Only extremely large, high frequency currents, very close to the component, can potentially be a concern. For the 1 MHz example noted, a 2.29 kA current must be placed 5 mm from the ADN4650/ADN4651/ADN4652 to affect component operation. The two types of insulation degradation of primary interest are breakdown along surfaces exposed to the air and insulation wear out. Surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. Insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. Surface Tracking Surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. Safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. Lower material group ratings are more resistant to surface tracking and, therefore, can provide adequate lifetime with smaller creepage. The minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation barrier, pollution degree, and material group. The material group and creepage for ADN4650/ADN4651/ADN4652 are presented in Table 4 and Table 5. Rev. D | Page 20 of 25 Data Sheet ADN4650/ADN4651/ADN4652 The lifetime of insulation caused by wear out is determined by its thickness, material properties, and the voltage stress applied. It is important to verify that the product lifetime is adequate at the application working voltage. The working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. It is the working voltage applicable to tracking that is specified in most standards. Testing and modeling show that the primary driver of long-term degradation is displacement current in the polyimide insulation causing incremental damage. The stress on the insulation can be broken down into broad categories, such as dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. The ratings in certification documents are usually based on 60 Hz sinusoidal stress because this reflects isolation from line voltage. However, many practical applications have combinations of 60 Hz ac and dc across the isolation barrier, as shown in Equation 1. Because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as shown in Equation 2. For insulation wear out with the polyimide materials used in this product, the ac rms voltage determines the product lifetime. VRMS = VAC RMS2 + VDC 2 (1) VAC RMS = VRMS 2 - VDC 2 (2) or The working voltage across the barrier from Equation 1 is VRMS = VAC RMS2 + VDC 2 VRMS = 2402 + 4002 VRMS = 466 V This VRMS value is the working voltage used together with the material group and pollution degree when looking up the creepage required by a system standard. To determine if the lifetime is adequate, obtain the time varying portion of the working voltage. To obtain the ac rms voltage, use Equation 2. VAC RMS = VRMS 2 - VDC 2 VAC RMS = 4662 - 4002 VAC RMS = 240 V rms In this case, the ac rms voltage is simply the line voltage of 240 V rms. This calculation is more relevant when the waveform is not sinusoidal. The value is compared to the limits for the working voltage in Table 12 for the expected lifetime, less than a 60 Hz sine wave, and it is well within the limit for a 50-year service life. Note that the dc working voltage limit in Table 12 is set by the creepage of the package as specified in IEC 60664-1. This value can differ for specific system level standards. ISOLATION VOLTAGE where: VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. creepage, clearance, and lifetime of a device, see Figure 42 and the following equations. Calculation and Use of Parameters Example The following example frequently arises in power conversion applications. Assume that the line voltage on one side of the isolation is 240 V ac rms and a 400 V dc bus voltage is present on the other side of the isolation barrier. The isolator material is polyimide. To establish the critical voltages in determining the Rev. D | Page 21 of 25 VAC RMS VPEAK VRMS VDC TIME Figure 42. Critical Voltage Example 13677-039 Insulation Wear Out ADN4650/ADN4651/ADN4652 Data Sheet APPLICATIONS INFORMATION High speed LVDS interfaces can be isolated using the ADN4650/ ADN4651/ADN4652 either between components, between boards, or at a cable interface. The ADN4650/ADN4651/ADN4652 offer full LVDS compliant inputs and outputs, allowing increased LVDS output drive strength compared to built-in reduced specification LVDS interfaces on other components. The LVDS compliant receiver inputs on the ADN4650/ADN4651/ADN4652 also ensure full compatibility with any LVDS source being isolated. Newer programmable logic controller (PLC) and input/output modules communicate across an LVDS backplane, illustrating a board to board LVDS interface, as shown in Figure 45. With a daisy-chain type topology for transmit and receive to either adjacent node, two ADN4651 (or ADN4652) devices on each node can isolate four LVDS channels. The addition of galvanic isolation allows a much more robust backplane interface port on the PLC or input/output modules. Isolated analog front-end applications provide an example of the ADN4650/ADN4651 isolating an LVDS interface between components. As shown in Figure 43, two ADN4650 components isolate the LVDS interface of the AD7960 analog-to-digital converter (ADC), including 600 Mbps data, a 300 MHz echoed clock, and a 5 MHz sample clock. Isolation of the AD7960 using two ADN4651 components is shown in Figure 44. The ADN4651 additive phase jitter is sufficiently low that it does not affect the ADC performance even when isolating the sample clock. In addition, implementing the galvanic isolation improves ADC performance by removing digital and power supply noise from the field-programmable gate array (FPGA) circuit. With galvanic isolation, even LVDS ports can be treated as full external ports, and transmitted along cable runs (see Figure 46), even in harsh environments where high common-mode voltages may be induced on the cable. The low jitter of the ADN4651/ADN4652 ensures that more of the jitter budget can be used to account for the cable effects, allowing the cable to be as long as possible. The ADN4651/ADN4652 offer a high drive strength, fully LVDS compliant output, capable of driving short cable runs of a few meters. This is in contrast to alternative isolation methods that degrade the LVDS signal quality. The data rate can be chosen as appropriate for the cable length; the ADN4651/ADN4652 operate not only at 600 Mbps but also at any arbitrary data rate down to dc. D 100 DCO 100 ISOLATION ADN4650 100 D 100 DCO FPGA/ASIC 100 CNV 100 100 CLK 100 CNV 13677-040 CLK ISOLATION AD7960 ADN4650 Figure 43. Example Isolated Analog Front-End Implementation (Isolated AD7960 Using the ADN4650) 100 D CLK 100 ISOLATION ADN4651 100 D 100 CLK AD7960 CNV 100 100 DCO 100 CNV ADN4651 Figure 44. Example Isolated Analog Front-End Implementation (Isolated AD7960 Using the ADN4651) Rev. D | Page 22 of 25 13677-040 100 DCO ISOLATION FPGA/ASIC Data Sheet ADN4650/ADN4651/ADN4652 ISOLATION 100 CONNECTOR 100 MODULE 1 100 ISOLATION 100 100 100 100 ISOLATION 100 MODULE 2 100 100 ISOLATION 100 ISOLATION 100 100 CONNECTOR 100 ADN4651 100 MCU 3 CONNECTOR ISOLATION 100 ADN4651 100 MODULE 3 Figure 45. Example Isolated Backplane Implementation for PLCs and Input/Output Modules Using the ADN4651 SHIELDED TWISTED PAIR CABLE Figure 46. Example Isolated LVDS Cable Application Using the ADN4651 Rev. D | Page 23 of 25 100 FPGA/ ASIC 100 13677-042 ISOLATION 100 ADN4651 CONNECTOR 100 CONNECTOR 100 FPGA/ ASIC 100 ADN4651 ISOLATION CONNECTOR ADN4651 100 MCU 2 13677-041 MCU 1 ADN4650/ADN4651/ADN4652 Data Sheet OUTLINE DIMENSIONS 13.00 (0.5118) 12.60 (0.4961) 11 20 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 10 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 1.27 (0.0500) BSC SEATING PLANE 0.75 (0.0295) 45 0.25 (0.0098) 8 0 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) 06-07-2006-A COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 47. 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters and (inches) 7.50 7.20 6.90 11 20 5.60 5.30 5.00 1 8.20 7.80 7.40 10 PIN 1 INDICATOR TOP VIEW 0.65 BSC PKG-004600 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 SIDE VIEW 0.38 0.22 SEATING PLANE END VIEW 8 4 0 COMPLIANT TO JEDEC STANDARDS MO-150-AE 0.95 0.75 0.55 06-01-2006-A 2.00 MAX Figure 48. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADN4650BRWZ ADN4650BRWZ-RL7 ADN4650BRSZ ADN4650BRSZ-RL7 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] 20-Lead Shrink Small Outline Package [SSOP] 20-Lead Shrink Small Outline Package [SSOP] Rev. D | Page 24 of 25 Package Option RW-20 RW-20 RS-20 RS-20 Data Sheet Model 1 ADN4651BRSZ ADN4651BRSZ-RL7 ADN4651BRWZ ADN4651BRWZ-RL7 ADN4652BRSZ ADN4652BRSZ-RL7 ADN4652BRWZ ADN4652BRWZ-RL7 EVAL-ADN4650EBZ EVAL-ADN4650EB1Z EVAL-ADN4651EBZ EVAL-ADN4651EB1Z EVAL-ADN4652EBZ EVAL-ADN4652EB1Z 1 ADN4650/ADN4651/ADN4652 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 20-Lead Shrink Small Outline Package [SSOP] 20-Lead Shrink Small Outline Package [SSOP] 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] 20-Lead Shrink Small Outline Package [SSOP] 20-Lead Shrink Small Outline Package [SSOP] 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] ADN4650 SSOP Evaluation Board ADN4650 SOIC_W Evaluation Board ADN4651 SSOP Evaluation Board ADN4651 SOIC_W Evaluation Board ADN4651 SSOP Evaluation Board ADN4652 SOIC_W Evaluation Board Z = RoHS Compliant Part. (c)2015-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13677-0-1/17(D) Rev. D | Page 25 of 25 Package Option RS-20 RS-20 RW-20 RW-20 RS-20 RS-20 RW-20 RW-20