HSMP-381x, 481x
Surface Mount RF PIN
Low Distortion Attenuator Diodes
Data Sheet
Features
x Diodes Optimized for:
– Low Distortion Attenuating
– Microwave Frequency Operation
x Surface Mount Packages
– Single and Dual Versions
– Tape and Reel Options Available
x Low Failure in Time (FIT) Rate[1]
x Lead free
Note:
1. For more information see the Surface Mount PIN Reliability Data
Sheet.
Package Lead Code Identification,
SOT-23
(Top View)
Description/Applications
The HSMP-381x series is specifically designed for low dis-
tortion attenuator applications. The HSMP-481x products
feature ultra low parasitic inductance in the SOT-23 and
SOT-323 packages. They are specifically designed for use
at frequencies which are much higher than the upper limit
for conventional diodes.
A SPICE model is not available for PIN diodes as SPICE
does not provide for a key PIN diode characteristic, carrier
lifetime.
COMMON
CATHODE
#4
COMMON
ANODE
#3
SERIES
#2
SINGLE
#0
12
3
12
3
12
3
12
3
4810
12
3
DUAL
CATHODE
REVERSE
SERIES
#5
12
3
Package Lead Code Identification,
SOT-323
(Top View)
COMMON
CATHODE
F
COMMON
ANODE
E
SERIES
C
SINGLE
B
481B
DUAL CATHODE
2
Absolute Maximum Ratings[1] TC = +25°C
Symbol Parameter Unit SOT-23 SOT-323
IfForward Current (1 µs Pulse) Amp 1 1
PIV Peak Inverse Voltage V Same as VBR Same as VBR
TjJunction Temperature °C 150 150
Tstg Storage Temperature °C -65 to 150 -65 to 150
Tjc Thermal Resistance [2] °C/W 500 150
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to the device.
2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to the circuit board.
Electrical Specifications TC = +25°C (Each Diode)
Conventional Diodes
Part
Number
HSMP-
Package
Marking
Code
Lead
Code Configuration
Minimum
Breakdown
Voltage VBR
(V)
Maximum
Total
Capacitance
CT (pF)
Minimum
Resistance
at
IF = 0.01mA,
RH (Ω)
Maximum
Resistance
at
IF = 20mA,
RL (Ω)
Maximum
Resistance
at
IF = 100mA,
RT (Ω)
Resistance
at
IF = 1mA,
RM (Ω)
3810 E0 0 Single
100 0.35 1500 10 3.0 48 to 70
3812 E2 2 Series
3813 E3 3 Common Anode
3814 E4 4 Common Cathode
3815 E5 5 Reverse Series
381B E0 B Single
381C E2 C Series
381E E3 E Common Anode
381F E4 F Common Cathode
Test Conditions VR = VBR
Measure
IR≤ 10uA
VR = 50V
f = 1MHz
IF = 0.01mA
f = 100MHz
IF = 20mA
f = 100MHz
IF = 100mA
f = 100MHz
IF = 1mA
f = 100MHz
High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes
Part
Number
HSMP-
Package
Marking
Code
Lead
Code Configuration
Minimum
Breakdown
Voltage
VBR (V)
Maximum
Series
Resistance
RS (Ω)
Series
Resistance
IF = 1mA,
RM (Ω)
Typical
Total
Capacitance
CT (pF)
Maximum
Total
Capacitance
CT (pF)
Typical
Total
Inductance
LT (nH)
4810 EB B Dual Cathode 100 3 48 - 70 0.35 0.4 1
481B EB B Dual Cathode
Test Conditions VR = VBR
Measure
IR ≤ 10A
IF = 100mA
f =
100MHz
IF = 1mA
f = 100MHz
VR = 50V
f = 1MHz
VR = 50V
f = 1MHz
f =
500MHz
- 3GHz
3
Typical Parameters at TC = 25°C
Part Number Series Resistance Carrier Lifetime Reverse Recovery Time
Total
Capacitance
HSMP- RS (Ω) W (ns) Trr (ns) CT (pF)
381x 53 1500 300 0.27 @ 50 V
Test Conditions IF = 1 mA
f = 100 MHz
IF = 50 mA
IR = 250 mA
VR = 10 V
IF = 20 mA
90% Recovery
f = 1 MHz
Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode
10000
1000
100
10
1
RF RESISTANCE (OHMS)
0.01 0.1 1 10 100
I
F
– FORWARD BIAS CURRENT (mA)
T
A
= +85 C
T
A
= +25 C
T
A
= –55 C
Figure 2. RF Resistance vs. Forward
Bias Current, f = 100MHz
0.15
0.30
0.25
0.20
0.35
0.40
0.45
02 64101281614 18 20
TOTAL CAPACITANCE (pF)
REVERSE VOLTAGE (V)
Figure 1. RF Capacitance vs. Reverse
Bias.
1 MHz
30 MHz
frequency>100 MHz
120
110
100
90
80
70
60
50
40
1000 100 10
Diode Mounted as a
Series Attenuator
in a 50 Ohm Microstrip
and Tested at 123 MHz
DIODE RF RESISTANCE (OHMS)
Figure 3. 2nd Harmonic Input
Intercept Point vs. Diode RF
Resistance.
INPUT INTERCEPT POINT (dBm)
100
10
1
0.1
0.01
0 0.2 0.4 0.6 0.8 1.0 1.2
I
F
– FORWARD CURRENT (mA)
V
F
– FORWARD VOLTAGE (mA)
Figure 4. Forward Current vs. Forward
Voltage.
125 C 25 C –50 C
INPUT RF IN/OUT
Figure 5. Four Diode π Attenuator. See Application Note 1048
for Details.
FIXED
BIAS
VOLTAGE
VARIABLE BIAS
Typical Applications for Multiple Diode Products
Notes:
3. Typical values were derived using limited samples during initial product characterization and may not be representative of the overall distribution.
4
Microstrip Series Connection for HSMP-481x Series
In order to take full advantage of the low inductance of the
HSMP-481x series when using them in series applications,
both lead 1 and lead 2 should be connected together, as
shown in Figure 7.
Microstrip Shunt Connections for HSMP-481x Series
In Figure 8, the center conductor of the microstrip
line is interrupted and leads 1 and 2 of the HSMP-481x
series diode are placed across the resulting gap. This forces
the 1.5 nH lead inductance of leads 1 and 2 to appear as
part of a low pass filter, reducing the shunt
parasitic inductance and increasing the maximum available
attenuation. The 0.3 nHof shunt inductance external to the
diode is created by the via holes, and is a good estimate
for 0.032" thick material.
Typical Applications for HSMP-481x Low Inductance Series
12
3
HSMP-481x
Figure 6. Internal Connections. Figure 7. Circuit Layout.
Figure 8. Circuit Layout. Figure 9. Equivalent Circuit.
50 OHM MICROSTRIP LINES
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
0.3 nH
0.3 nH
0.3 pFRj
1.5 nH 1.5 nH
R
j
0.08 + 2.5
I
b
0.9
5
Typical Applications for HSMP-481x Low Inductance Series (continued)
Co-Planar Waveguid
e
Groundplane
Center Conductor
Groundplane
0.3 pF
0.75 nH
R
j
Equivalent Circuit Model
HSMP-381x Chip*
Co-Planar Waveguide Shunt Connection for HSMP-481x
Series
Co-Planar waveguide, with ground on the top side of the
printed circuit board, is shown in Figure 10. Since it elimi-
nates the need for via holes to ground, it offers lower shunt
parasitic inductance and higher maximum attenuation
when compared to microstrip circuit.
Figure 10. Circuit Layout.
Figure 11. Equivalent Circuit.
0.18 pF*
* Measured at -20 V
2.5 Ω
R
j
R
s
C
j
R
T
= 2.5 + R
j
C
T
= C
P
+ C
j
I
= Forward Bias Current in mA
*See AN1124 for package models.
R
j
= 80
I
0.9
Ω
6
Assembly Information
SOT-323 PCB Footprint
A recommended PCB pad layout for the miniature SOT-323
(SC-70) package is shown in Figure 12 (dimensions are in
inches). This layout provides ample allowance for package
placement by automated assembly equipment without
adding parasitics that could impair the performance.
SMT Assembly
Reliable assembly of surface mount components is a
complex process that involves many material, process, and
equipment factors, including: method of heating (e.g., IR
or vapor phase reflow, wave soldering, etc.) circuit board
material, conductor thickness and pattern, type of solder
alloy, and the thermal conductivity and thermal mass of
components. Components with a low mass, such as the
SOT-323/-23 package, will reach solder reflow tempera-
tures faster than those with a greater mass.
After ramping up from room temperature, the circuit board
with components attached to it (held in place with solder
paste) passes through one or more preheat zones. The
preheat zones increase the temperature of the board and
components to prevent thermal shock and begin evaporat-
ing solvents from the solder paste. The reflow zone briefly
elevates the temperature sufficiently to produce a reflow
of the solder.
The rates of change of temperature for the ramp-up and
cool-down zones are chosen to be low enough to not
cause deformation of the board or damage to components
due to thermal shock. The maximum temperature in the
reflow zone (TMAX) should not exceed 260°C.
These parameters are typical for a surface mount assembly
process for Avago diodes. As a general guideline, the circuit
board and components should be exposed only to the
minimum temperatures and times necessary to achieve a
uniform reflow of solder.
0.026
0.039
0.079
0.022
Dimensions in inches
0.039
1
0.039
1
0.079
2.0
0.031
0.8
Dimensions in inches
mm
0.035
0.9
Figure 12. Recommended PCB Pad Layout
for Avago’s SC70 3L/SOT-323 Products.
Figure 13. Recommended PCB Pad Layout for Avago’s SOT-23 Products.
SOT-23 PCB Footprint
7
Package Dimensions
Outline 23 (SOT-23)
Package Characteristics
Lead Material .................................................... Copper (SOT-323); Alloy 42 (SOT-23)
Lead Finish .........................................................................Tin 100% (Lead-free option)
Maximum Soldering Temperature ............................................ 260°C for 5 seconds
Minimum Lead Strength ........................................................................... 2 pounds pull
Typical Package Inductance ...................................................................................... 2 nH
Typical Package Capacitance ..............................................0.08 pF (opposite leads)
Outline SOT-323 (SC-70)
Option Descriptions
-BLKG = Bulk, 100 pcs. per antistatic bag
-TR1G = Tape and Reel, 3000 devices per 7" reel
-TR2G = Tape and Reel, 10,000 devices per 13" reel
Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface
Mounted Components for Automated Placement.”
Ordering Information
Specify part number followed by option. For example:
HSMP - 381x - XXX
Bulk or Tape and Reel Option
Part Number; x = Lead Code
Surface Mount PIN
e
B
e2
e1
E1
C
EXXX
L
D
A
A1
Notes:
XXX-package marking
Drawings are not to scale
DIMENSIONS (mm)
MIN.
0.79
0.000
0.30
0.08
2.73
1.15
0.89
1.78
0.45
2.10
0.45
MAX.
1.20
0.100
0.54
0.20
3.13
1.50
1.02
2.04
0.60
2.70
0.69
SYMBOL
A
A1
B
C
D
E1
e
e1
e2
E
L
e
B
e1
E1
C
EXXX
L
D
A
A1
Notes:
XXX-package marking
Drawings are not to scale
DIMENSIONS (mm)
MIN.
0.80
0.00
0.15
0.08
1.80
1.10
1.80
0.26
MAX.
1.00
0.10
0.40
0.25
2.25
1.40
2.40
0.46
SYMBOL
A
A1
B
C
D
E1
e
e1
E
L
1.30 typical
0.65 typical
8
Note: "AB" represents package marking code.
"C" represents date code.
END VIEW
8 mm
4 mm
TOP VIEW
ABC ABC ABC ABC
USER
FEED
DIRECTION
COVER TAPE
CARRIER
TAPE
REEL
9 MAX
A
0
P
P
0
D
P
2
E
F
W
D
1
Ko 8 MAX
B
0
13.5 MAX
t1
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
3.15
±
0.10
2.77
±
0.10
1.22
±
0.10
4.00
±
0.10
1.00 + 0.05
0.124
±
0.004
0.109
±
0.004
0.048
±
0.004
0.157
±
0.004
0.039
±
0.002
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.50 + 0.10
4.00
±
0.10
1.75
±
0.10
0.059 + 0.004
0.157
±
0.004
0.069
±
0.004
PERFORATION
WIDTH
THICKNESS
W
t1
8.00 + 0.30 - 0.10
0.229
±
0.013
0.315 + 0.012 - 0.004
0.009
±
0.0005
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50
±
0.05
2.00
±
0.05
0.138
±
0.002
0.079
±
0.002
DISTANCE
BETWEEN
CENTERLINE
Tape Dimensions and Product Orientation
For Outline SOT-23
Device Orientation
For Outlines SOT-23/323
Tape Dimensions and Product Orientation
For Outline SOT-323
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
Obsoletes AV01-0378EN
AV02-0402EN - December 22, 2009
P
P
0
P
2
F
W
C
D
1
D
E
A
0
An
t
1
(CARRIER TAPE THICKNESS) T
t
(COVER TAPE THICKNESS)
An
B
0
K
0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
2.40
±
0.10
2.40
±
0.10
1.20
±
0.10
4.00
±
0.10
1.00 + 0.25
0.094
±
0.004
0.094
±
0.004
0.047
±
0.004
0.157
±
0.004
0.039 + 0.010
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.55
±
0.05
4.00
±
0.10
1.75
±
0.10
0.061
±
0.002
0.157
±
0.004
0.069
±
0.004
PERFORATION
WIDTH
THICKNESS
W
t
1
8.00
±
0.30
0.254
±
0.02
0.315
±
0.012
0.0100
±
0.0008
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50
±
0.05
2.00
±
0.05
0.138
±
0.002
0.079
±
0.002
DISTANCE
FOR SOT-323 (SC70-3 LEAD) An 8 C MAX
FOR SOT-363 (SC70-6 LEAD) 10 C MAX
ANGLE
WIDTH
TAPE THICKNESS
C
T
t
5.4
±
0.10
0.062
±
0.001
0.205
±
0.004
0.0025
±
0.00004
COVER TAPE