Revised June 2005 74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25: Series Resistors in the Outputs General Description Features The LVTH162373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LVTH162373 is designed with equivalent 25: series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH162373 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Input and output interface capability to systems at 5V VCC Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free bus loading Outputs include equivalent series resistance of 25: to make external termination resistors unnecessary and reduce overshoot and undershoot Functionally compatible with the 74 series 16373 Latch-up performance exceeds 500 mA ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number Package Number 74LVTH162373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBES] 74LVTH162373MEX (Note 1) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LVTH162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBES] 74LVTH162373MTX (Note 1) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Package Description Note 1: Use this Order Number to receive devices in Tape and Reel. Logic Symbol (c) 2005 Fairchild Semiconductor Corporation DS500354 www.fairchildsemi.com 74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25: Series Resistors in the Outputs October 2000 74LVTH162373 Connection Diagram Pin Descriptions Pin Names Description OEn Output Enable Input (Active LOW) LEn Latch Enable Input I0-I15 Inputs O0-O15 3-STATE Outputs Truth Tables Inputs Outputs LE1 OE1 I0-I7 O0-O7 Z X H X H L L L H L H H L L X Oo Inputs H L X Z Oo Outputs LE2 OE2 I8-I15 O8-O15 X H X Z H L L L H L H H L L X Oo HIGH Voltage Level LOW Voltage Level Immaterial HIGH Impedance Previous output prior to HIGH-to-LOW transition of LE Functional Description The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. www.fairchildsemi.com 2 74LVTH162373 Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVTH162373 Absolute Maximum Ratings(Note 2) Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value Conditions 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Units V V Output in 3-STATE V Output in HIGH or LOW State (Note 3) VI GND mA VO GND mA 64 VO ! VCC Output at HIGH State 128 VO ! VCC Output at LOW State mA r64 r128 65 to 150 mA mA qC Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage Min Max 2.7 3.6 Units V 0 5.5 V IOH HIGH Level Output Current 12 mA IOL LOW Level Output Current 12 mA TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V-2.0V, VCC 3.0V 40 85 qC 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VCC Parameter VIK Input Clamp Diode Voltage (V) TA 40qC to 85qC Min VIH Input HIGH Voltage 2.7-3.6 VIL Input LOW Voltage 2.7-3.6 VOH Output HIGH Voltage 2.7-3.6 VCC 0.2 3.0 2.0 VOL II(HOLD) Output LOW Voltage Bushold Input Minimum Drive Max 1.2 2.7 2.0 0.8 0.2 3.0 0.8 75 II(OD) Bushold Input Over-Drive 3.0 II Input Current Control Pins Data Pins IOFF IPU/PD Power Off Leakage Current Power Up/Down 3-STATE Output Current 500 V VO d 0.1V or V VO t VCC 0.1V V PA 500 Current to Change State II PA 75 Conditions 18 mA V V 2.7 3.0 Units IOH 100 PA IOH 12mA IOL 100 PA IOL 12 mA VI 0.8V VI 2.0V (Note 4) (Note 5) 3.6 10 VI 5.5V 3.6 r1 VI 0V or VCC VI 0V VI VCC 3.6 5 PA 1 0 r100 PA 0-1.5V r100 PA 0V d VI or VO d 5.5V VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC VO d 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled www.fairchildsemi.com 4 Symbol (Continued) VCC Parameter Power Supply Current 'ICC Increase in Power Supply Current 40qC to 85qC TA (V) ICCZ 74LVTH162373 DC Electrical Characteristics Min Units Conditions Max 3.6 0.19 mA VCC d VO d 5.5V, Outputs Disabled 3.6 (Note 6) 0.2 mA One Input at VCC 0.6V Other Inputs at VCC or GND Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol (Note 7) TA VCC Parameter (V) Min 25qC Typ Conditions Units Max CL 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 8) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 8) 500: Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA Symbol Parameter 40qC to 85qC, CL 50pF, RL 500: VCC 3.3V r 0.3V Min Max VCC Min 2.7V Units Max tPHL Propagation Delay 1.3 4.8 1.3 5.3 tPLH Dn to On 1.4 4.8 1.4 5.1 tPHL Propagation Delay 1.7 5.0 1.7 5.1 tPLH LE to On 1.4 5.1 1.4 5.8 tPZL Output Enable Time 1.6 5.0 1.6 6.0 1.0 5.4 1.0 6.6 Output Disable Time 1.6 5.1 1.6 5.0 1.8 5.4 1.8 5.7 tS Setup Time, Dn to LE 1.0 0.8 tH Hold Time, Dn to LE 1.0 1.1 ns tW LE Pulse Width 3.0 3.0 ns tOSHL Output to Output Skew (Note 9) tPZH tPLZ tPHZ tOSLH ns ns ns ns ns 1.0 1.0 1.0 1.0 ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 10) Symbol Parameter Conditions CIN Input Capacitance VCC OPEN, VI COUT Output Capacitance VCC 3.0V, VO Note 10: Capacitance is measured at frequency f 0V or VCC 0V or VCC Typical Units 4 pF 8 pF 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVTH162373 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A www.fairchildsemi.com 6 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com 74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25: Series Resistors in the Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)