CDK3405CTQ48 - Cadeka Microcircuits

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

Data Sheet

CDK3405

8-bit, 180MSPS, Triple Video DACs

FEATURES

8-bit resolution, 180MSPS

±2.5% gain matching

±0.5% linearity error

Sync and blank controls

1.0Vpp video into 37.5Ω or 75Ω load

Internal bandgap voltage reference

Low glitch energy

Single +3.3V power supply

APPLICATIONS

n Video signal conversion

– RGB

– YCBCR

– Composite, Y, C

n Multimedia systems

n Image processing

n PC Graphics

General Description

CDK3405 is a low-cost triple D/A converter that is tailored to t graphics and

video applications where speed is critical.

CMOS-level inputs are converted to analog current outputs that can drive

25-37.5Ω loads corresponding to doubly-terminated 50-75Ω loads. A sync

current following SYNC input timing is added to the IOG output. BLANK

will override RGB inputs, setting IOG, IOB and IOR currents to zero when

BLANK = L. Although appropriate for many applications, the internal 1.25V

reference voltage can be overridden by the VREF input.

Few external components are required, just the current reference resistor,

current output load resistors, bypass capacitors, and decoupling capacitors.

Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is

guaranteed from -40°C to +125°C.

Block Diagram

Ordering Information

Part Number Package Pb-Free RoHS Compliant Operating Temp Range Packaging Method Package Quantity

CDK3405ATQ48 TQFP-48 Yes Yes -40°C to +125°C Tray 250

CDK3405ATQ48Y TQFP-48 Yes Yes -40°C to +125°C Tray 1,250

Moisture sensitivity level for all parts is MSL-3.

8-bit D/A

Converter

SYNC

CLOCK

G7-0

COMP

+1.25V

Ref

IOG

BLANK

8-bit D/A

Converter

B7-0 IOB

8-bit D/A

Converter

R7-0 IOR

REF

SYNC

Data Sheet

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

Pin Conguration

TQFP-48

GND

SYNC

GND

RSET

VREF

COMP

IOR

IOG

VAA

IOB

GND

VAA

GND

CLOCK

BLANK 11

GND

B7 23

NC38

TQFP

CDK3405

Pin Assignments

Pin No. Pin Name Description

Clock and Pixel I/O

24 CLK

Clock Input

41-48 R7-0 Red Pixel Data Inputs

3-10 G7-0 Green Pixel Data Inputs

16-23 B7-0 Blue Pixel Data Inputs

Controls

12 SYNC Sync Pulse Input

11 BLANK Blanking Input

Video Outputs

34 IOR Red Current Output

32 IOG Green Current Output

28 IOB Blue Current Output

Voltage Reference

36 VREF Input for DACs or Voltage Reference Output (1.25V)

37 RSET Current-Setting Resistor

35 COMP Compensation Capacitor

Power and Ground

13, 29, 30 VAA Analog Power Supply

1, 2, 14,

15, 25, 26,

39, 40

GND Ground

27, 31, 33 NC No Connect

Data Sheet

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

Absolute Maximum Ratings

The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device

should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper

device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reect

the operating conditions noted on the tables and plots.

Parameter Min Max Unit

Power Supply Voltage

VAA (Measured to GND) -0.5 4.0 V

Digital Inputs

Applied Voltage (measured to GND)(2) -0.5 VAA + 0.5 V

Forced Current(3,4) -5.0 5.0 mA

Analog Inputs

Applied Voltage (measured to GND)(2) -0.5 VAA + 0.5 V

Forced Current(3,4) -10.0 10.0 mA

Analog Outputs

Applied Voltage (measured to GND)(2) -0.5 VAA + 0.5 V

Forced Current(3,4) -60.0 60.0 mA

Short Circuit Duration (single output in HIGH state to GND) unlimited sec

Reliability Information

Parameter Min Max Unit

Temperature

Operating, Ambient -40 125 °C

Junction 150 °C

Lead Soldering (10 seconds) 300 °C

Vapor Phase Soldering (1 minute) 220 °C

Storage -65 150 °C

Package Thermal Resistance (θJA)65 °C/W

Notes:

1. Functional operation under any of these conditions is NOT implied.

Performance and reliability are guaranteed only if Operating Conditions are not exceeded.

2. Applied voltage must be current limited to specied range.

3. Forcing voltage must be limited to specied range.

4. Current is specied as conventional current owing into the device.

ESD Protection

Parameter TQFP-48

Human Body Model (HBM) TBD

Charged Device Model (CDM) TBD

Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit

VAA Power Supply Voltage 3.0 3.3 3.6 V

VREF Reference Voltage, External 1.0 1.25 1.5 V

CC Compensation Capacitor 0.1 µF

RL Output Load 37.5 Ω

TA Ambient Temperature, Still Air -40 +125 °C

0.5

1.5

2.5

-40 -20 0 20 40 60 80 100 120

Maximum Power Dissipation (W)

Ambient Temperature (°C)

TQFP-48

CDK3405 Power Derating

Data Sheet

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

Electrical Characteristics

(TA = 25°C, VAA =3.3V, VREF = 1.25V, RL = 37.5Ω, unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

IDD Power Supply Current

TA = 25°C (1) 80 85 mA

TA = -40°C to +125°C (2) 95 mA

PD Total Power Dissipation(2) TA = -40°C to +125°C 300 mW

Digital Inputs

VIH Input Voltage, HIGH (1) TA = -40°C to +125°C 2.5 V

VIL Input Voltage, LOW (1) TA = -40°C to +125°C 0.8 V

IIH Input Current, HIGH (1) TA = -40°C to +125°C -1 1 μA

IIL Input Current, LOW (1) TA = -40°C to +125°C -1 1 μA

CIInput Capacitance 4 pF

Analog Outputs

Output Current (1) 30 mA

ROOutput Resistance 40 kΩ

CO Output Capacitance 7 pF

Reference Output

VREF Reference Voltage Output (1) TA = -40°C to +125°C 1.135 1.25 1.365 V

Notes:

1. 100% tested at 25°C.

2. Parameter is guaranteed (but not tested) by design and characterization data.

Switching Characteristics

(TA = 25°C, VAA =3.3V, VREF = 1.25V, RL = 37.5Ω, unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

Clock Input

Conversion Rate (1) TA = -40°C to +125°C 180 MSPS

tPWH Pulse-width HIGH (2) TA = -40°C to +125°C 2 ns

tPWL Pulse-width LOW (2) TA = -40°C to +125°C 2 ns

Data Inputs

tSSetup

TA = 25°C (1) 1.5 ns

TA = -40°C to +125°C (2) 2 ns

tHHold

TA = 25°C (1) 0.6 ns

TA = -40°C to +125°C (2) 0.6 ns

Data Outputs, with 50Ω doubly terminated load

tDClock to Output Delay TA = -40°C to +125°C 1.6 ns

tROutput Risetime TA = -40°C to +125°C 0.6 ns

tFOutput Falltime TA = -40°C to +125°C 0.4 ns

tSET Settling Time 2.5 ns

tSKEW Output Skew 0.3 ns

Notes:

1. 100% production tested at +25°C.

2. Parameter is guaranteed (but not tested) by design and characterization data.

Data Sheet

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

DC Performance

(TA = 25°C, VAA =3.3V, VREF = 1.25V, RL = 37.5Ω, unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

Resolution 8 bits

INL Integral Linearity Error

TA = 25°C (1) -0.5 0.5 LSB

TA = -40°C to +125°C (2) -0.5 0.5 LSB

DNL Differential Linearity Error

TA = 25°C (1) -0.5 0.5 LSB

TA = -40°C to +125°C (2) -0.5 0.5 LSB

Offset Error TA = -40°C to +125°C (2) 0.01 %FS

Gain Matching Error TA = -40°C to +125°C (1) -2.5 2.5 %FS

Absolute Gain Error TA = -40°C to +125°C (1) -3.5 3.5 %FS

Full-Scale Output Current

TA = 25°C (1) 18.0 18.7 19.4 mA

TA = -40°C to +125°C (2) 18.0 18.7 19.4 mA

TA = -40°C to +125°C , With internal

reference. Trim RSET to calibrate full-scale

current.

18.7 mA

PSRR Power Supply Rejection Ratio TA = -40°C to +125°C (2) -0.01 0 0.01 %/%

Notes:

1. 100% production tested at +25°C.

2. Parameter is guaranteed (but not tested) by design and characterization data.

AC Performance

(TA = 25°C, VAA = 3.3V, VREF = 1.25V, RL = 37.5Ω, unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

Analog Outputs

Glitch Energy 20 pVsec

DAC-to-DAC Crosstalk 30 dB

Data Feedthrough 50 dB

Clock Feedthrough 60 dB

Notes:

1. 100% production tested at +25°C.

2. Parameter is guaranteed (but not tested) by design and characterization data.

Data Sheet

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

RGB7-0 (MSB…LSB) BLUE AND RED GREEN

SYNC BLANK VOUT (V) SYNC BLANK VOUT (V)

1111 1111 1 1 0.700 1 1 1.007

1111 1111 0 1 0.700 0 1 0.700

1111 1110 1 1 0.697 1 1 1.004

1111 1101 1 1 0.695 1 1 1.001

• • • • • • •

• ••••••

1000 0000 1 1 0.351 1 1 0.658

0111 1111 1 1 0.349 1 1 0.656

0111 1111 0 1 0.349 0 1 0.349

• • • • • • •

• ••••••

0000 0010 1 1 0.005 1 1 0.312

0000 0001 1 1 0.003 1 1 0.310

0000 0000 1 1 0.000 1 1 0.307

0000 0000 0 1 0.000 0 1 0.000

XXXX XXXX 1 0 0.000 1 0 0.307

XXXX XXXX 0 0 0.000 0 0 0.000

Table 1. Output Voltage vs. Input Code, SYNC and BLANK, VREF = 1.25V, RREF = 348Ω, RL = 37.5Ω

CLK

Pixel Data

and Controls

OUTPUT

Data N+2Data N+1Data N

PWL

tstH

50%

3%/FS

90%

10%

tFtR

PWH

1/f

tDtSET

Figure 1. CDK3405 Timing Diagram

Data Sheet

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

Functional Description

Within the CDK3405 are three identical 8-bit D/A converters,

each with a current source output. External loads are

required to convert the current to voltage outputs. Data

inputs RGB7-0 are overridden by the BLANK input. SYNC

= H activates, sync current from IOS for sync-on-green

video signals.

Figure 2. CDK3405 Current Source Structure

Digital Inputs

Incoming GBR data is regsitered on the rising edge of the

clock input, CLK. Analog outputs follow the rising edge of

CLK after a delay, tDO.

Clock Input - CLK

Pixel data is registered on the rising edge of CLK. CLK

should be driven by a dedicated buffer to avoid reection

induced jitter, overshoot, and undershoot.

Pixel Data Inputs - R7-0, B7-0, G7-0

RGB digital inputs are registered on the rising edge of CLK.

SYNC and BLANK

SYNC and BLANK inputs control the output level (Figure

3 and Table 1, on the previous page) of the D/A convert-

ers during CRT retrace intervals. BLANK forces the D/A

outputs to the blanking level while SYNC = L turns off a

current source, IOS, that is connected to the green D/A

converter. SYNC = H adds a 112/256 fraction of full-scale

current to the green output. SYNC = L extinguishes the

sync current during the sync tip.

BLANK gates the D/A inputs.

If BLANK = HIGH, the D/A

inputs control the output currents to be added to the out-

put blanking level. If BLANK = Low, data inputs and the

pedestal are disabled.

Data: 660mV max.

Pedestal: 54mV

Sync: 286mV

Figure 3. Normal Output Levels

Sync Pulse Input - SYNC

Bringing SYNC LOW, disables a current source which su-

perimposes a sync pulse on the IOG output. SYNC and

pixel data are registered on the rising edge of CLK. SYNC

does not override any other data and should be used only

during the blanking interval. If sync pulses are not re-

quired, SYNC should be connected to GND.

Blanking Input - BLANK

When BLANK is LOW, pixel data inputs are ignored and

the D/A converter outputs are driven to the blanking level.

BLANK is registered on the rising edge of CLK.

D/A Outputs

Each D/A output is a current source from the VDDA supply.

Expressed in current units, the GBR transformation from

data to current is as follows:

G = G7-0 & BLANK + SYNC * 112

B = B7-0 & BLANK

R = R7-0 & BLANK

Typical LSB current step is 73.2μA. To obtain a voltage

output, a resistor must be connected to ground. Output

voltage depends upon this external resistor, the reference

voltage, and the value of the gain-setting resistor con-

nected between RREF and GND.

To implement a doubly-terminated 75Ω transmission line,

a shunt 75Ω resistor should be placed adjacent to the

analog output pin. With a terminated 75Ω line connected

to the analog output, the load on the CDK3405 current

source is 37.5Ω.

VDDA

SYNC

VDDA

G7-0

B7-0

VDDA

R7-0

IOS

VAA

Data Sheet

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

The CDK3405 may also be operated with a single 75Ω

terminating resistor. To lower the output voltage swing

to the desired range, the nominal value of the resistor on

RREF should be doubled.

R, G, and B Current Outputs - IOR, IOG, IOB

Current source outputs can drive VESA VSIS, and RS-

343A/SMPTE-170M compatible levels into doubly-termi-

nated 75Ω lines. Sync pulses can be added to the green

output. When SYNC is HIGH, the current added to IOG is:

IOS = 2.33 (VREF/ RREF)

Current-Setting Resistor - RREF

Full-scale output current of each D/A converter is deter-

mined by the value of the resistor connected between

RREF and GND. Nominal value of RREF is found from:

RREF = 5.31 (VREF/IFS)

where IFS is the full-scale (white) output current (in amps)

from the D/A converter (without sync). Sync is 0.439 * IFS.

D/A full-scale (white) current may also be calculated from:

IFS = VFS/RL

Where VFS is the white voltage level and RL is the total

resistive load (Ω) on each D/A converter. VFS is the blank

to full-scale voltage.

Voltage Reference

Full scale current is a multiple of the current ISET through

an external resistor, RSET connected between the RREF pin

and GND. Voltage across RSET is the reference voltage,

VREF, which can be derived from either the 1.25 volt in-

ternal bandgap reference or an external voltage reference

connected to VREF. To minimize noise, a 0.1μF capacitor

should be connected between VREF and ground. ISET is

mirrored to each of the GBR output current sources. To

minimize noise, a 0.1μF capacitor should be connected

between the COMP pin and the analog supply voltage VAA.

Voltage Reference Output/Input - VREF

An internal voltage source of +1.25V is output on the VREF

pin. An external +1.25V reference may be applied to over-

ride the internal reference. Decoupling VREF to GND with

a 0.1µF ceramic capacitor is required.

Power and Ground

Required power is a single +3.3V supply. To minimize power

supply induced noise, analog +3.3V should be connected

to all three supply pins with 0.1µF and 0.01µF decoupling

capacitors placed adjacent to each VAA pin or pin pair.

The high slew-rate of digital data makes capacitive cou-

pling to the outputs of any D/A converter a potential

problem. Since the digital signals contain high-frequency

components of the CLK signal, as well as the video out-

put signal, the resulting data feedthrough often looks

like harmonic distortion or reduced signal-to-noise perfor-

mance. All ground pins should be connected to a common

solid ground plane for best performance.

Data Sheet

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

Applications Dicussion

Figure 9 (on the following page) illustrates a typical CDK3405

interface circuit. In this example, an optional 1.2V band-

gap reference is connected to the VREF output, overriding

the internal voltage reference source.

Grounding

It is important that the CDK3405 power supply is well-

regulated and free of high-frequency noise. Careful power

supply decoupling will ensure the highest quality video

signals at the output of the circuit. The CDK3405 has

separate analog and digital circuits. To keep digital system

noise from the D/A converter, it is recommended that power

supply voltages come from the system analog power

source and all ground connections (GND) be made to the

analog ground plane. Power supply pins should be indi-

vidually decoupled at the pin.

Printed Circuit Board Layout

Designing with high-performance mixed-signal circuits

demands printed circuits with ground planes. Overall

system performance is strongly inuenced by the board

layout. Capacitive coupling from digital to analog circuits

may result in poor D/A conversion. Consider the following

suggestions when doing the layout:

1. Keep the critical analog traces (VREF, IREF, COMP, IOS,

IOR, IOG) as short as possible and as far as possible

from all digital signals. The CDK3405 should be

located near the board edge, close to the analog out-put

connectors.

2. The power plane for the CDK3405 should be separate

from that which supplies the digital circuitry. A single

power plane should be used for all of the VAA pins. If

the power supply for the CDK3405 is the same

as that of the system’s digital circuitry, power to the

CDK3405 should be decoupled with 0.1µF and

0.01µF capacitors and isolated with a ferrite bead.

3. The ground plane should be solid, not cross-hatched.

Connections to the ground plane should have very short

leads.

4. If the digital power supply has a dedicated power plane

layer, it should not be placed under the CDK3405,

the voltage reference, or the analog outputs. Capacitive

coupling of digital power supply noise from this layer

to the CDK3405 and its related analog circuitry can

have an adverse effect on performance.

5. CLK should be handled carefully. Jitter and noise on this

clock will degrade performance. Terminate the clock line

carefully to eliminate overshoot and ringing.

Improved Transisiton Times

Output shunt capacitance dominates slowing of output

transition times, whereas series inductance causes a small

amount of ringing that affects overshoot and settling time.

With a doubly terminated 75Ω load, transition times can

be improved by matching the capacitive impedance output

of the CDK3405. Output capacitance can be matched with

a 220nH inductor in series with the 75Ω source termination.

Figure 4. Schematic, Transition Time Sharpening Circuit

A 220nH inductor trims the performance of a 4ft cable,

quite well. In Figures 5 through 8, the glitch at 12.5ns, is

due to a reection from the source. Not shown, are smaller

glitches at 25 and 37.5ns, corresponding to secondary and

tertiary reections. Inductor values should be selected to

match the length and type of the cable.

CDK3405

75Ω

COAX

220nH

75Ω

IOG

IOB

IOR

Data Sheet

CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B

Figure 5. Unmatched tR

Figure 6. Matched tR

Figure 7. Unmatched tF

Figure 8. Matched tF

-5 0 5 10 15 20

0.8

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Time (ns)

ROUT (V)

-5 0 5 10 15 20

0.8

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Time (ns)

GOUT (V)

-5 0 5 10 15 20

0.8

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Time (ns)

GOUT (V)

-5 0 5 10 15 20

0.8

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Time (ns)

GOUT (V)

Figure 9. Typical Interface Circuit Diagram

Evaluation boards are available (CEB3405), contact CADEKA for more information.