1
GAL22LV10
Low Voltage E2CMOS PLD
Generic Array Logic™
228
NC
I/CLK
I
I
I
I
I
I
I
I
NC NC
NC
GND
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q I/O/Q
426
25
19
18
21
23
161412
11
9
7
5
Features
•HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—4 ns Maximum Propagation Delay
—Fmax = 250 MHz
—3 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
•3.3V LOW VOLT AGE 22V10 ARCHITECTURE
—JEDEC-Compatible 3.3V Interface Standard
—5V Compatible Inputs
—I/O Interfaces with Standard 5V TTL Devices
(GAL22LV10C)
•ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
•E
2 CELL TECHNOLOGY
—Reconfigurable Logic
—Reprogrammable Cells
—100% Tested/100% Y ields
—High Speed Electrical Erasure (<100ms)
—20 Year Data Retention
•TEN OUTPUT LOGIC MACROCELLS
—Maximum Flexibility for Complex Logic Designs
—Programmable Output Polarity
•PRELOAD AND POWER-ON RESET OF ALL REGISTERS
—100% Functional Testability
•APPLICATIONS INCLUDE:
—Glue Logic for 3.3V Systems
—DMA Control
—State Machine Control
—High Speed Graphics Processing
—Standard Logic Speed Upgrade
•ELECTRONIC SIGNATURE FOR IDENTIFICA TION
PROGRAMMABLE
AND-ARRAY
(132X44)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/CLK
I
I
I
I
I
I
I
I
I
I
RESET
PRESET
8
10
12
14
16
16
14
12
10
8OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
GAL22LV10
Top View
PLCC
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. June 2002
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Description
The GAL22L V10D, at 4 ns maximum propagation delay time, pro-
vides the highest speed performance available in the PLD market.
The GAL22L V10C can interface with both 3.3V and 5V signal levels.
The GAL22LV10 is manufactured using Lattice Semiconductor's
advanced 3.3V E2CMOS process, which combines CMOS with
Electrically Erasable (E2) floating gate technology . High speed erase
times (<100ms) allow the devices to be reprogrammed quickly and
efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
22lv10_05
New 5V
Tolerant
Inputs on
22LV10D
Functional Block Diagram
Pin Configuration
Specifications GAL22LV10
2
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
433 031JL4-D01VL22LAGCCLPdaeL-82
55.35.3031JL5-D01VL22LAGCCLPdaeL-82
5.75.6557JL7-C01VL22LAGCCLPdaeL-82
015.75.657JL01-C01VL22LAGCCLPdaeL-82
51010157JL51-C01VL22LAGCCLPdaeL-82
Blank = Commercial
Grade
Package
PowerL = Low Power
Speed (ns)
XXXXXXXX XX X X X
Device Name
_
J = PLCC
GAL22LV10D
GAL22LV10C
GAL22LV10 Ordering Information
Commercial Grade Specifications
Part Number Description
Specifications GAL22LV10
3
GAL22LV10 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the GAL22LV10 has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (SO and S1), which are nor-
mally controlled by the logic compiler . Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’ s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register , and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer . Both polarities (true and inverted)
of the pin are fed back into the AND array.
The GAL22LV10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 17 and 27), two have ten product terms
(pins 18 and 26), two have twelve product terms (pins 19 and 25),
two have fourteen product terms (pins 20 and 24), and two OLMCs
have sixteen product terms (pins 21 and 23). In addition to the
product terms available for logic, each OLMC has an additional
product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
The GAL22L V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
AR
SP
D
Q
QCLK
4 TO 1
MUX
2 TO 1
MUX
Output Logic Macrocell (OLMC)
Output Logic Macrocell Configurations
Specifications GAL22LV10
4
ACTIVE HIGHACTIVE LOW
ACTIVE HIGHACTIVE LOW
S0 = 1
S1 = 1
S0 = 0
S1 = 1
S0 = 0
S1 = 0 S0 = 1
S1 = 0
AR
SP
D
Q
Q
CLK
AR
SP
D
Q
Q
CLK
Registered Mode
Combinatorial Mode
Specifications GAL22LV10
5
PLCC Package Pinout
2
26
OLMC
S0
5810
S1
5811
0440
.
.
.
.
0880
3
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0481216202428323640
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
12
0000
5764
0044
.
.
.
0396
27
S0
5808
S1
5809
25
OLMC
S0
5812
S1
5813
0924
.
.
.
.
.
1452
4
5
6
24
OLMC
S0
5814
S1
5815
1496
.
.
.
.
.
.
2112
23
OLMC
S0
5816
S1
5817
2156
.
.
.
.
.
.
.
2860
21
OLMC
S0
5818
S1
5819
2904
.
.
.
.
.
.
.
3608
20
OLMC
S0
5820
S1
5821
3652
.
.
.
.
.
.
4268
OLMC
S0
5822
S1
5823
4312
.
.
.
.
.
4840
10
19
18
OLMC
S0
5824
S1
5825
4884
.
.
.
.
5324
11
5368
.
.
.
5720
17
OLMC
S0
5826
S1
5827
9
7
13 16
8
10
14
16
12
12
16
14
10
8
OLMC
Electronic Signature 5828, 5829 ... ... 5890, 5891
L
S
B
M
S
B
Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3
GAL22LV10 Logic Diagram/JEDEC Fuse Map
Specifications GAL22LV10
6
Specifications GAL22LV10D
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. V out = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 3.3V and TA = 25 °C
COMMERCIAL
ICC Operating Power VIL = 0V VIH = 3.0V Unused Inputs at VIL —90130 mA
Supply Current ftoggle = 1MHz Outputs Open
VIL Input Low V oltage Vss - 0.3 — 0.8 V
VIH Input High V oltage 2.0 — 5.25 V
I/O High V oltage 2.0 — Vcc+0.5 V
IIL1Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -100 µA
IIH Input or I/O High Leakage Current (Vcc-0.2)V ≤ VIN ≤ VCC ——10µA
Input High Leakage Current Vcc ≤ VIN ≤ 5.25V — — 10 µA
I/O High Leakage Current Vcc ≤ VIN ≤ 4.6V — — 20 mA
VOL Output Low V oltage IOL = MAX. Vin = VIL or VIH ——0.4 V
IOL = 500µA Vin = VIL or VIH ——0.2 V
VOH Output High V oltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOH = -100µA Vin = VIL or VIH Vcc-0.2V — — V
IOL Low Level Output Current — — 8 mA
IOH High Level Output Current — — –8 mA
IOS2Output Short Circuit Current VCC = 3.3V VOUT = 0.5V TA= 25°C-15 — -80 mA
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (TA)...............................0 to 75°C
Supply voltage (VCC)
with Respect to Ground ......................... +3.0 to +3.6V
Absolute Maximum Ratings(1)
Supply voltage VCC .................................... -0.5 to +4.6V
Input voltage applied ................................. -0.5 to +5.6V
I/O voltage applied .................................... -0.5 to +4.6V
Off-state output voltage applied ................ -0.5 to +4.6V
Storage Temperature .................................-65 to 150°C
Ambient Temperature with
Power Applied .........................................-55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
SYMBOL PARAMETER CONDITION MIN. TYP.3MAX. UNITS
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
Specifications GAL22LV10
7
Specifications GAL22LV10D
-5
MIN. MAX.
tpd2AInput or I/O to Combinational Output 1 4 1 5 ns
tco2AClock to Output Delay 1 3 1 3.5 ns
tcf3—Clock to Feedback Delay — 2.5 — 3 ns
tsu — Setup Time, Input or Feedback before Clock↑3—3.5 — ns
th—Hold T ime, Input or Feedback after Clock↑0—0 —ns
AMaximum Clock Frequency with 167 — 143 — MHz
External Feedback, 1/(tsu + tco)
fmax4AMaximum Clock Frequency with 182 — 154 — MHz
Internal Feedback, 1/(tsu + tcf)
AMaximum Clock Frequency with 250 — 200 — MHz
No Feedback
twh4—Clock Pulse Duration, High 2 — 2.5 — ns
twl4—Clock Pulse Duration, Low 2 — 2.5 — ns
ten B Input or I/O to Output Enabled 1 5 1 6 ns
tdis C Input or I/O to Output Disabled 1 5 1 6 ns
tar A Input or I/O to Asynchronous Reset of Register 1 4.5 1 5.5 ns
tarw — Asynchronous Reset Pulse Duration 4.5 — 5.5 — ns
tarr — Asynchronous Reset to Clock ↑ Recovery T ime 3.5 — 4 — ns
tspr — Synchronous Preset to Clock ↑ Recovery T ime 3.5 — 4 — ns
-4
MIN. MAX. UNITSPARAMETER TEST
COND1.DESCRIPTION
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIInput Capacitance 5 pF VCC = 3.3V, VI = 0V
CI/O I/O Capacitance 5 pF VCC = 3.3V, VI/O = 0V
1) Refer to Switching Test Conditions section.
2) Minimum values for tpd and tco are not 100% tested but established by characterization.
3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
4) Refer to fmax Descriptions section. Characterized but not 100% tested.
COM
COM
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (TA = 25°C, f = 1.0 MHz)
Specifications GAL22LV10
8
Specifications GAL22LV10C
Absolute Maximum Ratings(1)
Supply voltage VCC .................................... -0.5 to +5.6V
Input voltage applied ................................. -0.5 to +5.6V
Off-state output voltage applied ................ -0.5 to +5.6V
Storage Temperature .................................-65 to 150°C
Ambient Temperature with
Power Applied .........................................-55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (TA).............................0 to +75°C
Supply voltage (VCC)
with Respect to Ground ......................... +3.0 to +3.6V
Industrial Devices:
Ambient Temperature (TA)..........................-40 to +85°C
Supply voltage (VCC)
with Respect to Ground ......................... +3.0 to +3.6V
VIL Input Low V oltage Vss – 0.5 —0.8 V
VIH Input High V oltage 2.0 — 5.25 V
IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -10 µA
IIH Input or I/O High Leakage Current (VCC - 0.2)V ≤ VIN ≤ VCC ——10µA
VCC ≤ VIN ≤ 5.25V——30mA
VOL Output Low V oltage IOL = 8mA Vin = VIL or VIH ——0.4 V
IOL = 16 mA Vin = VIL or VIH ——0.5 V
IOL = 0.5 mA Vin = VIL or VIH ——0.2 V
VOH Output High V oltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOH = -0.5 mA Vin = VIL or VIH Vcc-0.45 — — V
IOH = -100 µA Vin = VIL or VIH Vcc-0.2 — — V
IOL Low Level Output Current VOL = 0.4 V — — 8 mA
VOL = 0.5V — — 16 mA
IOH High Level Output Current — — -4 mA
IOS1Output Short Circuit Current VCC = 3.3V VOUT = 0.5V TA = 25°C-15—-60 mA
SYMBOL PARAMETER CONDITION MIN. TYP.2MAX. UNITS
1) One output at a time for a maximum duration of one second. V out = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2) Typical values are at Vcc = 3.3V and TA = 25 °C
COMMERCIAL
ICC Operating Power VIL = 0.0V VIH = 3.0V — 45 75 mA
Supply Current ftoggle = 1MHz Outputs Open
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
INDUSTRIAL
ICC Operating Power VIL = 0.0V VIH = 3.0V -15 — 65 95 mA
Supply Current ftoggle = 1MHz Outputs Open
Specifications GAL22LV10
9
Specifications GAL22LV10C
tpd2AInput or I/O to Combinatorial Output 2 7.5 2 10 2 15 ns
tco2AClock to Output Delay 1 5 1 6.5 1 10 ns
tcf3—Clock to Feedback Delay — 3 — 5 — 5 ns
tsu — Setup Time, Input or Fdbk before Clk↑6—7.5 — 10 — ns
th—Hold T ime, Input or Fdbk after Clk↑0—0—0—ns
AMaximum Clock Frequency with 91 — 71 — 50 — MHz
External Feedback, 1/(tsu + tco)
fmax4AMaximum Clock Frequency with 11 1 — 80 — 66 — MHz
Internal Feedback, 1/(tsu + tcf)
AMaximum Clock Frequency with 125 — 1 11 — 83 — MHz
No Feedback
twh — Clock Pulse Duration, High 3.5 — 4 — 6 — ns
twl — Clock Pulse Duration, Low 3.5 — 4 — 6 — ns
ten B Input or I/O to Output Enabled 2 10 2 12 2 15 ns
tdis C Input or I/O to Output Disabled 2 10 2 12 2 15 ns
tar A Input or I/O to Asynch. Reset of Reg. 2 11 2 13 2 20 ns
tarw — Asynch. Reset Pulse Duration 6 — 8 — 10 — ns
tarr — Asynch. Reset to Clk↑ Recovery T ime 6 — 8 — 10 — ns
tspr — Synch. Preset to Clk↑ Recovery T ime 6 — 8 — 10 — ns
-15
MIN. MAX.
-10
MIN. MAX. UNITS
PARAM TEST
COND.1DESCRIPTION
COM
COM
-7
MIN. MAX.
COM
1) Refer to Switching Test Conditions section.
2) Minimum values for tpd and tco are not 100% tested but established by characterization.
3) Calculated from fmax with internal feedback. Refer to fmax Description section.
4) Refer to fmax Description section.
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIInput Capacitance 8 pF VCC = 3.3V, VI = 0V
CI/O I/O Capacitance 8 pF VCC = 3.3V, VI/O = 0V
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (TA = 25°C, f = 1.0 MHz)
Specifications GAL22LV10
10
Input or I/O to Output Enable/Disable
Registered Output
Combinatorial Output
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
su
t
co
t
h
(external fdbk)
1/
f
max
CLK
(w/o fdbk)
t
wh
t
wl
1/
f
max
Clock Width
REGISTERED
OUTPUT
CLK
t
arw
t
ar
t
arr
INPUT or
I/O FEEDBACK
DRIVING AR
fmax with Feedback
CLK
REGISTERED
FEEDBACK
t
cf
t
su
1/
f
max (internal fdbk)
Asynchronous ResetSynchronous Preset
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATORIAL
OUTPUT
REGISTERED
OUTPUT
CLK
INPUT or
I/O FEEDBACK
DRIVING SP
t
su
t
h
t
co
t
spr
Switching Waveforms
Specifications GAL22LV10
11
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
REGISTER
LOGIC
ARRAY
CLK
tsu + th
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
fmax Descriptions
Specifications GAL22LV10
12
*CL includes test fixture and probe capacitance.
TEST POINT
Z
0
= 50Ω, C
L
= 35pF*
FROM OUTPUT (O/Q)
UNDER TEST
+1.45V
R
1
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 1.5ns 10% – 90%
Input Timing Reference Levels 1.5V
Output T iming Reference Levels 1.5V
Output Load See Figure
Output Load Conditions (see figure)
Test Condition R1CL
A50Ω35pF
BHigh Z to Active High at 1.9V 50Ω35pF
High Z to Active Low at 1.0V 50Ω35pF
CActive High to High Z at 1.9V 50Ω35pF
Active Low to High Z at 1.0V 50Ω35pF
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 2.0ns 10% – 90%
Input Timing Reference Levels 1.5V
Output T iming Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition R1R2CL
A316Ω348Ω35pF
BActive High 316Ω348Ω35pF
Active Low 316Ω348Ω35pF
CActive High 316Ω348Ω5pF
Active Low 316Ω348Ω5pF
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+3.3V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
GAL22LV10D: Switching Test Conditions
GAL22LV10C: Switching Test Conditions
Specifications GAL22LV10
13
Electronic Signature
An electronic signature (ES) is provided in every GAL22LV10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is al-
ways available to the user independent of the state of the security
cell.
The electronic signature is an additional feature not present in other
manufacturers' 22V10 devices. To use the extra feature of the user-
programmable electronic signature it is necessary to choose a
Lattice Semiconductor 22V10 device type when compiling a set of
logic equations. In addition, many device programmers have two
separate selections for the device, typically a GAL22LV10 and a
GAL22V10-UES (UES = User Electronic Signature) or GAL22V10-
ES. This allows users to maintain compatibility with existing 22V10
designs, while still having the option to use the GAL device's ex-
tra feature.
The JEDEC map for the GAL22LV10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However , the
GAL22L V10 device can still be programmed with a standard 22V10
JEDEC map (5828 fuses) with any qualified device programmer .
Security Cell
A security cell is provided in every GAL22L V10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user , regardless of the state of this control cell.
Latch-Up Protection
GAL22L V10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of suf ficient
magnitude to prevent input undershoots from causing the circuitry
to latch.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user , and is done automatically as
part of the programming cycle.
Typical Input Pull-up Characteristic
Input Voltage (V)
Input Current (µA)
-80
-70
-60
-50
-40
-30
-20
-10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Register Preload
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL22L V10 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low . Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
Input Buffers
GAL22L V10 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
The input and I/O pins on the GAL22L V10D also have built-in active
pull-ups. As a result, floating inputs will float to a TTL high (logic
1). However , Lattice Semiconductor recommends that all unused
inputs and tri-stated I/O pins be connected to an adjacent active
input, Vcc, or ground. Doing so will tend to improve noise immu-
nity and reduce Icc for the device. (See equivalent input and I/O
schematics on the following page.)
Specifications GAL22LV10
14
Typ. V ref = Vcc
Typical Output
Typ. Vref = Vcc
Typical Input
Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr , 1µs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below . Because of the asyn-
chronous nature of system power-up, some conditions must be
met to provide a valid power-up reset of the GAL22V10. First, the
Vcc rise must be monotonic. Second, the clock input must be at
static TTL level as shown in the diagram during power up. The
registers will reset within a maximum of tpr time. As in normal sys-
tem operation, avoid clocking the device until all input and feed-
back path setup times have been met. The clock must also meet
the minimum pulse width requirements.
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up Circuit
(GAL22LV10D Only)
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Vcc
PIN
Vcc Vref
Active Pull-up Circuit
(GAL22LV10D Only)
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc (min.)
tpr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
twl
tsu
Device Pin
Reset to Logic "0"
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Power-Up Reset
Input/Output Equivalent Schematics
Specifications GAL22LV10
15
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.95
0.975
1
1.025
1.05
3.00 3.15 3.30 3.45 3.60
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55 -25 0 25 5075100125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-0.5
-0.4
-0.3
-0.2
-0.1
0
12345678910
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-0.5
-0.4
-0.3
-0.2
-0.1
0
12345678910
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-8
-4
0
4
8
12
16
20
050100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-4
0
4
8
12
16
20
050100150200 250 300
RISE
FALL
GAL22LV10D: Typical AC and DC Characteristic Diagrams
Specifications GAL22LV10
16
Vol vs Iol
Iol (mA)
Vol (V)
0
0.2
0.4
0.6
0.8
1
0.00 5.00 10.00 15.00 20.00 25.00 30.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
0.00 5.00 10.00 15.00 20.00
Voh vs Ioh
Ioh(mA)
Voh (V)
2.7
2.8
2.9
3
3.1
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.60
0.80
1.00
1.20
1.40
3.00 3.15 3.30 3.45 3.60
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 5075100 125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
1.00
1.05
1.10
1.15
1.20
1.25
1.30
0255075100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
1
2
3
4
5
6
7
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
5
10
15
20
25
30
35
-2.00 -1.50 -1.00 -0.50 0.00
GAL22LV10D: Typical AC and DC Characteristic Diagrams
Specifications GAL22LV10
17
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.95
0.975
1
1.025
1.05
3.00 3.15 3.30 3.45 3.60
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 5075100 125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 5075100 125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55 -25 0 25 5075100 125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-0.5
-0.4
-0.3
-0.2
-0.1
0
12345678910
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-0.5
-0.4
-0.3
-0.2
-0.1
0
12345678910
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-8
-4
0
4
8
12
16
20
24
28
050100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-6
-2
2
6
10
14
18
22
26
050100 150 200 250 300
RISE
FALL
GAL22LV10C: Typical AC and DC Characteristic Diagrams
Specifications GAL22LV10
18
Vol vs Iol
Iol (mA)
Vol (V)
0
0.2
0.4
0.6
0.8
1
0.00 10.00 20.00 30.00 40.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
0.00 5.00 10.00 15.00 20.00
Voh vs Ioh
Ioh(mA)
Voh (V)
2.7
2.8
2.9
3
3.1
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.60
0.80
1.00
1.20
1.40
3.00 3.15 3.30 3.45 3.60
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
-55 -25 0 25 5075100 125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
1.00
1.20
1.40
1.60
1.80
0255075100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
1
2
3
4
5
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
-2.00 -1.50 -1.00 -0.50 0.00
GAL22LV10C: Typical AC and DC Characteristic Diagrams
