SST30VR043-150-E-WH - Silicon Storage Technology

S71134-04-000 12/03

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

ComboMemory is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

FEATURES:

• ROM + SRAM ROM/RAM Combo

– SST30VR041: 512K x8 ROM + 128K x8 SRAM

– SST30VR043: 512K x8 ROM + 32K x8 SRAM

• ROM/RAM combo on a monolithic chip

• Equivalent ComboMemory (Flash + SRAM):

SST31LF041A for code development and

pre-production

• Wide Ope rating Vo ltag e Range: 2.7-3.3V

• Chip Acce ss Time

– SST30VR041 70 ns and 150 ns

– SST30VR043 150 ns

• Low Power Dissipation:

– Standby: 1.0 µW (Typical)

– Operating : 3.0 mW (Typical)

• Fully Static Operation

– No clock or refresh required

• Three-state Outputs

• Packages Available

– 32-lead TSOP (8mm x1 4mm )

PRODUCT DESCRIPTION

The SST30VR041/043 are ROM/RAM combo chips

consisting of 4 Mbit Read-Only Memory (ROM) orga-

nized as 512 KByte and a Static Random Access

Memory (SRAM) or gan ized as ei ther 128 or 32 KBy te.

Output Enable Input (OE#) is pin-shared with

RAMCS # (RAM Ena ble Input) sign al in order to mai n-

tain the standard 32-lead TSOP package.

The d evice is fabricat e d us ing S S T’s advanc ed CM OS low

po wer pr ocess technolo g y.

The SST30VR041/043 ha ve an output enab le input f or pre-

cise control of the data outputs. It also has two (2) separate

chip enable inputs for selection of either SRAM or ROM

and f o r mini mizing c urren t dr ain during pow er- down mode .

The SS T30VR 041 /043 is p ar t icul arl y well suit ed for use i n

low voltage (2.7-3.3V) supplies such as pagers , organizers

and other handheld applications.

RAMCS#

OE#/RAMCS#

ROMCS#

WE#

AMS-A0

Note: AMS = Most Significant Address

DQ7-DQ0

ROMCS#

RAM

ROM

WE#

OE#

1134 B1.2

Control

Circuit

Address Buffer

Data Buffer

FUNCTIONAL BLOCK DIAGRAM

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR041 / SST30VR043

SST30VR041 / 0434Mb Mask ROM (x8) + 1Mb / 256Kb SRAM (x8) Combo

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD TSOP

TABLE 1: PIN DESCRIPTION

Symbol Pin Name

AMS1-A0

1. AMS = Most significant address

Address Inputs:

ROM: AMS =A

RAM: AMS =A

16 fo r SST30VR041

A14 for SST30VR043

WE# Write Enable Input

OE#/RAMCS# Output Enable/RAM Enable Input

ROMCS# ROM Enable Input

DQ7-DQ0Data Input/Output

VDD Power Supply

VSS Ground

T1.3 1134

A11

A13

A14

A17

WE#

VDD

A18

A16

A15

A12

OE#/RAMCS#

A10

ROMCS#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

1134 32-tsop P1.0

Standard Pinout

To p V i ew

Die Up

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operatio n

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Voltage on An y Pin Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Soldering Temperature (10 Seconds Lead Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

OPERATING RANGE

Range Ambient Te mp VDD

Commercial 0°C to +70°C 2.7-3.3V

Extended -20°C to +85°C 2.7-3.3V

AC CONDITIONS OF TEST

Input Pulse Level. . . . . . . . . . . . . . . . . . . . 0-VDD

Input & Output Timing Reference Levels . . . VDD/2

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 150 ns

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

TABLE 2: RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min Max Units

VDD Supply Voltage 2.7 3.3 V

VSS Ground 0 0 V

VIH Input High Voltage 2.4 VDD + 0.5 V

VIL Input Low Voltage -0.3 0.3 V

T2.0 1134

TABLE 3: DC OPERATING CHARACTERISTICS

Symbol Parameter

VDD = 2.7-3. 3V

Test ConditionsMin Max Units

IDD1 ROM Operating Supply Current 4.0+1.1(f)1

1. f = Frequency of operati on (MHz) = 1/cycle time

mA ROMCS#=VIL, RAMCS#=VIH,

VIN=VIH or VIL, II/O=Opens

IDD2 SRAM Operating Supply Current 2.5+1(f)1mA ROMCS#=VIH, RAMCS#= VIL, II/O=Opens

ISB Standby VDD Current 10 µA ROMCS# ≥ VDD-0.2V, RAMCS# ≥ VDD-0.2V

VIN ≥ VDD-0.2V or VIN ≤0.2V

ILI Input Leakage Current -1 1 µA VIN=VSS to VDD

ILO Output Leakage Current -1 1 µA ROMCS#=RAMCS#=VIH or OE#=VIH or

WE#=VIL, VI/O=VSS to VDD

VOL Output Low Voltage 0.4 V IOL=1.0 mA

VOH Output High Voltage 2.2 V IOH=-0.5 mA

T3.5 1134

TABLE 4: CAPACITANCE (Ta = 25°C, f=1 Mhz)

P a rame ter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualif ication and after a design or proc es s change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 8 pF

CIN1Input Capacitance VIN = 0V 6 pF

T4.1 1134

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 3: A TEST LOAD EXAMPLE

1134 F07.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

A C test inputs are driven at VIHT (0.9 VDD) for a l ogic “1” and VILT (0.1 VDD) f or a logi c “0”. Measu rement reference points

f or inputs and outputs are VIT (0.5 VDD) and V OT (0.5 VDD). Input rise and f all times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LO W Test

1134 F08.0

TO TESTER

TO DUT

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

AC CHARACTERISTICS

I. ROM Operation

FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = OE# = VIL)

FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# & OE# CONTROLLED)

TABLE 5: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V

Symbol Parameter

SST30VR041-70 SST30VR041/043-150

UnitsMin Max Min Max

TRC Read Cycle Time 70 150 ns

TAA Address Access Time 70 150 ns

TCO Chip Select to Output 70 150 ns

TOE Output Enable to Valid Output 35 70 ns

TLZ Chip Select to Low-Z Output 0 0 ns

TOLZ Output Enable to Low-Z Output 0 0 ns

THZ Chip Disable to High-Z Output 25 30 ns

TOHZ Output Disable to High-Z Output 25 30 ns

TOH Output Hold from Address Change 10 15 n s

T5.2 1134

TRC

TAA

Data Valid

1134 F02.0

Data Out Previous Data Valid

Address

TOH

TRC

TAA

TCO

TLZ(2) TOHZ(1)

TOH

THZ(1,2)

Data Valid

1134 F03.0

Data Out

OE#

ROMCS#

High-Z

Address

TOE

TOLZ

Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition

and are referenced to the VOH or VOL.

2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given

device and from device to device.

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

II. SRAM Operation (ROMCS# = VIH)

TABLE 6: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V

Symbol Parameter

SST30VR041-70 SST30VR041/043-150

UnitsMin Max Min Max

TRC Read Cycle Time 70 150 ns

TAA Address Access Time 70 150 ns

TCO Chip Select to Output 70 150 ns

TLZ Chip Select to Low-Z Output 0 0 ns

THZ Chip Disable to High-Z Output 25 30 ns

TOH Output Hold from Address Change 10 15 n s

T6.2 1134

TABLE 7: WRITE CYCLE TIMING PARAMETERS VDD = 2.7-3.3V

Symbol Parameter

SST30VR041-70 SST30VR041/043-150

UnitsMin Max Min Max

TWC Write Cycle Time 70 150 ns

TCW Chip Select to End-of-Write 60 120 ns

TAW Address Valid to End-of-Write 60 120 ns

TAS Address Set-up Time 0 0 ns

TWP Write Pulse Width 60 120 ns

TWR Write Recovery Time 0 0 ns

TWHZ Write to Output High-Z 30 60 ns

TDW Data to Write Time Overlap 30 60 ns

TDH Data Hold from Write Time 0 0 ns

TOW End Write to Output Low-Z 0 10 ns

T7.2 1134

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE#/RAMCS# = VIL, WE# = V IH)

FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE#/RAMCS# CONTROLLED)

TRC

TAA

Data Valid

1134 F04.0

Data Out Previous Data Valid

Address

TOH

TRC

TAA

TCO

TLZ(2) TOH

THZ(1,2)

Data Valid

1134 F05.0

Data Out

OE#/RAMCS#

High-Z

Address

Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition

and are referenced to the VOH or VOL.

2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given

device and from device to device.

3. WE# is high for Read cycle.

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM

TWC

TAW

TCW(2)

TOH

TDH

TDW

TOW

TWR(4)

Data Valid

1134 F06.0

Data In

Data Out

WE#

OE#/RAMCS#

High-Z

High-Z (6) (7) (8)

Address

TWP(1)

TAS(3)

TWHZ(5)

Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among

RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high,

WP is measured from the beginning of write to the end of write.

2. TCW is measured from the later of RAMCS# going low to the end of write.

3. TAS is measured from the address valid to the beginning of write.

4. TWR is measured from the end of write to the address change.

5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state.

Inputs of opposite phase of the output must not be applied because bus contention can occur.

6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state.

7. DOUT is the same phase of the latest written data in this write cycle.

8. DOUT is the read data of new address

9. ROMCS# = VIH

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE

Address Inputs ROMCS# OE#/RAMCS#1

(Pin 32) WE# DQ7-DQ0

X2VIH VIH X Z Standby

AMS3-A0VIL OE# (H) X Z Output Floating

VIL OE# (L) X DOUT ROM Read

Only AMS4-A0 are valid VIH RAMCS# (L) VIH DOUT RAM Read

VIH RAMCS# (L) VIL DIN RAM Write

T8.4 1134

1. OE# & RAMCS# are pin-shared

2. X can be VIL or VIH, but no other value.

3. For ROM: AMS = A18 for SST30VR041 and SST30VR043

4. For SRAM: AMS = A16 for SST30VR041, A18-A17 must be fixed to “VIL” or “VIH”

AMS = A 14 for SST30VR043, A18-A15 must be fixed to “VIL” or “VIH”

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

PRODUCT ORDERING INFORMATION

Valid combinations for SST30VR041

SST30VR041-70-C-WH

SST30VR041-150-C-WH

SST30VR041-70-E-WH

SST30VR041-150-E-WH

Valid combinations for SST30VR043

SST30VR043-150-C-WH

SST30VR043-150-E-WH

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Package Modifier

H = 32 leads

Package T ype

W = TSOP (type 1, die up , 8mm x 14mm)

Temper atu re Rang e

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

Read Access Speed

70 = 70 ns

150 = 150 ns

Device Density

041 = 4 Mbit ROM + 1 Mbit SRAM

043 = 4 Mbit ROM + 256 Kbit SRAM

Voltage Range

V = 2.7-3.3V

Product Series

30 = ROM/RAM Combo

Device Speed Suffix1 Suffix2

SST30VR0xx -XXX -X -XX

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Data Sheet

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

PACKAGING DIAGRAMS

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

TABLE 9: REVISION HISTORY

Number Description Date

02 •2002 Data Book Feb 2002

03 •Added Revision History Aug 2003

04 •2004 Data Book Dec 2003

32-tsop-WH-7

Note: 1.Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2.All linear dimensions are in millimeters (max/min).

3.Coplanarity: 0.1 mm

4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0˚- 5˚

DETAIL

Silicon Stor age Technol ogy, Inc. • 1171 Sonor a Court • Sunnyvale, CA 94086 • Telephone 408-73 5-91 10 • Fax 408-735-90 36

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