SCLS121D − DECEMBER 1982 − REVISED OCT OBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DWide Operating Voltage Range of 2 V to 6 V
DOutputs Can Drive Up To 10 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 13 ns
D±4-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
DSingle Down/Up Count-Control Line
DLook-Ahead Circuitry Enhances Speed of
Cascaded Counters
DFully Synchronous in Count Modes
DAsynchronously Presettable With Load
Control
description/ordering information
The ’HC191 devices are 4-bit synchronous,
reversible, up/down binary counters.
Synchronous counting operation is provided by
having all flip-flops clocked simultaneously so that
the outputs change coincident with each other
when instructed by the steering logic. This mode
of operation eliminates the output counting spikes
normally associated with asynchronous
(ripple-clock) counters.
The outputs of the four flip-flops are triggered on
a low- to high-level transition of the clock (CLK)
input if the count-enable (CTEN) input is low. A
high at CTEN inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U) input. When D/U is l o w, the counter
counts up, and when D/U is high, it counts down.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74HC191N SN74HC191N
Tube of 40 SN74HC191D
−40°C to 85°CSOIC − D Reel of 2500 SN74HC191DR HC191
−40 C to 85 C
SOIC − D
Reel of 250 SN74HC191DT
HC191
SOP − NS Reel of 2000 SN74HC191NSR HC191
CDIP − J Tube of 25 SNJ54HC191J SNJ54HC191J
−55°C to 125°CCFP − W Tube of 150 SNJ54HC191W SNJ54HC191W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC191FK SNJ54HC191FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
QB
QA
CTEN
D/U
QC
QD
GND
VCC
A
CLK
RCO
MAX/MIN
LOAD
C
D
SN54HC191 ...J OR W PACKAGE
SN74HC191 . . . D, N, OR NS PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
CLK
RCO
NC
MAX/MIN
LOAD
QA
CTEN
NC
D/U
QC
Q
B
NC
D
CV
A
D
GND
NC
SN54HC191 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
B
CC
Q
Copyright 2003, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
&)$#!" #&(! ! 012343 (( &%!%" % !%"!%)
$(%"" !+%-"% !%)* (( !+% &)$#!" &)$#!
&#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"*
SCLS121D − DECEMBER 1982 − REVISED OCT OBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that
modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter is dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a
low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with
the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N
dividers simply by modifying the count length with the preset inputs.
Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum
(MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one
complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15)
counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low.
The counters can be cascaded easily by feeding RCO to CTEN of the succeeding counter if parallel clocking
is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed
operation.
SCLS121D − DECEMBER 1982 − REVISED OCT OBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
Pin numbers shown are for the D, J, N, NS, and W packages.
SC1
1D
R
7
9
SC1
1D
R
6
10
SC1
1D
R
2
1
SC1
1D
R
3
15
11
14
5
4
12
13
QA
QB
QC
QD
RCO
CTEN
D/U
LOAD
MAX/MIN
CLK
A
B
C
D
SCLS121D − DECEMBER 1982 − REVISED OCT OBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical load, count, and inhibit sequence
The following sequence is illustrated below:
1. Load (preset) to binary 13
2. Count up to 14, 15 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 15, 14, and 13
Data
Inputs
Data
Outputs
LOAD
A
B
C
D
CLK
D/U
CTEN
MAX/MIN
QA
QB
QC
QD
Load
Count Up Inhibit
13 14 15 0 1 2
RCO
Count Down
2210151413
SCLS121D − DECEMBER 1982 − REVISED OCT OBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC191 SN74HC191
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 3.15 V
VIH
High-level input voltage
VCC = 6 V 4.2 4.2
V
VCC = 2 V 0.5 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VIL
Low-level input voltage
VCC = 6 V 1.8 1.8
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
∆t/∆v‡Input transition rise/fall time VCC = 4.5 V 500 500 ns
∆t/∆v‡
Input transition rise/fall time
VCC = 6 V 400 400
ns
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
‡If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
SCLS121D − DECEMBER 1982 − REVISED OCT OBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC191 SN74HC191
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
I
OH
= −20 µA4.5 V 4.4 4.499 4.4 4.4
V
OH
V
I
= V
IH
or V
IL
IOH = −20 µA
6 V 5.9 5.999 5.9 5.9 V
VOH
VI = VIH or VIL
IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84
V
IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
I
OL
= 20 µA4.5 V 0.001 0.1 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
IOL = 20 µA
6 V 0.001 0.1 0.1 0.1 V
VOL
VI = VIH or VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
V
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci2 V to 6 V 3 10 10 10 pF
SCLS121D − DECEMBER 1982 − REVISED OCT OBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HC191 SN74HC191
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
2 V 4.2 2.8 3.3
f
clock
Clock frequency 4.5 V 21 14 17 MHz
fclock
Clock frequency
6 V 24 16 19
MHz
2 V 120 180 150
LOAD low 4.5 V 24 36 30
tw
Pulse duration
LOAD low
6 V 21 31 26
ns
twPulse duration 2 V 120 180 150 ns
CLK high or low 4.5 V 24 36 30
CLK high or low
6 V 21 31 26
2 V 150 230 188
Data before LOAD↑4.5 V 30 46 38
Data before LOAD↑
6 V 25 38 32
2 V 205 306 255
CTEN before CLK↑4.5 V 41 61 51
tsu
Setup time
CTEN before CLK↑
6 V 35 53 44
ns
tsu Setup time 2 V 205 306 255 ns
D/U before CLK↑4.5 V 41 61 51
D/U before CLK↑
6 V 35 53 44
2 V 150 225 190
LOAD inactive before CLK↑4.5 V 30 45 38
LOAD inactive before CLK↑
6 V 25 38 32
2 V 555
Data after LOAD↑4.5 V 555
Data after LOAD↑
6 V 555
2 V 555
t
h
Hold time CTEN after CLK↑4.5 V 555ns
th
Hold time
CTEN after CLK↑
6 V 555
ns
2 V 555
D/U after CLK↑4.5 V 555
D/U after CLK
6 V 555
SCLS121D − DECEMBER 1982 − REVISED OCT OBER 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HC191 SN74HC191
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 4.2 8 2.8 3.3
f
max
4.5 V 21 42 14 17 MHz
fmax
6 V 24 48 16 19
MHz
2 V 130 264 396 330
LOAD Any Q 4.5 V 40 53 79 66
LOAD
Any Q
6 V 33 45 67 56
QA, QB, QC,
2 V 135 240 360 300
A, B, C, or D QA, QB, QC,
or QD
4.5 V 36 48 72 60
A, B, C, or D
or QD
6 V 30 41 61 51
2 V 58 120 180 150
RCO 4.5 V 17 24 36 30
RCO
6 V 14 21 31 26
2 V 107 192 288 240
CLK Any Q 4.5 V 31 38 58 48
tpd
CLK
Any Q
6 V 26 32 49 41
ns
tpd 2 V 123 252 378 315 ns
MAX/MIN 4.5 V 39 50 76 63
MAX/MIN
6 V 32 43 65 54
2 V 102 228 342 285
RCO 4.5 V 29 46 68 57
D/U
RCO
6 V 24 38 59 49
D/U 2 V 86 192 288 240
MAX/MIN 4.5 V 24 38 58 48
MAX/MIN
6 V 20 32 49 41
2 V 50 132 198 165
CTEN RCO 4.5 V 15 26 40 33
CTEN
RCO
6 V 13 23 34 28
2 V 38 75 110 95
t
t
Any 4.5 V 8 15 22 19 ns
tt
Any
6 V 6 13 19 16
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 50 pF
SCLS121D − DECEMBER 1982 − REVISED OCT OBER 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50%
V
CC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VC
C
VO
H
VO
L
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VO
H
VO
L
tr
tf
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
are the same as t
pd
.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-86891012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
86891012A
SNJ54HC
191FK
5962-8689101EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8689101EA
SNJ54HC191J
SN54HC191J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC191J
SN74HC191D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191DE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191DRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191DT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191DTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191DTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC191N
SN74HC191N3 OBSOLETE PDIP N 16 TBD Call TI Call TI -40 to 85
SN74HC191NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC191N
SN74HC191NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SN74HC191NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC191NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC191
SNJ54HC191FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
86891012A
SNJ54HC
191FK
SNJ54HC191J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8689101EA
SNJ54HC191J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC191DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC191NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC191DR SOIC D 16 2500 333.2 345.9 28.6
SN74HC191NSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
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