S23
28 PIN SSOP PACKAGE
FEATURES
APPLICATIONS
ARA2001S23
CATV Reverse Amplifier with Step Attenuator
Advanced Product Information - Rev. 2
·Low cost integrated monolithic GaAs
amplifier with step attenuator.
·Attenuation Range: 0 58 dB, variable in
1 dB steps via 8 bit serial input.
·Meets DOCSIS distortion requirements at
+60 dBmV
·Low distortion & Low noise figure
·Frequency range: 5 100 MHz
·5 Volt operation
·MCNS/DOCSIS Compliant Cable Modems
·CATV Interactive Set-Top Box
·Telephony over Cable Systems
Description
The ARA2001S23 is a GaAs IC designed to provide the reverse path amplification and output level control
functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step
attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver
amplifier. This part is a balanced design that meets or exceeds the MCNS/DOCSIS requirement for
harmonic performance @ +60dBmV output levels while only requiring a single polarity +5V supply. Both the
input and output are matched to 75 ohms. The precision attenuator provides up to 58 dB of attenuation in 1
dB increments. The ARA2001S23 is supplied in a 28-pin SSOP package featuring a thermal heat slug on the
bottom of the package. Soldering this heat slug to the ground plane of the PC board ensures the lowest
possible thermal resistance for the device resulting in a long MTF.
· Open Cable Set-Top Box
PA
MAC
QAM
Receiver
w/FEC
SAW
Double
Conversion
Tuner
Microcontroller
w/Enet MAC RAM
ROM
10Base-T
Tranceiver
Balun
ARA
2001
Reverse Amp
54-860 MHz
Gain Control
Clock
Clock
Data
Data
RJ45
Connector
45 MHz IF
Tx Enable/Disable
CLK
DAT
EN
CMOS IC
PA
PA
"Shutdown"
~
Low Pass
Filter
Diplexer
Filter
Coax Input
ATTN
1/2/4/8/16/32 dB
PA
~
"Shutdown"
Low Pass
Filter
Upstream
QPSK/
16-QAM
Modulator
Figure 1: Cable Modem or Interactive Set-Top Box Block Diagram
2
ARA2001S23
32 dB 16 dB 8 dB 4 dB 2 dB 1 dB
EFET
EFET
GaAs IC
Attn In
Amp Out
Amp In
ISET 1
Control 1
Amp Out
Amp In
Attn In
32 dB 16 dB 8 dB 4 dB 2 dB 1 dB
Attn Out
Amp In
Amp Out
Control 2
ISET 2
Amp Out
Amp In
Attn Out
CMOS IC (Serial to Parallel Interface)
8-Bit Shift
Register
Buffer
Control Latch
P5 P4 P3 P2 P1 P0
8
Clock
Data
Enable
Figure 2: ARA 2001 Block Diagram
V
DD
)42,12,9,4,2SNIP(9CDV
V
NIFR
)8,5SNIP(3-ot0CDV
TTA
NI
TTA)01,3(
TUO
V)62,91(5CDV
I
TES
)22,7SNIP( 2CDV
SNIP(egatloVtupnIFR
8,5
*)
06+VmBd
erutarepmeTegarotS002+ot55-C°
erutarepmeTgniredloS062C°
emiTgniredloS5ceS
erutarepmeTesaCgnitarepO58+ot0C°
ABSOLUTE MAXIMUM RATINGS
PARAMETER PARAMETER
3
ARA2001S23
ELECTRICAL CHARACTERISTICS (TYPICAL) (VDD=5 VDC, TC=25 °C)
RETEMARAPNIMPYTXAMTINUSTNEMMOC
niaG
1
zHM01@5.723.925.03BdgnittesnoitaunettaBd0tA
ssentalFniaG
1
-57.0-BdzHM24ot5
pmeTrevOnoitairaVniaG-600.0--c°/Bd
spetSnoitaunettA
1
Bd1
Bd2
Bd4
Bd8
Bd61
Bd23
56.0
6.1
6.3
5.7
0.51
2.03
38.0
07.1
57.3
57.7
04.51
57.03
00.1
50.2
0.4
0.8
8.51
3.13
Bd
2
dn
leveLnoitrotsiDcinomraH
2
zHM01-57-35-cBdVmBd06+ta
3
dr
leveLnoitrotsiDcinomraH
2
zHM01 -06-35-cBdVmBd06+ta
3
dr
tnioPtpecretnItuptuOredrO87-- VmBd
tnioPnoisserpmoCniaGBd1-5.86- VmBd
erugiFesioN
1
-0.30.4BdssolnulabtupnisedulcnI
rewoPesioNtupuO
gnitteS.nttAniM/langiSoN/evitcA
gnitteS.nttAxaM/langiSoN/evitcA
-
-
-
-
5.52-
8.04-
VmBd htdiwdnabzHK0023ynA
zHM24-5morf
zHM54@edomelbasidxTninoitalosI-56-Bd
langistuptuoniecnereffiD
/elbanexTneewteblevel
elbasid
ecnadepmItupnI
1
-57-mho
ssoLnruteRtupnI
1
-02-21-BddelbanexT
ssoLnruteRtupnI
1
-5--BddelbasidxT
ecnadepmItuptuO
1
-57-mho
ssoLnruteRtuptuO
1
-71-21-BddelbanexT
ssoLnruteRtuptuO
1
-51-01-BddelbasidxT
V
1DD
V,
2DD
)42,12,9,4sniP(-57V
V
DD
)2niP(latigiD-5-V
V
DD
)11niP(SOMC3-5V
I
1DD
)9dna4sniP()pmAtupnI(-8408AmdelbanexT
4
ARA2001S23
ELECTRICAL CHARACTERISTICS (TYPICAL) (VDD=5 VDC, TC=25 °C) (Continued)
Attenuation Level vs Control Word
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
0 4 8 121620242832364044485256
Control Word
Attenuation (dB)
Notes:
1. As measured in ANADIGICS test fixture
2. At +60 dBmV output level into 75 ohm load
RETEMARAPNIMPYTXAMTINUSTNEMMOC
I
1DD
-4.26AmdelbasidxT
I
2DD
)42dna12sniP()pmAtuptuO(-77021AmdelbanexT
I
2DD
-7.39AmdelbasidxT
I
DD
)2niP()rotaunettA(latigiD-951Am
noitpmusnoCrewoP-76.080.1W delbanexT
noitpmusnoCrewoP-57051WmdelbasidxT
eziSpetSrotaunettA6.0-4.1Bd
ssentalFniaG
1
-5.1-BdzHM56-5
tneisnarTegatloVtuptuO
1
elbasid/elbanexT
-
-
-
4
001
7
p-pVm
-
gnitteSrotaunettAbd0tA
gnitteSrotaunettAbd42tA
noitaunettAmumixaM6.853.06
5
ARA2001S23
Gain & Noise Figure vs Frequency
5
10
15
20
25
30
35
10 20 30 40 50 60 70 80 90 100
Frequency (MHz)
Gain (dB)
2
3
4
5
6
7
8
NF (dB)
Gain Noise Figure
Gain & Noise Figure vs VDD
20
23
26
29
32
35
34567
VDD ( Volts )
GAIN (dB)
1
2
3
4
5
6
NF (dB)
Gain Noise Figure
Measured @ 30 MHz
GAIN & N oise Figure vs Temperature
20
23
26
29
32
35
-40 -25 -10 5 20 35 50 65 80
Temperature (Co)
GAIN (dB)
1
2
3
4
5
6
NF (dB)
Gain Noise Figure
Me asured @ 30 M Hz
6
ARA2001S23
-80
-70
-60
-50
-40
-30
-20
34567
VDD ( Volts )
Harmonic Level (d Bc)
2nd Harmonic 3rd Harmonic
Measured @ 5 MHz
Harmonic Distortion vs VDD
Pout = 58 dBmV
-80
-70
-60
-50
-40
-30
-20
34567
VDD ( Volts )
Harmoni c L evel (d B c)
2nd Harmonic 3rd Harmonic
Measured @ 12 MHz
Harmonic Distortion vs VDD
Pout = 58 dBmV
Harm onic Distor tion vs Temperature
Pout = 58 dBmV
-80
-75
-70
-65
-60
-55
-50
-45
-40
-40 -25 -10 5 20 35 50 65 80
Temperature (Co)
Harmonic level (dBc)
2nd Harmoni c 3rd Harmonic
Me asured @ 5 MHz
7
ARA2001S23
Harmonic Distortion vs Power Out
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
49 51 53 55 57 59 61 63 65 67
Pout ( dBmV)
Harmonics (dBc)
2nd 3rd
Transients vs Attenuation
Pout = 55 dBmV at 0dB attenuation.
0
10
20
30
40
50
60
70
80
90
100
0 102030405060
Power Attenuation (dB)
Transient ( m V)
DOCSIS 1.1 Spec. ARA2001
Measured @ 10 MHz
8
ARA2001S23
Harmonic Pe rformanc e vs F reque nc y
Pout = + 62 dBmV
-72
-70
-68
-66
-64
-62
-60
-58
-56
-54
-52
-50
5 101520253035
Frequency (MHz)
Harmonic Level (dBc)
2nd Ha rm oni c 3rd Ha rmonic
IIP2 & IIP3 vs Frequency
20
24
28
32
36
40
5 101520253035404550556065707580859095100
Frequency (MHz)
IIP
2
(dBm)
4
6
8
10
12
14
IIP
3
(dBm)
IIP2 IIP3
Meas ured @ VDD = 5 Volts
Pin = -20 dBm per tone
IIP2 & IIP3 vs VDD
20
24
28
32
36
40
34567
VDD (Vol ts )
IIP
2
(dBm)
-5
-1
3
7
11
15
IIP
3
(dBm)
IIP2 IIP3
Measured @ 65 MHz
Two tones @ 29.5 MHz & 35.5 MHz
Pin = -20 dBm per tone
9
ARA2001S23
TEST CIRCUIT
ARA2000 & 2001
Balanced Reverse Amp Test Fixture with 3 Wire Int erface
gnd
1
Vattn
2
3
Attn In +
4
Out A1 +
gnd
Attn Out +
In A2 +
28
27
26
25
In A1 +
5
Vg1
6
7
SB1
8
In A1 -
Out A2 +
Vg2
SB2
Out A2 -
24
23
22
21
Data
13
nc
16
Enable
14
nc
15
Out A1 -
9
Attn In -
10
11
Vdd CMOS
12
Clock
In A2 -
Attn Out -
Gnd CMOS
nc
20
19
18
17
+5V (Vdd1 & Vattn) +5V (Vdd2)
+5V (Vdd1)
Control A1
0 / +3 V
R
Vdd CM OS
CLOCK
DATA
ENABLE
2:11:2
RF Input (75 ohm )
Control A2
0 / +3 V
10uH
10uH
1200
ohms
1200
ohms
3.9 ohms
1000pF 1000pF
1000pF 1000pF
1uF0.1uF 1uF 0.1uF
470pF
1K ohm
2K ohms
470pF
1K ohm
2K ohms
0.1uF
1uF
470pF
470pF
1500pF
0.1uF
1uF
Toko Bal un
P/N 616PT- 1 030
Note:
Tx Enable = Contr ol
Tx Disable = Control 1
2K ohms
2K ohms
Toko Balun
P/N 616PT-1030
10
ARA2001S23
SERIAL
DATA FUNCTION
P0 1 dB Attenuator Bit
Data Port Description
P7
P6
P5
P4
P3
P2
P1 2 dB Attenuator Bit
4 dB Attenuator Bit
8 dB Attenuator Bit
16 dB Attenuator Bit
32 dB Attenuator Bit
N/A
N/A
DATA
CLOCK
ENABLE
ENABLE
OR
D
7
: MSB D
6
D
5
D
4
D
1
D
0
: LSB
SERIAL DATA INPUT TIMING
Programming Word
Figure 4
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
P0 P1 P2 P3 P4 P5 P6 P7
Figure 3
11
ARA2001S23
niPnoitcnuFnoitpircseD
1dnuorG
2V
NTTA
rotaunettArofylppuS
3TTA
NI
)+()+(tupnIrotaunettA
41A
TUO
)+(tuptuO)+(1reifilpmA
51A
NI
)+(tupnI)+(1reifilpmA
61gVlortnoC)-/+(1AreifilpmA
7I
1TES
tsujdAtnerruC)-/+(1AreifilpmA
81A
NI
)-(tupnI)-(1AreifilpmA
91A
TUO
)-(tuptuO)-(1AreifilpmA
01TTA
NI
)-()-(tupnIrotaunettA
11SOMCtiucriCSOMClatigiDroFylppuS
21KLCkcolC
31TADataD
41nEelbanE
51C/NnoitcennoCoN
61C/NnoitcennoCoN
71C/NnoitcennocoN
81SOMCtiucriCSOMClatigiDrofdnuorG
91TTA
TUO
)-()-(tuptuOrotaunettA
022A
NI
)-(tupnI)-(2AreifilpmA
122A
TUO
)-(tuptuO)-(2AreifilpmA
22 I
2TES
tsujdAtnerruC)-/+(2AreifilpmA
322gVlortnoC)-/+(2AreifilpmA
422A
TUO
)+(tuptuO)+(2AreifilpmA
522A
NI
)+(tupnI)+(2AreifilpmA
62TTA
TUO
)+()+(tuptuOrotaunettA
72C/NnoitcennoCoN
82DNGdnuorG
PIN DESCRIPTION
12
ARA2001S23
NOTE
1. PACKAGE BODY SIZES EXCLUDE MOLD FLASH AND
GATE BURRS
2. TOLERANCE 0.0 04in .[0.10 mm] UNLESS OTHERWISE SPECIFIED
3 . C ONT R O L L ING D I M E NSIO N ARE INCHES.
4 . REF . - MO-137
A1
y
θ
D
e
L
E
H
b
C
A2
SYMBOLS
A0.0040.000
0.025
0.150
0°
−−−
0.016
0.228
0.386
0.007
0.008
0.004
8°
0.394
0.050
0.157
0.244
0.012
0.010
DIMENSIONS IN INCHES
0.057
MIN MAX
0.061
θ
S
T0.096
0.190
−−−
−−−
0.100.00
.64
3.81
0°
−−−
0.40
5.80
9.80
0.18
0.20
0.10
8°
10.00
1.27
4.00
6.20
0.30
0.25
DIMENSIONS IN MILLIMETERS
1.45
MIN MAX
1.55
2.43
4.82
−−−
−−−
0.057 1.45
Package Outline
13
ARA2001S23
NOTES
14
ARA2001S23
NOTES
15
ARA2001S23
NOTES
16
ARA2001S23
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or discontinue any product at any time without notice.
The Advanced Product data sheets and product specifications contained in this data sheet are subject to change prior to
a products formal introduction. The information in this data sheet has been carefully checked and is assumed to be reliable.
However, ANADIGICS assumes no responsibility for inaccuracies. ANADIGICS strongly urges customers to verify that the
information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
ANADIGICS, Inc.
35 Technology Drive
Warren, New Jersey 07059
Tel: (908) 668-5000
Fax: (908) 668-5132
http://www.anadigics.com
Mktg@anadigics.com
