International: USA:
Connect One Ltd.
2 Hanagar Street
Kfar Saba 44425, Israel
Tel: +972-9-766-0456
Fax: +972-9-766-0461
E-mail: info@connectone.com
http://www.connectone.com
Connect One Semiconductors, Inc.
15818 North 9th Ave.
Phoenix, AZ 85023
Tel: 408-986-9602
Fax: 602-485-3715
E-mail: info@connectone.com
http://www.connectone.com
Pub. No. 11-2100-02, Copyright © March 2005
iChipTM
iChip CO210AG
Data Sheet
Ver. 1.20
Information provided by Connect One Ltd. is believed to be accurate and reliable.
However, Connect One assumes no responsibility for its use, nor any infringement of
patents or other rights of third parties, which may result from its use. No license is
granted by implication or otherwise under any patent rights of Connect One other than for
circuitry embodied in Connect One’s products. Connect One reserves the right to change
circuitry at any time without notice. This document is subject to change without notice.
The software described in this document is furnished under a license agreement and may
be used or copied only in accordance with the terms of such a license agreement. It is
forbidden by law to copy the software on any medium except as specifically allowed in
the license agreement. No part of this document may be reproduced or transmitted in any
form or by any means, electronic or mechanical, including but not limited to
photocopying, recording, transmitting via fax and/or modem devices, scanning, and/or
information storage and retrieval systems for any purpose without the express written
consent of Connect One.
iChip, iChip LAN, iChip Plus, Socket iChip, Embedded iModem, Internet Controller,
SerialNET, iConnector, iLAN, iModem, AT+i, Instant Internet, and Connect One are
trademarks of Connect One Ltd.
Copyright 2000 - 2005 Connect One Ltd. All rights reserved.
iChip CO210AG Data Sheet ii
Connect One Revision History
Revision History 11-2100-02
Version Date Description
0.30 April 2004 Original Release for iChip CO210AG.
0.35 June 2004 Fixed Typos.
1.10 November 2004 Added following sections: Functional Description,
Hardware Interface, Interface Timing and Waveforms,
Soldering Profile, iChip Designs, Internet Protocol
Compliance, and List of Terms and Acronyms.
1.20 March 2005 Corrected iChip pin numbering in diagrams.
Updated protocol compliance section.
iChip CO210AG Data Sheet iii
Connect One Contents
Contents
1 Introduction.............................................................................................................. viii
2 Ordering Information............................................................................................... 2-1
2.1 iChip Order Number ........................................................................................ 2-1
3 Functional Description............................................................................................. 3-2
3.1 Overview.......................................................................................................... 3-2
3.2 Technical Specifications .................................................................................. 3-2
3.2.1 General.....................................................................................................3-2
3.2.2 Operation.................................................................................................. 3-2
3.2.3 Local BUS Connection to an Ethernet LAN Controller ..........................3-3
3.2.4 Host Connection....................................................................................... 3-3
3.2.5 Serial Connection to Analog Modem ...................................................... 3-4
3.2.6 Hardware and Software Flow Control .....................................................3-4
4 Hardware Interface................................................................................................... 4-1
4.1 Serial Host Interface ........................................................................................ 4-1
4.2 Parallel Host Interface...................................................................................... 4-1
4.2.1 80x86 BUS............................................................................................... 4-2
4.2.2 MC68xxx BUS ........................................................................................ 4-3
4.3 LAN Interface ..................................................................................................4-4
4.4 Serial Modem Interface.................................................................................... 4-4
4.5 Dual Interface................................................................................................... 4-5
5 Pin Descriptions....................................................................................................... 5-1
5.1 iChip CO210AG Pin Assignments .................................................................. 5-1
5.2 iChip Pin Functional Descriptions................................................................... 5-2
5.2.1 Local BUS Signals...................................................................................5-2
5.2.2 Miscellaneous Signals.............................................................................. 5-4
5.2.3 Host Serial Interface Signals.................................................................... 5-7
5.2.4 iChip Serial Modem Signals .................................................................... 5-9
6 Electrical Specifications........................................................................................... 6-1
6.1 Environmental Specifications .......................................................................... 6-1
6.1.1 Absolute Maximum Ratings .................................................................... 6-1
6.1.2 DC Operating Characteristics .................................................................. 6-1
6.1.3 Command Response Delays .................................................................... 6-2
6.2 Interface Timing and Waveforms .................................................................... 6-3
6.2.1 Switching Characteristics......................................................................... 6-3
6.2.2 Local BUS Read Cycle ............................................................................ 6-4
6.2.3 Local BUS Write Cycle ........................................................................... 6-4
6.2.4 Clock Waveform...................................................................................... 6-5
6.2.5 Reset Timing............................................................................................6-5
6.2.6 Parallel BUS Read Cycle......................................................................... 6-6
6.2.7 Parallel BUS Write Cycle ........................................................................ 6-6
7 Recommended Soldering Profile .............................................................................7-1
8 Mechanical Dimensions........................................................................................... 8-1
9 iChip Designs........................................................................................................... 9-1
iChip CO210AG Data Sheet iv
Connect One Contents
9.1 Serial Host and Ethernet Controller Environment ........................................... 9-1
9.2 Parallel Host and Ethernet Controller Environment ........................................9-1
9.3 Selecting the Reset Circuit............................................................................... 9-2
9.3.1 RC Network ............................................................................................. 9-2
9.3.2 Supervisory Circuit .................................................................................. 9-2
10 Internet Protocol Compliance ............................................................................ 10-1
11 List of Terms and Acronyms ............................................................................. 11-1
iChip CO210AG Data Sheet v
Connect One Figures
Figures
Figure 4-1 Interface to an 80x86 Type BUS.................................................................... 4-2
Figure 4-2 Interface to an MC68xxx Type BUS............................................................. 4-3
Figure 4-3: iChip CO210AG with LAN and Serial Modem Interface ............................ 4-5
Figure 5-1 Pinout for 121-ball uBGA Package (Bottom View) ...................................... 5-1
Figure 6-1 Local BUS Read Cycle.................................................................................. 6-4
Figure 6-2 Local BUS Write Cycle.................................................................................6-4
Figure 6-3 Clock Waveform............................................................................................ 6-5
Figure 6-4 Reset Timing.................................................................................................. 6-5
Figure 6-5 Parallel BUS Read Cycle............................................................................... 6-6
Figure 6-6 Parallel BUS Write Cycle.............................................................................. 6-6
Figure 8-1: Mechanical Dimensions................................................................................ 8-1
Figure 9-1 Serial Host and Ethernet Controller Environment ......................................... 9-1
Figure 9-2 Parallel Host and Ethernet Controller Environment ...................................... 9-1
Figure 9-3 RC Reset Circuit............................................................................................9-2
Figure 9-4 Supervisory Reset Circuit.............................................................................. 9-2
iChip CO210AG Data Sheet vi
Connect One Tables
Tables
Table 4-1 Host Data Format............................................................................................ 4-1
Table 4-2 Modem Data Format........................................................................................ 4-4
Table 6-1 Environmental Specifications – Maximum Ratings........................................ 6-1
Table 6-2 Command Response Delays............................................................................6-2
Table 6-3 Switching Characteristics................................................................................ 6-3
Table 7-1 Recommended Soldering Profile..................................................................... 7-1
Table 10-1 Internet Protocol Compliance...................................................................... 10-1
Table 11-1 Terms and Acronyms.................................................................................. 11-2
iChip CO210AG Data Sheet vii
Connect One Introduction
1 Introduction
Description
iChip™ CO210AG Internet Controller™ is a
high-performance, firmware-based intelligent
peripheral device that provides Internet
connectivity solutions for a wide range of
embedded devices. The firmware provides
Internet communication via 10BaseT and
10/100BaseT Ethernet LANs, 802.11b Wireless
LAN, dial-up and cellular modems. CO210AG
is packaged in a 121-ball uBGA form factor.
iChip CO210AG Firmware is updateable only
through its local serial port.
CO210AG is designed for high-bandwidth
applications. Its host interface and 66 MHz
clock support 230 kbits/second in Serial mode
and up to 400 kBytes/second sustained
throughput and 500 kBytes/second (4 Mbps) in
Parallel mode (to be implemented in version
801xxx). The CO210AG also features a Power
Save mode for saving energy. CO210AG
operates in the industrial temperature range.
As an embedded, self-contained Internet
engine, iChip acts as mediator device between a
host processor and an Internet communications
platform. By completely offloading Internet
connectivity and standard protocols, it relieves
the host from the burden of handling Internet
communications. From the perspective of a
host device, the complexity of establishing and
maintaining Internet-related sessions are
reduced to simple, straightforward commands
that are entirely dealt with within iChip’s
domain.
A serial BUS interfaces iChip CO210AG to a
device’s host processor via an on-chip UART.
Alternatively, iChip CO210AG may be
interfaced over a parallel BUS with some
external glue logic. iChip CO210AG also
directly interfaces an Ethernet controller, a
WiFi controller or a serial data modem, through
which it supports independent communications
on the Internet via a dial-up or wireless ISP
connection.
In addition to supporting dial-up modems, iChip
CO210AG also supports AMPS, CDMA, CDMA2000,
CDPD, GPRS, GSM, IDEN and TDMA cellular
modems.
Through its host Application Programming
Interface (API), iChip CO210AG accepts commands
formatted in Connect One's AT+i™ extension to the
industry-standard Hayes AT command set. iChip
supports several levels of status reporting to the host.
Commands are available to store and manipulate
functional and Internet-related non-volatile parameter
data; utilize TCP and UDP sockets; retrieve Network
time-of-day and route local serial data to/from the
Internet; transmit and receive textual Email messages;
transmit and receive binary (MIME encoded) Email
messages; fetch HTML web pages; manipulate files
and directories via FTP; maintain Telnet sessions and
download parameter updates for the host device or
iChip itself. iChip includes a Web server engine that
hosts an internal configuration Web site as well as a
customizable application Web site. iChip also includes
a WAP server that can host a WAP site.
When the host CPU issues standard AT commands and
the modem platform is selected, iChip gains direct
access to the modem, and automatically operates in
Transparent mode, emulating a direct host-to-modem
environment.
iChip supports 10BaseT Ethernet LANs with the
addition of an external 16-bit Cirrus Logic Crystal
LAN CS8900A. It also supports 10/100BaseT LANs
with the addition of an SMSC LAN91C111 or ASIX
AX88796L Ethernet controller. 802.11b WiFi is
supported with an addition of a PCMCIA or CF
Wireless LAN card module based on Prism 2.5/3.0
WiFi chipset. AT commands enable iChip to send and
receive Internet commands through the LAN.
Upon receiving an AT+i command, iChip operates in
Internet mode, controls the modem or Ethernet
controller, and independently manages standard
Internet protocols to transmit and receive messages or
data over sockets. iChip provides all the necessary
procedures to log-on to an ISP, authenticate the user
and establish an Internet session.
iChip CO210AG Data Sheet viii
Connect One Introduction
Functional Block Diagram Pin Diagram
uBGA-121 Bottom View
iChip CO210AG Data Sheet 1-1
iChip
General Features General Protocols
● Microprocessor-controllable through a serial
connection or parallel BUS.
● 256KB SRAM and 512KB flash memory.
● Driven by Connect One’s “AT+i" extension to the
AT command set.
● Stand-alone Internet communication capabilities.
● Binary Base64 encoding and MIME.
● Opens up to 10 simultaneous TCP or UDP sockets
and up to 2 Listen (server) sockets.
● Power Save mode.
● 3.3-volts, CMOS technology for I/O and 1.8 volt
for core.
● Onboard non-volatile memory stores all functional
and Internet-related parameters.
● Supports several layers of status reports.
● Internal self-test procedures.
● Internal "Watchdog" guard circuit.
● Auto baud rate detection.
● Supports up to 230,400 bps in Serial mode.
● Supports up to 400 kBytes/sec (3.2Mbps).
sustained throughput and 500 kBytes/sec (4Mbps)
bursts in Parallel1 mode.
● Includes hardware and software flow control.
● 121-ball uBGA package (10 x 10 x 1.2 mm with
0.8mm ball pitch).
● Locally updateable firmware
Note 1: Future Implementation
● Supports following Internet Protocols:
IP, TCP, UDP, DNS, SMTP, POP3, MIME, HTTP,
FTP, Telnet, SNTP, SNMP1, SSL31, PING
● Includes embedded configuration Web and WAP
server.
● SerialNET mode for serial-to-Internet routing.
Dial-up Features
● Supports dial-up Internet Protocols:
PPP, LCP, IPCP, and PAP, CHAP, or Script
authentication.
● Supports data modems up to 56 Kbps.
● Supports AMPS, CDMA, CDMA2000, CDPD,
GPRS, GSM, IDEN and TDMA wireless cellular
modems.
● Stay-on-line feature for multiple send/receive
sessions.
● Transparent mode supports direct modem commands.
● Always-Online mode with communications
“watchdog”.
LAN Features
● Supports LAN Internet Protocols:
ARP, ICMP, and DHCP.
● Provides 10BaseT Ethernet LAN connectivity via
Crystal LAN CS8900A Ethernet controller.
● Provides 10/100BaseT Ethernet LAN connectivity
via SMSC LAN91C111 and ASIX AX88796L
Ethernet controller.
● Provides Wireless LAN connectivity via PCMCIA or
CF WiFi module based on Prism 2.5/3.0 802.11b
WiFi chipset.
D0-D15
A0-A20
RESET
Rx,Tx,CTS,RTS
DTR,DSR,CD
Serial
Host
Interface
Serial
Modem
Interface
Rx,Tx,CTS,RTS,
DTR,DSR,CD,RI
Osc.
CPU
Core
SRAM
256KB
FLASH
512 KB
Clock
Unit
1 1 10 9 8 7 6 5 4 3 2 1
Local Parallel
Interface
ABC DEF G H J K L
Parallel
Host
Interface
-RD
-WR
Parallel Bus
LANINT
Connect One Ordering Information
2 Ordering Information
2.1 iChip Order Number
Connect One’s standard products are available in several packages and operating ranges.
The order number (valid combination) is formed by a combination of the elements below.
CO210AG /66 B I – 3
Product Code
Clock:
66 = MHz
Package:
121-ball uBGA
Temperature Range:
I = Industrial
(-40 to +85°C/-40° to +185° F)
Voltage:
3 = 3.3V
iChip CO210AG Data Sheet 2-1
Connect One Functional Description
3 Functional Description
3.1 Overview
Connect One’s iChip Internet Controller is an integrated, firmware-driven, self-contained
Internet engine that is available in a 121-pin uBGA package. iChip accepts simple ASCII
commands from a host CPU via a serial communication channel and manages an Internet
communication session to send and receive email, Web or WAP pages/files, utilize FTP
and Telnet, serve as a serial-to-Internet router, or to manipulate sockets through a linked
modem or Ethernet communications platform.
For 10BaseT Ethernet applications, iChip CO210AG includes the firmware and pinout
necessary to drive an external Crystal LAN CS8900A. For 10/100BaseT Ethernet
applications, iChip includes the firmware and pin out necessary to drive an external
SMSC LAN91C111 or ASIX AX88796L Ethernet LAN controller. For Wireless LAN
applications, iChip CO210AG includes the firmware and pin out necessary to drive a
PCMCIA or CF WiFi card based on the Prism 2.5/3.0 802.11b WiFi chipset.
iChip contains a non-volatile FLASH memory to store its firmware and Internet-related
operational parameters. Firmware and parameter updates are supported only through the
local host link.
3.2 Technical Specifications
3.2.1 General
iChip constitutes a complete Internet messaging solution for non-PC embedded devices.
It acts as a mediator device to completely offload the host processor of Internet-related
software and activities. An industry-standard asynchronous serial link connects iChip to
the host processor. Programming, monitoring and control are fully supported using
Connect One’s AT+iTM extension to the standard AT command set.
iChip connects to serial modems and to an Ethernet controller for Internet access. An
AT+i command is provided to switch between the serial modem and Ethernet.
3.2.2 Operation
All iChip Internet and parameter operations are controlled by AT+i commands.
3.2.2.1 Transparent Mode
In modem communications mode, iChip defaults to Transparent mode, allowing the host
to control the modem device directly. Control is implemented by issuing standard AT
commands to iChip. In this mode, iChip transparently echoes the AT commands to the
modem, as well as echoing the modem responses back to the host. iChip supports
interlacing AT+i and AT commands while the modem is in Command mode. When the
modem is put into Data mode by issuing a dial command, Transparent mode is sustained
throughout the Data mode session.
iChip CO210AG Data Sheet 3-2
Functional Description
3.2.2.2 Command Mode
iChip commands are implemented using the AT+i command set. Command flow exists
only on the host serial link between the host and iChip.
3.2.2.3 Internet Mode
iChip enters Internet mode after being issued an Internet command such as to send or
receive an email message, open a socket, etc. iChip attempts to establish an Internet
connection and carry out the required activity through the communication platform link.
While in this mode, AT+i commands are supported to monitor and control the process
when needed.
3.2.2.4 SerialNET Mode
iChip SerialNET mode extends a local asynchronous serial link to a TCP or UDP socket
across a LAN or Internet. Its main purpose is to allow simple devices, which normally
interact over a serial line, to interact in a similar fashion across a network, without
requiring any changes in the device itself. iChip contains a set of associated operational
parameters which define the nature of the desired network connection. iChip supports
both Server and Client modes in SerialNET mode. AT+i commands are not required to
operate SerialNET mode. Thus, SerialNET mode may be used in existing systems with
little or no need to modify the application program.
3.2.3 Local BUS Connection to an Ethernet LAN Controller
iChip interfaces an Ethernet LAN controller connected to its 16-bit local BUS.
3.2.4 Host Connection
iChip can interface a host processor through one of two methods: Serial or Parallel.
3.2.4.1 Host Serial Connection
iChip supports a full-duplex, TTL-level serial communications link with the host
processor. Full EIA-232-D hardware flow control, including Tx, Rx, CTS, RTS, DTR,
DSR, CD and RI lines, is supported.
CO210AG supports standard baud rate configurations from 2,400 bps up to 230,400 bps
on the host asynchronous serial communications channel. The default baud rate may be
changed permanently by using the AT+iBDRF command. Auto baud rate setting is
supported for all baud rates except 230,400 bps.
3.2.4.2 Host Parallel Connection
iChip supports an 8-bit parallel BUS interface with some additional logic. The parallel
BUS may be defined as an 80x86 (Intel) BUS or an MC68xxx (Motorola) BUS. This
interface will be implemented from firmware version 801xxx.
iChip CO210AG Data Sheet 3-3
Functional Description
3.2.5 Serial Connection to Analog Modem
iChip CO210AG supports a full-duplex, TTL-level serial communications link with the
modem device. Full EIA-232-D hardware flow control, including Tx, Rx, CTS, RTS,
DTR, DSR and CD lines, is supported. It does not support the RI line.
3.2.6 Hardware and Software Flow Control
Hardware flow control is supported between the host serial connection and iChip.
Flow control is programmed via the AT+iFLW command. The default flow control
method is set to “Wait/Continue” software flow control (which is similar to XON/XOFF
software flow control) between iChip and the host processor.
The hardware flow control method frees the host CPU from monitoring and handling the
software flow control. The host can program iChip to either use hardware flow control or
“Wait/Continue” software flow control. The flow control mechanism is based on the
RTS/CTS signals.
The host parallel connection has built-in hardware flow control signals as part of the
interface logic.
iChip CO210AG Data Sheet 3-4
Preliminary Hardware Interface
4 Hardware Interface
iChip CO210AG may interface a host CPU in one of two methods: Serial or Parallel.
The actual interface depends on the state of the –SER/PAR pin.
4.1 Serial Host Interface
The host interface is a serial DTE interface. Speeds of 2400, 4800, 9600, 19200,
38400, 57600, 115200 and 230400 bps are supported in the following data format:
Parity Data Length
(No. of Bits)
No. of
Stop Bits
Transmission
Length
(No. of Bits)
None 8 11 10
Table 4-1 Host Data Format
4.2 Parallel Host Interface
In Parallel interface2 mode, iChip connects to a host CPU through a parallel interface
using a PAL (i.e., Altera “EPM7032AEC44”). The host parallel BUS may be an
80x86 (Intel) or a 68K (Motorola) BUS. With some small changes to the PAL, the
user may customize an interface to any other BUS architecture. iChip is connected to
the interface PAL through the following signals:
• PCS: Parallel chip select signal. When PCS is HIGH, the PAL is selected.
• -RD: When –RD is LOW, iChip reads data from PAL.
• -WR: When –WR is LOW, iChip writes data to PAL.
• D0-D7: Bi-directional data BUS.
• -PRES: Parallel reset. When LOW, generates a reset signal to the parallel
interface.
• -PERR: Parallel error. When LOW, indicates a parallel interface error.
• POBE: Parallel Output Buffer Empty. When HIGH, indicates that the output
buffer is empty and iChip may send additional data to host. When iChip sends
a data byte, this signal goes LOW until the host reads the data.
• PIBF: Parallel Input Buffer Full. When HIGH, indicates that the input buffer
is full and iChip may read a data byte from the host. When iChip reads the
data byte, this signal goes LOW.
Notes: 1: When hardware flow control is enabled, the iChip transmitter will add an
additional stop bit.
2: Parallel interface mode is available only from iChip firmware version 801xxx.
iChip CO210AG Data Sheet 4-1
Hardware Interface
4.2.1 80x86 BUS
Host
80x86
HOBE
HIBF
-HCS
-HRD
-HWR
HD0-HD7
-HRES
-ERROR
EPM7032AEC44
PAL
iChip
CO210AG
POBE
PIBF
PCS
-RD
-WR
D0-D7
-PRES
-PERR
iChip CO210AG Data Sheet 4-2
Figure 4-1 Interface to an 80x86 Type BUS
This BUS type includes the following signals:
• -HCS: Host Chip-Select signal. When -HCS is LOW, PAL is selected.
• -HRD: Host Read Data. When –HRD is LOW, a data byte is read from the
PAL.
• -HWR: Host Write Data. When –HWR is LOW, a data byte is written to the
PAL.
• HD0 – HD7: Bi-directional Host data BUS.
• -HRES: Parallel reset. A LOW generates a reset signal to the parallel
interface. This pin may be connected to an 80x86 output port.
• -HERR: Parallel error. A LOW indicates a parallel interface error. This pin
may be connected to an input port on the 80x86.
• HOBE1: Host Output Buffer Empty. When HIGH, indicates that the output
buffer is empty and the host may send a data byte to iChip. When the
Host sends a data byte, this signal goes LOW until iChip reads the
data. This signal may be connected to an interrupt or I/O pin on the
80x86.
• HIBF1: Host Input Buffer Full. When HIGH, indicates that the input buffer is
full and the host may read a data byte from iChip. When the host
reads the data, this signal goes LOW. This pin may be connected to
an interrupt or I/O pin on the 80x86.
Note 1: HOBE and HIBF complement PIBF and POBE respectively.
Hardware Interface
4.2.2 MC68xxx BUS
Host
MC68302
HOBE
HIBF
-HCS
HR/-W
HD0-HD7
-HRES
-ERROR
EPM7032AEC44
PAL iChip
CO210AG
POBE
PIBF
PCS
-RD
-WR
D0-D7
-PRES
-PERR
iChip CO210AG Data Sheet 4-3
Figure 4-2 Interface to an MC68xxx Type BUS
This BUS type includes the following signals:
• -HCS: Host Chip-Select signal. When -HCS is LOW, PAL is selected.
• -HR/-W: Host read/write data from/to iChip. When HR/-W is LOW, it
indicates a write cycle; otherwise it is a read cycle.
• HD0 – HD7: Bi-directional Host data BUS.
• -HRES: Parallel reset. A LOW generates a reset signal to the parallel
interface. This pin may be connected to a MC68xxx output port.
• -HERR: Parallel error. A LOW indicates a parallel interface error. This pin
may be connected to an input port on the 80x86.
• HOBE1: Host Output Buffer Empty. When HIGH, indicates that the output
buffer is empty and the host may send a data byte to iChip. When
the Host sends a data byte, this signal goes LOW until iChip reads
the data. This signal may be connected to an interrupt or I/O pin on
the MC68xxx.
• HIBF1: Host Input Buffer Full. When HIGH, indicates that the input buffer
is full and the host may read a data byte from iChip. When the host
reads the data, this signal goes low. This pin may be connected to
an interrupt or I/O pin on the MC68xxx.
Note 1: HOBE and HIBF complement PIBF and POBE respectively.
Hardware Interface
4.3 LAN Interface
iChip directly interfaces an Ethernet LAN MAC/PHY device on its 16-bit local BUS.
Currently iChip supports the Crystal LAN CS8900A Ethernet controllers for 10BaseT
and SMSC LAN91C111 and ASIX AX88796L Ethernet controllers for 10/100BaseT.
For Wireless LAN applications, iChip CO210AG needs some minor glue logic to
connect to a PCMCIA or CF WiFi card based on the Prism 2.5/3.0 802.11b WiFi
chipset.
4.4 Serial Modem Interface
iChip includes a dedicated port to interface a serial modem.
The modem interface is a serial DCE interface. Speeds of 2400, 4800, 9600, 19200,
38400, 57600, 115200 and 230400 bps are supported in the following data format:
Parity Data Length
(No. of Bits)
No. of
Stop Bits
Transmission
Length
(No. of Bits)
None 8 1 10
Table 4-2 Modem Data Format
Actual baud rate may be preprogrammed or dynamically defined as equal to the auto
baud rate detected on the serial host interface (when the iChip operates in Serial
mode). When iChip operates in Parallel mode, the modem interface baud rate must be
preprogrammed.
iChip CO210AG Data Sheet 4-4
Hardware Interface
4.5 Dual Interface
iChip CO210AG Data Sheet 4-5
Figure 4-3: iChip CO210AG with LAN and Serial Modem Interface
Serial
Modem
RJ45
LAN
Controller
CPU
Core
Internal FLASH
512 KB
Internal SRAM
256 KB
Three 16-bit Timers
Local Parallel
Interface
Local Bus
UART with
auto baud rate
Interrupt
Controller
Modem
UART
Rx,Tx,
CTS,RTS,DTR,DSR,
Rx,Tx,
CTS,RTS,DTR,DSR
HOST
Connect One Pin Descriptions
5 Pin Descriptions
5.1 iChip CO210AG Pin Assignments
iChip CO210AG Data Sheet 5-1
1110987654321
ΟΟΟΟΟΟΟΟΟΟΟ
A
VDDi/o
TXDM RXDM -DTRM GND GND NC -CS_LAN -WAIT -CSE GND
ΟΟΟΟΟΟΟΟΟΟΟ
__
33/66_FSEL B
CLKIN NC -WR VDDcore GND A0 A1
GND CLKO/HBT
/Z6
-RTSM
ΟΟΟΟΟΟΟΟΟΟΟ
C
MSEL Z9 -BHE -RES NC GND A2 VDDi/o Z0 GND A4
ΟΟΟΟΟΟΟΟΟΟΟ
D
RXDH Z8 TXDH -RTSH/
-PERR
A3 NC NC NC A5 A7 A6
ΟΟΟΟΟΟΟΟΟΟΟ E
GND NC VDDi/o A8 -RD LBO LBI NC VDDi/o VDDi/o
ΟΟΟΟΟΟΟΟΟΟΟ F
Z2/POBE LANINT VDDi/o D11 D9 D2 NC VDDi/o A10 A9
ΟΟΟΟΟΟΟΟΟΟΟ G
VDDcore VDDi/o -DTRH A14 D10 A11 D5 D0 GND A13 A12
ΟΟΟΟΟΟΟΟΟΟΟ
H
-DSRM ABDD A15 D13 D7 D4 D1 GND GND GND
-RIH/
-SER
ΟΟΟΟΟΟΟΟΟΟΟ
J
VDDi/o Z5 A16 D12 NC D8 D6 Z1/PCS A19 A17
-DSRH/
-PRES
ΟΟΟΟΟΟΟΟΟΟΟ
K
GND GND D15 D14 NC NC GND NC VDDi/o -CDM A18
ΟΟΟΟΟΟΟΟΟΟΟ
L
Z3 Z4 VDDi/o D3 NC NC NC VDDcore A20
-CDH/
-RCV
-SER/PAR
Figure 5-1 Pinout for 121-ball uBGA Package (Bottom View)
Connect One Pin Descriptions
5.2 iChip Pin Functional Descriptions
5.2.1 Local BUS Signals
Signal
Type
Pin No.
Description
A[20:0]
O
L1,J3,K1,
J2,J9,H8,
G8,G2,G1,
G6,F2,F1,
E7,D2,D1,
D3,C1,D7,
C5,B1,B2
Address BUS: These pins supply addresses to the
system.
D[15:0]
O/I
K9,K8,H7,
J8,F7,G7,
F6,J6,H6,
J5,G5,H5,
L7,F5,H4,
G4
Data BUS: These pins supply data to/from the
system.
-BHE
O
C9
BUS HIGH Enable: This pin and the least-
significant address bit (A0) indicate to the system,
which bytes of the data BUS (upper, lower, or
both) participate in a BUS cycle. The -BHE and A0
ins are encoded as shown in the table below.
p
-BHE A0 Type of BUS cycle
0 0 Word Transfer
1 0 Even Byte Transfer
0 1 Odd Byte Transfer
1 1 N/A
-RD
O
E6
READ: This pin indicates that iChip is performing
a read cycle.
-WR
O
B5
WRITE: This pin indicates that iChip is
performing a write cycle.
-WAIT
I
A3
WAIT: when this pin is LOW, the CPU adds a wait
state to each memory cycle. This pin should be
pulled up to VDDi/o.
iChip CO210AG Data Sheet 5-2
Connect One Pin Descriptions
Signal
Type
Pin No.
Description
LBO
O
E5
Loop Back Out.
Must connect to LBI.
LBI
I
E4
Loop back input.
Must connect to LBO.
-CS_LAN O A4 Chip Select for external LAN controller.
-CSE
O
A2
Chip Select Extended this pin is reserved for future
use and should be NC (Not Connected).
iChip CO210AG Data Sheet 5-3
Connect One Pin Descriptions
5.2.2 Miscellaneous Signals
Signal
Type
Pin No.
Description
MSEL
I
C11
Modem Mode Select:
• When this pin is held LOW during power
up for at least 5 seconds, iChip will
automatically enter the Boot Loader’s
monitor mode.
• During a firmware update procedure,
when an external modem dials to the
iChip pulling this pin down to LOW will
cause iChip to immediately answer the
call and begin the update session.
• When this pin is held LOW during power
up for less than 5 seconds, it forces iChip
into auto baud rate detection. If iChip
was in SerialNET mode, it will exit this
mode and startup in normal command
mode.
-RES
I
C8
RESET: When -RES is LOW, iChip
immediately terminates its present activity
and clears its internal logic.
-RES must be held LOW for at least 1 ms
after power arrive to 90%.
This input is provided with a Schmidt trigger
to facilitate power-on reset generation via an
RC network.
CLKIN
I
B8
Input clock.
Selectable to 33MHz or 66MHz via pin B11.
CLKO/HBT/
Z6
O
B7
AT+i Configurable Pin:
CLKO (default): Clock Output. This pin
provides a clock-out to the system at the
same frequency as CLKIN. During reset the
clock out is disabled.
HBT: Heartbeat. Provides a 50% duty cycle,
40 mSec frequency square wave when iChip
firmware is properly running.
In the future, it may be changed to a GPIO.
This pin is configurable with the AT+iPN44
command (see AT+i Programmer’s Manual).
ABDD
I
H10
Auto baud rate detect. Must be connected to
RXDH (D11) pin to support auto baud rate.
iChip CO210AG Data Sheet 5-4
Connect One Pin Descriptions
Signal
Type
Pin No.
Description
LANINT
I
F9
LAN Interrupt. Indicates that LAN controller
has information available for iChip.
-SER/PAR
I
L3
Serial/Parallel mode select. This pin is sampled
on the rising edge of the –RES signal. If it is
LOW, iChip functions in Serial mode.
Otherwise, it functions in Parallel mode.
Z1/PCS
I/O
J4
In Serial mode, Z1 is available as a GPIO for
future use and should be left Not Connected.
In Parallel mode, PCS is used as a chip-select
for the parallel interface PAL.
Z2/POBE
I/O
F11
In Serial mode, Z2 is available as a GPIO for
future use and should be left Not Connected.
In Parallel mode, POBE is used as the Parallel
Output Buffer Empty signal. When HIGH,
iChip may send a parallel data byte to the host.
Z[9-8]
Z[5-4]
Z3,Z0
I/O
C10,D10
J11, L10
L11,C3
General Purpose I/O (GPIO) for future use.
These pins should be NC (Not Connected).
GND
P
A1,A6,A7,
B3,B9,C2,
C6,E11,G3,
H1,H2,H3,
K5,K10,K11
Ground: iChip Ground signal.
VDDcore
P
B4,G11,L2
Power Supply: This pin supplies power (+1.8V)
to core of iChip.
iChip CO210AG Data Sheet 5-5
Connect One Pin Descriptions
Signal
Type
Pin No.
Description
VDD I/O
P
A9,C4,E1,
E2,E8,F3,
F8,G10,J1,
K3,L8
Power Supply: This pin supplies power
(+3.3V) to I/O pin of iChip.
__
33/66_FSEL
I B11 Oscillator Frequency Select.
Connect to GND when CLKIN (Pin B8) is
connected to a 33MHz oscillator.
Connect to VDDi/o when CLKIN (Pin B8) is
connected to a 66MHz oscillator.
NC
---
A5,B6,C7,
D4,D5,D6,
E3,E9,F4,
J7,K4,K6,
K7,L4,L5,
L6
NC (Not Connected) Pins.
iChip CO210AG Data Sheet 5-6
Connect One Pin Descriptions
5.2.3 Host Serial Interface Signals
Signal
Type
Pin No.
Description
TXDH
O
D9
Transmit Data Host: This pin supplies asynchronous
serial transmit data to the host.
RXDH
I
D11
Receive Data Host: This pin supplies asynchronous
serial receive data from the host.
When not used, this pin should be connected to VDDi/o.
Must be connected to ABDD (H10) pin to support auto
baud rate.
-CTSH/PIBF
I
E10
In Serial mode, Clear-to-Send Host: -CTSH is active
only when host hardware flow control is enabled.
When -CTSH is LOW, flow control is enabled for the
host serial port, i.e., iChip may transmit to the
host.
When -CTSH is HIGH, the iChip transmitter holds its
data in the serial port transmit register.
-CTSH is sampled only at the beginning of a frame
transmission. If -CTSH is raised while a character
frame is being transmitted, that frame will be
completed.
Connect -CTSH to -RTSH when not in use.
In Parallel mode, Parallel Input Buffer Full: when
HIGH, indicates that the host has sent a data byte
which has not yet been read.
-RTSH/-PERR
O
D8
In Serial mode, Ready-to-Send Host: -RTSH is active
only when host hardware flow control is enabled.
When -RTSH is LOW, flow control is enabled for the
host serial port, i.e., the host may transmit to iChip.
When -RTSH is HIGH, iChip indicates that
its receiver is busy and cannot receive data from host.
Connect -RTSH to -CTSH when not in use.
In Parallel mode, Parallel Error: When LOW,
indicates to the host that an error has occurred in the
parallel interface circuit.
-DSRH/-PRES
I
J10
In Serial mode, Data Set Ready Host: when -DSRH is
LOW, it indicates that the host is attached and ready to
communicate with iChip.
Connect -DSRH to GND when not in use.
In Parallel mode, Parallel Reset: when LOW,
generates a reset to the parallel interface.
iChip CO210AG Data Sheet 5-7
Connect One Pin Descriptions
Signal
Type
Pin No.
Description
-DTRH
O
G9
Data Terminal Ready Host: When -DTRH is LOW,
it indicates to the host that iChip is attached and
ready to communicate.
During an Internet session, this signal is used to
indicate if buffered data exists on one of iChip’s
sockets (see AT+i Programmers Manual).
-CDH/-RCV
O
L9
In dial-up mode, this pin functions as –CDH. In
LAN mode, it functions as –RCV.
Carrier Detect Host: This pin indicates to the host
that the modem communication device detects a
carrier signal.
Receive LAN Packet: when LOW, indicates that
iChip may receive a data packet from the LAN
Controller.
During firmware update, -CDH and -RIH are used to
display the firmware update status.
-RIH/-SER
O
H9
In dial-up mode, this pin functions as –RIH. In LAN
mode, it functions as –SER.
Ring Indicator Host: This pin indicates to the host
that the modem communication device detects a
Ring signal.
Serial Indicator Host: when LOW, indicates that
iChip may receive a legal character from the host.
During firmware update, -CDH and -RIH are used to
display the firmware update status.
iChip CO210AG Data Sheet 5-8
Connect One Pin Descriptions
5.2.4 iChip Serial Modem Signals
Signal
Type
Pin No.
Description
TXDM
O
A11
Transmit Data Modem: This pin provides
asynchronous serial transmit data to the modem
from the serial port.
On reset, this pin must remain HIGH -- It is
recommended to apply an external 330KΩ pull-up
resistor to this pin.
RXDM
I
A10
Receive Data Modem: This pin provides
asynchronous serial receive data from the modem to
the asynchronous modem serial port.
When this pin is not used, connect it to VDDi/o.
-CTSM
I
F10
Clear-to-Send Modem: -CTSH is active only when
modem hardware flow control is enabled.
When -CTSM is LOW, flow control is enabled for
the modem serial port, i.e., iChip may transmit to the
modem.
When -CTSM is HIGH, the iChip transmitter holds
its data in the serial port transmit register.
Connect -CTSM to -RTSM when not in use.
-RTSM
O
B10
Ready-to-Send Modem: -RTSM is active only when
modem hardware flow control is enabled.
When -RTSM is LOW, flow control is enabled for
the modem serial port, i.e., the modem may transmit
to iChip. When -RTSM is HIGH, iChip indicates
that its receiver is busy and cannot receive data from
modem.
Connect -RTSM to -CTSM when not in use.
-DSRM
I
H11
Data Set Ready Modem: When -DSRM is LOW, it
indicates that the modem is attached and ready to
communicate with iChip.
Connect -DSRM to GND when not in use.
-DTRM
O
A8
Data Terminal Ready Modem: When -DTRM is
LOW, it indicates to the modem that iChip is
attached and ready to communicate.
-CDM
I
K2
Carrier Detect Modem: This pin indicates to iChip
that the modem detects a carrier signal.
iChip CO210AG Data Sheet 5-9
Connect One Electrical Specifications
6 Electrical Specifications
6.1 Environmental Specifications
6.1.1 Absolute Maximum Ratings
Parameter Rating
Voltage at any pin with respect to ground -0.3 to +3.6 Volts
Operating temperature -40°C to 85°C (-40°F to 185°F)
Storage temperature -60°C to 150°C (–76°F to 302°F)
Table 6-1 Environmental Specifications – Maximum Ratings
6.1.2 DC Operating Characteristics
Parameter Min Typical Max Units
VDDi/o 3.0 3.3 3.6 Volts
VDDcore 1.65 1.8 1.95 Volts
High-level Input 2.0 VDDi/o+0.3 Volts
Low-level Input -0.3 0.8 Volts
High-level Output1 @16mA VDDi/o-0.4 Volts
High-level Output2 @8mA VDDi/o-0.4 Volts
High-level Output3 @2mA VDDi/o-0.4 Volts
High-level Output4 @0mA VDDi/o-0.2 Volts
Low-level Output1 @16mA 0.4 Volts
Low -level Output2 @8mA 0.4 Volts
Low -level Output3 @2mA 0.4 Volts
Low -level Output4 @0mA 0.2 Volts
Input leakage current 10 µA
Power supply current from
VDDcore (Operating Mode) 5
10 mA
Power supply current from
VDDcore (Power Save Mode) 5
2.4 mA
Power supply current from
VDDi/o (Operating Mode) 5
50 mA
Power supply current from
VDDi/o (Power Save Mode) 5
18 mA
Input Capacitance 6 pF
Table 6-2 DC Operating Characteristics
Notes: 1 On -RD, -WR and -BHE pins.
2 On D[15-0], A[20-0], -CS0 and –CS1 pins.
3 All other pins.
4 All output pins.
5 CLKIN=33.333MHz.
iChip CO210AG Data Sheet 6-1
Connect One Electrical Specifications
6.1.3 Command Response Delays
Command Min Typical Max Units
Factory Defaults 12 20 Seconds
Parameter Value Update 20 20,0001 mSec
Software Reset 20 20,0001 mSec
Table 6-2 Command Response Delays
Notes: 1 The maximum command response is due to the possibility of a garbage collection
process.
iChip CO210AG Data Sheet 6-2
Connect One Electrical Specifications
6.2 Interface Timing and Waveforms
6.2.1 Switching Characteristics
Parameter Symbol Min. Typical Max. Units
CLKIN frequency Fclk 33.33 33.333 33.336 MHz
CLKIN period Tclk 1/Fck us
CLKIN falling to address or
chip select change
Txfac 3.7 8.6 ns
CLKIN rising to read active Txrra 3.8 7.3 ns
CLKIN falling to read inactive Txfri 4.1 8.6 ns
Data setup before read high Tdsbrh 8 ns
Data setup after read high Tdsarh 3.1 ns
CLKIN rising to write active Txrwa 3.8 6.3 ns
CLKIN rising to data valid Txrdv 4.2 7.5 ns
CLKIN rising to write inactive Txrwi 4.2 6.7 ns
Data out valid after write high Tdovaw 2.2 ns
CLKIN fall time 1 Tckhl 5 ns
CLKIN rise time 2 Tcklh 5 ns
CLKIN LOW time Tclck 13.5 15 16.5 ns
CLKIN HIGH time Tchck 13.5 15 16.5 ns
CLKIN to CLKO skew Tcico 4.4 6.7 ns
Reset pulse Trst 1 ms
RXDM high before rising reset Trmbr 2 us
RXDM high after rising reset Trmar 2 us
Read rising to input parallel
buffer full
Trrbf 0 ns
Write rising to output parallel
buffer empty
Twrbe 0 ns
Table 6-3 Switching Characteristics
Notes: All switching timing when CLKIN is 33.333MHz.
1 Fall time is from 2.3V to 1V.
2 Rise time is from 1V to 2.3V.
iChip CO210AG Data Sheet 6-3
Connect One Electrical Specifications
6.2.2 Local BUS Read Cycle
A20-A0
-BHE Address
D15-D0
(Read)
CLKIN
Tclk
-CS_LAN
or -CSE
-RD
Data
Txfac
Txrra Txfri
Tdsbrh
Txfac
Tdsarh
Figure 6-1 Local BUS Read Cycle
6.2.3 Local BUS Write Cycle
igure 6-2 Local BUS Write Cycle
A20-A0
-BHE Address
D15-D0
(Write)
CLKIN
-CS_LAN
or -CSE
Data
Txfac
Txrwa Txfwi
Txfac
Tdovaw
-WR
Txrdv
F
iChip CO210AG Data Sheet 6-4
Connect One Electrical Specifications
6.2.4 Clock Waveform
iChip CO210AG Data Sheet 6-5
Figure 6-3 Clock Waveform
6.2.5 Reset Timing
Figure 6-4 Reset Timing
Tcico
CLKIN
Tckhl Tcklh
Tclck Tchck
CLKOUT
-RES
TXDM
Trst
Don't careDon't care
Trmbr
Trmar
Connect One Electrical Specifications
6.2.6 Parallel BUS Read Cycle
D7-D0
(Read) Data
PCS
-RD
CLKIN
PIBF
-WR*-CS
Host
Txfac
Txrra
Txfri
Tdsbrh
Tdsarh
Trrbf
Figure 6-5 Parallel BUS Read Cycle
6.2.7 Parallel BUS Write Cycle
igure 6-6 Parallel BUS Write Cycle
CLKIN
Tdovaw
PCS
POBE
Txfac
Twrbe
Txfri
Txrdv
D7-D0
(Write) Data
-WR
-RD*-CS
Host
F
iChip CO210AG Data Sheet 6-6
Connect One Soldering Profile
7 Recommended Soldering Profile
Based on JEDEC J-STD-20:
Convection or IR/Convection VPR
Average Ramp-up rate (183ºC to Peak) 3ºC/sec. Max. 10ºC/sec.
Preheat temperature 125ºC ± 25ºC 120 sec. Max.
Temperature maintained above 183ºC 60 sec. to 150 sec.
Time within 5ºC of actual peak temperature 10 sec. to 20 sec. 60 sec.
Peak temperature range 220 +5/-0ºC 215ºC to 219ºC
Ramp down rate 6ºC/sec. 10ºC/sec.
Time 25ºC to peak temperature 6 min. max.
Table 7-1 Recommended Soldering Profile
Note: A maximum of three reflow passes are allowed per device.
iChip CO210AG Data Sheet 7-1
Connect One Mechanical Dimensions
8 Mechanical Dimensions
Top View Bottom View
iChip CO210AG Data Sheet 8-1
Figure 8-1: Mechanical Dimensions
Side View
0.26
1.20
10.00
A1 Corner
A1 Corner
1 2 3 4 5 6 7 8 9 10 11 11 10 987654321
0.80
A
B
C
D
E
F
G
H
J
K
L
ABCDE FGHJKL
8.00 10.00
Φ0.38 0.80
8.00
Connect One iChip Designs
9 iChip Designs
9.1 Serial Host and Ethernet Controller Environment
iChip CO210AG Data Sheet 9-1
Figure 9-1 Serial Host and Ethernet Controller Environment
9.2 Parallel Host and Ethernet Controller Environment
Figure 9-2 Parallel Host and Ethernet Controller Environment
Modem
Serial
Ethernet
Controller
iChip
D0-D15
Embedded
CPU (Host) LAN
A0-A19
Serial
-RD
LANINT
-WR
Modem
Ethernet
Controller
D0-D15
LAN
-RD
LANINT
-WR
iChip
A0-A19
Parallel
PAL
Embedded
CPU
(Host)
Parallel
Serial
Connect One iChip Designs
9.3 Selecting the Reset Circuit
9.3.1 RC Network
The Reset signal may be designed with an RC network. τ should be greater than 10 mSec.
This is a low-cost solution.
Vcc
D
10U
10K
-RES
Figure 9-3 RC Reset Circuit
9.3.2 Supervisory Circuit
GND
GND
GND
Vcc
GND
Vcc
+
C15
1UF/16V
R1
4.7K
U3
MAX708R
1
4
8
7
5
2
3
6
MR
PFI
RESET
RESET
PFO
VCC
GND
NC
C11
0.1UF
-RES
Figure 9-4 Supervisory Reset Circuit
iChip CO210AG Data Sheet 9-2
Connect One Protocol Compliance
10 Internet Protocol Compliance
iChip CO210AG complies with the following Internet standards:
RFC 768 User Datagram Protocol (UDP)
RFC 791 Internet Protocol (IP)
RFC 792 ICMP – Internet Control Message Protocol
RFC 793 Transmission Control Protocol (TCP)
RFC 821 Simple Mail Transfer Protocol (SMTP)
RFC 822 Standard for the Format of ARPA Internet Text Messages
RFC 826 Ethernet Address Resolution Protocol (ARP)
RFC 959 File Transfer Protocol (FTP)
RFC 854 TELNET protocol specification
RFC 857 Telnet ECHO option
RFC 858 Telnet suppress Go-Ahead option
RFC 1034 DOMAIN NAMES (DNS) - Concepts and Facilities
RFC 1035 DOMAIN NAMES (DNS) - Implementation and Specification
RFC 1091 Telnet terminal type option
RFC 1073 Telnet window size option
RFC 1321 MD5 Message Digest Algorithm
RFC 1331 Point-to-Point Protocol (PPP)
RFC 1332 PPP Internet Protocol Control Protocol (IPCP)
RFC 1334 PPP Authentication Protocol (PAP)
RFC 1570 PPP LCP Extensions
RFC 1661 Point-to-Point Protocol (PPP)
RFC 1877 PPP IPCP Extensions for Name Server Addresses
RFC 1939 Post Office Protocol - Version 3 (POP3)
RFC 1957 Some Observations on the Implementations of the Post Office
Protocol (POP3)
RFC 1994 PPP Challenge Handshake Authentication Protocol (CHAP)
RFC 2030 Simple Network Time Protocol (SNTP)
RFC 2045 Multipurpose Internet Mail Extensions (MIME) Part One: Format of
Internet Message Bodies
RFC 2046 Multipurpose Internet Mail Extensions (MIME) Part Two: Media
Types
RFC 2047 MIME (Multipurpose Internet Mail Extensions) Part Three: Message
Header Extensions for Non-ASCII Text
RFC 2048 Multipurpose Internet Mail Extensions (MIME) Part Four:
Registration Procedures
RFC 2049 Multipurpose Internet Mail Extensions (MIME) Part Five:
Conformance Criteria and Examples
RFC 2068 HyperText Transfer Protocol HTTP/1.1
RFC 2131 Dynamic Host Configuration Protocol (DHCP)
RFC 2132 DHCP Options (only relevant parts)
Table 10-1 Internet Protocol Compliance
iChip CO210AG Data Sheet 10-1
Connect One List of Terms and Acronyms
11 List of Terms and Acronyms
AT+iTM Connect One's Internet extension to the industry-standard Hayes AT
command set. Supports simplified Internet connectivity commands in the
spirit of the AT syntax.
Base64 Encoding scheme, which converts arbitrary binary data into a 64-character
subset of US ASCII. The encoded data is 33% larger than the original data.
CHAP Challenge Authentication Protocol. Extends the PAP procedure by
introducing advanced elements of security.
DNS Domain Name System. Defines the structure of Internet names and their
association with IP addresses.
FTP File Transfer Protocol. Used to provide file and directory services for remote
server file systems.
iChipTM Connect One’s Internet Controller for embedded Internet connectivity.
ICMP Internet Control Message Protocol. Network layer Internet protocol that
reports errors and provides other information relevant to IP packet processing.
IP Internet Protocol. Provides for transmitting blocks of data, called datagrams,
from sources to destinations, which are hosts identified by fixed length
addresses. Also provides for fragmentation and reassemble of long datagrams,
if necessary.
IPCP Internet Protocol Control Protocol. Establishes and configures the Internet
Protocol over PPP. Also negotiates Van Jacobson TCP/IP header compression
with PPP.
ISP Internet Service Provider. Commercial company that provides Internet
access to end (mostly PC) users through a dial-up connection.
LCP Link Control Protocol. Negotiates data link characteristics and tests the
integrity of the link.
"Leave on
Server"
An option designating whether retrieved Email messages are to be left intact
on the server for subsequent downloads or are to be deleted from the server
after a successful download.
MIME Multipurpose Internet Mail Extensions. Extends the format of mail message
bodies to allow multi-part textual and non-textual data to be represented and
exchanged between Internet mail servers.
PAP Password Authentication Protocol. Used optionally by the PPP protocol to
identify the user to the ISP.
ping ICMP protocol ECHO message and its reply. Often used to debug IP
networks and to test the accessibility of a network device.
POP3 Post Office Protocol Version 3. Allows a workstation/PC to dynamically
retrieve mail from a mailbox kept on a remote server.
PPP Point-to-Point Protocol. Communications protocol used to send data across
serial communication links, such as modems.
RFC Request For Comments. Collections of standards that define the way remote
computers communicate over the Internet.
SMTP Simple Mail Transfer Protocol. Provides for transferring mail reliably and
efficiently over the Internet.
iChip CO210AG Data Sheet 11-1
Connect One List of Terms and Acronyms
SNTP Simple Network Time Protocol. Used to retrieve accurate time of day from a
networked time server. The accurate UTC/GMT time is retrieved.
TCP Transmission Control Protocol. Provides reliable stream-oriented
connections over the Internet. Works in conjunction with its underlying IP
protocol.
Telnet Network Terminal Protocol. Provides remote terminal connectivity, which
allows to execute tasks on a remote application server.
Table 11-1 Terms and Acronyms
iChip CO210AG Data Sheet 11-2
