Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. H
01/13/2010
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IS62WV12816ALL
IS62WV12816BLL
128K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 45ns, 55ns, 70ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
– 1.65V--2.2V VDD (62WV12816ALL)
– 2.5V--3.6V VDD (62WV12816BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• 2CS Option Available
• Lead-free available
DESCRIPTION
The ISSI IS62WV12816ALL/ IS62WV12816BLL are high-
speed, 2M bit static RAMs organized as 128K words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS62WV12816ALL and IS62WV12816BLL are packaged
in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and
44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
JANUARY 2010
A0-A16
CS1
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
CS2
IS62WV12816ALL, IS62WV12816BLL
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. H
01/13/2010
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
(Package Code B)
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CS1, CS2 Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
VDD Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 N/C
I/O8UB A3 A4 CSI I/O0
I/O9I/O10 A5 A6 I/O1I/O2
GND I/O11 NC A7 I/O3VDD
VDD I/O12 NC A16 I/O4GND
I/O14 I/O13 A14 A15 I/O5I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
48-Pin mini BGA (6mm x 8mm)
2 CS Option (Package Code B2)
44-Pin mini TSOP (Type II)
(Package Code T)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 CS2
I/O
8
UB A3 A4 CS1 I/O
0
I/O
9
I/O
10
A5 A6 I/O
1
I/O
2
GND I/O
11
NC A7 I/O
3
VDD
VDD I/O
12
NC A16 I/O
4
GND
I/O
14
I/O
13
A14 A15 I/O
5
I/O
6
I/O
15
NC A12 A13 WE I/O
7
NC A8 A9 A10 A11 NC
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Rev. H
01/13/2010
IS62WV12816ALL, IS62WV12816BLL
TRUTH TABLE
I/O PIN
Mode WEWE
WEWE
WE CS1CS1
CS1CS1
CS1 CS2 OEOE
OEOE
OE LBLB
LBLB
LB UBUB
UBUB
UB I/O0-I/O7 I/O8-I/O15 VDD Current
Not Selected X H X X X X High-Z High-Z ISB1, ISB2
X X L X X X High-Z High-Z ISB1, ISB2
XXXXHH High-Z High-Z ISB1, ISB2
Output Disabled H L H H L X High-Z High-Z ICC
H L H H X L High-Z High-Z ICC
Read H L H L L H DOUT High-Z ICC
H L H L H L High-Z DOUT
HLHL LL DOUT DOUT
Write L L H X L H DIN High-Z ICC
L L H X H L High-Z DIN
LLHXLL DIN DIN
OPERATING RANGE (VDD)
Range Ambient Temperature IS62WV12816ALL IS62WV12816BLL
Commercial 0°C to +70°C 1.65V - 2.2V 2.5V - 3.6V
Industrial –40°C to +85°C 1.65V - 2.2V 2.5V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.2 to VDD+0.3 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
IS62WV12816ALL, IS62WV12816BLL
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Rev. H
01/13/2010
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Input/Output Capacitance VOUT = 0V 10 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions VDD Min. Max. Unit
VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V 1.4 — V
IOH = -1 mA 2.5-3.6V 2.2 — V
VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V — 0.2 V
IOL = 2.1 mA 2.5-3.6V — 0.4 V
VIH Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V
2.5-3.6V 2.2 VDD + 0.3 V
VIL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V
2.5-3.6V –0.2 0.6 V
ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
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Rev. H
01/13/2010
IS62WV12816ALL, IS62WV12816BLL
IS62WV12816ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Test Conditions Max. Unit
70
ICC VDD Dynamic Operating VDD = Max., Com. 15 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 20
ICC1Operating Supply VDD = Max., Com. 3 mA
Current IOUT = 0 mA, f = 0 Ind. 3
ISB1TTL Standby Current VDD = Max., Com. 0.3 mA
(TTL Inputs) VIN = VIH or VIL Ind. 0.3
CS1 = VIH , CS2 = VIL,
f = 1 MHZ
OR
ULB Control
VDD = Max., VIN = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
ISB2CMOS Standby VDD = Max., Com. 5 µA
Current (CMOS Inputs) CS1
≥
V DD – 0.2V, Ind. 10
CS2
≤ 0.2V,
VIN
≥
V DD – 0.2V, or
VIN
≤
0.2V, f = 0
OR
ULB Control VDD = Max., CS1 = VIL, CS2=VIH
VIN ≤ 0.2V, f = 0; UB / LB = VDD – 0.2V
IS62WV12816BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Test Conditions Max. Max. Unit
45 55
ICC VDD Dynamic Operating VDD = Max., Com. 35 25 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 40 30
typ.
(2)
25 20
ICC1Operating Supply VDD = Max., Com. 3 3 mA
Current IOUT = 0 mA, f = 0 Ind. 3 3
ISB1TTL Standby Current VDD = Max., Com. 0.3 0.3 mA
(TTL Inputs) VIN = VIH or VIL Ind. 0.3 0.3
CS1 = VIH , CS2 = VIL,
f = 1 MHZ
OR
ULB Control
VDD = Max., VIN = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
ISB2CMOS Standby VDD = Max., Com. 10 10 µA
Current (CMOS Inputs) CS1
≥
V DD – 0.2V, Ind. 10 10
CS2
≤ 0.2V,
typ.
(2)
33
VIN
≥
V DD – 0.2V, or
VIN
≤
0.2V, f = 0
OR
ULB Control VDD = Max., CS1 = VIL, CS2=VIH
VIN ≤ 0.2V, f = 0; UB / LB = VDD – 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
IS62WV12816ALL, IS62WV12816BLL
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Rev. H
01/13/2010
AC TEST CONDITIONS
Parameter 62WV12816ALL 62WV12816BLL
(Unit) (Unit)
Input Pulse Level 0.4V to VDD-0.2V 0.4V to VDD-0.3V
Input Rise and Fall Times 5 ns 5ns
Input and Output Timing VREF VREF
and Reference Level
Output Load See Figures 1 and 2 See Figures 1 and 2
AC TEST LOADS
Figure 1 Figure 2
1.65-2.2V 2.5V - 3.6V
R1(Ω)Ω)
Ω)Ω)
Ω) 3070 3070
R2(Ω)Ω)
Ω)Ω)
Ω) 3150 3150
VREF 0.9V 1.5V
VTM 1.8V 2.8V
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
R1
30 pF
Including
jig and
scope
R2
OUTPUT
VTM
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Rev. H
01/13/2010
IS62WV12816ALL, IS62WV12816BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
45 ns 55 ns 70 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 45 — 55 — 70 — ns
tAA Address Access Time — 45 — 55 — 70 ns
tOHA Output Hold Time 10 — 10 — 10 — ns
tACS1/tACS2 CS1/CS2 Access Time — 45 — 55 — 70 ns
tDOE OE Access Time — 20 — 25 — 35 ns
tHZOE(2) OE to High-Z Output — 15 — 20 — 25 ns
tLZOE(2) OE to Low-Z Output 5 — 5 — 5 — ns
tHZCS1/tHZCS2(2) CS1/CS2 to High-Z Output 0 15 0 20 0 25 ns
tLZCS1/tLZCS2(2) CS1/CS2 to Low-Z Output 10 — 10 — 10 — ns
tBA LB, UB Access Time — 45 — 55 — 70 ns
tHZB LB, UB to High-Z Output 0 15 0 20 0 25 ns
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
IS62WV12816ALL, IS62WV12816BLL
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Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. H
01/13/2010
DATA VALID
PREVIOUS DATA VALID
tAA
tOHA tOHA
tRC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL)
tRC
tOHA
tAA
tDOE
tLZOE
tACE1/tACE2
tLZCE1/
tLZCE2
tHZOE
HIGH-Z DATA VALID
tHZCS1/
tHZCS2
ADDRESS
OE
CS1
CS2
DOUT
LB
,
UB
tHZB
tBA
tLZB
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = VIL. CS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW transition.
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Rev. H
01/13/2010
IS62WV12816ALL, IS62WV12816BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
45ns 55 ns 70 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 45 — 55 — 70 — ns
tSCS1/tSCS2 CS1/CS2 to Write End 35 — 45 — 60 — ns
tAW Address Setup Time to Write End 35 — 45 — 60 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 35 — 45 — 60 — ns
tPWE WE Pulse Width 35 — 40 — 50 — ns
tSD Data Setup to Write End 20 — 25 — 30 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
tHZWE(3) WE LOW to High-Z Output — 20 — 20 — 20 ns
tLZWE(3) WE HIGH to Low-Z Output 5 — 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V
and output loading specified in Figure 1.
2.
The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
IS62WV12816ALL, IS62WV12816BLL
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Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. H
01/13/2010
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
LB, UB
t
PWB
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
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Rev. H
01/13/2010
IS62WV12816ALL, IS62WV12816BLL
DATA-IN VALID
DATA UNDEFINED
t
WC
tSCS1
tSCS2
tAW
tHA
tPWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
IS62WV12816ALL, IS62WV12816BLL
12
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. H
01/13/2010
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
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Rev. H
01/13/2010
IS62WV12816ALL, IS62WV12816BLL
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
t
HD
t
SA
t
HZWE
ADDRESS
CS1
UB, LB
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
UB_CSWR4.eps
HIGH
CS2
AC WAVEFORMS
WRITE CYCLE NO. 4 (UB/LB Controlled)
IS62WV12816ALL, IS62WV12816BLL
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Rev. H
01/13/2010
DATA RETENTION WAVEFORM (CS1 Controlled)
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 1.0 3.6 V
IDR Data Retention Current VDD = 1.0V, CS1 ≥ VDD – 0.2V — 10 µA
tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC —ns
DATA RETENTION WAVEFORM (CS2 Controlled)
VDD
CS1 ≥ VDD
- 0.2V
tSDR tRDR
VDR
CS1
GND
Data Retention Mode
CS2 ≤ 0.2V
tSDR tRDR
V
DR
CS2
GND
Data Retention Mode
VDD
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Rev. H
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IS62WV12816ALL, IS62WV12816BLL
ORDERING INFORMATION: IS62WV12816ALL (1.65V - 2.2V)
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
70 IS62WV12816ALL-70T TSOP (Type II)
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
70 IS62WV12816ALL-70TI TSOP (Type II)
70 IS62WV12816ALL-70BI mini BGA (6mm x 8mm)
70 IS62WV12816ALL-70BLI mini BGA (6mm x 8mm), Lead-free
70 IS62WV12816ALL-70B2I mini BGA (6mm x 8mm), 2 CS Option
ORDERING INFORMATION: IS62WV12816BLL (2.5V - 3.6V)
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
45 IS62WV12816BLL-45B mini BGA (6mm x 8mm)
45 IS62WV12816BLL-45B2 mini BGA (6mm x 8mm), 2 CS Option
55 IS62WV12816BLL-55T TSOP (Type II)
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
45 IS62WV12816BLL-45TLI TSOP (Type II), Lead-free
55 IS62WV12816BLL-55TI TSOP (Type II)
55 IS62WV12816BLL-55TLI TSOP (Type II), Lead-free
55 IS62WV12816BLL-55BI mini BGA (6mm x 8mm)
55 IS62WV12816BLL-55BLI mini BGA (6mm x 8mm), Lead-free
55 IS62WV12816BLL-55B2I mini BGA (6mm x 8mm), 2 CS Option
55 IS62WV12816BLL-55B2LI mini BGA (6mm x 8mm), 2 CS Option, Lead-free
IS62WV12816ALL, IS62WV12816BLL
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Rev. H
01/13/2010
2. Reference document : JEDEC MO-207
1. CONTROLLING DIMENSION : MM .
NOTE :
08/12/2008
Package Outline
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Rev. H
01/13/2010
IS62WV12816ALL, IS62WV12816BLL
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
06/04/2008
Package Outline
