S7030/S7031 series is a family of FFT-CCD image sensors specifically designed for low-light-level detection in scientific applications. By using
the binning operation, S7030/S7031 series can be used as a linear image sensor having a long aperture in the direction of the device length. This
makes S7030/S7031 series ideally suited for use in spectrophotometry. The binning operation offers significant improvement in S/N and signal
processing speed compared with conventional methods by which signals are digitally added by an external circuit. S7030/S7031 series also
features low noise and low dark signal (MPP mode operation). This enables low-light-level detection and long integration time, thus achieving a
wide dynamic range.
S7030/S7031 series has an effective pixel size of 24 × 24 µm and is available in image areas ranging from 12.288 (H) × 1.392(V) mm2 (512 × 58
pixels) up to a large image area of 24.576 (H) × 6.000 (V) mm2 (1024 × 250 pixels).
Features
l
Non-cooled type: S7030 series
One-stage TE-cooled type: S7031 series
l
Pixel size: 24 × 24 µm
l
Line, pixel binning
l
Greater than 90 % quantum efficiency at peak sensitivity
wavelength
l
Wide spectral response range
l
Low readout noise
l
Wide dynamic range
l
MPP operation
l
High UV sensitivity with good stability
Applications
l
Fluorescence spectrometer, ICP
l
Industrial inspection requiring
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Semiconductor inspection
l
DNA sequencer
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Low-light-level detection
IMAGE SENSOR
CCD area image sensor
Back-thinned FFT-CCD
S7030/S7031 series
■ Selection guide
Type No. Cooling Number of total
pixels
Number of active
pixels
Active area
[mm (H) × mm (V)]
Suitable
multichannel
detector head
S7030-0906 532 × 64 512 × 58 12.288 × 1.392
S7030-0907 532 × 128 512 × 122 12.288 × 2.928
S7030-0908 532 × 256 512 × 250 12.288 × 6.000
S7030-1006 1044 × 64 1024 × 58 24.576 × 1.392
S7030-1007 1044 × 128 1024 × 122 24.576 × 2.928
S7030-1008
Non-cooled
1044 × 256 1024 × 250 24.576 × 6.000
C7040
S7031-0906S 532 × 64 512 × 58 12.288 × 1.392
S7031-0907S 532 × 128 512 × 122 12.288 × 2.928
S7031-0908S 532 × 256 512 × 250 12.288 × 6.000
S7031-1006S 1044 × 64 1024 × 58 24.576 × 1.392
S7031-1007S 1044 × 128 1024 × 122 24.576 × 2.928
S7031-1008S
One-stage
TE-cooled
1044 × 256 1024 × 250 24.576 × 6.000
C7041
■ General ratings
Parameter S7030 series S7031 series
Pixel size 24 (H) × 24 (V) µm
Vertical clock phase 2 phases
Horizontal clock phase 2 phases
Output circuit One-stage MOSFET source follower
Package 24 pin ceramic DIP (refer to dimensional outlines)
Window *1 Quartz glass AR-coated sapphire
*1: Temporary window type (ex. S7030-0906N) is available upon request.
(Temporary window is fixed by tape to protect the CCD chip and wire bonding.)
1
CCD area image sensor
S7030/S7031 series
■ Absolute maximum ratings (Ta=25 °C)
Parameter Symbol Min. Typ. Max. Unit
Operating temperature *2Topr -50 - +30 °C
Storage temperature Tstg -50 -+70 °C
OD voltage VOD -0.5 - +25 V
RD voltage VRD -0.5 -+18 V
ISV voltage VISV -0.5 - +18 V
ISH voltage VISH -0.5 -+18 V
IGV voltage VIG1V, VIG2V -10 - +15 V
IGH voltage VIG1H, VIG2H -10 -+15 V
SG voltage VSG -10 - +15 V
OG voltage VOG -10 -+15 V
RG voltage VRG -10 - +15 V
TG voltage VTG -10 -+15 V
Vertical clock voltage VP1V, VP2V -10 - +15 V
Horizontal clock voltage VP1H, VP2H -10 -+15 V
*2: Chip temperature
■ Operating conditions (MPP mode, Ta=25 °C)
Parameter Symbol Min. Typ. Max. Unit
Output transistor drain voltage VOD 18 20 22 V
Reset drain voltage VRD 11.5 12 12.5 V
Output gate voltage VOG 13 5V
Substrate voltage VSS - 0 - V
Test point (vertical input source) VISV -V
RD -V
Test point (horizontal input source) VISH - VRD - V
Test point (vertical input gate) VIG1V, VIG2V -9
Test point (horizontal input gate) VIG1H, VIG2H -9-8 - V
High VP1VH, VP2VH 46 8
Vertical shift register
clock voltage Low VP1VL, VP2VL -9 -8 -7 V
High VP1HH, VP2HH 4 6 8
Horizontal shift register
clock voltage Low VP1HL, VP2HL -9 -8 -7 V
High VSGH 46 8
Summing gate voltage Low VSGL -9 -8 -7 V
High VRGH 4 6 8
Reset gate voltage Low VRGL -9 -8 -7 V
High VTGH 46 8
Transfer gate voltage Low VTGL -9 -8 -7 V
■ Electrical characteristics (Ta=25 °C)
Parameter Symbol Min. Typ. Max. Unit
Signal output frequency fc - 0.25 1 MHz
S703*-0906 -750 -
S703*-0907/-1006 1500 -
S703*-0908/-1007 3000 -
Vertical shift register
capacitance
S703*-1008
CP1V, CP2V
6000 -
pF
S703*-0906/-0907/-0908 110
Horizontal shift register
capacitance S703*-1006/-1007/-1008 CP1H, CP2H -180 -pF
Summing gate capacitance CSG -30 -pF
Reset gate capacitance CRG -30 -pF
S703*-0906/-0907/-0908 55
Transfer gate capacitance S703*-1006/-1007/-1008 CTG -75 -pF
Charge transfer efficiency *3CTE 0.99995 0.99999 - -
DC output level *4Vout 14 16 18 V
Output impedance *4Zo - 3 4 kΩ
Power consumption *4 *5P - 13 14 mW
*3: Charge transfer efficiency per pixel, measured at half of the full well capacity.
*4: The values depend on the load resistance. (Typical, VOD=20 V, Load resistance=22 kΩ)
*5: Power consumption of the on-chip amplifier.
2
-
-8 V
CCD area image sensor
S7030/S7031 series
0
10
100 200
WAVELENGTH (nm)
TRANSMITTANCE (%)
300 400 500 600 700 800 900
1000 1100 1200
20
30
40
50
60
70
80
90
100 (Typ. Ta=25 ˚C)
QUARTZ WINDOW
AR COATED SAPPHIRE
QUANTUM EFFICIENCY (%)
WAVELENGTH (nm)
(Typ. Ta=25 ˚C)
0
200 400 600 800 1000 1200
10
20
30
40
50
60
70
80
90
100
FRONT-SIDED
FRONT-SIDED
(UV COAT)
BACK-THINNED
● W indow material
Type No. Window material
S7030 series Quartz glass *15
(option: window-less)
S7031 series AR-coated sapphire *16
(option: window-less)
S7032 series
(two-stage
TE-cooled types,
made to order)
AR-coated sapphire *16
(option: window-less)
*15: Resin sealing
*16: Hermetic sealing
*14: Spectral response with quartz glass or AR-coated
sapphire are decreased by the transmittance.
■ Spectral response (without window) *14 ■ Spectral transmittance characteristics
KMPDB0058EA KMPDB0110EA
■ Dark current vs. temperature
3
-50 -40 -30 -20 0-10 10 20 30
TEMPERATURE (˚C)
0.01
1
0.1
10
100
1000
DARK CURRENT (e
-
/pixel/s)
(Typ.)
KMPDB0256EA
■ Electrical and optical characteristics (Ta=25 °C, unless otherwise noted)
Parameter Symbol Min. Typ. Max. Unit
Saturation output voltage Vsat - Fw × Sv - V
Vertical 240 320 -
Full well capacity Horizontal *6 Fw 800 1000 - ke-
CCD node sensitivity Sv 1.8 2.2 - µV/e-
25 °C - 100 1000 D ark current *7
MPP mode
(tentative data) 0 °C DS - 10 100 e-/pixe l/s
Readout noise *8 Nr - 8 16 e- rm s
Line binning 100000 125000 - -
Dynamic range *9 Area scanning DR 30000 40000 - -
Photo response non-uniformity *10 PRNU - ±3 ±10 %
Spectral response range λ - 200 to 1100 - nm
W hite spots - - 0 -
Point defect *11 Black spots - - 10 -
Cluster defect *12 - - 3 -
Blemish
Colum n defect *13
-
- - 0 -
*6: The linearity is ±1.5 % .
*7: Dark current nearly doubles for every 5 to 7 °C increase in temperature.
*8: Measured with a HAMAMATSU C4880 digital CCD camera with a CDS circuit (sensor temperature: -40 °C, operating frequency:
150 kHz).
*9: Dynamic range (DR) = Full well/Readout noise
*10: Measured at one-half of the saturation output (full well capacity) using a white fluorescent lamp.
*11: W hite spots
Pixels whose dark current is higher than 1 ke- after one-second integration at 0 °C.
Black spots
Pixels whose sensitivity is lower than one-half of the average pixel output. (Measured with uniform light producing one-half
of the saturation charge)
*12: 2 to 9 contiguous defective pixels
*13: 10 or more contiguous defective pixels
Fixed pattern noise (peak to peak)
Signal × 100
Photo response non-uniformity (PRNU) [%]
CCD area image sensor
S7030/S7031 series
■ Device structure (Conceptual drawing of top view)
23
22
21
20
14
15
24
1
2
12
11
893
4
5
2 BEVEL
SIGNAL OUT
2n
4 BLANK 4 BLANK
V=58, 122, 250
H=512, 1024
4 BEVEL
THINNING
THINNING
12345
2
3
4
5
V
H
6 BEVEL 6 BEVEL
2
nSIGNAL OUT
13
10
KMPDC0016EB
INTEGRATION PERIOD
(Shutter must be open) VERTICAL BINNING PERIOD
(Shutter must be closed)
P1V
P2V, TG
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
3.. 62
3..126
3..254
63
127
255
64←
128←
256←
58 + 6 (BEVEL): S703*-0906/-1006
122 + 6 (BEVEL): S703*-0907/-1007
250 + 6 (BEVEL): S703*-0908/-1008
Tpwv
Tovr
Tpwh, Tpws
Tpwr
123
531
1043 532
1044: S703*-0906/-0907/-0908
: S703*-1006/-1007/-1008
4..530
4..1042
12
D19D2D1 D20
D3..D10, S1..S1024, D11..D18
RG
OS
S1..S512
: S703*-0906/-0907/-0908
: S703*-1006/-1007/-1008
■ Timing chart
KMPDC0017EB
Parameter Symbol Remark Min. Typ. Max. Unit
Pulse width Tpwv 6 *18 8 - µs
P1V, P2V, TG Rise and fall time Tprv, Tpfv
*17
10 - - ns
Pulse width Tpwh 500 2000 - ns
Rise and fall time Tprh, Tpfh 10 - - ns
P1H, P2H
Duty ratio -
*17
- 50 - %
Pulse width Tpws 500 2000 - ns
Rise and fall time Tprs, Tpfs 10 - - ns
SG
Duty ratio -
-
- 50 - %
Pulse width Tpwr 100 - - ns
RG Rise and fall time Tprr, Tpfr - 5 - - ns
TG – P1H Overlap time Tovr - 3 - - µs
*17: The clock pulses should be overlapped at 50 % of clock pulse amplitude.
*18: In case of S7030-0908/-1007, S7031-0908S/-1007S
Line bininng
4
CCD area image sensor
S7030/S7031 series
Parameter Symbol Remark Min. Typ. Max. Unit
Pulse width Tpwv 6 *20 8 - µs
P1V, P2V, TG Rise and fall time Tprv, Tpfv *19 10 - - ns
Pulse width Tpwh 500 2000 - ns
Rise and fall time Tprh, Tpfh 10 - - ns
P1H, P2H
Duty ratio -
*19
- 50 - %
Pulse width Tpws 500 2000 - ns
Rise and fall time Tprs, Tpfs 10 - - ns
SG
Duty ratio -
-
- 50 - %
Pulse width Tpwr 100 - - ns
RG Rise and fall time Tprr, Tpfr - 5 - - ns
TG - P1H Overlap time Tovr - 3 - - µs
*19: The clock pulses should be overlapped at 50 % of clock pulse amplitude.
*20: In case of S7030-0908/-1007, S7031-0908S/-1007S
5
INTEGRATION PERIOD
(Shutter must be open)
P1V
RG
OS
P2V, TG
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
ENLARGED VIEW
Tpwv
Tovr
Tpwr
D1 D2 D3 D4 D18 D19 D20
D5..D10, S1..S1024, D11..D17
P2V, TG
P1H
P2H, SG
RG
OS
Tpwh, Tpws
123
S1..S512 : S703 *-0906/-0907/-0908
: S703 *-1006/-1007/-1008
4.. 63
4..127
4..255
64←58 + 6 (BEVEL): S703 *-0906/-1006
128←122 + 6 (BEVEL): S703 *-0907/-1007
256←250 + 6 (BEVEL): S703 *-0908/-1008
KMPDC0127EA
Area scanning: large full well mode
CCD area image sensor
S7030/S7031 series
6
WINDOW 16.3 *
21
8.2 *
21
34.0 ± 0.34
50.0 ± 0.30
2.54 ± 0.13
22.9 ± 0.3
19.0
4.0
42.0
22.4 ± 0.3
a
7.3 ± 0.63
1.0
7.7 ± 0.68
6.65 ± 0.63
4.89 ± 0.15
ACTIVE AREA
12.29
PHOTOSENSITIVE SURFACE
1st PIN INDICATION PAD
3.0
TE-COOLER
S7031-0906S: a=1.392
S7031-0907S: a=2.928
S7031-0908S: a=6.000 (24 ×) 0.5 ± 0.05
4.4 ± 0.44
4.8 ± 0.49
2.35 ± 0.15
3.75 ± 0.44
PHOTOSENSITIVE SURFACE
1st PIN INDICATION PAD
3.0
(24 ×) 0.5 ± 0.05
WINDOW 16.3 *
21
8.2 *
21
34.0 ± 0.34
2.54 ± 0.13
22.9 ± 0.30
22.4 ± 0.30
a
ACTIVE AREA
12.29
S7030-0906: a=1.392
S7030-0907: a=2.928
S7030-0908: a=6.000
■ Dimensional outlines (unit: mm)
S7030-0906/-0907/-0908 S7030-1006/-1007/-1008
KMPDA0046EC KMPDA0047ED
S7031-0906S/-0907S/-0908S S7031-1006S/-1007S/-1008S
KMPDA0048ED KMPDA0049EE
3.0
PHOTOSENSITIVE SURFACE
4.4 ± 0.44
2.35 ± 0.15
4.8 ± 0.49
3.75 ± 0.44
WINDOW 28.6 *21
22.9 ± 0.3
22.4 ± 0.3
ACTIVE AREA 24.58
a
8.2 *21
44.0 ± 0.44
2.54 ± 0.13
1st PIN INDICATION PAD
S7030-1006: a=1.392
S7030-1007: a=2.928
S7030-1008: a=6.000
(24 ×) 0.5 ± 0.05
(24 ×) 0.5 ± 0.05
7.3 ± 0.63
1.0
3.0
6.65 ± 0.63
4.89 ± 0.15
PHOTOSENSITIVE SURFACE
7.7 ± 0.68
1st PIN INDICATION PAD
a
4.0
19.0
22.4 ± 0.3
22.9 ± 0.3
44.0 ± 0.44
52.0
60.0 ± 0.3
2.54 ± 0.13
WINDOW 28.6 *
21
ACTIVE AREA 24.58
8.2 *
21
S7031-1006S: a=1.392
S7031-1007S: a=2.928
S7031-1008S: a=6.000
TE-COOLER
*21: Size of window that guarantees the transmittance in the "Spectral transmittance characteristics" graph
CCD area image sensor
S7030/S7031 series
■ Pin connections
S7030 series S7031 series
Pin
No. Symbol Function Symbol Function
Remark
(standard operation)
1 RD Reset drain RD Reset drain +12 V
2OS Output transistor source OS Output transistor source
R
L
=10 k to 100 k
Ω
3 OD Output transistor drain OD Output transistor drain +20 V
4OG Output gate OG Output gate +3 V
5 SG Summing gate SG Summing gate
Same pulse as P2H
6 - -
7- -
8P2H CCD horizontal register clock-2 P2H CCD horizontal register clock-2
9 P1H CCD horizontal register clock-1 P1H CCD horizontal register clock-1
10 IG2H Test point (horizontal input gate-2) IG2H Test point (horizontal input gate-2) -8 V
11 IG1H Test point (horizontal input gate-1) IG1H Test point (horizontal input gate-1) -8 V
12 ISH Test point (horizontal input source) ISH Test point (horizontal input source) Connect to RD
13 TG *22 Transfer gate TG *22 Transfer gate
Same pulse as P2V
14 P2V CCD vertical register clock-2 P2V CCD vertical register clock-2
15 P1V CCD vertical register clock-1 P1V CCD vertical register clock-1
16 -Th1 Thermistor
17 - Th2 Thermistor
18 -P- TE-cooler-
19 - P+ TE-cooler+
20 SS Substrate (GND) SS Substrate (GND) GND
21 ISV Test point (vertical input source) ISV Test point (vertical input source) Connect to RD
22 IG2V Test point (vertical input gate-2) IG2V Test point (vertical input gate-2) -8 V
23 IG1V Test point (vertical input gate-1) IG1V Test point (vertical input gate-1) -8 V
24 RG Reset gate RG Reset gate
*22: Isolation gate between vertical register and horizontal register. In standard operation, TG should be applied the same pulse as
P2V.
0
1
2
3
VOLTAGE (V)
CCD TEMPERATURE (˚C)
4
7
6
5
-40
-30
432
CURRENT (A)
10
-20
-10
0
10
20
30
(Typ. Ta=25 ˚C)
VOLTAGE vs. CURRENT
CCD TEMPERATURE vs. CURRENT
0
1
2
3
VOLTAGE (V)
CCD TEMPERATURE (˚C)
4
7
6
5
-40
-30
2.01.51.0
CURRENT (A)
0.50
-20
-10
0
10
20
30
(Typ. Ta=25 ˚C)
VOLTAGE vs. CURRENT
CCD TEMPERATURE vs. CURRENT
KMPDB0178EA KMPDB0179EA
S7031-0906S/-0907S/-0908S S7031-1006S/-1007S/-1008S
7
■ Specifications of built-in TE-cooler (Typ. Reference data in vacuum condition)
Parameter Symbol Condition S7031-0906S/-0907S/-0908S S7031-1006S/-1007S/-1008S Unit
Internal resistance Rint Ta=25 °C 2.5 1.2
Ω
Maximum current *23 Imax Tc *24=Th *25=25 °C 1.5 3.0 A
Maximum voltage Vmax Tc *24=Th *25=25 °C 3.8 3.6 V
Maximum heat absorption
*26
Qmax 3.4 5.1 W
Maximum temperature
of heat radiating side - 70 70 °C
*23: Maximum current Imax:
If the current greater than this value flows into the thermoelectric cooler, the heat absorption begins to decrease due to the
Joule heat. It should be noted that this value is not the damage threshold value. To protect the thermoelectric cooler and
maintain stable operation, the supply current should be less than 60 % of this maximum current.
*24: Temperature of the cooling side of thermoelectric cooler
*25: Temperature of the heat radiating side of thermoelectric cooler
*26: Maximum heat absorption Qmax.
This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler when the
maximum current is supplied to the unit.
CCD area image sensor
S7030/S7031 series
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658
France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
Information furnished by HAMAMATSU is believed to be reliable . However, no responsibility is assumed for possible inaccuracies or omissions.
Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2007 Hamamatsu Photonics K.K.
Input Symbol Value
Supply voltage
VD1
VA1+
VA1-
VA2
VD2
Vp
VF
+5 Vdc, 200 mA
+15 Vdc, +100 mA
-15 Vdc, -100 mA
+24 Vdc, 30 mA
+5 Vdc, 30 mA (C7041)
+5 Vdc, 2.5 A (C7041)
+12 Vdc, 100 mA (C7041)
Master start φms
HCMOS logic compatible
Master clock φmc HCMOS logic compatible,
1 MHz
Features
l
C7040: for S7030 series
C7041: for S7031 series
l
Area scanning or full line-binnng operation
l
Readout frequency: 250 kHz
l
Readout noise: 20 e-rms
l
∆T=50 ˚C (∆T changes by cooling method.)
Cat. No. KMPD1023E14
Nov. 2007 DN
Multichannel detector heads C7040, C7041
■ Precaution for use (Electrostatic countermeasures)
● Handle these sensors with bare hands or wearing cotton glove s. In addition, wear anti-static clothing or use a wrist band with
an earth r ing, in order to prevent electrostatic damage due to electrical charges from friction.
● Avoid directly placing these sensors on a work-desk or work-bench that may carr y an electrostatic charge.
● Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electr icity to dis-
charge.
● Ground the tools used to handle these sensors, such as tweezers and solder ing irons.
It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the
amount of damage that occurs.
■ Element cooling/heating temperature incline r ate
When cooling the CCD by an externally attached cooler, set the cooler operation so that the temperature gradient (rate of tempera-
ture change) for cooling or allowing the CCD to warm back is less than 5 K/minute.
■ Specifications of built-in temperature sensor
A chip thermistor is built in the same package with a CCD chip, and the CCD chip temperature can be monitored with it. A relation
between the thermistor resistance and absolute temperature is expressed by the following equation.
R1 = R2 × expB (1 / T1 - 1 / T2)
where R1 is the resistance at absolute temperature T1 (K)
R2 is the resistance at absolute temperature T2 (K)
B is so-called the B constant (K)
The characteristics of the thermistor used are as follows.
R (298K) = 10 kΩ
B (298K / 323K) = 3450 K
KMPDB0111EB
10 kΩ
220 240 260
TEMPERATURE (K)
RESISTANCE
280 300
100 kΩ
1 MΩ
8
