ATL60GA-3.6-03/02 ATL60/ATLS60 Gate Array/Embedded Array Description..................................................................................................................... 1-2 ATL60 and ATLS60 Array Organizations: Tables ....................................................... 1-2 Design ............................................................................................................................ 1-3 Design Systems Supported .................................................................................... 1-3 Design Tools .......................................................................................................... 1-3 Design Flow ........................................................................................................... 1-3 Pin Definition Requirements ................................................................................. 1-3 ATL60 Gate Array Design Flow ........................................................................... 1-4 Design Options .............................................................................................................. 1-4 VHDL/Verilog-HDL ............................................................................................. 1-4 ASIC Design Translation....................................................................................... 1-4 Design Entry .......................................................................................................... 1-4 FPGA and PLD Conversions ................................................................................. 1-4 Macro Cores................................................................................................................... 1-5 AVRTM (8-bit RISC) Microcontroller (8515).......................................................... 1-5 ARM7TDMITM Embedded Microcontroller Core .................................................. 1-5 OakDSPCoreTM ....................................................................................................... 1-5 5.0 Volt DC Characteristics: Table................................................................................ 1-6 3.3 Volt DC Characteristics: Table................................................................................ 1-7 2.0 Volt DC Characteristics: Table................................................................................ 1-7 I/O Buffer DC Characteristics: Table ............................................................................ 1-8 I/O Buffers ............................................................................................................. 1-8 I/O Options ............................................................................................................ 1-8 AC Characteristics ......................................................................................................... 1-9 Source of CMOS Power Dissipation ........................................................................... 1-10 Power Calculation................................................................................................ 1-10 ATL60 Power Estimation Worksheet.......................................................................... 1-10 Power Estimation Worksheet Examples...................................................................... 1-11 Timing and Derating Factors ....................................................................................... 1-17 ATL60 5.0 Volt Derating Factors........................................................................ 1-17 ATL60 3.3 Volt Derating Factors........................................................................ 1-17 Power/Ground .............................................................................................................. 1-18 Power/Ground Rules............................................................................................ 1-18 Fixed Power/Ground Pads ................................................................................... 1-18 1-1 ATL60GA-3.6-03/02 Description Atm el' s ATL60 S e rie s CM O S G a t e A rr ays a n d Embedded Arrays are fabricated using a 0.6m drawn gate, triple level metal process. Extensive cell libraries are available and support the major CAD software tools. As with all Atmel ASIC families, customer involvement and satisfaction is integral to all steps of the design flow. A variety of Design for Testability techniques are su p p o rte d b y the lib ra rie s, an d a wide ra ng e o f packaging options are available. The ATLS60 version utilizes a fine pitch staggered row of bond pads to achieve the smallest die size possible for a given pad count. The ATLS60 is only available in a limited number of PQFP packages. ATL60 Array Organization Device Number Raw Gates Routable Gates Max Pin Count Max I/O Pins Gate(1) Speed ATL60/4 4,000 3,000 44 36 200 ps ATL60/15 15,000 10,000 68 60 200 ps ATL60/25 25,000 16,900 84 76 200 ps ATL60/40 38,000 25,400 100 92 200 ps ATL60/60 58,000 34,600 120 112 200 ps ATL60/85 86,000 51,900 144 136 200 ps ATL60/110 110,000 65,900 160 152 200 ps ATL60/150 149,000 89,300 184 176 200 ps ATL60/200 195,000 116,900 208 200 200 ps ATL60/235 232,000 139,500 226 218 200 ps ATL60/300 301,000 181,000 256 248 200 ps ATL60/435 430,000 260,000 304 296 200 ps ATL60/550 545,000 288,000 340 332 200 ps ATL60/700 693,000 363,000 380 372 200 ps ATL60/870 870,000 456,000 424 416 200 ps ATL60/1100 1,119,000 590,000 480 472 200 ps ATLS60 Array Organization Device Number Raw Gates Routable Gates Max Pin Count Max I/O Pins Gate(1) Speed ATLS60/80 12,500 8,000 80 72 200 ps ATLS60/100 20,400 13,000 100 92 200 ps ATLS60/120 30,200 17,500 120 112 200 ps ATLS60/144 44,600 26,000 144 136 200 ps ATLS60/160 55,300 32,500 160 152 200 ps ATLS60/208 96,500 57,000 208 200 200 ps ATLS60/225 113,500 67,500 225 217 200 ps ATLS60/256 148,200 88,000 256 248 200 ps Note: 1-2 1. Nominal 2 Input NAND Gate with a Fan Out of 2 ATL60 Gate Arrays ATL60GA-3.6-03/02 Design Design Systems Supported Design Flow Atmel supports several major software systems with complete macro cell libraries, as well as utilities for the netlist verification and accurate delay simulations. CadenceTM Verilog-XLTM is Atmel's golden simulator. MentorTM QuickSim IITM and SynopsysTM VSSTM are signoff level simulators. Atmel provides four methods for implementing a gate array design, while maintaining the same basic design flow for each of them. This flow involves both the C u s to m e r an d A t m el a t a ll c r itic a l r ev ie w a n d acceptance steps, as can be seen from the chart below. Database Acceptance occurs when Atmel receives and accepts the complete design database. The Preliminary D esign Review follow s Caden ce simulation and verification by Atmel. This includes functional as well as timing performance evaluation. The following design systems are supported: System Tools TM Cadence OpusTM - Schematic Capture VeritimeTM - Static Timing Verilog - XLTM - Simulator High Level Design - Floor Planning Viewlogic TM ViewDRAWTM - Schematic Capture ViewSIM TM - Simulator MotiveTM- Static Timing MentorTM NetedTM - Schematic Capture QuickSIMIITM - Simulator AutologicTM - Synthesis Quick PathTM - Static Timing SynopsysTM VSSTM - Simulator VHDL SimulationTM - Vital Libraries Design CompilerTM - Synthesis Test CompilerTM - Scan Insertion and ATPG VeribestTM ACEPlusTM - Schematic Capture VeribestTM - Simulator Model TechTM VHDL SimulationTM - Vital Libraries ExemplarTM LeonardoTM - Synthesis SunriseTM TestGenTM - Scan Insertion and ATPG Upon completion of this critical step, Atmel performs physical place-and-route. Additional simulations are performed, based on the physical design, including the generation of a back annotation report to provide the customer with the most accurate timing information available. Final Design Review is the last step of the design flow prior to generation of masks. After this acceptance step is completed, masks are generated and released, and prototype parts, in ceramic packages, are delivered. Pin Definition Requirements The corner pads on each die are reserved and programmable for Power and Ground only. All other buffer pins are fully programmable as Input, Output, Bidirectional, Clock-into-Array, Power or Ground. 1016A 1-3 ATL60GA-3.6-03/02 ATL60 Gate Array Design Flow Design Options VHDL/Verilog-HDL FPGA and PLD Conversions Atmel can accept Register Transfer Level (RTL) designs for VHDL (MIL-STD-454, IEEE STD 1076) or VerilogHDLTM format. Atmel fully supports Synopsys for VHDLTM simulation as well as synthesis. VHDL or Verilog-HDL is Atmel's preferred database format for Gate Array/ Embedded Array design. Atmel has successfully translated existing FPGA/PLD designs from most major vendors (Xilinx TM, ActelTM, AlteraTM, AMDTM and Atmel) into the gate arrays. There are four primary reasons to convert from an FPGA/PLD to a gate array. Conversion of high volume devices for a single or combined design is cost effective. Performance can often be optimized for speed or low power consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing onboard space requirements. Finally, in situations where an FPGA/PLD was used for fast cycle time prototyping, a gate array may provide a lower cost answer for long-term volume production. ASIC Design Translation Atmel has successfully translated existing designs from most major ASIC vendors (LSI LogicTM, MotorolaTM, SMOSTM, OkiTM, NECTM, FujitsuTM, AMITM and others) into the gate arrays. These designs have been optimized for speed and gate count and modified to add logic or memory, or replicated for a pin-for-pin compatible, dropin replacement. Design Entry Design entry is performed by the customer using an Atmel provided macro cell library. A complete netlist and vector set must be provided to Atmel. Upon acceptance of this data set, Atmel continues with the standard design flow. 1-4 ATL60 Gate Arrays ATL60GA-3.6-03/02 Macro Cores AVRTM (8-bit RISC) Microcontroller (8515) The AVR RISC Microcontroller is a true 8-bit RISC Architecture, ideally suited for embedded control applications. The AVR is offered as a gate level, soft macro in the ATL60 family. The AVR supports a powerful set of 120 instructions. The AVR pre-fetches an instruction during prior instruction execution, enabling the execution of one instruction per clock cycle. The Fast Access RISC register file consists of 32 general purpose working registers. These 32 registers eliminate the data transfer delay in the traditional program code intensive accumulator architectures. The AVR can incorporate up to 8k x 8 program memory (ROM) and 64k x 8 data memory (SRAM). Also included are several optional peripherals: UART, 8-bit timer/ counter, 16 bit timer/counter, external and internal interrupts and programmable watchdog timer. ARM7TDMITM Embedded Microcontroller Core The ARM7TDMI (Advanced RISC Machines) is a powerful 32-bit processor offered as an embedded core in the ATL60 series arrays. The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance for very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard dynamic SRAMs. The ARM7TDMI core includes several optional peripheral macros. The options offered are Real Time Clock, DMA Controller, USART, External Bus Interface, Interrupt, Timer and Advanced Power Management and Controller. OakDSPCoreTM Atmel's embedded OakDSPCore is a 16-bit, generalpurpose low-power, low-voltage and high-speed Digital Signal Processor (DSP). OAK is designed for mid-to-high-end telecommunications and consumer electronics applications, where lowpower and portability are major requirements. Among the applications supported are digital cellular telephones, fast modems, advanced facsimile machines and hard disk drives. OAK is available as a DSP core in Atmel's Gate Array cell library, to be utilized as an engine for DSP-based Gate Array/Embedded Array. It is specified with several levels of modularity in SRAM, ROM, I/O blocks, allowing efficient DSP-based Gate Array/Embedded Array development. OAK is aimed at achieving the best cost-performance factor for a given (small) silicon area. As a key element of a system-on-chip, it takes into account such requirements as program size, data memory size, glue logic, power management, etc. The OAK core consists of three main execution units operating in parallel: the Computation/Bit-Manipulation Unit (CBU), the Data Addressing Arithmetic Unit (DAAU) and the Program Control Unit (PCU). The Core also contains ROM and SRAM addressing units, and Program Control Logic (PCL). All other peripheral blocks, which are application specific, are defined as part of the user-specific logic, implemented around the DSP core on the same silicon die. OAK has an enhanced set of DSP and general microprocessor functions to meet the application requirements. The OAK programming model and instruction set are aimed at straightforward generation of efficient and compact code. 1-5 ATL60GA-3.6-03/02 Absolute Maximum Ratings* Operating Temperature .................... -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground .............-0.6V to VDD+0.75V1 Maximum Operating Voltage ............................... 6.0V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VDD + 0.75V dc which may overshoot to +7.0V for pulses of less than 20 ns. 5.0 Volt DC Characteristics Applicable over recommended operating range from Ta = -55C to +125C, VDD = 4.5V to 5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units IIH Input Leakage High VIN=VDD, V DD=5.5V 10 A IIL Input Leakage Low (no pull-up) Max R pull-up (U31) VIN=VSS, V DD=5.5V VIN=VSS, V DD=5.5V -10 -40 -5 A IOZ Output Leakage (no pull-up) VIN=VDD or VSS, V DD=5.5V -10 10 A IOS Output Short Circuit Current P01(2mA Buffer)(1) VIN=0, VDD=5V, VOUT=VDD VIN=VDD=5V, VOUT=VSS VIL TTL Input Low Voltage VIL CMOS Input Low Voltage VIH TTL Input High Voltage VIH CMOS Input High Voltage VT TTL Switching Threshold CMOS Switching Threshold VDD=5.0V, 25C VDD=5.0V, 25C 1.4 2.4 VOL Output Low Voltage Output buffer has 12 stages of drive capability with 2 mA I OL per stage IOL=as rated VDD=4.5V 0.2 VOH Output High Voltage Output buffer has 12 stages of drive capability with -2 mA IOH per stage IOH=as rated VDD=4.5V 16 14 mA mA 0.8 V 0.3 x VDD V 2.0 V 0.7 x VDD V 0.7 x VDD 4.2 V V 0.4 V V Note: 1. This is the specification for the P01 Buffer. Output short circuit current for other outputs will scale accordingly. Not more than one output shorted at a time, for a maximum of one second, is allowed. 1-6 ATL60 Gate Arrays ATL60GA-3.6-03/02 3.3 Volt DC Characteristics Applicable over recommended operating range from Ta = -55C to +125C, VDD = 2.7V to 3.6V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units IIH Input Leakage High VIN=VDD, VDD=3.6V 5 A IIL Input Leakage Low (no pull-up) Max R pull-up (U31) VIN=VSS, VDD=3.6V VIN=VSS, VDD=3.6V -5 -25 -3 IOZ Output Leakage (no pull-up) VIN=VDD or VSS, VDD=3.6V -5 5 IOS Output Short Circuit Current P01(1mA Buffer) (1) VDD=3.3V, VOUT=VDD VDD=3.3V, VOUT=VSS VIL CMOS Input Low Voltage VIH CMOS Input High Voltage VT CMOS Switching Threshold VDD=3.0V, 25C 1.5 VOL Output Low Voltage Output buffer has 12 stages of drive capability with 1 mA IOL per stage. IOL=as rated VDD=2.7V 0.11 VOH Output High Voltage Output buffer has 12 stages of drive capability with -1 mA IOH per stage. IOH=as rated VDD=2.7V A 8 7 mA mA 0.3 x VDD 0.7xVDD 0.7xVDD A V V V 0.4 2.3 V V 2.0 Volt DC Characteristics Applicable over recommended operating range from Ta = 0C to +70C, VDD = 1.8 V to 2.2 V (unless otherwise noted). Symbol Parameter Test Condition IIH Input Leakage High VIN=VDD, V DD=2.2 V IIL Input Leakage Low (no pull-up) Max R pull-up (U31) VIN=VSS, V DD=2.2V VIN=VSS, V DD=2.2V IOZ Output Leakage (no pull-up) VIN=VDD or VSS, V DD=2.2V IOS Output Short Circuit Current P01(0.5 mA Buffer)(1) VDD=2.0V, V OUT=VDD VDD=2.0V, V OUT=VSS VIL CMOS Input Low Voltage VIH CMOS Input High Voltage VT CMOS Switching Threshold VDD=3.0 V, 25C VOL Output Low Voltage Output buffer has 12 stages of drive capability with 0.5mA IOL per stage. IOL=as rated VDD=1.8 V VOH Output High Voltage Output buffer has 12 stages of drive capability with -0.5mA IOH per stage. IOH=as rated VDD=1.8 V Min Typ Max Units 5 A -5 -15 -2 A A -5 5 A 4 3 mA mA 0.2 x VDD 0.8xVDD V 0.5 x VDD V 0.2 x VDD 0.8xVDD V V V Note: 1. This is the specification for the P01 Buffer. Output short circuit current for other outputs will scale accordingly. Not more than one output shorted at a time, for a maximum of one second, is allowed. 1-7 ATL60GA-3.6-03/02 I/O Buffer DC Characteristics Symbol Parameter Test Condition Min Typ Max Units CIN Capacitance, Input Buffer (die) 5.0V, 3.3V, 2.0V 2.4 pF COUT Capacitance, Output Buffer (die) 5.0V, 3.3V, 2.0V 5.6 pF CI/O Capacitance, Bi-Directional 5.0V, 3.3V, 2.0V 6.6 pF V+ TTL Positive Threshold CMOS Positive Threshold 25C, 5.0V 25C, 5.0V 1.8 3.0 V- TTL Negative Threshold CMOS Negative Threshold 25C, 5.0V 25C, 5.0V V TTL Hysteresis CMOS Hysteresis V+ Schmitt Trigger 0.8 1.5 2.0 3.5 V V 1.0 2.0 V V 25C, 5.0V 25C, 5.0V 0.8 1.0 V V CMOS Positive Threshold 25C, 3.3V 1.8 V- CMOS Negative Threshold 25C, 3.3V V CMOS Hysteresis 25C, 3.3V 1.0 2.3 V 1.3 V 0.5 V I/O Buffers * Programmable output drive (2 to 24 mA IOL, -2 to -24 mA IOH for 5.0V 1 to 12 mA I OL, -1 to -12 mA IOH for 3.3V) The ATL60 series input/output ring contains the I/O buffer circuitry capable of sourcing and sinking currents up to 24 mA, and responds to CMOS or TTL logic levels. I/O locations on this ring can accommodate bidirectional and Tri-StateTM cells. I/O Options Input, Output, Bi-directional, Tri-StateTM Output, Internal Clock Driver and Oscillator Output Drive Value Programmable from 2 mA to 24 mA in 2 mA increments CMOS or TTL Operation Schmitt Trigger (Bi-directional, Input) Inverting and Non-inverting Input Buffers (Bi-directional, Input) Pull-Up Resistor - 12K to 372K (Low R values may invalidate VIL specification) Pull-Down Resistor - 4K to 124K (Low R values may invalidate VIH specification) 1-8 ATL60 Gate Arrays ATL60GA-3.6-03/02 AC Characteristics Delay vs Fanout 0.6 1.2 0.5 1 Prop Delay (ns) Prop Delay (ps) Prop Delay (ns) Delay vs VCC 0.4 0.3 0.2 0.1 0.8 0.6 0.4 0.2 0 3.0 3.3 3.6 4.5 5.0 0 5.5 2 4 Volts 8 16 50 100 Fanout 3.3 Volts VDD 3.3 Volts VDD 5.0 Volts VDD 5.0 Volts VDD 2 input NAND Temp = 25 C FO = 3 2 input NAND Temp = 25 C Delay vs Temperature Output Buffer vs Load 0.5 8 7 Prop Delay (ns) Prop PropDelay Delay (ns) (ps) 0.4 0.3 0.2 6 5 4 3 2 0.1 1 0 0 -55 25 125 10 Temperature ( C) Capacitive Load (pF) 3.3 Volts VDD 3.3 Volts VDD 5.0 Volts VDD 5.0 Volts VDD 2 input NAND FO = 3 25 PO4 - Output Buffer 8 mA Temp = 25 C 1-9 ATL60GA-3.7-10/98 ATL60GA-3.6-03/02 Source of CMOS Power Dissipation There are two primary components in standard CMOS power consumption. Flip Flop Power Equation: 1) P (uW) @ 3.3V = [2.5(1-DC) + (5.5 + 0.20X/2)*DC] N * Fc(MHz) The major portion of the power dissipation is related to charging and discharging of gate and interconnect capacitance during switching. It directly varies with capacitance load, square of supply voltage, and frequency (P = C x V**2 x F). 2) Quiescent or stand-by power dissipation comes primarily from two parasitic leakage paths. One is through the reverse bias P/N junctions inherent in CMOS and the second is the subthreshold source to drain current of MOS transistors in their off state. Quiescent Power = 0.025 W/Gate (typical) Atmel provides a methodology for calculating both components separately. The power factors given in the following calculations are accurate to within 25 percent. Power Calculation P (uW) @ 5V = [7.0(1-DC) + (15.7 + .45X/2)*DC] N * Fc(MHz) Where; DC = Duty Cycle = # cycles data changes/# of clock cycles Fc = FF Clock frequency X = average output load on FF(logic+wire)in unit loads N= number of FFs Peak current at 5 volt is 4N mA. It is recommended that an Gate Array/Embedded Array have at least 1 power and ground pin for each amp of peak current. Gate Power Estimation: P (uW) @ 5V = (.84 + .45X) * G * DC *Fc(MHz) P (uW) @ 3.3V = (.46 + 0.20X) * G * DC *Fc(MHz) Where; G = total gates less FFs DC = duty cycle (typically .05 to .20) Switching power can be divided into sequential cell (FF) power, combinational cell power, and I/O POWER. Flip flops and latches have internal clock buffering, and therefore dissipate power when a clock is active, even if data is not changing. This is shown below as 0% DC (duty cycle). All other power numbers assume 100% duty cycle, that is the cell output switches every time the input switches. 5 Volt Parameters FF Gates Duty Cycle 0% 100% 7.0 15.7 0.84 Peak Current (Ip) 2.5 Load Factor 0.45 I/O Units 16-30 uW/MHz uW/MHz mA uW/MHz/Unit Load 0.45 I/O Load Factor 12.5 uW/MHz/Pf Duty Cycle 0% 100% 2.5 5.5 Peak Current (Ip) 1.5 Load Factor 0.20 I/O Load Factor 1-10 P (uW) @ 5V = (16 + 12.5 * P) * N * Fd * DC P (uW) @ 3.3V = (7 + 5.4 * P) * N * Fd * DC Where; P = average output load in PF N = number of outputs Fd = Output frequency in MHz DC = Duty Cycle ATL60 Power Estimation Worksheet The following pages are Power Estimation Worksheets th a t c a n b e us ed to e s ti m a t e t otal c h ip po w e r consumption. Worksheet Examples have been provided and can be used as reference for chip power calculation. The directions below explain how to use the worksheets. 1. For each clock domain, fill out a Flip Flop Power Estimation Worksheet and an associated Gate Power Workstation. 3 Volt Parameters FF I/O Power: Gates I/O Units 16-30 uW/MHz uW/MHz 2. Complete the I/O Power Consumption Worksheet. 3. Sum up the results of all sheets for a whole chip power estimation. mA uW/MHz/Unit Load 0.20 5.4 uW/MHz/Pf ATL60 Gate Arrays 4. Use the estimated power to calculate the transistor junction temperature. Use the junction temperature in simulations. ATL60GA-3.6-03/02 Power Estimation Worksheet Examples Assume the following design: 5 volt VDD ,100K used gates with 2 clock domains. Domain A has 60K gates and 1500 Flip Flops running at 50MHz, with a duty cycle of 0.3 and an average output load of 3U.L. The data frequency is 25MHz with a duty cycle of 0.2 and an average gate loading of 3U.L. Domain B has 40K gates and 1K Flip Flops running at 12MHz with a duty cycle of 0.4 and an average load of 4U.L. The data frequency is 6MHz having a duty cycle of 0.4 and an average gate loading of 4U.L. Note that with duty cycle we mean the estimated percentage that a Flip Flop or logic gate transitions relative to its clock or data frequency. For example, if a Flip Flop transitions at Flip Flop clock frequency (F c), the duty cycle would be 1.0 or 100%. A more typical value would be 0.3. Likewise for combinational logic. Data can transition through logic at F d, but in practice you might only see one transition in 5 cycles, leading to a duty cycle of 0.2. There are 90 Output buffers and 10 Bi-directional buffers with a frequency of 20MHz, a duty cycle of 0.4 and an average capacitive load of 40pf. Flip Flop Power Estimation Worksheet Example - Domain A Description Variables Values Number of Flip Flop N 1500 Flip Flop Clock Frequency Fc 50MHz Duty Cycle (Flip Flop output transitions/clock cycles) DC 0.3 X 3 Average Loading, wire and pin capacitance on Flip Flop 5 Volt VDD P= [7(1-DC)+(15.7+.45X/2)*DC]N*Fc P= [7(1-0.3)+(15.7+.45*3/2)*0.3]1500*50 Power Consumed by Flip Flops = 736mW Gate Power Estimation Worksheet Example - Domain A Description Variables Values Number of Gates (not including Flip Flop) G 60K Data Frequency (typically 1/2Fc) Fd 25MHz Duty Cycle (%of Fd that data changes, typically 0.1 - 0.4) DC 0.2 X 3UL Average Loading, wire and pin capacitance on gate *1 5 Volt VDD P= (.84+.45X)*G*DC*Fd P= (.84+.45*3)*60,000*0.2*25 Power Consumed by Gates = 657mW *1 typical value of 3 Unit Loads 1-11 ATL60GA-3.6-03/02 Flip Flop Power Estimation Worksheet Example - Domain B Description Variables Values Number of Flip Flop N 1000 Flip Flop Clock Frequency Fc 12MHz Duty Cycle (Flip Flop output transitions/clock cycles) DC 0.4 X 4 Average Loading, wire and pin capacitance on Flip Flop 5 Volt VDD P= [7(1-DC)+(15.7+.45X/2)*DC]N*Fc P= [7(1-0.4)+(15.7+.45*4/2)*0.4]1000*12 Power Consumed by Flip Flops = 130mW Gate Power Estimation Worksheet Example - Domain B Description Variables Values Number of Gates (not including Flip Flop) G 40K Data Frequency (typically 1/2Fc) Fd 6MHz Duty Cycle (% of Fd that data changes, typically 0.1 - 0.4) DC 0.4 X 4UL Average Loading, wire and pin capacitance on gate *1 5 Volt VDD P= (.84+.45X)*G*DC*Fd P= (.84+.45*4)*40,000*0.4*6 Power Consumed by Gates = 253mW *1 Typical Value of 3 Unit Loads 1-12 ATL60 Gate Arrays ATL60GA-3.6-03/02 I/O Power Estimation Worksheet Example Description Variables Values Number of Outputs/Bidis or Tri State Buffers N 90 Data Frequency Fd 20MHz Duty Cycle (% of Fd that data changes, typically 0.2 - 0.5) DC 0.4 P 40 Average Capacitive Loading (pf) 5 Volt VDD P= (16+12.5P)*N*Fd*DC P= (16+12.5*40)*90*20*0.4 Total Power Consumed by I/O = 372 mW Estimated Chip Power Domain A Flip Flop Power 736mW Gate Power 657mW Domain B Flip Flop Power 130mW Gate Power 253mW I/O Power 372mW ___________________________ Total 2.15Watt 1-13 ATL60GA-3.6-03/02 ATL60 Flip Flop Power Estimation Worksheet Description Variables Number of Flip Flop N Flip Flop Clock Frequency Fc Duty Cycle (Flip Flop output transitions/clock cycles) DC Average loading, wire and pin capacitance on Flip Flop 5 Volt VDD P=[7(1-DC)+(15.7+0.45X/2)*DC]N*Fc Power Consumed by Flip Flops = _______ mW 3 Volt VDD P=[2.5(1-DC)+(5.5+0.20X/2)*DC]N*Fc Power Consumed by Flip Flops = _______ mW 1-14 ATL60 Gate Arrays X Values ATL60GA-3.6-03/02 ATL60 Combinational Gate Power Estimation Worksheet Description Variables Number of Gate (not including Flip Flop) G Data Frequency (typically 1/2 Fc) Fd Duty Cycle (% of Fd that data changes, typically 0.1 - 0.4) DC Average loading, wire and pin capacitance on gate *1 Values X 5 Volt VDD P=(.84+0.45X)*G*DC*Fd Process Consume by Gates I/O = _______ mW 3 Volt VDD P=(.46+0.20X)*G*DC*Fd Power Consumed by Gates I/O = _______ mW *1 typical value of 3 Unit Loads 1-15 ATL60GA-3.6-03/02 ATL60 I/O Power Estimation Worksheet Description Variables Number of Outputs/Bidis and Tri State Buffers N Data Frequency Fd Duty Cycle (% of Fd that data changes, typically 0.2 - 0.5) DC Average Capacitive Loading (pf) 5 Volt VDD P=(16+12.5*P)*N*Fd*DC Total Power Consumed by I/O = _______ mW 3 Volt VDD P=(7+5.4*P)*N*Fd*DC Total Power Consumed by I/O = _______ mW 1-16 ATL60 Gate Arrays P Values ATL60GA-3.6-03/02 Timing and Derating Factors Cell timing is generated from comprehensive transistor level circuit simulation over variations in temperature, voltage, loading and process variations. The Cell Library section includes pin-to-pin timing. Delays are represented as mx+b form, where b is the intrinsic delay through the cell (zero load), x is the output load and m is the load factor. All delay s are expressed in nanoseconds. Load factors are in nanoseconds per picofarad for output buffers and in nanoseconds per unit load for all internal cells. A unit load is one N channel and one P channel transistor gate. The Cell Library section contains m and b numbers for each input to output path, for output rising and output falling, under nominal conditions. For sequential logic, set up and hold times used, are the worst case values for a military environment. In set up measurements, timing is measured from the rising or falling edge of the data pin (50% of V DD) to the rising edge of the clock (50% of V DD). Hold measurements are taken from the rising edge of the clock to the rising or falling edge of the data pin. If set up or hold times are negative, the value is set to zero. Simulation libraries contain individual derating for each cell, provid ing the most accurate delay numbers possible. The tables below show the total derating fa ctors f o r milita ry, industrial and co m me rcial environments. ATL60 5.0 Volt Derating Factors Process Derating Factors Best Case Worst Case 0.748 1.265 Combined Derating Factors - Voltage, Temperature, and Process Conditions Best Case Worst Case 0.550 1.600 Industrial 0.60 1.45 Commercial 0.67 1.40 Military (4.5 Volts to 5.5 Volts) (-55C to 125C) ATL60 3.3 Volt Derating Factors Process Derating Factors Best Case Worst Case 0.748 1.265 Combined Derating Factors - Voltage, Temperature, and Process Conditions Best Case Worst Case 0.55 1.75 Industrial 0.61 1.53 Commercial 0.67 1.49 Military (2.7 Volts to 3.9Volts) (-55C to 125C) 1-17 ATL60GA-3.6-03/02 Power/Ground Simultaneous switching of outputs can result in large transient currents. Since the board, package, and chip ground wiring has a finite impedance, this current produces a transient increase in the local ground voltage, known as ground bounce. If a buffer site containing an input buffer experiences sufficient ground bounce, the input data may be erroneously detected by the buffer. Ground bounce may also adversely affect the speed performance of both input and output buffers. As a maximum, one power and one ground pin together can handle up to 80 mA of simultaneous switching output current. For example, ten 8 mA buffers would require a minimum of one power and one ground pin. Power and ground pins can supply both input and output buffers, or separate input and output buffers can be specified. Generally, simultaneously switching inputs and outputs should be grouped separately with additional supply pins between the groups. Several steps can be taken to help alleviate ground bounce problems. Use only minimum drive buffers necessary to achieve required output switching speeds. Atmel allows output drive on a single pin to be programmed in 2 mA increments from 2-24 mA. Adding extra power and ground pins will lessen ground bounce. Choice of input buffers also impacts the number of power and ground pins required. A TTL buffer with a switching point of 0.8 to 2.0V is more susceptible to ground bounce noise than a CMOS buffer. Unless other requirements dictate TTL level inputs, a CMOS buffer switching at 2.5V will offer more noise immunity. For excessively noisy environments, a Schmitt Trigger input is available. Power and ground distribution is provided by dedicated pins in each corner of the die, plus additional power and ground pins that can be placed at any pad location on any side. The dedicated corner pins supply power and ground to both the I/O ring and the internal array. Corner pins can be either power or ground. For custom package designs, these pins connect to low inductance and low resistance power and ground paths to the external package pins. Power/Ground Rules Rigorous solution of the ground bounce problem requires simulation of the board, package and chip together, with accurate models of the inductance, resistance and capacitance of the power distribution and buffer loads. Atmel will provide transistor level simulation results for specific applications as required. Fixed Power/Ground Pads 80 mA of simultaneous switching current between power or ground pins is the maximum allowed The corner pins (8) of all die are fixed as power or ground. Group inputs together and outputs together, with supply pins between groups All other pins are fully programmable Group bi-directional buffers with a common Tri-StateTM control 1-18 ATL60 Gate Arrays